Array substrate and display device

Abstract

The invention provides a display device and an array substrate thereof. The array substrate comprises: a substrate; the plurality of grid lines and the plurality of data lines are arranged on the substrate, the plurality of grid lines and the plurality of data lines intersect to define a plurality of sub-pixels, and a common electrode lead is arranged between each grid line and any row of sub-pixels adjacent to the grid line; the plurality of common electrodes are arranged on the substrate base plate and are arranged in the sub-pixels; each common electrode lead is connected with each common electrode in the sub-pixels in the same row, and each common electrode in the sub-pixels in the same row is connected with two common electrode leads on the two sides in the column direction of the sub-pixels in the row respectively.

Description

Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular, to an array substrate and a display device. Background Art

[0002] At present, liquid crystal display devices have been widely used. Generally, as the core component of liquid crystal display devices, array substrates integrate thin film transistors, gate lines, data lines, pixel electrodes, common electrodes, and common electrode leads. Light leakage is a common problem of liquid crystal display devices, which is mainly caused by light leakage around the pixel area.

[0003] In order to prevent light leakage, the liquid crystal display device is provided with a black matrix, which effectively blocks the propagation of unexpected light caused by light leakage by forming a light shielding structure around the pixel area. Therefore, a liquid crystal display device with a larger black matrix can better prevent light leakage. However, the use of a black matrix with a larger area reduces the aperture ratio of the liquid crystal display device, thereby affecting the brightness and color performance of the display device. Summary of the invention

[0004] The present disclosure aims to solve at least one of the technical problems existing in the prior art, and proposes an array substrate and a display device, which can form a shading structure around the pixel area to block the propagation of unintended light, while reducing the area of ​​the black matrix, thereby improving the aperture ratio of the display device.

[0005] To achieve the above objectives, the present disclosure provides an array substrate, including:

[0006] substrate substrate;

[0007] A plurality of gate lines and a plurality of data lines are arranged on the base substrate, the plurality of gate lines and the plurality of data lines intersect to define a plurality of sub-pixels, and a common electrode lead is provided between each of the gate lines and any adjacent row of the sub-pixels;

[0008] A plurality of common electrodes are arranged on the base substrate and in the sub-pixels; each of the common electrode leads is connected to the common electrodes in the sub-pixels in the same row, and each of the common electrodes in the sub-pixels in the same row is connected to two common electrode leads on both sides along the column direction of the sub-pixels in the row.

[0009] Optionally, the common electrode lead is arranged in the same layer as the gate line.

[0010] Optionally, each of the common electrode leads is provided in a different layer from the common electrodes in the sub-pixels in the same row, and is electrically connected through a first via hole.

[0011] Optionally, the common electrodes in two adjacent rows of sub-pixels are electrically connected one by one via a connecting line;

[0012] The connection line is extended along the column direction of the sub-pixels; the common electrodes in two adjacent rows of sub-pixels are arranged in different layers from the connection line, and are electrically connected to the connection line through a second via hole.

[0013] Optionally, the array substrate further comprises a pixel electrode, wherein the pixel electrode is disposed on the base substrate and disposed within the sub-pixel;

[0014] The connecting line is arranged in the same layer as the pixel electrode.

[0015] Optionally, an orthographic projection of the common electrode lead on the array substrate overlaps with an orthographic projection of the pixel electrode disposed in the same sub-pixel on the array substrate.

[0016] Optionally, the array substrate further comprises a common electrode edge lead arranged in the non-display area, and the common electrode edge lead and the common electrode lead are arranged in the same layer in the non-display area and are electrically connected.

[0017] Optionally, the array substrate further comprises a gate driving circuit disposed in the non-display area, and the gate driving circuit is connected to the plurality of gate lines in the non-display area through transfer vias;

[0018] Wherein, there is a gap between the common electrode edge lead and the transfer via hole.

[0019] Optionally, the array substrate further comprises: a plurality of data line terminals, which are used to be connected to the flexible circuit board, and the plurality of data line terminals are electrically connected to the data lines;

[0020] A plurality of the data line terminals have a preset distance from the edge of the adjacent array substrate.

[0021] Optionally, the plurality of data line terminals include a first data line terminal and a second data line terminal, the first data line terminal is electrically connected to the data lines with odd numbers, and the second data line terminal is electrically connected to the data lines with even numbers.

[0022] Optionally, the plurality of data line terminals include a first data line terminal, a second data line terminal, a third data line terminal, a fourth data line terminal, a fifth data line terminal and a sixth data line terminal, the first data line terminal being electrically connected to the data lines with odd numbers corresponding to the red sub-pixels, the second data line terminal being electrically connected to the data lines with odd numbers corresponding to the green sub-pixels, the third data line terminal being electrically connected to the data lines with odd numbers corresponding to the blue sub-pixels; the fourth data line terminal being electrically connected to the data lines with even numbers corresponding to the red sub-pixels, the fifth data line terminal being electrically connected to the data lines with even numbers corresponding to the green sub-pixels, and the sixth data line terminal being electrically connected to the data lines with even numbers corresponding to the blue sub-pixels.

[0023] Optionally, the array substrate further includes a plurality of test signal lines arranged in the non-display area, each of the test signal lines is connected to the corresponding data line terminal, and the other end of each of the test signal lines extends to one of the four corner areas of the non-display area.

[0024] Optionally, the array substrate further includes:

[0025] A pixel electrode, the pixel electrode is disposed on the base substrate and disposed in the sub-pixel;

[0026] A plurality of test signal lead-out terminals are arranged in the same layer as the pixel electrodes and are connected to the plurality of test signal lines through third via holes.

[0027] Optionally, the preset distance is greater than or equal to 200 μm.

[0028] Optionally, each of the common electrode lead lines includes a first lead line segment overlapping the data line and a second lead line segment not overlapping the data line, and a line width of the first lead line segment is smaller than a line width of the second lead line segment.

[0029] On the other hand, the present disclosure provides a display device including the above array substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figure 1 A schematic diagram of an array substrate provided in some embodiments of the present disclosure;

[0031] Figure 2 It is a light leakage simulation inverted color diagram of an array substrate in the prior art;

[0032] Figure 3 A light leakage simulation inverted color diagram of an array substrate provided in some embodiments of the present disclosure;

[0033] Figure 4A plan view of the circuit distribution in a local area of ​​an array substrate provided in an embodiment of the present disclosure;

[0034] Figure 5 For along Figure 4 Sectional view along line A-A';

[0035] Figure 6 For along Figure 4 Sectional view along line B-B';

[0036] Figure 7 A plan view of the circuit distribution in a local area of ​​an array substrate provided in an embodiment of the present disclosure;

[0037] Figure 8 A plan view of the circuit distribution in a local area of ​​an array substrate provided in an embodiment of the present disclosure;

[0038] Fig. 9 A schematic diagram of area division of an array substrate provided in some embodiments of the present disclosure;

[0039] Fig.10 A schematic diagram of area division of an array substrate provided in some embodiments of the present disclosure;

[0040] Fig.11 A partial schematic diagram of area division of an array substrate provided in some embodiments of the present disclosure;

[0041] Fig.12 A partial schematic diagram of the connection relationship between the data line terminal of the test signal line of the array substrate provided in some embodiments of the present disclosure and the corresponding data line and the test signal line;

[0042] Fig.13 A schematic diagram of area division of an array substrate provided in some embodiments of the present disclosure;

[0043] Fig.14 It is a partial structural schematic diagram of the peripheral area and the display area of ​​the display substrate provided in some embodiments of the present disclosure.

[0044] Fig.15 A schematic diagram of a display device provided in some embodiments of the present disclosure. DETAILED DESCRIPTION

[0045] The specific implementation of the present disclosure is described in detail below in conjunction with the accompanying drawings. It should be understood that the specific implementation described herein is only used to illustrate and explain the present disclosure, and is not used to limit the present disclosure.

[0046] In order to make the purpose, technical solution and advantages of the embodiments of the present disclosure clearer, the technical solution of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0047] Unless otherwise defined, the technical terms or scientific terms used in the embodiments of the present disclosure should be understood by people with ordinary skills in the field to which the present disclosure belongs. The "first", "second" and similar words used in the present disclosure do not represent any order, quantity or importance, but are only used to distinguish different components. Similarly, "including" or "comprising" and similar words mean that the elements or objects appearing in front of the word cover the elements or objects listed after the word and their equivalents, without excluding other elements or objects. "Connect" or "connected" and similar words are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0048] As used herein, "parallel" and "perpendicular" include the described situation and the situation similar to the described situation, and the range of the similar situation is within the acceptable deviation range, wherein the acceptable deviation range is determined by a person of ordinary skill in the art taking into account the measurement in question and the error associated with the measurement of a specific quantity (i.e., the limitations of the measurement system). For example, "parallel" includes absolute parallelism and approximate parallelism, wherein the acceptable deviation range of approximate parallelism can be, for example, a deviation within 5°; "perpendicular" includes absolute perpendicularity and approximate perpendicularity, wherein the acceptable deviation range of approximate perpendicularity can also be, for example, a deviation within 5°.

[0049] Exemplary embodiments are described herein with reference to cross-sectional views and / or plan views that are idealized exemplary drawings. In the drawings, the thickness of layers and regions are exaggerated for clarity. Therefore, variations in shape relative to the drawings due to, for example, manufacturing techniques and / or tolerances are conceivable. Therefore, the exemplary embodiments should not be interpreted as being limited to the shapes of the regions shown herein, but include deviations in shape due to, for example, manufacturing. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to illustrate the actual shapes of regions of the device, and are not intended to limit the scope of the exemplary embodiments.

[0050] In the embodiment of the present disclosure, the first direction X, the second direction Y and the third direction Z intersect each other. In the present disclosure, the first direction X and the second direction Y are perpendicular to each other in the plane where the substrate is located, the first direction X is a horizontal direction (i.e., a row direction, or an extension direction of a gate line), the second direction Y is a vertical direction (i.e., a column direction, or an extension direction of a data line), and the third direction Z is a vertical direction, which is perpendicular to the plane where the substrate is located, for illustration, but does not constitute a limitation to the present disclosure.

[0051] In the embodiments of the present disclosure, "the same layer" refers to a layer structure formed by using the same film-forming process to form a film layer for forming a specific pattern, and then using the same mask to form a patterning process. Depending on the specific pattern, the sequential patterning process may include multiple exposure, development or etching processes, and the specific pattern of the same layer formed may be continuous or discontinuous, and these specific patterns may also be at different heights or have different thicknesses. It should be understood that when a layer or an element is referred to as being on another layer or substrate, the layer or element may be directly on the other layer or substrate, or there may be an intermediate layer between the layer or element and the other layer or substrate.

[0052] Before introducing the specific structure of the array substrate of the present disclosure, the application scenario and circuit structure of the array substrate provided by the present disclosure are first described in detail. The array substrate of the present disclosure is applied to liquid crystal display, that is, a liquid crystal array substrate.

[0053] like Figure 1 and Figure 4 As shown, an embodiment of the present disclosure provides an array substrate 1. The array substrate 1 includes a base substrate 10, a plurality of gate lines 20, a plurality of data lines 30 and a plurality of common electrodes 70. The plurality of gate lines 20 and the plurality of data lines 30 are arranged on the base substrate 10. The plurality of gate lines 20 and the plurality of data lines 30 cross to define a plurality of sub-pixels 50. The plurality of sub-pixels 50 are distributed in an array. A common electrode lead 60 is provided between each gate line 20 and any row of sub-pixels 50 adjacent thereto. In other words, two common electrode leads 60 are provided between each gate line 20 and another gate line 20 adjacent thereto, and a row of sub-pixels 50 is provided between the two common electrode leads 60. The plurality of common electrodes 70 are provided on the base substrate 10 and are provided in the sub-pixels 50. Each common electrode lead 60 is connected to each common electrode 70 in the same row of sub-pixels 50, and each common electrode 70 in the same row of sub-pixels 50 is respectively connected to two common electrode leads 60 on both sides along the column direction of the row of sub-pixels 50. In other words, for each sub-pixel 50, two common electrode leads 60 adjacent thereto can be connected to the common electrode 70 of the sub-pixel 50.

[0054] In order to prevent the light leakage area from affecting the actual display effect, it is necessary to make the black matrix on the box substrate shield the light leakage area. Specifically, a black matrix is ​​provided on the box substrate, and the black matrix includes a plurality of light shielding strips, wherein the orthographic projection of a part of the light shielding strips on the base substrate 10 covers the orthographic projection of the gate line 20 on the base substrate 10; and the orthographic projection of another part of the light shielding strips on the base substrate 10 covers the orthographic projection of the data line 30 on the base substrate 10.

[0055] The prior art generally adopts increasing the width of the light shielding strip of the black matrix to prevent light leakage. In comparison, the array substrate 1 of the embodiment of the present disclosure can shield the light leakage area between the gate line 20 and the sub-pixel 50 by providing common electrode leads 60 on both sides of the same row of sub-pixels 50, thereby reducing the width requirement of the light shielding strip for shielding and improving the aperture ratio of the pixel. At the same time, by providing two common electrode leads 60, the overall conductivity of the common electrode 70 can be improved.

[0056] Figure 2 This is a light leakage simulation inversion color diagram of an array substrate in the prior art. Figure 3 This is a light leakage simulation inverted color diagram of an array substrate provided in some embodiments of the present disclosure. Figure 2 As shown in FIG. 1 , no common electrode lead is disposed between one side of the sub-pixel of the array substrate and the gate line GL in the prior art. In this case, the width a1 of the light leakage area of ​​this part is about 10 μm. Figure 3 As shown, the array substrate 1 provided in some disclosed embodiments is provided with an additional common electrode lead 60, so that a part of the light leakage between the gate line 20 and the sub-pixel 50 is shielded by the common electrode lead 60, thereby reducing the width a2 of this part of the light leakage area to about 5 μm compared with the width a1 in the prior art. On this basis, the width of the first light shielding strip can be greatly reduced, thereby improving the aperture ratio of the pixel.

[0057] Figure 5 For along Figure 4 Sectional view along line A-A'. Figure 6 For along Figure 4 The cross-sectional view of the B-B' line. Figure 5 As shown, the common electrode lead 60 and the gate line 20 can be arranged in the same layer. By arranging the common electrode lead 60 and the gate line 20 in the same layer, the process steps can be reduced, and the production complexity and manufacturing cost can be reduced. At the same time, the common electrode lead 60 and the gate line 20 are arranged in the same layer to avoid occupying additional space in the display area, and while the coverage of the common electrode lead 60 is increased to reduce the resistance, the aperture ratio of the pixel is maintained without being reduced.

[0058] In some embodiments, Figure 5As shown, each common electrode lead 60 and each common electrode 70 in the same row of sub-pixels 50 can be arranged in different layers, and as shown in FIG. Figure 7 As shown, the common electrode lead 60 is electrically connected to the corresponding common electrode 70 through the first via hole V1. The array substrate 1 of this embodiment arranges each common electrode lead 60 and each common electrode 70 in the same row of sub-pixels 50 in different layers, and realizes the electrical connection between the two through the first via hole V1, thereby avoiding complex wiring on the same layer, simplifying the process flow, reducing the probability of adverse conditions such as line short circuit and open circuit during the production process, improving product yield, and at the same time, making the wiring planning more reasonable, further improving the space utilization, and greatly alleviating the wiring congestion problem that may occur when more common electrode leads 60 are introduced.

[0059] In some embodiments, Figure 6 As shown, the common electrodes 70 in two adjacent rows of sub-pixels 50 can be electrically connected one by one through the connection line 80. The connection line 80 can be extended along the column direction of the sub-pixels 50. Figure 7 As shown, each common electrode 70 and the connection line 80 in two adjacent rows of sub-pixels 50 are arranged in different layers, and are electrically connected to the connection line 80 through the second via hole V2. Similarly, the array substrate 1 of this embodiment adopts a different layer arrangement method, which avoids complex wiring on the same layer and further improves space utilization.

[0060] In some embodiments, as described in 1, Figures 4 to 6 As shown, the array substrate 1 may further include a pixel electrode 90. The pixel electrode 90 is disposed on the base substrate 10 and disposed in the sub-pixel 50. The connecting line 80 is disposed in the same layer as the pixel electrode 90. The connecting line 80 of the array substrate 1 of this embodiment can avoid occupying an additional pixel opening area, and realize a compact design of the signal transmission path while maintaining the pixel opening ratio.

[0061] In some embodiments, Figure 1 and Figure 4 As shown, the orthographic projection of the common electrode lead 60 on the array substrate 1 overlaps with the orthographic projection of the pixel electrode 90 disposed in the same sub-pixel on the array substrate 1 .

[0062] In some embodiments, Figures 9 to 11 and Fig.13 As shown, the array substrate 1 has a display area AA and a non-display area BB surrounding the display area AA. The display area AA refers to the area of ​​the array substrate 1 that actually displays an image. The non-display area BB refers to the area of ​​various circuits and wirings in the array substrate 1 that are used to send signals to pixels (e.g., sub-pixels). The sub-pixels 50 are all located in the display area AA. In some embodiments, Fig. 9 and Fig.10As shown, the array substrate 1 may also include a common electrode edge lead 100 disposed in the non-display area BB. The common electrode edge lead 100 and the common electrode lead 60 are disposed in the same layer in the non-display area BB and are electrically connected. The array substrate 1 of this embodiment can optimize the signal transmission path and reduce the impedance of the common electrode by integrating the common electrode edge lead 100 in the non-display area BB and the common electrode lead 60 in the display area AA in the same conductive layer, thereby improving the voltage uniformity of the display panel and reducing problems such as screen flickering or uneven brightness. At the same time, the design does not require additional film layers or process steps, which is conducive to simplifying the manufacturing process and reducing production costs. The common electrode edge lead 100 is disposed in the non-display area BB, which can make full use of the frame space for signal wiring, avoid affecting the aperture ratio of the display area AA, and help to achieve a narrower frame design. This structure can also enhance the current carrying capacity of the common electrode and improve the stability and reliability of the display device.

[0063] In some embodiments, Figure 8 As shown, the array substrate 1 may further include a gate drive circuit GOA disposed in the non-display area BB. The gate drive circuit GOA is connected to a plurality of gate lines 20 in the non-display area BB through a transfer via SV. There is a gap SP between the common electrode edge lead 100 and the transfer via SV.

[0064] In some embodiments, Figures 9 to 13 As shown, the array substrate 1 may further include a plurality of data line terminals 210. The plurality of data line terminals 210 are used to connect to the flexible circuit board, and the plurality of data line terminals 210 are electrically connected to the data line 30. The plurality of data line terminals 210 have a preset distance h1 from the edge S of the adjacent array substrate 1. In some embodiments, the preset distance h1 may be greater than or equal to 200 μm. The data line terminals of the prior art usually extend to the edge of the array substrate, and static electricity in the external environment is easily conducted to the inside of the array substrate through the metal residual end of the data line terminal. The introduction of static electricity often causes the data line terminal to burn, which in turn seriously affects the display effect, and reduces product performance and user experience. In comparison, the array substrate 1 of this embodiment can enhance anti-static ability.

[0065] In some embodiments, Figure 1 As shown, each common electrode lead line 60 may include a first lead line segment 62 overlapping with the data line 30, and a second lead line segment 64 not overlapping with the data line 30. The line width of the first lead line segment is smaller than the line width of the second lead line segment. Thus, the array substrate 1 of this embodiment can ensure that when the number of common electrode leads 60 increases, the overlapping area between the common electrode leads 60 and the data lines 30 is reduced, so that the parasitic capacitance Cdc between the common electrode leads 60 and the data lines 30 does not increase.

[0066] In some embodiments, Fig. 9 As shown, the plurality of data line terminals 210 may include a first data line terminal 211 and a second data line terminal 212. The first data line terminal 211 is electrically connected to each data line DO with an odd number. The second data line terminal 212 is electrically connected to each data line DE with an even number. By independently connecting the odd and even data lines in groups, a physically isolated transmission channel can be formed, thereby reducing crosstalk between adjacent data lines and improving signal transmission stability.

[0067] In some embodiments, Figures 10 to 13 As shown, the plurality of data line terminals 210 may include a first data line terminal 221, a second data line terminal 222, a third data line terminal 223, a fourth data line terminal 224, a fifth data line terminal 225, and a sixth data line terminal 226. The first data line terminal 221 is electrically connected to the data line DRO of each odd number corresponding to the red sub-pixel. The second data line terminal 222 is electrically connected to the data line DGO of each odd number corresponding to the green sub-pixel. The third data line terminal 223 is electrically connected to the data line DBO of each odd number corresponding to the blue sub-pixel. The fourth data line terminal 224 is electrically connected to the data line DRE of each even number corresponding to the red sub-pixel. The fifth data line terminal 225 is electrically connected to the data line DGE of each even number corresponding to the green sub-pixel. The sixth data line terminal 226 is electrically connected to the data line DBE of each even number corresponding to the blue sub-pixel. By connecting the data lines of the three primary colors of red, green and blue to the odd and even data line terminals respectively, a transmission channel divided by color gamut is formed, which can reduce the signal crosstalk between sub-pixels of different colors. For example, the red data lines DRO and DRE are transmitted through the first data line terminal 221 and the fourth data line terminal 224, which can avoid the influence of electromagnetic coupling generated by the high-frequency driving of the green sub-pixel on the red channel. During the test, the pixels of the three primary colors of red, green and blue can be tested separately, for example, the pure colors of the three primary colors of red, green and blue can be detected to improve the efficiency of picture detection.

[0068] In some embodiments, Figures 9 to 13As shown, the array substrate 1 may also include a plurality of test signal lines 300 disposed in the non-display area BB, each test signal line 300 being connected to a corresponding data line terminal 210. The other end of each test signal line 300 extends to one of the four corner areas CC of the non-display area BB. Through the above arrangement, the array substrate 1 of this embodiment can centrally arrange the test signal lines 300 in the corner area CC of the non-display area BB, which can significantly optimize the utilization of the wiring space and reduce the interference of the test signal lines to other functional lines. At the same time, this centralized wiring design facilitates unified lead-out during the array substrate test phase, improves test efficiency and reduces test complexity. In addition, extending the test signal line 300 to the corner area CC can also make the terminal for test signal lead-out (for example, the test signal lead-out terminal 310 described below) only remain in the corner area CC after the array substrate 1 is cut, so as not to affect the display area AA. At the same time, after the test is completed, the test signal line 300 between the adjacent data line terminals 210 will be cut off to ensure that the data line terminals are no longer connected to each other to ensure normal display.

[0069] In some embodiments, Fig.14 As shown, the array substrate 1 may also include a plurality of test signal lead terminals 310. The plurality of test signal lead terminals 310 are arranged in the same layer as the pixel electrode 90, and are connected to the plurality of test signal lines 300 through the third via V3. By arranging the test signal lead terminals 310 in the same layer as the pixel electrode 90, the array substrate 1 of this embodiment can simplify the manufacturing process, reduce additional mask plates and etching steps, thereby reducing production costs and improving production efficiency. At the same time, the third via V3 is used to realize the connection between the test signal lead terminals 310 and the test signal lines 300, thereby improving the transmission reliability of the test signal. In addition, the structural design optimizes the wiring space, avoids occupying additional film layers, is conducive to realizing a narrow frame design, and enhances the overall integration of the array substrate.

[0070] like Fig.15 As shown, the embodiment of the present disclosure further provides a display device 400, including an array substrate 1. In some embodiments, the display device 400 includes a pairing substrate 500, and the array substrate 1 and the pairing substrate 500 are arranged opposite to each other. The display device 400 may also include a liquid crystal layer 600 located between the array substrate 1 and the pairing substrate 500. The pairing substrate 500 may specifically be a color filter substrate, which includes a color filter layer and a black matrix 520 arranged on a base 510. The black matrix 520 includes a plurality of shading strips to cover the orthographic projections of devices such as gate lines 20, data lines 30, common electrode leads 60, and connecting lines 80 on the base substrate 10.

[0071] In some embodiments, the display device 400 may be a curved display device.

[0072] In some embodiments, the display device 400 can be used in any product or component with a display function, such as electronic paper, mobile phones, tablet computers, televisions, monitors, laptop computers, digital photo frames, and navigators.

[0073] Those skilled in the art will readily appreciate other embodiments of the present disclosure after considering the specification and practicing the disclosure disclosed herein. The present disclosure is intended to cover any variations, uses, or adaptations of the present disclosure that follow the general principles of the present disclosure and include common knowledge or customary techniques in the art that are not disclosed in the present disclosure. The description and examples are to be considered exemplary only, and the true scope and spirit of the present disclosure are indicated by the following claims.

[0074] It should be understood that the present disclosure is not limited to the exact structures that have been described above and shown in the drawings, and that various modifications and changes may be made without departing from the scope thereof. The scope of the present disclosure is limited only by the appended claims.

Claims

1. An array substrate, characterized in that: include: substrate substrate; A plurality of gate lines and a plurality of data lines are arranged on the base substrate, the plurality of gate lines and the plurality of data lines intersect to define a plurality of sub-pixels, and a common electrode lead is provided between each of the gate lines and any adjacent row of the sub-pixels; A plurality of common electrodes are arranged on the base substrate and in the sub-pixels; each of the common electrode leads is connected to the common electrodes in the sub-pixels in the same row, and the common electrodes in the sub-pixels in the same row are respectively connected to two common electrode leads on both sides along the column direction of the sub-pixels in the row.

2. The array substrate according to claim 1, characterized in that: The common electrode lead is arranged in the same layer as the gate line.

3. The array substrate according to claim 2, characterized in that: Each of the common electrode leads is arranged in a different layer from the common electrodes in the sub-pixels in the same row, and is electrically connected through a first via hole.

4. The array substrate according to claim 3, characterized in that: The common electrodes in two adjacent rows of sub-pixels are electrically connected one by one via a connecting line; The connection line is extended along the column direction of the sub-pixels; the common electrodes in two adjacent rows of sub-pixels are arranged in different layers from the connection line, and are electrically connected to the connection line through a second via hole.

5. The array substrate according to claim 4, characterized in that: Also included is a pixel electrode, which is disposed on the base substrate and disposed in the sub-pixel; The connecting line is arranged in the same layer as the pixel electrode.

6. The array substrate according to claim 5, characterized in that: The orthographic projection of the common electrode lead on the array substrate overlaps with the orthographic projection of the pixel electrode disposed in the same sub-pixel on the array substrate.

7. The array substrate according to claim 3, characterized in that: It also includes a common electrode edge lead disposed in the non-display area. The common electrode edge lead and the common electrode lead are disposed in the same layer in the non-display area and are electrically connected.

8. The array substrate according to claim 7, characterized in that: It also includes a gate driving circuit disposed in the non-display area, wherein the gate driving circuit is connected to the plurality of gate lines in the non-display area through transfer vias; Wherein, there is a gap between the common electrode edge lead and the transfer via hole.

9. The array substrate according to claim 1, characterized in that: Also includes: A plurality of data line terminals, used to be connected to the flexible circuit board, and the plurality of data line terminals are electrically connected to the data lines; A plurality of the data line terminals have a preset distance from the edge of the adjacent array substrate.

10. The array substrate according to claim 9, characterized in that: The plurality of data line terminals include a first data line terminal and a second data line terminal, the first data line terminal is electrically connected to the data lines with odd numbers, and the second data line terminal is electrically connected to the data lines with even numbers.

11. The array substrate according to claim 9, characterized in that: The multiple data line terminals include a first data line terminal, a second data line terminal, a third data line terminal, a fourth data line terminal, a fifth data line terminal and a sixth data line terminal, the first data line terminal is electrically connected to the data line with each odd number corresponding to the red sub-pixel, the second data line terminal is electrically connected to the data line with each odd number corresponding to the green sub-pixel, the third data line terminal is electrically connected to the data line with each odd number corresponding to the blue sub-pixel; the fourth data line terminal is electrically connected to the data line with each even number corresponding to the red sub-pixel, the fifth data line terminal is electrically connected to the data line with each even number corresponding to the green sub-pixel, and the sixth data line terminal is electrically connected to the data line with each even number corresponding to the blue sub-pixel.

12. The array substrate according to any one of claims 9 to 11, characterized in that: It also includes a plurality of test signal lines arranged in the non-display area, each of the test signal lines is connected to the corresponding data line terminal, and the other end of each of the test signal lines extends to one of the four corner areas of the non-display area.

13. The array substrate according to claim 12, characterized in that: Also includes: A pixel electrode, the pixel electrode is disposed on the base substrate and disposed in the sub-pixel; A plurality of test signal lead-out terminals are arranged in the same layer as the pixel electrodes and are connected to a plurality of the test signal lines through third via holes.

14. The array substrate according to any one of claims 9 to 11, characterized in that: The preset distance is greater than or equal to 200 μm.

15. The array substrate according to claim 1, characterized in that: Each of the common electrode lead lines includes a first lead line segment overlapping the data line and a second lead line segment not overlapping the data line, and a line width of the first lead line segment is smaller than a line width of the second lead line segment.

16. A display device, characterized in that: Comprising the array substrate as described in any one of claims 1 to 15.

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