Etching groove depth uniformity control method
By preparing and patterning the etch stop layer on the waveguide substrate, combined with the preparation of the waveguide and silicon oxide layers, the problem of etching groove depth uniformity control is solved, and the precise regulation of etching depth and the improvement of device yield is achieved.
Patent Information
- Application Number
- CN202510124224.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-01-26
- Publication Date
- 2025-05-13
AI Technical Summary
The prior art is difficult to effectively control the uniformity of the depth of the etching groove, resulting in a decrease in the unevenness of subsequent process processing and device yield.
An etch stop layer is prepared on the waveguide substrate and patterned to form a patterned etch stop layer structure. Then, a waveguide layer is prepared on the etch stop layer structure and patterned to form a patterned waveguide structure. A first silicon oxide layer is then formed on the waveguide structure, and a metal deposition groove is prepared thereon, so that the bottom of the groove extends internally to the etch stop layer, and the stop layer is removed to obtain the final metal deposition groove.
By preparing the etching stop layer in advance, the uniformity of the etching depth is effectively controlled, the flatness of the subsequent process and the device yield are improved, and the etching depth is accurately adjusted.
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Figure CN119987130A_ABST
Abstract
Description
Technical Field
[0001] The invention relates to the technical field of optical modulation devices, and in particular to a method for controlling the uniformity of etching groove depth. Background Art
[0002] Integrated photonic microsystems are used in various fields such as communication, sensing and computing. The demand for optical communication bandwidth in modern society is increasing, and optical modulation devices play a vital role in this regard. With the rise of commercial integrated photonics, various modulation platforms have been proven to have wafer-level manufacturing capabilities, among which lithium niobate material has become one of the most preferred materials due to its special electro-optical properties. The inhomogeneous heterogeneous integration of lithium niobate material and waveguide platform shows excellent modulation performance.
[0003] The existing technical solution first prepares the waveguide substrate and prepares various optical devices; then etches the silicon oxide material around the optical waveguide to form an etching groove for the subsequent preparation of metal electrode leads; after filling the silicon oxide and flattening the surface, the lithium niobate substrate and the waveguide substrate are heterogeneously integrated. This solution can solve the problems of incompatibility between lithium niobate materials and CMOS processes and large optical losses of waveguide devices in traditional integration solutions.
[0004] However, in the existing scheme, the metal electrode needs to meet a certain thickness (~1μm) to ensure good electrical properties. Therefore, the depth of the etched metal deposition groove is generally greater than 1μm. At this time, it is impossible to effectively control the uniformity of the etching depth by optimizing the etching process, and the accuracy is greater than ±10%. It has a great impact on subsequent process processing such as metal / dielectric thin film deposition, etching, and CMP uniformity control, while reducing the device yield and is not conducive to improving production capacity. Summary of the invention
[0005] In view of this, an embodiment of the present application provides a method for controlling the uniformity of the etched groove depth, so as to achieve the purpose of controlling the uniformity of the etched groove depth, thereby improving the device yield.
[0006] The embodiment of the present application provides the following technical solution: a method for controlling the uniformity of etching groove depth, comprising:
[0007] Forming an etch stop layer on a waveguide substrate, and patterning the etch stop layer to obtain a patterned etch stop layer structure;
[0008] Forming a waveguide layer on the etch stop layer structure, and patterning the waveguide layer to obtain a patterned waveguide structure;
[0009] Forming a first silicon oxide layer on the waveguide structure, so that the first silicon oxide layer completely covers the waveguide structure, the etch stop layer structure and the waveguide substrate;
[0010] A metal deposition groove is prepared at a position on the first silicon oxide layer corresponding to the etch stop layer structure, and the bottom of the metal deposition groove is extended inward to the etch stop layer structure. The etch stop layer structure is removed to obtain the final metal deposition groove for forming a metal electrode.
[0011] According to an embodiment of the present application, the waveguide layer includes a first waveguide layer and a second waveguide layer formed in sequence, the first waveguide layer is patterned to form a corresponding first waveguide structure, and the second waveguide layer is patterned to form a corresponding second waveguide structure.
[0012] According to an embodiment of the present application, the first waveguide layer is a silicon-rich silicon nitride layer, and the second waveguide layer is a silicon nitride layer.
[0013] According to an embodiment of the present application, the etch stop layer is made of any one of silicon nitride and polysilicon.
[0014] According to an embodiment of the present application, the method further includes: preparing a waveguide layer on the waveguide substrate to use the waveguide layer as the etch stop layer, and patterning the waveguide layer to obtain the etch stop layer structure and the waveguide structure.
[0015] According to an embodiment of the present application, the waveguide substrate includes a silicon substrate and a second silicon oxide layer which are formed in sequence, and the etch stop layer is formed on the second silicon oxide layer.
[0016] According to an embodiment of the present application, the first silicon oxide layer is prepared by chemical vapor deposition, and the second silicon oxide layer is prepared by thermal oxidation.
[0017] According to an embodiment of the present application, the method further includes: before preparing a metal deposition groove at a position on the first silicon oxide layer corresponding to the etch stop layer structure, planarizing the surface of the first silicon oxide layer.
[0018] According to an embodiment of the present application, the method further includes: depositing a metal electrode layer on a surface of the metal deposition groove and a surface of the first silicon oxide layer, so as to cover the metal deposition groove and the first silicon oxide layer with the metal electrode layer;
[0019] A patterned photoresist layer is formed on the metal electrode layer in the metal deposition tank; the metal electrode layer is patterned using the photoresist layer as a mask, and then the photoresist layer is removed to form a metal electrode in the metal deposition tank.
[0020] According to an embodiment of the present application, the thickness of the metal electrode does not exceed the groove depth of the metal deposition groove, and the top of the metal electrode is not higher than the top of the waveguide structure.
[0021] Compared with the prior art, the beneficial effects that can be achieved by at least one of the above-mentioned technical solutions adopted in the embodiments of this specification include at least the following: the embodiments of the present invention prepare and form an etch stop layer on a waveguide substrate, and perform patterning on the etch stop layer to obtain a patterned etch stop layer structure; prepare and form a waveguide layer on the etch stop layer structure, and perform patterning on the waveguide layer to obtain a patterned waveguide structure; prepare and form a first silicon oxide layer on the waveguide structure, so that the first silicon oxide layer completely covers the waveguide structure, the etch stop layer structure and the waveguide substrate; prepare a metal deposition groove at a position corresponding to the etch stop layer structure on the first silicon oxide layer, and extend the bottom of the metal deposition groove inward to the etch stop layer structure, remove the etch stop layer structure, and obtain the final metal deposition groove for forming a metal electrode. In the embodiment of the present invention, an etching stop layer is prepared in advance in the grooved area, so that the silicon oxide etching process stops when encountering the stop layer, and the stop layer is removed after the etching is completed. For deep grooves with an etching depth exceeding 1μm, the depth uniformity can be effectively controlled, providing a good flat surface for subsequent thin film deposition, etching and other processes; at the same time, when deep grooves are prepared by this method, the etching depth can be accurately controlled by controlling parameters such as the stop layer thickness and spacing. BRIEF DESCRIPTION OF THE DRAWINGS
[0022] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.
[0023] Figure 1 It is a schematic flow chart of a method for controlling the uniformity of etching groove depth according to an embodiment of the present invention;
[0024] Figure 2 is a first structural schematic diagram of a method for controlling the uniformity of etching groove depth in a first embodiment of the present invention;
[0025] Figure 3 is a second structural schematic diagram of the process of the etching groove depth uniformity control method of the first embodiment of the present invention;
[0026] Figure 4 is a third structural schematic diagram of the process of the etching groove depth uniformity control method of the first embodiment of the present invention;
[0027] Figure 5is a fourth structural schematic diagram of the process of the etching groove depth uniformity control method of the first embodiment of the present invention;
[0028] Figure 6 is a fifth structural schematic diagram of the process of the etching groove depth uniformity control method of the first embodiment of the present invention;
[0029] Figure 7 is a first structural schematic diagram of a method for controlling the uniformity of etching groove depth in a second embodiment of the present invention;
[0030] Figure 8 is a second structural schematic diagram of a method for controlling the uniformity of etching groove depth in a second embodiment of the present invention;
[0031] Fig. 9 is a third structural schematic diagram of the process of the etching groove depth uniformity control method of the second embodiment of the present invention;
[0032] Fig.10 is a fourth structural schematic diagram of the process of the etching groove depth uniformity control method of the second embodiment of the present invention;
[0033] Fig.11 is a fifth structural schematic diagram of the process of the etching groove depth uniformity control method of the second embodiment of the present invention;
[0034] Among them, 10, 20 are silicon substrates, 11, 21 are thermally oxidized silicon layers, 12, 23 are silicon-rich silicon nitride layers, 22 are etch stop layers, 13, 24 are silicon nitride layers, 14, 25 are chemical vapor deposited silicon oxide layers, and 15, 26 are metal deposition tanks. DETAILED DESCRIPTION
[0035] The embodiments of the present application are described in detail below with reference to the accompanying drawings.
[0036] The following describes the implementation methods of the present application through specific specific examples, and those skilled in the art can easily understand other advantages and effects of the present application from the content disclosed in this specification. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. The present application can also be implemented or applied through other different specific implementation methods, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present application. It should be noted that, in the absence of conflict, the features in the following embodiments and embodiments can be combined with each other. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in the field without making creative work belong to the scope of protection of the present application.
[0037] like Figure 1As shown, an embodiment of the present invention provides a method for controlling the uniformity of etching groove depth, comprising:
[0038] 101. Forming an etch stop layer on a waveguide substrate, and patterning the etch stop layer to obtain a patterned etch stop layer structure;
[0039] 102. Forming a waveguide layer on the etch stop layer structure, and patterning the waveguide layer to obtain a patterned waveguide structure;
[0040] 103. Forming a first silicon oxide layer on the waveguide structure, so that the first silicon oxide layer completely covers the waveguide structure, the etch stop layer structure and the waveguide substrate;
[0041] 104. Prepare a metal deposition groove at a position on the first silicon oxide layer corresponding to the etch stop layer structure, and extend the bottom of the metal deposition groove inward to the etch stop layer structure, remove the etch stop layer structure, and obtain the final metal deposition groove for forming a metal electrode.
[0042] The embodiment of the present invention prepares an etch stop layer structure in advance in the groove corresponding area before etching silicon oxide. The silicon oxide etching process stops when encountering the etch stop layer structure. For deep grooves with an etching depth exceeding 1 μm, the uniformity of the etched groove depth can be effectively controlled, providing a good flat surface for subsequent thin film deposition, etching and other processes, improving the subsequent process preparation window, and finally removing the etch stop layer structure to obtain a deep groove with a uniform and controllable etching depth, and prepare the required device structure in the groove. At the same time, when the deep groove is prepared by this method, the etching depth can be accurately controlled by controlling parameters such as the stop layer thickness and spacing.
[0043] In the specific implementation, regarding the specific parameters of the thickness and position of the etch stop layer, it is necessary to verify the process according to the design, the stop layer material, and the etching selectivity ratio of the stop layer and the underlying silicon oxide, and then determine the specific parameters. Among them, the thickness of the etch stop layer can be controlled more accurately by the designed recipe (precisely defined process parameters and operating procedures), with a deviation within 10%. It can also be measured by step profiler testing and SEM / FIB slice observation of the film structure to obtain a more accurate planar growth film thickness. Since the position of the etch stop layer corresponds to the position of the metal deposition tank, the position of the etch stop layer is determined according to the position of the subsequent metal deposition tank.
[0044] According to some embodiments of the present invention, the waveguide layer may be a double-layer waveguide structure, that is, the waveguide layer includes a first waveguide layer and a second waveguide layer formed sequentially from bottom to top, the first waveguide layer is patterned to form a corresponding first waveguide structure, and the second waveguide layer is patterned to form a corresponding second waveguide structure. In a specific implementation, the first waveguide layer may be a silicon-rich silicon nitride waveguide layer, and the second waveguide layer may be a silicon nitride waveguide layer.
[0045] In this embodiment, the etching stop layer is made of any one of silicon nitride and polysilicon. In this embodiment, before preparing the silicon-rich silicon nitride waveguide structure, another stop layer (silicon nitride, polysilicon, etc.) is prepared, and then the silicon oxide is etched to the etching stop layer structure and then stopped. The process can arbitrarily adjust the stop layer thickness, spacing and other parameters to control the etching depth and meet the design requirements.
[0046] According to some embodiments of the present invention, the method further comprises: preparing a waveguide layer on the waveguide substrate to use the waveguide layer as the etch stop layer, and patterning the waveguide layer to obtain the etch stop layer structure and the waveguide structure.
[0047] This embodiment uses a waveguide layer as an etch stop layer. After the waveguide layer is patterned, the etch stop layer structure and the desired waveguide structure are obtained respectively. The preparation process is simple. The etch stop layer structure is also obtained while the waveguide layer is patterned. Then, the silicon oxide is etched to the etch stop layer structure and then stopped.
[0048] According to some embodiments of the present invention, the waveguide layer is a double-layer waveguide structure, including a first waveguide layer and a second waveguide layer formed sequentially from bottom to top, and the method further includes: preparing and forming the first waveguide layer on the waveguide substrate, using the first waveguide layer as the etch stop layer, and performing patterning on the first waveguide layer to obtain the etch stop layer structure and the first waveguide structure.
[0049] This embodiment adopts a double-layer waveguide structure, and uses the front silicon-rich silicon nitride waveguide layer (first waveguide layer) as an etch stop layer. After the silicon-rich silicon nitride waveguide layer is patterned, the etch stop layer structure and the required waveguide structure are obtained respectively. The preparation process is simple, and the etch stop layer is obtained while the waveguide layer is patterned, that is, the etch stop layer structure is also obtained while the silicon-rich silicon nitride waveguide structure is formed, and then the etching of silicon oxide stops when the etch stop layer structure is reached.
[0050] According to some embodiments of the present invention, the waveguide substrate includes a silicon substrate and a second silicon oxide layer formed in sequence, and the etching stop layer is prepared on the second silicon oxide layer. The first silicon oxide layer is a silicon oxide layer prepared by chemical vapor deposition, and the second silicon oxide layer is a silicon oxide layer prepared by thermal oxidation. The two layers of silicon oxide are non-same-layer thin film structures, and there is a silicon nitride waveguide structure in the middle: the second silicon oxide layer is prepared by thermal oxidation, which has the best density and the best film quality, and can be used as a lower silicon oxide layer to grow a silicon nitride thin film layer with good crystal quality to optimize the optical performance; after the silicon nitride thin film layer is grown, it is impossible to continue to prepare silicon oxide by thermal oxidation, so the upper cladding silicon oxide is prepared by chemical vapor deposition to form a first silicon oxide layer. The film quality is slightly worse than that of the second silicon oxide layer, but it can be used as a cladding to protect the silicon nitride waveguide structure.
[0051] According to some embodiments of the present invention, the method also includes: before preparing a metal deposition groove at a position on the first silicon oxide layer corresponding to the etch stop layer structure, performing chemical mechanical polishing on the surface of the first silicon oxide layer to make the surface of the first silicon oxide layer smooth and flat, thereby accurately controlling the uniformity of the etching depth of the metal deposition groove.
[0052] According to some embodiments of the present invention, the method further includes: depositing a metal electrode layer on the surface of the metal deposition tank and the surface of the first silicon oxide layer, so as to cover the metal deposition tank and the first silicon oxide layer with the metal electrode layer; forming a patterned photoresist layer on the metal electrode layer in the metal deposition tank; using the photoresist layer as a mask, patterning the metal electrode layer, and then removing the photoresist layer to form the metal electrode in the metal deposition tank. Wherein, the thickness of the metal electrode does not exceed the depth of the metal deposition tank, and the top of the metal electrode is not higher than the top of the waveguide structure. In specific implementation, the metal electrode layer can be made of materials such as Al and Cu. The thickness of the metal electrode layer does not exceed the groove depth of the metal deposition groove, and the gap between the top of the metal electrode and the top of the waveguide structure is controlled to be 0-100nm. The reason is that after the metal electrode structure is prepared, it is necessary to cover the cladding silicon oxide and perform a CMP process (chemical mechanical polishing) on the cladding silicon oxide to control the cladding silicon oxide to be 100nm higher than the silicon nitride waveguide layer, optimize the optical performance and prepare for the subsequent bonding process; if the metal electrode is higher than the waveguide layer, there is not enough process window to control the requirement of 100nm silicon oxide thickness on the silicon nitride waveguide layer, which affects the optical performance and may also cause damage to the metal electrode during the CMP process, thereby affecting the electrical performance.
[0053] Next, refer to the attached Figure 2-Figure 11 , the embodiments of the present invention are described in detail.
[0054] Embodiment 1: Using the front silicon-rich silicon nitride waveguide layer as an etch stop layer (double-layer waveguide structure).
[0055] This embodiment proposes a solution for controlling the uniformity of the depth of the etching groove by preparing a stop layer. The following is a specific description of the process steps using a Si3N4 waveguide substrate as an example (unless otherwise specified, all schematic diagrams are cross-sectional views):
[0056] like Figure 2 As shown, first, a thermal oxide substrate is prepared, including a silicon substrate 10 and a thermal oxide silicon layer 11 formed in sequence. Next, a silicon-rich silicon nitride layer is prepared and patterned by photolithography and etching processes to form a desired structure, such as Figure 3 As shown, a silicon-rich silicon nitride layer 12 is formed on the thermal oxide silicon layer 11, and the silicon-rich silicon nitride layer 12 is used as an etching stop layer. The position ① of the silicon-rich silicon nitride layer 12 is an etching stop layer structure, and the rest is a waveguide structure and a dummy (component or structure without circuit function) structure. Next, a silicon nitride layer 13 and a chemical vapor deposition silicon oxide layer 14 are grown, and the silicon nitride layer 13 is patterned to cover the cladding silicon oxide, and the surface of the chemical vapor deposition silicon oxide layer 14 is chemically mechanically polished (CMP), as shown in FIG. Figure 4 shown.
[0057] Next, the chemical vapor deposited silicon oxide layer 14 is etched to prepare a metal deposition groove 15. Due to the presence of an etching stop layer structure, etching is stopped when the stop layer is reached. At this time, the etching depth uniformity is good and the precision is controllable. Figure 5 Finally, the etch stop layer structure is removed and the etching depth is increased to meet the metal deposition conditions. Since the etch stop layer is thin, the etching depth is controllable, as shown in FIG. Figure 6 shown.
[0058] Embodiment 2: An etch stop layer is prepared separately in the grooved area (double-layer waveguide structure).
[0059] like Figure 7 As shown, first, a thermal oxide substrate is prepared, including a silicon substrate 20 and a thermal oxide silicon layer 21 formed in sequence. Next, an etch stop layer 22 (silicon nitride, polysilicon, etc.) is prepared, and a patterning process such as photolithography and etching is performed to obtain a desired structure, which is used as an etch stop layer structure and protects the grooved area. By controlling the thickness of the etch stop layer and the spacing between the etch stop layer and the subsequent silicon nitride layer, the groove depth can be controlled to meet the design requirements and process deviations, such as Figure 8 shown.
[0060] Next, a silicon nitride waveguide structure and a chemical vapor deposition silicon oxide layer 25 are prepared, such as Fig. 9As shown, the silicon nitride waveguide structure includes a silicon-rich silicon nitride layer 23 and a silicon nitride layer 24 formed in sequence. Next, the chemical vapor deposited silicon oxide layer 25 is etched to the etching stop layer 22 to form a metal deposition groove 26. At this time, the depth of the etching groove can be controlled, such as Fig.10 Finally, the etching stop layer 22 is etched to completely remove the etching stop layer 22 to obtain the desired metal deposition groove 26, as shown in FIG. Fig.11 shown.
[0061] The embodiment of the present invention can effectively control the depth uniformity of the metal deposition groove, and provide a good flat surface for subsequent thin film deposition, etching and other processes; at the same time, by using this method to prepare deep grooves, the etching depth can be precisely controlled by controlling parameters such as the stop layer thickness and spacing.
[0062] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any changes or substitutions that can be easily thought of by a person skilled in the art within the technical scope disclosed in the present application should be included in the protection scope of the present application. Therefore, the protection scope of the present application shall be based on the protection scope of the claims.
Claims
1. A method for controlling the uniformity of etching groove depth, characterized in that: include: Forming an etch stop layer on a waveguide substrate, and patterning the etch stop layer to obtain a patterned etch stop layer structure; Forming a waveguide layer on the etch stop layer structure, and patterning the waveguide layer to obtain a patterned waveguide structure; Forming a first silicon oxide layer on the waveguide structure, so that the first silicon oxide layer completely covers the waveguide structure, the etch stop layer structure and the waveguide substrate; A metal deposition groove is prepared at a position on the first silicon oxide layer corresponding to the etch stop layer structure, and the bottom of the metal deposition groove is extended inward to the etch stop layer structure. The etch stop layer structure is removed to obtain the final metal deposition groove for forming a metal electrode.
2. The method for controlling the uniformity of etching groove depth according to claim 1, characterized in that: The waveguide layer includes a first waveguide layer and a second waveguide layer which are formed in sequence. The first waveguide layer is patterned to form a corresponding first waveguide structure, and the second waveguide layer is patterned to form a corresponding second waveguide structure.
3. The method for controlling the uniformity of etching groove depth according to claim 2, characterized in that: The first waveguide layer is a silicon-rich silicon nitride layer, and the second waveguide layer is a silicon nitride layer.
4. The method for controlling the uniformity of etching groove depth according to claim 2, characterized in that: The etching stop layer is made of any one of silicon nitride and polysilicon.
5. The method for controlling the uniformity of etching groove depth according to claim 1, characterized in that: The method further includes: preparing a waveguide layer on the waveguide substrate to use the waveguide layer as the etch stop layer, and patterning the waveguide layer to obtain the etch stop layer structure and the waveguide structure.
6. The method for controlling the uniformity of etching groove depth according to claim 1, characterized in that: The waveguide substrate comprises a silicon substrate and a second silicon oxide layer which are formed in sequence, and the etching stop layer is formed on the second silicon oxide layer.
7. The method for controlling the uniformity of etching groove depth according to claim 6, characterized in that: The first silicon oxide layer is prepared by chemical vapor deposition, and the second silicon oxide layer is prepared by thermal oxidation.
8. The method for controlling the uniformity of etching groove depth according to claim 1, characterized in that: The method further includes: before preparing a metal deposition groove at a position on the first silicon oxide layer corresponding to the etch stop layer structure, planarizing the surface of the first silicon oxide layer.
9. The method for controlling the uniformity of etching groove depth according to claim 1, characterized in that: The method further comprises: Depositing a metal electrode layer on a surface of the metal deposition groove and a surface of the first silicon oxide layer, so that the metal deposition groove and the first silicon oxide layer are covered by the metal electrode layer; A patterned photoresist layer is formed on the metal electrode layer in the metal deposition tank; the metal electrode layer is patterned using the photoresist layer as a mask, and then the photoresist layer is removed to form the metal electrode in the metal deposition tank.
10. The method for controlling the uniformity of etching groove depth according to claim 9, characterized in that: The thickness of the metal electrode does not exceed the depth of the metal deposition groove, and the top of the metal electrode is not higher than the top of the waveguide structure.