Simulation route tracking self-checking control method and system of radar seeker digital signal processor

Abstract

The invention discloses a simulation route tracking self-checking control method and system of a radar seeker digital signal processor. The digital signal processor mainly comprises an FPGA (Field Programmable Gate Array) and a DSP (Digital Signal Processor), the FPGA is connected with the servo, receives servo read-back data and sends the data to the DSP, the DSP processes the data and sends the data to the FPGA, and the FPGA controls the servo to move according to a DSP instruction. The tracking self-checking step comprises the following steps: presetting simulation route parameters; the radar seeker servo starts to move from an initial position; the backward reading frame angle and the servo angle of the preset track at the current time point are subtracted to obtain track angle deviation, and whether self-inspection fails or not is judged according to the deviation; the difference between the frame angle and the servo angle of the predetermined track at the next time point is obtained to obtain an error angle, and the error angle is divided by the control step length to obtain an error angular speed to control servo; and repeating the steps until the simulation route is finished.

Description

Technical Field

[0001] The invention belongs to the field of missile terminal guidance, and in particular relates to a simulation route tracking self-checking control method and system of a radar seeker digital signal processor. Background Art

[0002] The servo stabilization platform of the seeker is a precision mechanical electronic system, which is composed of many components. Traditional self-test methods, such as checking the motor, potentiometer, resolver, gyroscope, controller and other unit modules, cannot ensure that the servo platform system is normal. The tracking loop and stabilization loop of the platform cannot be checked by setting, so the self-test coverage is low. Summary of the invention

[0003] The object of the present invention is to provide a method and system for controlling the simulated route tracking self-check of a digital signal processor of a radar seeker, which can detect the tracking situation multiple times in the simulated route and can effectively perform self-check on the tracking mode of the seeker.

[0004] The technical scheme for realizing the purpose of the present invention is: a method for self-checking and controlling a simulated route tracking of a digital signal processor of a radar seeker, wherein the digital signal processor comprises an FPGA and a DSP, wherein the FPGA communicates with the servo via UART, the FPGA issues a control servo motion instruction, and receives frame angle information sent back by the servo; the DSP communicates with the FPGA via SRIO and GPIO, the FPGA sends the frame angle information fed back by the servo to the DSP via SRIO, and informs the DSP via GPIO that the sending is complete; the DSP processes and judges according to the pre-stored track information, and then issues the motion angular velocity of the next frame to the FPGA servo via SRIO; the tracking self-checking steps comprise: pre-setting simulation route parameters; the radar seeker servo starts to move from an initial position; reading back the frame angle and the servo angle at the current time point of the predetermined track to obtain the track angle deviation, and judging whether the self-checking is faulty according to the deviation; the frame angle and the servo angle at the next time point of the predetermined track to obtain the error angle, and dividing the error angle velocity by the control step length to control the servo; and repeating the above steps until the simulation route ends.

[0005] Furthermore, the simulation route tracking self-check control method specifically includes the following steps:

[0006] Step 1, pre-set the simulation path parameters, including: the starting position and speed of the seeker and the target, the simulation track movement time T, the seeker servo control cycle time Δt, the track sampling point number N, N = T / Δt, which is also the number of frames required for the tracking self-test; according to the above data, simulate the relative motion track of the two, and obtain the function θ(n) of the seeker servo azimuth and pitch angle position changing with time points, Store the two functions in DSP;

[0007] Step 2: The seeker servo angle starts to move from the starting position; DSP starts counting frames from 0;

[0008] Step 3: FPGA reads back the current pitch frame angle θ fed back by the servo through the UART port fb , azimuth frame angle Send these two frame corners to DSP through SRIO, and notify DSP to process through GPIO;

[0009] Step 4: Subtract the frame angle from the servo angle at the current time point of the predetermined track to obtain the aircraft angle deviation θ dif =θ(n)-θ fb , Determine whether the two deviation angles are less than a preset first threshold. If they are less than the first threshold, proceed to step 5. If they are greater than the first threshold, perform a self-check failure and exit directly.

[0010] Step 5: Subtract the frame angle from the servo angle at the next time point of the predetermined track to obtain an error angle Δθ=θ(n+1)-θ fb ,

[0011] Step 6: Divide the error angle by the control step length to obtain the error angular velocity ω = Δθ / Δt.

[0012] Step 7, DSP sends the error angular velocity to FPGA via SRIO, and FPGA controls the servo to move according to the error angular velocity via UART;

[0013] Step 8, repeat steps 3 to 7 until the DSP count reaches N, that is, the simulation track ends; FPGA reads the servo frame angle θ at this time fb and and the predetermined end position θ(N) and If the difference is less than the set second threshold, it means that the servo angle has reached the predetermined position and the self-test has passed; if it is greater than or equal to, it means that the servo angle has not reached the predetermined position and the self-test has failed.

[0014] Based on the same inventive concept, the present invention also provides a simulated route tracking self-checking control system of a radar seeker digital signal processor, which is used to implement the above method. The system includes a servo, an FPGA and a DSP. The FPGA communicates with the servo via UART, and the FPGA issues control servo motion instructions and receives frame angle information sent back by the servo. The DSP communicates with the FPGA via SRIO and GPIO. The FPGA sends the frame angle information fed back by the servo to the DSP via SRIO, and informs the DSP via GPIO that the sending is completed; the DSP processes and judges according to the pre-stored track information, and then sends the motion angular velocity of the next frame to the FPGA servo via SRIO.

[0015] A computer device comprises a memory, a processor and a computer program stored in the memory and executable on the processor, wherein the steps of the above method are implemented when the processor executes the program.

[0016] A computer-readable storage medium stores a computer program, which implements the steps of the above method when executed by a processor.

[0017] A computer program product comprises a computer program, which implements the steps of the above method when executed by a processor.

[0018] Compared with the prior art, the invention has the following beneficial effects: the invention uses a digital signal processor to perform a tracking self-check on the servo of a simulated route, and makes multiple judgments to determine the stability of the servo and the tracking mode of the radar seeker, with a higher self-check coverage and better effect. Moreover, the servo motion is similar to the servo motion in the actual working scene of the radar seeker, which is more practical. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 This is a flow chart of the simulation route tracking self-checking control method of the present invention.

[0020] Figure 2 The hardware structure diagram of the method of the present invention is shown in FIG. DETAILED DESCRIPTION

[0021] The present invention is further described in detail below in conjunction with the accompanying drawings.

[0022] See also Figure 2 , Figure 2 The hardware system block diagram of the present invention is a simulation route tracking self-checking control method of a radar seeker digital signal processor of the present invention, involving hardware including servo, FPGA and DSP. FPGA is responsible for controlling the servo and receiving servo feedback, and DSP is responsible for calculation and judgment.

[0023] The FPGA and servo communicate via UART. The FPGA sends the servo motion control instructions and receives the frame angle information sent back by the servo. The DSP and FPGA communicate via SRIO and GPIO. The FPGA sends the frame angle information fed back by the servo to the DSP via SRIO and informs the DSP via GPIO that the sending is completed. The DSP processes and judges the pre-stored track information and sends the motion angular velocity of the next frame to the FPGA servo via SRIO.

[0024] As a specific example, the FPGA chip model on the digital processor is XC7K480T, and the DSP chip model is TMS320C6678.

[0025] See also Figure 1, the self-test method is explained in detail with examples, and the specific steps are as follows:

[0026] Step 1, pre-set the simulation route parameters, for example: the initial straight-line distance between the missile and the target is 10km, the incident angle is 10°, and the missile altitude is 1.736km. At the beginning, the missile azimuth is facing the target, and the pitch angle is horizontal. The target moves at 40m / s along the normal line of the missile-target direction at sea level. The missile maintains an unchanged altitude, and the azimuth moves horizontally at a speed of 900m / s along the initial missile-target direction. The total simulation track motion time T is 5s, the seeker servo control cycle time Δt is 50ms, and the number of track sampling points N is 100. During this process, the radar seeker keeps tracking the target. According to the above data, the relative motion trajectory of the two is simulated, and the function of the seeker servo azimuth and pitch angle position changing with time can be obtained: Store the two functions in DSP;

[0027] Step 2: The seeker servo angle changes from the starting position θ(0) = 10°. Start the movement. DSP starts counting frames from 0;

[0028] Step 3: FPGA reads back the current pitch frame angle θ fed back by the servo through the UART port fb , azimuth frame angle Send these two frame corners to DSP through SRIO, and notify DSP to process through GPIO;

[0029] Step 4: Subtract the frame angle from the servo angle at the current time point of the predetermined track to obtain the aircraft angle deviation θ dif =θ(n)-θ fb , Determine whether the two deviation angles are less than a preset acceptable first threshold. If they are less than, proceed to step 5. If they are greater than, self-check for faults and exit directly.

[0030] Step 5: Subtract the frame angle from the servo angle at the next time point of the predetermined track to obtain an error angle Δθ=θ(n+1)-θ fb ,

[0031] Step 6: Divide the error angle by the control step length to obtain the error angular velocity ω = Δθ / Δt.

[0032] Step 7: DSP sends the error angular velocity to FPGA via SRIO, and FPGA controls the servo to move according to the error angular velocity via UART.

[0033] Step 8: Repeat steps 3 to 7 until the DSP count reaches N, which means the simulation track ends. FPGA reads the servo frame angle θ at this time. fb and and the predetermined end position θ(100) = 17.98° and If the difference is less than the set acceptable second threshold, it means that the servo angle has reached the predetermined position and the self-test has passed. If it is greater than or equal to, it means that the servo angle has not reached the predetermined position and the self-test has failed.

[0034] In summary, the present invention proposes a method for self-checking control of simulated route tracking of a radar seeker digital signal processor, which simulates the tracking mode of the radar seeker by presetting a simulated route, and performs self-checks on the servo and tracking stability of the radar seeker.

[0035] The above contents are further detailed descriptions of the present invention in combination with specific preferred embodiments, and it cannot be determined that the specific implementation of the present invention is limited to these descriptions. For ordinary technicians in the technical field of the present invention, several simple deductions or substitutions can be made without departing from the concept of the present invention, which should be regarded as falling within the scope of protection of the present invention.

Claims

1. A method for controlling the simulated route tracking self-check of a radar seeker digital signal processor, characterized in that: The digital signal processor includes FPGA and DSP. The FPGA and the servo communicate through UART. The FPGA issues control servo motion instructions and receives frame angle information sent back by the servo. The DSP and the FPGA communicate through SRIO and GPIO. The FPGA sends the frame angle information fed back by the servo to the DSP through SRIO and informs the DSP through GPIO that the sending is complete. DSP processes and judges the pre-stored track information and sends it to FPGA through SRIO to serve the angular velocity of the next frame; The tracking self-checking steps include: presetting simulation route parameters; The radar seeker servo starts to move from the initial position; the frame angle is read back and the servo angle at the current time point of the predetermined track is subtracted to obtain the track angle deviation, and the self-test is judged whether it is a fault according to the deviation size; the frame angle is subtracted from the servo angle at the next time point of the predetermined track to obtain the error angle, and the error angular velocity is obtained by dividing it with the control step size to control the servo; the above steps are repeated until the simulation route is completed.

2. The method for controlling the simulated route tracking self-check of the radar seeker digital signal processor according to claim 1, characterized in that: The method specifically comprises the following steps: Step 1, pre-set the simulation path parameters, including: the starting position and speed of the seeker and the target, the simulation track movement time T, the seeker servo control cycle time Δt, the track sampling point number N, N = T / Δt, which is also the number of frames required for the tracking self-test; according to the above data, simulate the relative motion track of the two, and obtain the function θ(n) of the seeker servo azimuth and pitch angle position changing with time points, Store the two functions in DSP; Step 2: The seeker servo angle starts to move from the starting position; DSP starts counting frames from 0; Step 3: FPGA reads back the current pitch frame angle θ fed back by the servo through the UART port fb , azimuth frame angle Send these two frame corners to DSP through SRIO, and notify DSP to process through GPIO; Step 4: Subtract the frame angle from the servo angle at the current time point of the predetermined track to obtain the aircraft angle deviation θ dif =θ(n)-θ fb , Determine whether the two deviation angles are less than a preset first threshold. If they are less than, proceed to step 5. If they are greater than or equal to, self-check failure and exit directly; Step 5: Subtract the frame angle from the servo angle at the next time point of the predetermined track to obtain an error angle Δθ=θ(n+1)-θ fb , Step 6: Divide the error angle by the control step length to obtain the error angular velocity ω0 = Δθ / Δt. Step 7, DSP sends the error angular velocity to FPGA via SRIO, and FPGA controls the servo to move according to the error angular velocity via UART; Step 8, repeat steps 3 to 7 until the DSP count reaches N, that is, the simulation track ends; FPGA reads the servo frame angle θ at this time fb and and the predetermined end position θ(N) and If the difference is less than the set second threshold, it means that the servo angle has reached the predetermined position and the self-test has passed; if it is greater than or equal to, it means that the servo angle has not reached the predetermined position and the self-test has failed.

3. A radar seeker digital signal processor simulation route tracking self-checking control system, characterized in that: The system is used to implement any of the methods described in claims 1 to 2, and includes a servo, an FPGA, and a DSP. The FPGA is responsible for controlling the servo and receiving servo feedback, and the DSP is responsible for calculation and judgment. The FPGA communicates with the servo via UART, and the FPGA issues control servo motion instructions and receives frame angle information sent back by the servo. The DSP communicates with the FPGA via SRIO and GPIO, and the FPGA sends the frame angle information fed back by the servo to the DSP via SRIO, and notifies the DSP via GPIO that the sending is complete. The DSP processes and judges based on the pre-stored track information, and then sends the motion angular velocity of the next frame to the FPGA servo via SRIO.

4. A computer device comprising a memory, a processor and a computer program stored in the memory and executable on the processor, characterized in that: When the processor executes the program, the steps of the method according to any one of claims 1 to 2 are implemented.

5. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the program is executed by a processor, the steps of the method described in any one of claims 1 to 2 are implemented.

6. A computer program product comprising a computer program, characterized in that When the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 2 are implemented.

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