Multi-channel audio vibration data processing method and system based on FPGA

Abstract

The invention discloses a multi-channel audio vibration data processing method and system based on an FPGA, and relates to the technical field of data processing. Comprising the following steps: collecting and preprocessing audio vibration signals; fPGA data vibration signal processing is carried out; and processing the vibration signal of the upper computer. The FPGA is adopted as a core control unit, accurate control over multi-channel ADC register configuration and the data acquisition process is achieved through the design of the finite-state machine, the synchronism and real-time performance of data acquisition are remarkably improved, and data loss and processing delay caused by resource conflicts are avoided. The adaptive wavelet filtering technology and the dynamic signal-to-noise ratio analysis method are combined, filtering parameters can be dynamically optimized according to signal characteristics, and efficient suppression of noise in a complex dynamic environment and high-fidelity reconstruction of signal details are achieved. An eight-channel parallel input architecture is adopted, the efficient parallel computing capacity of the FPGA is fully played, hardware resource allocation is optimized, the data processing efficiency is greatly improved, and the high expansibility and adaptability are achieved.

Description

Technical Field

[0001] The present invention relates to the technical field of data processing, and in particular to a multi-channel audio vibration data processing method and system based on FPGA. Background Art

[0002] With the increasing demand for high-quality signal processing and data acquisition in modern society, especially in the fields of industrial monitoring and environmental testing, the demand for efficient and reliable signal processing is becoming increasingly urgent. Traditional acquisition systems are insufficient in terms of synchronous acquisition, real-time processing and noise suppression, and are usually difficult to meet the needs of complex application scenarios. They are prone to data loss, delays and signal distortion, thus affecting the accurate analysis and evaluation of dynamic processes. In addition, the parallel acquisition of multi-channel signals is inefficient in the prior art, with serious resource conflicts, and the noise processing and high-fidelity reconstruction capabilities of the collected signals are also relatively limited. The present invention proposes a new solution from the perspectives of the synchronization of multi-channel acquisition, the accuracy of noise processing and the efficient use of hardware resources.

[0003] The Chinese patent publication number is "CN115542814A", and the name is "An intelligent detection system for industrial equipment". This technology transmits the signal to the main control circuit for reflected wave comparison analysis through the ultrasonic flaw detection circuit, acquisition circuit and vibration acquisition circuit, and finally stores the detected abnormal data in the storage circuit. Its advantage is that it can use multiple types of signals for analysis at the same time, and enhances the comprehensiveness of detection through the joint acquisition and comparative analysis of multiple signals. However, there are still deficiencies in multi-channel parallel acquisition efficiency, noise processing capabilities and hardware resource utilization, especially in complex dynamic environments. It is difficult to ensure the high quality and real-time performance of the signal. Summary of the invention

[0004] The technical solution of the present invention to solve the above technical problem is to provide a signal processing method based on an audio vibration sensor, comprising the following steps:

[0005] Step 1, audio vibration signal acquisition and preprocessing: collect external or vibration signals, remove noise and interference through adaptive wavelet filtering, and perform analog-to-digital conversion through ADC data acquisition;

[0006] Step 2, FPGA data vibration signal processing: Control the DDR storage unit through the FPGA main control unit to read and store data from the FIFO cache of multiple channels in a polling manner; Use the FIFO buffer to buffer the data rate to match the Ethernet transmission rate; Transmit the data in the DDR to the host computer through the Ethernet interface, where the MAC layer is responsible for frame encapsulation, address control, access control and error detection, and the PHY layer is responsible for signal modulation, encoding and clock recovery;

[0007] Step 3: Process the vibration signal on the host computer, save the data to files and arrays, and use MATLAB's signal processing algorithm to digitally restore the collected data and reconstruct the original signal.

[0008] Further, in step S1, the adaptive wavelet filtering includes:

[0009] Signal preprocessing: First input the signal The signal is collected by the audio vibration sensor and converted into a digital signal after low-noise amplification and anti-aliasing filtering. ;The preprocessed signal is sent to wavelet filtering;

[0010] Multiscale wavelet decomposition: Using filter banks to decompose signals Decompose layer by layer into low-frequency components and high-frequency components. The low-frequency components and high-frequency components are expressed as:

[0011] ;

[0012] ;

[0013] in, For low frequency components, through a low pass filter extract; For high frequency components, use a high pass filter Extraction; j is the number of decomposition layers, and This is achieved by using FIR filters, and filtering is accomplished using convolution;

[0014] Adaptive feature analysis: high-frequency components obtained from wavelet decomposition and low frequency components On this basis, the key characteristics of the signal are extracted through adaptive feature analysis, and the signal-to-noise ratio and noise standard deviation σ of the signal are calculated based on the high-frequency component to accurately estimate the noise level in the signal; the signal-to-noise ratio formula is:

[0015] ;

[0016] Utilize spectrum analysis technology to extract the amplitude distribution characteristics of high-frequency components, dynamically determine the number of decomposition layers based on signal bandwidth, and dynamically select the optimal wavelet basis. and the number of decomposition layers J; for scenes with more significant transient signals and high-frequency noise, select the Haar wavelet basis to capture the mutation characteristics; for stationary signals, select the Daubechies or Symlet wavelet basis to preserve the smoothness and trend of the signal;

[0017] At the same time, the dynamic threshold T used for threshold filtering is calculated, and the formula is:

[0018] ;

[0019] Among them, k is the adaptive adjustment coefficient, which can optimize the noise suppression effect for different scenes represents the standard deviation of noise, and N is the number of sample points. Through real-time dynamic analysis of high-frequency components, the threshold can be accurately adjusted according to the signal characteristics to achieve effective retention of detail information and significant suppression of noise.

[0020] Adaptive threshold denoising: Based on the results of dynamic feature analysis, adaptive threshold denoising is used to denoise high frequency components. Perform precise denoising to suppress noise to the maximum extent and retain signal detail characteristics; this is done by real-time calculation of the noise standard deviation σ and dynamic setting of the threshold , adaptively select denoising strategies based on different signal characteristics, including:

[0021] Hard threshold denoising:

[0022] ;

[0023] This method directly sets the high-frequency components that are less than the threshold to zero, which is suitable for high signal-to-noise ratio signals and effectively removes meaningless subtle interference;

[0024] Soft threshold denoising:

[0025] ;

[0026] This method retains more signal details by gradually reducing the amplitude of high-frequency components. It is suitable for low signal-to-noise ratio signals and can achieve a dynamic balance between noise suppression and detail preservation.

[0027] Inverse wavelet transform reconstruction: After completing high-frequency component denoising and low-frequency component retention, the inverse wavelet transform restores the signal through layer-by-layer iterative reconstruction. To ensure high fidelity and spectral integrity of the signal; through a low-pass filter and high pass filter The decomposition layers are restored step by step, and the reconstruction formula is:

[0028] ;

[0029] in, Represents the value of the reconstructed signal in the time domain, all decomposition layers The low frequency component And the high frequency components after denoising , respectively, through a low-pass filter and high pass filter After the convolution operation, the layers are stacked up to reconstruct the final signal layer by layer. ; The low-frequency component retains the overall trend information of the signal, while the high-frequency component supplements the detailed structure of the signal to form a high-quality signal in the full frequency band;

[0030] Multi-channel parallel processing: Build multiple channels, and each channel independently configures the full-process signal processing unit including wavelet decomposition, adaptive threshold calculation and reconstruction unit.

[0031] Furthermore, in step S1,

[0032] The ADC configures the registers and transmits data of ADS1256 through the SPI communication protocol, and configures the ADC and collects and reads data through the operation of the finite state machine. The various timing states of the finite state include: IDLE, PREPARE_C, WREG, SYNC, WAKEUP, WAIT1, RDATAC, MISO, WAIT2 and SDATAC states.

[0033] Furthermore, in step S2, the Ethernet interface includes a MAC controller and a PHY layer. The MAC controller is used for frame encapsulation, address control, access control and error detection of data; the PHY layer is used to convert the data frame from the MAC layer into an analog signal suitable for transmission through a physical medium, and to restore the received signal to digital data.

[0034] In order to solve the above technical problems, the invention further proposes a signal processing system based on an audio vibration sensor, which is used to execute the signal processing method based on the audio vibration sensor as described above, comprising:

[0035] The front-end data acquisition unit includes an audio vibration sensor, an adaptive wavelet filter module, an ADC data acquisition module and a FIFO buffer module. Its function is to collect external or vibration signals, then remove noise and interference through the adaptive wavelet filter module, then perform analog-to-digital conversion through the ADC data acquisition module, and finally temporarily store the processed digital signals in the FIFO buffer modules of each channel to wait for S2 arbitration to read them respectively;

[0036] The PGA data vibration signal processing unit includes a DDR storage module, a FIFO buffer module and an Ethernet data transmission module. Its function is to read and write the collected digital signal through the DDR storage module, match the speed and bit width through the FIFO buffer module, and finally transmit the data to the PC through the Ethernet communication module;

[0037] The vibration signal processing unit is a host computer module written in MATLAB. After the data is transmitted to the host computer, the data is saved in files and arrays. The collected data is digitally restored and the original signal is reconstructed through the signal processing algorithm of MATLAB.

[0038] Compared with the prior art, this application has the following beneficial effects:

[0039] 1. The present invention realizes the synchronous acquisition of eight-channel vibration signals. Compared with the traditional single-channel system, the present invention synchronously acquires signals at a high sampling rate, avoiding signal delay and data loss caused by channel switching. In addition, the multi-channel architecture adapts to the needs of complex scenarios, and simultaneously acquires and analyzes multi-source signals, which significantly improves work efficiency and data reliability, making the system more stable and responsive in a big data environment.

[0040] 2. The present invention designs an efficient multi-channel signal processing method based on adaptive wavelet filtering. By calculating each signal-to-noise ratio, spectrum distribution and noise level in real time, the optimal wavelet basis and decomposition layer are adaptively selected to achieve dynamic threshold denoising, thereby significantly improving noise suppression efficiency and signal fidelity. At the same time, combined with hardware resource optimization and wavelet filtering collaborative design, the system performance is greatly improved through on-chip resource allocation and real-time algorithm scheduling, ensuring data integrity and processing efficiency in complex dynamic scenes.

[0041] 3. The present invention designs a multi-channel ADC register configuration and data processing method based on a finite state machine (FSM), which realizes efficient configuration and real-time control of each ADC register through the state machine to ensure accurate synchronization of each channel acquisition task. Under the control of the finite state machine, the system can realize automatic management of various ADC operations (such as configuration commands, data reading and sampling triggering), avoid resource conflicts and delays caused by traditional serial configuration methods, and reduce idle waiting time through an efficient state switching mechanism, significantly improving the efficiency and stability of multi-channel data acquisition.

[0042] 4. The present invention is based on the Ethernet transmission protocol for data transmission. Compared with the traditional communication mode, it can meet the real-time transmission requirements of large-scale data. By supporting up to gigabit transmission bandwidth, the system can cope with complex multi-channel data acquisition tasks and improve the overall performance and reliability of the system. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on the structures shown in these drawings without paying creative work.

[0044] Figure 1 A flow chart of the steps of the signal processing method based on the audio vibration sensor of the present invention;

[0045] Figure 2 This is a workflow diagram of the adaptive wavelet filtering of the front-end data acquisition unit of the present invention;

[0046] Figure 3 It is the timing control diagram of the SPI communication protocol described in the present invention;

[0047] Figure 4 It is a finite state machine control flow chart of the front-end data acquisition unit ADC data acquisition module of the present invention;

[0048] Figure 5 It is a data packing structure diagram of the MAC layer in the Ethernet data transmission module of the FPGA data vibration signal processing unit of the present invention;

[0049] Figure 6 This is a hardware connection structure diagram of the Ethernet data transmission module of the FPGA data vibration signal processing unit of the present invention;

[0050] Figure 7 The present invention is a structural schematic diagram of a multi-channel signal acquisition system based on FPGA adaptive wavelet filtering.

[0051] Description of the accompanying drawings: 10, front-end data acquisition unit; 20, PGA data vibration signal processing unit 30, vibration signal processing unit. DETAILED DESCRIPTION

[0052] The present invention proposes a multi-channel audio vibration data processing method and system based on FPGA, aiming to design a signal processing method based on audio vibration sensor to solve the high synchronization and high real-time requirements of signal acquisition and processing in complex dynamic environments.

[0053] The multi-channel audio vibration data processing method based on FPGA proposed by the present invention will be described in the following specific embodiments:

[0054] Embodiment 1: A signal processing method based on an audio vibration sensor, such as Figure 1 As shown, the following steps are included:

[0055] Step 1, audio vibration signal acquisition and preprocessing: collect external or vibration signals, remove noise and interference through adaptive wavelet filtering, and perform analog-to-digital conversion through ADC data acquisition;

[0056] Step 2, FPGA data vibration signal processing: Control the DDR storage unit through the FPGA main control unit to read and store data from the FIFO cache of multiple channels in a polling manner; Use the FIFO buffer to buffer the data rate to match the Ethernet transmission rate; Transmit the data in the DDR to the host computer through the Ethernet interface, where the MAC layer is responsible for frame encapsulation, address control, access control and error detection, and the PHY layer is responsible for signal modulation, encoding and clock recovery;

[0057] Step 3: Process the vibration signal on the host computer, save the data to files and arrays, and use MATLAB's signal processing algorithm to digitally restore the collected data and reconstruct the original signal.

[0058] Furthermore, in step S1, if Figure 2 As shown, the adaptive wavelet filtering includes:

[0059] Step 11, signal preprocessing: First input the signal The signal is collected by the audio vibration sensor and converted into a digital signal after low-noise amplification and anti-aliasing filtering. ;The preprocessed signal is sent to wavelet filtering;

[0060] Step 12, multi-scale wavelet decomposition: use filter banks to decompose the signal Decompose layer by layer into low-frequency components and high-frequency components. The low-frequency components and high-frequency components are expressed as:

[0061] ;

[0062] ;

[0063] in, For low frequency components, through a low pass filter extract; For high frequency components, use a high pass filter Extraction; j is the number of decomposition layers, and This is achieved by using FIR filters, and filtering is accomplished using convolution;

[0064] Step 13, adaptive feature analysis: high-frequency components obtained from wavelet decomposition and low frequency components Based on the above, the key characteristics of the signal are extracted through adaptive feature analysis, and the signal-to-noise ratio (SNR) and noise standard deviation σ of the signal are calculated based on the high-frequency component to accurately estimate the noise level in the signal; the signal-to-noise ratio formula is:

[0065] ;

[0066] Utilize spectrum analysis technology to extract the amplitude distribution characteristics of high-frequency components, dynamically determine the number of decomposition layers based on signal bandwidth, and dynamically select the optimal wavelet basis. and the number of decomposition layers J; for scenes with more significant transient signals and high-frequency noise, select the Haar wavelet basis to capture the mutation characteristics; for stationary signals, select the Daubechies or Symlet wavelet basis to preserve the smoothness and trend of the signal;

[0067] At the same time, the dynamic threshold T used for threshold filtering is calculated, and the formula is:

[0068] ;

[0069] Among them, k is the adaptive adjustment coefficient, which can optimize the noise suppression effect for different scenes represents the standard deviation of noise, and N is the number of sample points. Through real-time dynamic analysis of high-frequency components, the threshold can be accurately adjusted according to the signal characteristics to achieve effective retention of detail information and significant suppression of noise.

[0070] Step 14, adaptive threshold denoising: Based on the results of dynamic feature analysis, adaptive threshold denoising is performed on high-frequency components. Perform precise denoising to suppress noise to the maximum extent and retain signal detail characteristics; this is done by real-time calculation of the noise standard deviation σ and dynamic setting of the threshold (where N is the number of signal sample points) and adaptively selects denoising strategies based on different signal characteristics, including:

[0071] Hard threshold denoising:

[0072] ;

[0073] This method directly sets the high-frequency components that are less than the threshold to zero, which is suitable for high signal-to-noise ratio signals and effectively removes meaningless subtle interference;

[0074] Soft threshold denoising:

[0075] ;

[0076] This method retains more signal details by gradually reducing the amplitude of high-frequency components. It is suitable for low signal-to-noise ratio signals and can achieve a dynamic balance between noise suppression and detail preservation.

[0077] Step 15, inverse wavelet transform reconstruction: After completing high-frequency component denoising and low-frequency component retention, the inverse wavelet transform restores the signal by iteratively reconstructing layer by layer. To ensure high fidelity and spectral integrity of the signal; through a low-pass filter and high pass filter The decomposition layers are restored step by step, and the reconstruction formula is:

[0078] ;

[0079] in, Represents the value of the reconstructed signal in the time domain, all decomposition layers The low frequency component And the high frequency components after denoising , respectively, through a low-pass filter and high pass filter After the convolution operation, the layers are stacked up to reconstruct the final signal layer by layer. The low-frequency component (after denoising) retains the overall trend information of the signal, while the high-frequency component supplements the detailed structure of the signal to form a high-quality signal in the full frequency band.

[0080] Step 16, multi-channel parallel processing: construct multiple channels, and each channel independently configures a full-process signal processing unit including wavelet decomposition, adaptive threshold calculation and reconstruction unit.

[0081] Specifically, channel independence and resource isolation: Each channel is independently configured with a full-process signal processing unit, including a wavelet decomposition module, an adaptive threshold calculation module, and a reconstruction unit, avoiding data conflicts and delay accumulation problems caused by shared resources in traditional designs. The on-chip BRAM (Block RAM) is divided into independent cache areas to provide isolated intermediate data storage space for each channel, ensuring that multi-channel data is independent of each other and does not interfere with each other in parallel processing. Hardware acceleration and dynamic scheduling: In the wavelet filter convolution calculation, the FPGA's DSP (Digital Signal Processing) module is fully utilized to achieve hardware acceleration and significantly reduce the operation delay. A dynamic task scheduling algorithm is introduced to dynamically allocate on-chip computing resources (such as DSP and BRAM) according to the spectral characteristics and signal-to-noise ratio of each channel signal, improve the efficiency of hardware resource utilization, and adapt to different signal characteristics. Multi-stage pipeline parallel architecture: The tasks such as wavelet decomposition, denoising, and reconstruction are divided into multiple sub-stages to build a multi-stage pipeline architecture. Tasks in each stage run independently in different clock cycles, fully tapping the parallel computing capabilities of the FPGA and improving throughput. The combination of horizontal parallel processing and vertical pipeline design enables real-time processing capabilities for high-density signal channels

[0082] Furthermore, in step S1, the ADC model is ADS1256, 24-bit data width, supports eight-channel data acquisition, and the registers of ADS1256 need to be configured through the SPI communication protocol, such as Figure 3 The following is a timing control diagram of the SPI communication protocol. The SPI communication protocol is used to configure registers and transmit data to the ADS1256. Figure 4The figure shows the finite state machine control flow chart of the ADC data acquisition module. The ADC is configured and data is collected and read through the operation of the finite state machine. The following are the various timing states of the finite state:

[0083] IDLE: The system enters the idle waiting state. After receiving the control command, it switches to the PREPARE_C state.

[0084] PREPARE_C: After drdy is pulled high in the current state, a register configuration command is sent to the ADC and the state jumps to the WREG state.

[0085] WREG: Transmit the WREG command on the DIN line. After sending the WREG command, send the SYNC command after 10 SCLKs.

[0086] SYNC: After sending the SYNC command, send the WAKEUP command after 10 SCLKs.

[0087] WAKEUP: After sending the WAKEUP command, the state jumps to the WAIT1 state, which is the DRDY high level state.

[0088] WAIT1: The RDATAC command is sent after DRDY is pulled low, so you need to wait for the DRDY signal to be pulled low before sending the RDATAC continuous read command.

[0089] RDATAC: Continuous read command, after the RDATAC command is transmitted to the DIN line through SCLK, the state jumps to MISO after 10 SCLK times, and the first 24-bit data returned is read.

[0090] MISO: Read the 24-bit value returned by ADC in the current state. Each subsequent receipt needs to wait for drdy to be pulled low before reading. So when the 24-bit data is read, enter the WAIT2 state and wait for drdy to be pulled low again.

[0091] WAIT2: When the continuous read function is in progress, every time the drdy signal generates a falling edge, it returns to the MISO state to read the returned data. However, after the serial port sends a stop continuous read command, the state jumps to the SDATAC state when the next drdy signal generates a falling edge.

[0092] SDATAC: Send the stop continuous reading command to end the ADC operation. After sending, the state jumps to the idle state.

[0093] After detecting that the ADC data is ready, it automatically enters the continuous acquisition state, reads 24-bit data through the SPI interface and stores it in the FIFO buffer. The ideal relationship between the 24-bit value and the full-scale input voltage is The default value of PGA is 1, where The ideal voltage is 2.5V, and 7FFFFF corresponds to a full-scale voltage of 5V. So the minimum output bit weight is , the measured voltage is obtained by multiplying the output 24-bit value by the weight, and finally stored in the FIFO of the corresponding channel.

[0094] Furthermore, in step S2, the Ethernet interface includes a MAC controller and a PHY layer. The MAC controller is used for frame encapsulation, address control, access control and error detection of data; the PHY layer is used to convert the data frame from the MAC layer into an analog signal suitable for transmission through a physical medium, and to restore the received signal to digital data.

[0095] Specifically, in the DDR storage module, first, in the FIFO data preparation stage, each FIFO is responsible for storing the collected data of a channel. When the collected data from S1 stored in the FIFO reaches a certain amount, the non-empty signal will be pulled high to notify the DDR controller that the data is ready for reading. Subsequently, the DDR controller starts data request and arbitration, sending read requests to the 8 FIFOs in turn. In a multi-channel system, the DDR controller performs data arbitration on the 8 FIFOs in a polling manner to determine which FIFO should currently read data from, so as to ensure the stability and effectiveness of data reading.

[0096] The DDR controller reads the data block from the selected FIFO, and the data is output from the FIFO and transmitted to the DDR controller through the data bus. The read data will be written to the corresponding storage address of the DDR through the address and control logic of the DDR controller. To ensure that the data of the 8 channels will not be confused, the DDR controller allocates different memory areas for each channel, so that the data of each channel is stored independently and orderly in the DDR, which is convenient for subsequent reading and processing.

[0097] In the process of data from the DDR storage module to the Ethernet data transmission module, the data needs to be rate buffered by the FIFO buffer module in S2 to smoothly transition the high-bandwidth DDR output to match the Ethernet transmission rate and prevent data loss and overload. Secondly, FIFO also has the function of matching the data bit width, dividing the bit width of the transmitted data into a granularity suitable for Ethernet interface processing, thereby ensuring that the transmission of each data packet meets the technical requirements of the interface.

[0098] Ethernet data transmission, where the Ethernet interface is mainly composed of two parts: MAC (Media Access Control) controller and physical layer interface PHY (Physical Layer, PHY).

[0099] MAC controller (Media Access Control Layer): The MAC layer belongs to the data link layer of the OSI model and is mainly responsible for data frame encapsulation, address control, access control and error detection. The data packaging format is as follows Figure 7 The structure of the Ethernet MAC frame includes multiple key fields, each of which has a fixed length (in bytes), thus ensuring the standardization of the frame format. Figure 5 As shown:

[0100] Preamble: It consists of 7 bytes, usually a repeating sequence of 01010101. The function of the preamble is to enable the receiving end to synchronize the clock signal and ensure that the receiver can correctly decode the subsequent data.

[0101] Frame start character: 0xD5, used to indicate that the next byte starts with the destination MAC address field. It marks the official start of the MAC frame and helps the receiving device confirm the starting point of the data frame.

[0102] Destination MAC address: The receiver address of the data frame, including the MAC address of the receiving network interface card (NIC). The MAC address is a physical address that uniquely identifies a network device. It consists of 6 bytes and is used to determine to which device the data frame should be transmitted.

[0103] Source MAC address: Contains the MAC address of the sender, used to identify the device sending data. It consists of 6 bytes to ensure the uniqueness of each device in the network.

[0104] Length / Type: Indicates the length of the data field (if the value is less than 1500), and is also used to indicate the type of data (if the value is greater than 1500, for example, 0x0800 indicates IPv4, 0x0806 indicates ARP). It helps to distinguish different upper-layer protocols or applications.

[0105] Data and padding: The data field contains the actual transmitted data (such as TCP / IP data packets), and its length ranges from 46 to 1500 bytes. The Ethernet standard stipulates that the minimum frame length is 64 bytes, so if the data part is less than 46 bytes, padding is required to ensure the minimum length of the frame. The padding data has no practical significance, but is only used to meet the specified minimum length requirements.

[0106] Frame Check Sequence: 4 bytes, this field is used to check the integrity of the frame. It contains the CRC (Cyclic Redundancy Check) value calculated by the sending device, which the receiving device uses to check whether errors occurred during the transmission of the frame. If an error is detected, the frame is discarded and a retransmission is requested.

[0107] PHY layer (physical layer): The PHY layer belongs to the physical layer of the OSI model, which is responsible for converting the data frames from the MAC layer into analog signals suitable for transmission through physical media (such as cables and optical fibers), and restoring the received signals to digital data. The PHY layer involves signal modulation, coding, clock recovery, etc., to ensure that the signal can be transmitted stably in the physical medium and provide the transmission rate required by the data link.

[0108] In step 2, the Ethernet data transmission module hardware connection structure diagram is as follows Figure 6 As shown, first read the data in the DDR storage module in S2, and enter the MAC layer (media access control layer) of Ethernet through the FIFO buffer module in S2. The MAC layer is mainly responsible for frame encapsulation of digital signals, adding necessary information such as source address, destination address and frame check sequence to ensure the correct transmission of data frames in Ethernet. The frame encapsulation process includes adding Ethernet headers and tails to the data, which contain necessary control information to ensure that each data packet can be accurately transmitted to the target device. The MAC layer is also responsible for controlling media access, using the CSMA / CD (Carrier Sense Multiple Access / Collision Detection) mechanism to avoid conflicts and ensure that data can be effectively transmitted through the shared communication medium. In addition, the MAC layer also performs error detection (such as CRC check) and flow control to improve the reliability and efficiency of data transmission.

[0109] The encapsulated data is passed to the PHY module (physical layer), which communicates with the MAC layer through GMII (Gigabit Media Independent Interface) or RGMII (Reduced Gigabit Media Independent Interface). The PHY module converts the data frame of the MAC layer into an analog signal suitable for physical transmission, including modulation and coding of the signal. First, the PHY module performs encoding operations, such as 4B / 5B or 8B / 10B encoding, to improve the transmission efficiency and anti-interference ability of the signal. Then, the PHY module converts the digital signal into an analog signal and adapts it to the transmission requirements of the physical medium through modulation technology. The task of the PHY layer is to ensure that the signal is transmitted with high anti-interference ability in a complex physical environment, maintaining a low bit error rate and signal stability, which is particularly important for data transmission in an industrial environment.

[0110] The signal processed by the PHY module is connected to the standard Ethernet cable through the RJ45 interface. As a standard physical layer connector, the RJ45 interface ensures that the signal can reliably enter the transmission medium, while the Ethernet cable effectively reduces the impact of common mode noise through differential signal transmission. In addition, the shielding layer of the cable provides additional protection, further reducing the signal attenuation and bit error rate caused by external electromagnetic interference. Ensure that the signal can be stably and reliably transmitted to the host computer in S3.

[0111] In step 3, when the signal is transmitted to the host computer (PC end) via Ethernet, the network interface of the host computer first receives the Ethernet data frame transmitted through the PHY module and the RJ45 interface. After the host computer receives the data, it first splices the data according to 24 bits, and the data of each channel is stored in the array in turn according to the timestamp and channel identifier, which is used to save it as a file in mat format. Then, the data of each channel is normalized, and the converted analog signal is oscillated around 1.45V with 1.45V as the mean voltage. After normalization, the collected signals are restored respectively according to the timestamp using MATLAB tools, and data visualization operations such as spectrum analysis and feature extraction are performed on the data. The whole process continues until the set number of acquisitions is reached. After the acquisition is completed, the host computer sends a command to stop the acquisition through the serial port, and the FPGA stops data acquisition and puts the system in standby mode. Subsequently, the host computer closes the serial port and releases resources.

[0112] The purpose of normalization is to eliminate the DC offset of the signal and make the data more suitable for subsequent analysis and processing. The received data is not only stored in the local array, but also plotted in real time in MATLAB so that users can intuitively observe the collected data of each channel, especially when debugging and verifying system behavior, users can intuitively understand the dynamic changes of the signal through these graphical representations.

[0113] After the data collection is completed and saved as a MAT file, the host computer further processes and analyzes the collected data through MATLAB code. First, MATLAB loads the previously saved The file contains the collected vibration signal data. Since the output signal of the vibration sensor in S1 fluctuates around 1.45V, the collected data is normalized and adjusted to a signal varying between -1 and +1, that is, , which can effectively remove the DC offset and make the signal fluctuate around zero mean. Finally, by Function playback (here is the sampling frequency The vibration signal normalized by σ is the collected data bit width to simulate the collected vibration sound wave.

[0114] Embodiment 2: A signal processing system based on an audio vibration sensor, used to execute the signal processing method based on an audio vibration sensor as described in Embodiment 1, the system structure is as follows Figure 7 As shown, including:

[0115] The front-end data acquisition unit 10 includes an audio vibration sensor, an adaptive wavelet filter module, an ADC data acquisition module and a FIFO buffer module, and its function is to collect external or vibration signals, then remove noise and interference through the adaptive wavelet filter module, then perform analog-to-digital conversion through the ADC data acquisition module, and finally temporarily store the processed digital signals in the FIFO buffer modules of each channel to wait for S2 arbitration to read them respectively;

[0116] The PGA data vibration signal processing unit 20 includes a DDR storage module, a FIFO buffer module and an Ethernet data transmission module. Its function is to read and write the collected digital signal through the DDR storage module, match the speed and bit width through the FIFO buffer module, and finally transmit the data to the PC end through the Ethernet communication module;

[0117] The vibration signal processing unit 30 is a host computer module written based on MATLAB. After the data is transmitted to the host computer, the data is saved in files and arrays, and the collected data is digitally restored through the signal processing algorithm of MATLAB to reconstruct the original signal.

[0118] The above is only a preferred specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily thought of by a person skilled in the art within the technical scope disclosed by the present invention should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention should be based on the protection scope of the claims.

Claims

1. A signal processing method based on an audio vibration sensor, characterized in that: The following steps are involved: Step 1, audio vibration signal acquisition and preprocessing: collect external or vibration signals, remove noise and interference through adaptive wavelet filtering, and perform analog-to-digital conversion through ADC data acquisition; Step 2, FPGA data vibration signal processing: the DDR storage unit is controlled by the FPGA main control unit to read and store data from the FIFO buffer of multiple channels in a polling manner; the data is rate buffered using the FIFO buffer to match the Ethernet transmission rate; The data in DDR is transmitted to the host computer through the Ethernet interface, where the MAC layer is responsible for frame encapsulation, address control, access control and error detection, and the PHY layer is responsible for signal modulation, encoding and clock recovery; Step 3: Process the vibration signal on the host computer, save the data to files and arrays, and use MATLAB's signal processing algorithm to digitally restore the collected data and reconstruct the original signal.

2. The signal processing method based on the audio vibration sensor according to claim 1, characterized in that: In step S1, the adaptive wavelet filtering includes: Signal preprocessing: First input the signal The signal is collected by audio vibration sensor and converted into digital signal after low noise amplification and anti-aliasing filtering. ;The preprocessed signal is sent to wavelet filtering; Multiscale wavelet decomposition: Using filter banks to decompose signals Decompose layer by layer into low-frequency components and high-frequency components. The low-frequency components and high-frequency components are expressed as: ； ； in, For low frequency components, through a low pass filter extract; For high frequency components, use a high pass filter Extraction; j is the number of decomposition layers, and This is achieved by using FIR filters, and filtering is done using convolution; Adaptive feature analysis: high-frequency components obtained from wavelet decomposition and low frequency components On this basis, the key characteristics of the signal are extracted through adaptive feature analysis, and the signal-to-noise ratio and noise standard deviation σ of the signal are calculated based on the high-frequency component to accurately estimate the noise level in the signal; the signal-to-noise ratio formula is: ； Utilize spectrum analysis technology to extract the amplitude distribution characteristics of high-frequency components, dynamically determine the number of decomposition layers based on signal bandwidth, and dynamically select the optimal wavelet basis. and the number of decomposition layers J; for scenes with more significant transient signals and high-frequency noise, select the Haar wavelet basis to capture the mutation characteristics; for stationary signals, select the Daubechies or Symlet wavelet basis to preserve the smoothness and trend of the signal; At the same time, the dynamic threshold T used for threshold filtering is calculated, and the formula is: ； Among them, k is the adaptive adjustment coefficient, which can optimize the noise suppression effect for different scenes represents the standard deviation of noise, and N is the number of sample points. Through real-time dynamic analysis of high-frequency components, the threshold can be accurately adjusted according to the signal characteristics to achieve effective retention of detail information and significant suppression of noise. Adaptive threshold denoising: Based on the results of dynamic feature analysis, adaptive threshold denoising is used to denoise high frequency components. Perform precise denoising to suppress noise to the maximum extent and retain signal detail characteristics; this is done by real-time calculation of the noise standard deviation σ and dynamic setting of the threshold , adaptively select denoising strategies based on different signal characteristics, including: Hard threshold denoising: ； Directly set the high-frequency components less than the threshold to zero; Soft threshold denoising: ； More signal details are retained by gradually reducing the amplitude of high-frequency components; Inverse wavelet transform reconstruction: After completing high-frequency component denoising and low-frequency component retention, the inverse wavelet transform restores the signal through layer-by-layer iterative reconstruction. , used to ensure high fidelity and spectral integrity of the signal; through a low-pass filter and high pass filter The decomposition layers are restored step by step, and the reconstruction formula is: ； in, Represents the value of the reconstructed signal in the time domain, all decomposition layers The low frequency component And the high frequency components after denoising , respectively, through a low-pass filter and high pass filter After convolution operation, the layers are stacked up to reconstruct the final signal layer by layer. ; The low-frequency component retains the overall trend information of the signal, while the high-frequency component supplements the detailed structure of the signal to form a high-quality signal in the full frequency band; Multi-channel parallel processing: Build multiple channels, and each channel independently configures the full-process signal processing unit including wavelet decomposition, adaptive threshold calculation and reconstruction unit.

3. The signal processing method based on the audio vibration sensor according to claim 1, characterized in that: In step S1, The ADC configures the registers and transmits data of ADS1256 through the SPI communication protocol, and configures the ADC and collects and reads data through the operation of the finite state machine. The various timing states of the finite state include: IDLE, PREPARE_C, WREG, SYNC, WAKEUP, WAIT1, RDATAC, MISO, WAIT2 and SDATAC states.

4. The signal processing method based on the audio vibration sensor according to claim 1, characterized in that: In step S2, the Ethernet interface includes a MAC controller and a PHY layer. The MAC controller is used for data frame encapsulation, address control, access control, and error detection; the PHY layer is used to convert the data frames from the MAC layer into analog signals suitable for transmission through physical media, and to restore the received signals to digital data.

5. A signal processing system based on an audio vibration sensor, used to execute the signal processing method based on an audio vibration sensor as claimed in any one of claims 1 to 4, characterized in that: include: The front-end data acquisition unit includes an audio vibration sensor, an adaptive wavelet filter module, an ADC data acquisition module and a FIFO buffer module. Its function is to collect external or vibration signals, then remove noise and interference through the adaptive wavelet filter module, then perform analog-to-digital conversion through the ADC data acquisition module, and finally temporarily store the processed digital signals in the FIFO buffer modules of each channel to wait for S2 arbitration to read them respectively; The PGA data vibration signal processing unit includes a DDR storage module, a FIFO buffer module and an Ethernet data transmission module. Its function is to read and write the collected digital signal through the DDR storage module, match the speed and bit width through the FIFO buffer module, and finally transmit the data to the PC through the Ethernet communication module; The vibration signal processing unit is a host computer module written in MATLAB. After the data is transmitted to the host computer, the data is saved in files and arrays. The collected data is digitally restored and the original signal is reconstructed through the signal processing algorithm of MATLAB.

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