Scheduling method and device, semiconductor process equipment and computer readable storage medium

Abstract

The embodiment of the invention provides a scheduling method and device, semiconductor process equipment and a storage medium, and the scheduling method comprises the steps: obtaining a plurality of first alternative sequences through traversing a next target module of a target wafer in a current state when the target wafer is located on a first manipulator; in this way, the first alternative sequence is obtained by traversing the next target module of the target wafer, and the problem that the algorithm solving scale is too large is avoided. In addition, the first alternative sequence comprises a step of putting the target wafer into the next target module, and an inserted step of taking out the wafer violating the residence time constraint before the target wafer is put into the next target module and under the condition that the wafer violating the residence time constraint exists in other target modules, so that the wafer violating the residence time constraint is taken out. The problem that other wafers may violate the residence time constraint due to operation of the target wafer can be avoided, and the adverse effect of other wafers on the wafer due to violation of the residence time constraint can be avoided or reduced.

Description

Technical Field

[0001] The present specification relates to the field of semiconductor technology, specifically, to equipment scheduling technology in the field of semiconductor technology, and more specifically, to a scheduling method, device, semiconductor process equipment, and computer-readable storage medium. Background Art

[0002] Cluster Tool is a kind of equipment widely used in semiconductor wafer manufacturing. Cluster Tool can include modules such as Aligner, Robot, LoadLock, LoadPort and multiple process chambers. Cluster Tool can realize automatic processing and circulation of wafers.

[0003] When using cluster equipment to process wafers, in order to improve equipment utilization efficiency, usually multiple wafers need to be circulated or processed in each module, which puts high demands on the scheduling of the robot. The current scheduling method usually has complex logic and a long solution time. It is necessary to propose a scheduling method with simple logic. Summary of the invention

[0004] The embodiments of this specification provide a scheduling method, an apparatus, a semiconductor process equipment, and a computer-readable storage medium to achieve the purpose of providing a scheduling method with simple logic, fast solution, and no violation of the mainstream time constraints of the wafer.

[0005] To achieve the above technical objectives, the embodiments of this specification provide the following technical solutions:

[0006] In a first aspect, an embodiment of the present specification provides a scheduling method for generating a scheduling sequence, wherein the scheduling sequence is used to control a first robot in a semiconductor process equipment, wherein the first robot is used to schedule wafers between target modules, wherein the target module includes a processing module of the semiconductor process equipment or a wafer slot of a vacuum lock, wherein the scheduling method includes:

[0007] Determining a target wafer, the target wafer comprising: a movable wafer in the semiconductor process equipment in a current state;

[0008] If the target wafer is located on the first robot in the current state, the next target module of the target wafer is traversed to obtain multiple first alternative sequences; the next target module includes a target module for executing the next process of the target wafer; the first alternative sequence includes: a step of placing the target wafer into the next target module, and if there is a wafer violating the residence time constraint in other target modules, the first alternative sequence also includes: before placing the target wafer into the next target module, inserting a step of taking out the wafer violating the residence time constraint;

[0009] The scheduling sequence is determined among a plurality of candidate sequences; the plurality of candidate sequences include a plurality of the first candidate sequences.

[0010] In a second aspect, an embodiment of the present specification provides a scheduling device for generating a scheduling sequence, characterized by comprising: a processor and a memory;

[0011] Wherein, the memory is connected to the processor, and the memory is used to store a computer program;

[0012] The processor is used to implement any of the scheduling methods described above by running the computer program stored in the memory.

[0013] In a third aspect, an embodiment of the present specification provides a scheduling device for generating a scheduling sequence, wherein the scheduling sequence is used to control a first robot in a semiconductor process equipment, wherein the first robot is used to schedule wafers between target modules, wherein the target module includes a processing module of the semiconductor process equipment or a wafer slot of a vacuum lock, wherein the scheduling device includes:

[0014] A state acquisition module, used to determine a target wafer, the target wafer comprising: a movable wafer in the semiconductor process equipment in a current state;

[0015] A first generating module is used for, if in a current state, the target wafer is located on the first robot, traversing the next target module of the target wafer to obtain a plurality of first candidate sequences; the next target module includes a target module for executing a next process of the target wafer; the first candidate sequence includes: a step of placing the target wafer into the next target module, and if there is a wafer violating the residence time constraint in other target modules, the first candidate sequence also includes: before placing the target wafer into the next target module, inserting a step of taking out the wafer violating the residence time constraint;

[0016] The sequence evaluation module is used to determine the scheduling sequence among multiple candidate sequences.

[0017] In a fourth aspect, an embodiment of the present specification provides a semiconductor process equipment, comprising: a first robot, a control module and a plurality of target modules; the target module comprises a wafer slot of a processing module or a vacuum lock;

[0018] The control module is used to generate a scheduling sequence according to any of the scheduling methods described above, and control the first robot to schedule the wafer between the multiple target modules according to the scheduling sequence.

[0019] In a fifth aspect, an embodiment of the present specification provides a semiconductor process scheduling device for generating a scheduling sequence, including: a processor and a memory;

[0020] Wherein, the memory is connected to the processor, and the memory is used to store a computer program;

[0021] The processor is used to implement any of the scheduling methods described above by running the computer program stored in the memory.

[0022] In a sixth aspect, an embodiment of this specification provides an electronic device, including: a processor and a memory;

[0023] Wherein, the memory is connected to the processor, and the memory is used to store a computer program;

[0024] The processor is used to implement the above-mentioned scheduling method by running the computer program stored in the memory.

[0025] In a seventh aspect, an embodiment of the present specification provides a computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, the scheduling method as described above is implemented.

[0026] In an eighth aspect, an embodiment of the present specification provides a computer program product or a computer program, wherein the computer program product includes a computer program, and the computer program is stored in a computer-readable storage medium; the processor of the computer device reads the computer program from the computer-readable storage medium, and the processor implements the steps of the above-mentioned scheduling method when executing the computer program.

[0027] It can be seen from the above technical solution that in the scheduling method provided in the embodiment of this specification, when the target wafer is located on the first robot in the current state, multiple first alternative sequences are obtained by traversing the next target module of the target wafer; in this way, the first alternative sequence is obtained by traversing the next target module of the target wafer, which can greatly reduce the length of the process path required to be searched during the traversal process, and reduce the scale of the process branches required to be searched during the traversal process, thereby avoiding the problem of excessive algorithm solution scale due to the long process path length when solving multi-wafer scheduling problems.

[0028] In addition, the first alternative sequence includes: the step of placing the target wafer into the next target module, and if there are wafers violating the residence time constraint in other target modules, the first alternative sequence also includes: before placing the target wafer into the next target module, the step of removing the wafer violating the residence time constraint is inserted. In this way, the problem of other wafers violating the residence time constraint due to operating the target wafer can be avoided, or the problem of further increasing the residence time of wafers violating the residence time constraint in other target modules due to operating the target wafer can be avoided, thereby avoiding or reducing the adverse effects of other wafers on the wafer due to violating the residence time constraint. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] In order to more clearly illustrate the embodiments of this specification or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of this specification. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without paying creative work.

[0030] Figure 1 A schematic diagram of the structure of a semiconductor process equipment provided for one embodiment of the present specification;

[0031] Figure 2 A flowchart of a scheduling method provided for one embodiment of this specification;

[0032] Figure 3 A flowchart of another scheduling method provided for one embodiment of this specification;

[0033] Figure 4 A flowchart of a method for determining a scheduling sequence provided for one embodiment of this specification;

[0034] Figure 5 A schematic diagram of a scheduling sequence determination process provided for one embodiment of this specification;

[0035] Figure 6 A schematic diagram of another scheduling sequence determination process provided for one embodiment of this specification;

[0036] Figure 7 A schematic diagram of the structure of a scheduling device provided for one embodiment of this specification;

[0037] Figure 8 A schematic diagram of the structure of another semiconductor process equipment provided for one embodiment of the present specification;

[0038] Fig. 9 A schematic diagram of the structure of an electronic device provided for one embodiment of the present specification. DETAILED DESCRIPTION

[0039] Unless otherwise defined, the technical terms or scientific terms used in the embodiments of this specification shall have the common meanings understood by persons with ordinary skills in the field to which this specification belongs. The words "first", "second" and similar words used in the embodiments of this specification do not indicate any order, quantity or importance, but are only used to avoid confusion of constituent elements.

[0040] Unless the context requires otherwise, throughout the specification, "plurality" means "at least two", and "including" is interpreted as an open, inclusive meaning, that is, "including, but not limited to". In the description of the specification, the terms "one embodiment", "some embodiments", "exemplary embodiments", "examples", "specific examples" or "some examples" are intended to indicate that a particular feature, structure, material or characteristic associated with the embodiment or example is included in at least one embodiment or example of the specification. The schematic representation of the above terms does not necessarily refer to the same embodiment or example.

[0041] The following will be combined with the drawings in the embodiments of this specification to clearly and completely describe the technical solutions in the embodiments of this specification. Obviously, the described embodiments are only part of the embodiments of this specification, not all of the embodiments. Based on the embodiments in this specification, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this specification.

[0042] Overview

[0043] refer to Figure 1 , still taking the cluster type equipment as an example, a schematic diagram of the structure of the semiconductor process equipment is shown, the semiconductor process equipment may include a first robot 10, a second robot 20, a vacuum lock 30, a wafer loading and unloading position 21, a calibration module 22 and a plurality of processing modules 11; wherein,

[0044] Each wafer loading and unloading position 21 can hold a wafer box, and each wafer box can hold multiple wafers.

[0045] The calibration module 22 may include a slot, and the calibration module 22 may calibrate the wafer placed in the slot.

[0046] The second robot 20 may be a single-arm robot. The second robot may have a slot on which a wafer may be placed. The second robot is responsible for transporting the wafer between the wafer loading and unloading position 21 , the comparison module 22 and the vacuum lock 30 .

[0047] Processing module 11 (Processing Module), each processing module 11 has a slot, which can place a wafer for processing.

[0048] There are two slots on the vacuum lock 30 (LoadLock) ( Figure 1 For convenience, two slots are used to represent it (left and right), each slot can hold a wafer, and the vacuum lock 30 can switch between the atmospheric state and the vacuum state. When the vacuum lock 30 is converted to the atmospheric state, the wafer located on the second robot side can be sent into the vacuum lock 30; when the vacuum lock 30 is converted to the vacuum state, the wafer located on the first robot side can be sent into the vacuum lock 30.

[0049] The first robot 10 can be a double-arm robot. The two arms of the double-arm robot can be 180° and fixed. Each arm has a slot, and each slot can hold a wafer. Generally, the two arms cannot perform wafer picking and placing operations at the same time; the first robot 10 is responsible for transporting wafers between the vacuum lock 30 and multiple process modules 11.

[0050] The processing path and process time of the wafer are generally specified by the process personnel according to the wafer process requirements, and are usually flexibly changed. For example: wafer loading and unloading position 21->second robot 20->calibration module 22->second robot 20->vacuum lock 30->first robot 10->first process module 11->first robot 10->second process module 11->first robot 10->third process module 11->first robot 10->fourth process module 11->first robot 10->vacuum lock 30->second robot 20->wafer loading and unloading position 21, wherein each step consumes time, and the wafer can be processed in parallel or serially between the process modules 11. The process personnel can set strict residence time constraints in each process module 11 (such as the residence time of the first process module 11 must be less than or equal to 30 seconds). If the residence time of the wafer after processing in the process module 11 exceeds the residence time constraint, the residual gas or temperature in the process module 11 may have an adverse effect on the wafer.

[0051] Since the scheduling module of wafers from the wafer loading and unloading position 21 to the vacuum lock 30 and from the vacuum lock 30 to the wafer loading and unloading position 21 does not involve the problem of residence time constraint, and the scheduling logic is relatively simple (it can be satisfied by common rules, such as when the first robot 10 takes the wafer on the vacuum lock 30 and puts it into the process module 11 for processing, the second robot 20 can take a wafer from the wafer loading and unloading position 21 and put it into the vacuum lock 30, ensuring that there are wafers to be processed in the vacuum lock 30 at all times; when the first robot 10 puts the processed wafer into the vacuum lock 30, the second robot 20 should take it away as soon as possible and put it back into the wafer loading and unloading position 21.

[0052] Therefore, current scheduling methods for semiconductor process equipment mostly focus on the scheduling of the first robot.

[0053] The inventor found through research that due to the time fluctuations required for each action of the robot, the chamber cleaning of the process module 11 and other factors, it will be difficult to form a stable periodic scheduling scenario, that is, it is difficult to control the robot action in a periodic scheduling manner. The specific reasons include: periodic scheduling belongs to static scheduling, which means forming an optimized scheduling method under the premise of known equipment status and processing tasks. The scheduling scheme is to generate a periodic robot activity sequence. For example, at time t0, the robot activity sequence with a period of T is solved as t1, t2, t3, .., tn; then at t0+T, the system state is the same as t0, T is the basic period, and the subsequent actions are t1+T, t2+T, t3+T, ... tn+T; at t0+T+T, the system state is the same as t0, and the subsequent actions are t1+2T, t2+2T, t3+2T, ... tn+2T, and so on. Once the scheduling scheme is generated, the processing scheme and robot activity sequence of all wafers are determined, and will not change in the subsequent processing process. However, as mentioned above, due to time fluctuations when the robot performs certain actions or factors such as chamber cleaning, the system state at t0+T and t0+T+T may be different from the system state at t0, causing the robot activity sequence with a period of T to no longer apply.

[0054] Further research has found that the scheduling problem for multiple wafers can be solved as an NP-Hard (Nondeterministic Polynomial) problem. The scale of solving NP-Hard problems increases exponentially with the increase in the number of wafers and the length of the process path.

[0055] The inventors have found that this problem can be solved by mathematical programming algorithms or branch-and-bound methods. The mathematical programming algorithm needs to take the possible action sequence and action occurrence time of the manipulator as variables, establish a mixed integer programming model with action execution time constraints, residence time constraints, wafer process path constraints, etc., and use a solver to solve. Due to the large number of variables, the solution time is very long or even impossible to solve, which cannot meet the real-time scheduling requirements;

[0056] The branch and bound method requires an in-depth search for all possible robot operation sequences based on the process path of the wafers in the current device until all wafers return to wafer loading and unloading position 21 to terminate the search. The branch scale is huge and it is difficult to solve in a short time.

[0057] In order to solve the problem of the above method solving the problem of too large scale, the inventor found through further research that the algorithm solving scale can be greatly reduced by searching the target module that the target wafer may go to next, improving the solving efficiency and meeting the needs of real-time scheduling. In addition, before the step of placing the target wafer into the next target module, if there are wafers that violate the residence time constraint in other target modules, the step of removing the wafers that violate the residence time constraint can be inserted. In this way, the problem of other wafers violating the residence time constraint that may be caused by operating the target wafer can be avoided, and the adverse effects of other wafers on the wafer due to violating the residence time constraint can be avoided or reduced. Furthermore, the optimal alternative sequence can be selected for execution by the index evaluation method to ensure that the output scheduling sequence has better performance.

[0058] Based on the above-mentioned inventive concept, the implementation mode of this specification provides a scheduling method, and the scheduling method provided by the implementation mode of this specification will be exemplarily described below in conjunction with the accompanying drawings.

[0059] Exemplary Methods

[0060] An embodiment of the present specification provides a scheduling method for generating a scheduling sequence, wherein the scheduling sequence is used to control a first robot 10 in a semiconductor process equipment, wherein the first robot 10 is used to schedule wafers between target modules, wherein the target modules include a processing module 11 of the semiconductor process equipment or a wafer slot of a vacuum lock 30, such as Figure 2 As shown, the scheduling method includes:

[0061] S201: Determine a target wafer, the target wafer comprising: a movable wafer in the semiconductor process equipment in a current state;

[0062] S202: If in the current state, the target wafer is located on the first robot, then traverse the next target module of the target wafer to obtain multiple first alternative sequences; the next target module includes a target module for executing the next process of the target wafer; the first alternative sequence includes: a step of placing the target wafer into the next target module, and if there are wafers violating the residence time constraint in other target modules, the first alternative sequence also includes: before placing the target wafer into the next target module, inserting a step of taking out the wafer violating the residence time constraint;

[0063] S203: Determine the scheduling sequence among multiple candidate sequences; the multiple candidate sequences include multiple first candidate sequences.

[0064] Figure 2 A feasible application scenario of a scheduling method is also shown. During the operation of the semiconductor process equipment, the control module of the semiconductor process equipment obtains the status of other modules of the semiconductor process equipment (the first manipulator 10, the processing module 11 and the vacuum lock 30, etc.), and executes the scheduling method to obtain a scheduling sequence, and schedules the first manipulator 10 and other modules according to the scheduling sequence. The control module can be a lower computer of the semiconductor process equipment, and specifically can be a device with computing and communication capabilities, such as a computer. In other application scenarios, it can also be an external module of the semiconductor process equipment that executes the scheduling method to generate the scheduling sequence and sends it to the lower computer of the semiconductor process equipment, so that the lower computer schedules the first manipulator 10 according to the scheduling sequence.

[0065] The current state may refer to the state of each module in the semiconductor process equipment at the current moment (for example, whether there is a wafer in the slot of the processing module 11, whether the processing module 11 is in a processing state, whether there is a wafer in the slot of the first robot 10, etc.). A movable wafer may refer to a wafer in a non-processing state. If a wafer is in the processing module 11 and is in a processing state, it is not a movable wafer.

[0066] In semiconductor process equipment, there may be multiple next target modules for the target wafer, still refer to Figure 1 , assuming that there are 4 process modules 11 in the semiconductor process equipment, and these 4 process modules 11 can be, for example, PM1, PM2, PM3 and PM4 respectively. Assuming that at the current moment, PM1 and PM2 are both in an idle state and can provide the chamber required for the next step of processing for the target wafer, then PM1 and PM2 can both serve as the next step modules for the target wafer.

[0067] The residence time refers to the time that the wafer waits to be taken out after being processed in the processing module 11. The residence time constraint means that the residence time of the wafer cannot exceed the set maximum residence time. If the residence time of the wafer exceeds the set maximum residence time, it is called a violation of the residence time constraint. When the residence time constraint is violated, the residual gas or residual temperature in the processing module 11 may have a bad impact on the wafer.

[0068] Before placing the target wafer into the next target module, there may be two situations where wafers violating the residence time constraint exist in other target modules: wherein, situation one is: before placing the target wafer into the next target module, there are already wafers violating the residence time constraint in other target modules, and if the step of taking out the wafers violating the residence time constraint is not inserted at this time, the residence time of the wafers violating the residence time constraint will be further increased, resulting in the residual gas or residual temperature in the processing module 11 bringing further adverse effects to the wafers;

[0069] Scenario two is: before placing the target wafer into the next target module, there is no wafer violating the residence time constraint in other target modules. However, during the process of placing the target wafer into the next target module, wafers violating the residence time constraint appear in other target modules. In this case, the wafer violating the residence time constraint that appears when placing the target wafer into the next target module is also called a wafer violating the residence time constraint. It is necessary to insert a step to remove the wafer violating the residence time constraint to avoid the wafer violating the residence time constraint during the process of "placing the target wafer into the next target module".

[0070] In general, in order to avoid the situation where wafers in other target modules violate the residence time constraints due to operating the target wafer or the residence time of wafers that violate the residence time constraints in other target modules is further increased, in this implementation formula, before placing the target wafer into the next target module, it is determined whether there are wafers that violate the residence time constraints in other target modules. If there are wafers that violate the residence time constraints in other target modules, then before placing the target wafer into the next target module, a step of removing the wafers that violate the residence time constraints is inserted. In this way, the purpose of preferentially removing the wafers that violate the residence time constraints before placing the target wafer into the next target module is achieved, thereby avoiding the situation where wafers in other target modules violate the residence time constraints due to operating the target wafer or the residence time of wafers that violate the residence time constraints in other target modules is further increased due to operating the target wafer.

[0071] To summarize, in the scheduling method provided in the implementation mode of the present specification, when the target wafer is located on the first robot in the current state, multiple first alternative sequences are obtained by traversing the next target module of the target wafer; in this way, the first alternative sequence is obtained by traversing the next target module of the target wafer, which can greatly reduce the length of the process path required to be searched during the traversal process, and reduce the scale of process branches required to be searched during the traversal process, thereby avoiding the problem of excessive algorithm solution scale due to the long process path length when solving multi-wafer scheduling problems. In addition, the first alternative sequence includes: the step of placing the target wafer into the next target module, and if there are wafers violating the residence time constraint in other target modules, the first alternative sequence also includes: before placing the target wafer into the next target module, the step of removing the wafer violating the residence time constraint is inserted. In this way, the problem of other wafers violating the residence time constraint due to operating the target wafer can be avoided, or the problem of further increasing the residence time of wafers violating the residence time constraint in other target modules due to operating the target wafer can be avoided, thereby avoiding or reducing the adverse effects of other wafers on the wafer due to violating the residence time constraint.

[0072] In order to prevent the target wafer from violating the residence time constraint, in one embodiment of the present specification, the scheduling method further includes:

[0073] If the target wafer is located in the target module in the current state, then when the target wafer is in the first state, the action of grabbing the target wafer is used as the second alternative sequence, and the step of traversing the next target module of the target wafer is entered; the first state includes: if the target wafer is not grabbed in the current state, the residence time constraint of the target wafer will be violated;

[0074] The plurality of candidate sequences also includes the second candidate sequence.

[0075] In some cases, if the target wafer is located in the target module in the current state, it is necessary to consider whether the target wafer will violate the residence time constraint of the target wafer if the target wafer is not grabbed immediately. If so, the action of grabbing the target wafer is taken as the second alternative sequence, and the step of traversing the next target module of the target wafer is entered. In this way, the short sequence of the action of grabbing the target wafer (i.e., the second alternative sequence) can be saved first to avoid the situation that when this short sequence forms a longer sequence (i.e., the first alternative sequence) after entering the step of traversing the next target module of the target wafer, there is no empty slot on the first robot in a certain step and the grabbing action cannot be performed, and the situation is deleted, thereby achieving the purpose of saving the action of grabbing the target wafer that is about to violate the mainstream time constraint as the second alternative sequence, and the action of grabbing the target wafer in the second alternative sequence can be avoided in the subsequent step of traversing the next module of the target wafer. Deleted (for example, Figure 3 The situation of step S4 in the above example is avoided, thereby avoiding the situation that the target wafer violates the residence time constraint due to failure to capture the target wafer in time.

[0076] In some embodiments, the first candidate sequence includes: at least one step that the first robot needs to perform during the process of placing the target wafer into the next target module;

[0077] The second alternative sequence includes at least one step in which the first robot takes the target wafer out of the target module when the target wafer is in a first state.

[0078] In one embodiment, the scheduling method generates the first alternative sequence and the second alternative sequence by simulating the possible execution steps of the first robot, that is, when simulating and generating the first alternative sequence, the scheduling method can record the steps required to be executed by the first robot from the position of the target wafer in the current state to the step of placing the target wafer into the next target module into the current first alternative sequence; similarly, when generating the second alternative sequence, the steps from the position of the target wafer in the current state to the step of taking the target wafer out of the target module can be recorded into the current second alternative sequence. In this way, it can be ensured that the first alternative sequence and the second alternative sequence at least include the key steps of the first robot in each sequence.

[0079] In general, in one embodiment, when executing the scheduling method, starting from the current state, each action simulated by the first robot can be recorded as a step in the current alternative sequence. When it is found that the alternative sequence does not meet the requirements, the current alternative sequence can be deleted and other next target modules of the target wafer can be traversed. Or, after the target modules of the target wafer are traversed, the target wafer can be replaced and the alternative sequence and scheduling sequence can be generated for it.

[0080] In an optional embodiment, a method of traversing the next target wafer of the target wafer is provided, such as Figure 3 As shown, the next step target module of traversing the target wafer, obtaining multiple first candidate sequences and recording them includes:

[0081] Performing simulation sequence generation on each of the next step modules of the target wafer to obtain a plurality of the first candidate sequences;

[0082] The steps of generating the simulation sequence include:

[0083] If there is a wafer to be picked up in the next target module, there is an empty slot in the first robot, and there is no wafer violating the residence time constraint in other target modules, then the step of taking out the wafer to be picked up and placing the target wafer in the next target module is recorded in the first candidate sequence;

[0084] If the wafer to be grabbed does not exist in the next target module, then if there is a wafer violating the residence time constraint in other target modules, the wafer violating the residence time constraint will be taken out and the step of placing the target wafer into the next target module will be recorded into the first alternative sequence.

[0085] In an optional embodiment, still referring to Figure 3 , the step of generating the simulation sequence further comprises:

[0086] If the wafer to be grasped already exists in the next target module and there is no empty slot in the first robot, the current candidate sequence is deleted;

[0087] If the wafer to be grasped is already in the next target module, there is an empty slot in the first robot, and there are wafers in the other target modules that violate the residence time constraint, the current candidate sequence is deleted.

[0088] In this embodiment, if the wafer to be grasped is already in the next target module and there is no empty slot in the first manipulator, the action of taking the wafer to be grasped out of the next target module cannot be performed due to the problem of no empty slot in the first manipulator, so that the target wafer can actually not be placed in the next target module. Therefore, the current alternative sequence can be deleted to avoid the situation where an invalid alternative sequence is recorded.

[0089] Similarly, if the wafer to be grasped is already in the next target module and there is an empty slot in the first robot, although the first robot can take out the wafer to be grasped and place the target wafer into the next target module, since there are wafers in other target modules that are in a state of violating the residence time constraint, the current alternative sequence is recorded, which may cause other wafers to violate the residence time constraint. Therefore, deleting the current alternative sequence can avoid the problem of causing other wafers to violate the residence time constraint.

[0090] Specific reference Figure 3 , Figure 3 Steps S9 to S15 in FIG. 4 show feasible execution steps for simulation sequence generation:

[0091] S9: if it is determined that there is a wafer to be grabbed in the target module in the next step, then the process goes to step S10, otherwise, the process goes to step S14;

[0092] S10: Determine whether there are any empty slots in the first manipulator, if yes, proceed to step S11, if no, proceed to step S4: delete the current candidate sequence;

[0093] S11: recording the steps of taking out the wafer to be grasped and placing the target wafer into the next target module into the first candidate sequence;

[0094] S12: Determine whether there is a wafer that violates the residence time constraint in other target modules. If yes, proceed to step S4: delete the current candidate sequence; if no, return to step S8: traverse the next target module of the target wafer until all the next target modules of the target wafer are traversed;

[0095] S13: Determine whether there are wafers in other target modules that violate the residence time constraint. If yes, proceed to step S14; if no, proceed to step S15;

[0096] S14: recording the step of taking out the wafer that violates the residence time constraint and placing the target wafer into the next target module into the first candidate sequence;

[0097] S15: The step of placing the target wafer into the next target module is entered into the first candidate sequence.

[0098] In this embodiment, through the two judgments of step S12 and step S13, it is ensured that in the process of generating the first alternative sequence, other wafers are prevented from violating the residence time constraint, which is conducive to avoiding the adverse effects that may be caused by other wafers violating the residence time constraint. Specifically, since the first manipulator needs to consume a certain amount of time when performing actions such as grabbing the target wafer, as the number of actions of the first manipulator in the alternative sequence increases, if other wafers are already in the target module, the residence time of other wafers in the target module will increase accordingly, so other wafers may violate the residence time constraint. In the present embodiment, in step S12, before traversing the next target module, if there are wafers violating the residence time constraint in other target modules, the current alternative sequence is deleted to avoid the situation where wafers violating the residence time constraint appear in other target modules; correspondingly, in step S13, a judgment is also made on whether there are wafers violating the residence time constraint in other target modules. If the judgment is yes, the wafers violating the residence time constraint are removed first, thereby reducing the duration of the wafer violating the residence time constraint and reducing the adverse effects that may be caused by violating the residence time constraint on the wafer.

[0099] In an optional implementation, the scheduling method further includes:

[0100] If in the current state, the target wafer is located in the target module and there is no empty slot on the first robot, the current candidate sequence is deleted.

[0101] Similarly, in the current state, if the target wafer is located in the target module, but there is no empty slot on the first robot, the first robot will not be able to actually perform the action of removing the target wafer from the target module, resulting in the inability to perform subsequent actions. Therefore, deleting the current alternative sequence can avoid the situation where invalid alternative sequences are recorded.

[0102] Still reference Figure 3 An implementation of this specification provides a specific execution process of a feasible scheduling method, which specifically includes:

[0103] S1: Determine the target wafer;

[0104] S2: Determine whether the target wafer is on the first robot, if yes, proceed to step S3; if not, proceed to step S8;

[0105] S3: Determine whether there is an empty slot on the first robot, if yes, proceed to step S5, if not, proceed to step S4: delete the current candidate sequence;

[0106] S5: recording the target wafer grabbed by the first robot into the current candidate sequence;

[0107] S6: Determine whether the dwell time constraint will be violated if the target wafer is not captured, if yes, proceed to step S7, if no, proceed to step S8;

[0108] S7: taking the action of grabbing the target wafer as a second candidate sequence;

[0109] S8: traverse the next target module of the target wafer.

[0110] For the introduction of the next target module of traversing the target wafer, please refer to the introduction of steps S9 to S15 above, and this specification will not go into details here.

[0111] In order to determine the best candidate sequence from multiple candidate sequences as a scheduling sequence, in one embodiment of the present specification, determining the scheduling sequence from multiple candidate sequences includes:

[0112] The scheduling sequence is determined according to the evaluation parameters of the candidate sequences; the evaluation parameters are used to describe the priority of the candidate sequences, and the scheduling sequence is the candidate sequence with the highest priority.

[0113] In this embodiment, by setting evaluation parameters for each candidate sequence, the candidate sequence with the highest priority is used as the scheduling sequence. In this way, it can be ensured that the scheduling sequence determined each time is the candidate sequence with the highest priority among multiple candidate sequences, which is conducive to improving the scheduling effect of the scheduling sequence determined by the scheduling method.

[0114] When there are multiple candidate sequences with the highest parallel priority, in an optional implementation, one candidate sequence can be randomly selected from the multiple candidate sequences with the highest parallel priority as the scheduling sequence, or a unique candidate sequence with the highest priority can be determined by setting multiple indicators.

[0115] For example, in one embodiment of the present specification, the evaluation parameter includes the accumulated value of the dwell time in the candidate sequence;

[0116] The determining the scheduling sequence according to the evaluation parameters of the candidate sequence comprises:

[0117] Among the multiple candidate sequences, the candidate sequence with the smallest accumulated value of the dwell time is used as the scheduling sequence.

[0118] The method for determining the scheduling sequence provided in this embodiment can be applied to the case where each processing module 11 is set with a residence time constraint. In this case, by using the candidate sequence with the smallest cumulative value of the residence time as the scheduling sequence, it can be ensured that the residence time of the target wafer in the processing module 11 is reduced as much as possible during the execution of the scheduling sequence, which is conducive to minimizing the time that the target wafer is affected by the residual gas / temperature in the processing module 11 after the processing is completed. In some embodiments, when each processing module 11 is set with a residence time constraint, if there are two or more candidate sequences with the smallest cumulative value of the residence time among the multiple candidate sequences, then an alternative sequence can be randomly selected from the candidate sequences with the smallest cumulative value of the residence time as the scheduling sequence.

[0119] In addition to the above-mentioned implementation modes, in order to make the evaluation parameters have evaluation significance for the alternative sequences obtained in various situations, the parameter types in the evaluation parameters can be expanded. For example, in another implementation mode, another method of evaluating the alternative sequences is provided. Specifically, as described above, when there are multiple alternative sequences with the smallest cumulative values ​​of the residence time among the multiple alternative sequences, one can be randomly selected from the multiple parallel alternative sequences with the smallest cumulative values ​​of the residence time as the scheduling sequence, and other indicators can be added to determine an optimal scheduling sequence.

[0120] For example, in one embodiment, reference Figure 4 , the evaluation parameters include: the cumulative value of the residence time, the cumulative value of the wafer waiting time, the cumulative value of the robot waiting time and the cumulative value of the number of times the robot takes the wafer; the wafer waiting time includes the difference between the time when the wafer completes the processing process in the target module and the time when the first robot grabs the wafer; the robot waiting time includes the time when the first robot waits to grab the wafer;

[0121] The determining the scheduling sequence according to the evaluation parameters of the candidate sequence comprises:

[0122] If there is a unique candidate sequence with the smallest cumulative value of residence time among the multiple candidate sequences, the candidate sequence with the smallest cumulative value of residence time is used as the scheduling sequence;

[0123] If there are multiple candidate sequences with the smallest cumulative values ​​of the dwell times, then the candidate sequence with the largest cumulative value of the wafer waiting time among the multiple candidate sequences with the smallest cumulative values ​​of the dwell times is used as the scheduling sequence;

[0124] If there are multiple candidate sequences with the largest cumulative value of wafer waiting time, then among the multiple candidate sequences with the largest cumulative value of wafer waiting time, the candidate sequence with the smallest cumulative value of robot waiting time is used as the scheduling sequence;

[0125] If there are multiple candidate sequences with the smallest cumulative value of robot waiting time, the candidate sequence with the largest cumulative value of robot fetching times among the candidate sequences with the smallest cumulative value of robot waiting time is used as the scheduling sequence.

[0126] In this embodiment, the alternative sequence is evaluated in turn by multiple indicators (the cumulative value of the residence time, the cumulative value of the wafer waiting time, the cumulative value of the robot waiting time, and the cumulative value of the number of times the robot takes the film), so as to increase the probability of selecting an optimal alternative sequence as the scheduling sequence from multiple alternative sequences. In addition, by setting other indicators besides the cumulative value of the residence time, it is beneficial to expand the applicability of the process of determining the scheduling sequence and meet the scheduling sequence determination requirements when the residence time constraint is not set. Moreover, when determining the optimal alternative sequence through this embodiment, the wafer quality (guaranteed by the two indicators of the cumulative value of the residence time and the cumulative value of the wafer waiting time) and the production capacity (guaranteed by the two indicators of the cumulative value of the robot waiting time and the cumulative value of the number of times the robot takes the film) are comprehensively considered, so that the optimal alternative sequence determined by the above method can guarantee the wafer quality and wafer production capacity.

[0127] Specifically, refer to Figure 4 , the method of determining the scheduling sequence may include:

[0128] S21: sorting the multiple candidate sequences from small to large according to the accumulated values ​​of the residence time;

[0129] S22: Determine whether there is a unique candidate sequence with the smallest accumulated value of the dwell time, if yes, proceed to step S23, if no, proceed to step S24;

[0130] S23: taking the candidate sequence with the smallest accumulated value of the dwell time as the scheduling sequence;

[0131] S24: sorting the candidate sequences with the smallest accumulated values ​​of the multiple dwell times from large to small according to the accumulated values ​​of the wafer waiting times;

[0132] S25: Determine whether there are multiple candidate sequences with the largest cumulative value of the wafer waiting time. If not, proceed to step S26; if yes, proceed to step S27;

[0133] S26: taking, among the candidate sequences with the smallest accumulated values ​​of the dwell times, the candidate sequence with the largest accumulated value of the wafer waiting time as the scheduling sequence;

[0134] S27: sorting the candidate sequences with the largest cumulative values ​​of the waiting time of multiple wafers in ascending order according to the cumulative values ​​of the waiting time of the robot;

[0135] S28: Determine whether there are multiple candidate sequences with the smallest cumulative value of the waiting time of the manipulators. If not, proceed to step S29; if yes, proceed to step S30;

[0136] S29: taking, among the candidate sequences with the largest accumulated values ​​of the waiting times of the wafers, the candidate sequence with the smallest accumulated value of the waiting time of the robot as the scheduling sequence;

[0137] S30: Among the candidate sequences with the smallest accumulated value of the waiting time of the robot, the candidate sequence with the largest accumulated value of the number of times the robot takes the sheets is used as the scheduling sequence.

[0138] For example, refer to Figure 5 Assuming that there are four candidate sequences, the four candidate sequences are sequence A, sequence B, sequence C and sequence D. First, they are sorted according to the cumulative value of the residence time. Assuming that the cumulative values ​​of the residence time of sequence A, sequence B, sequence C and sequence D are 2, 3, 1, and 4 respectively, then after sorting them from small to large according to the cumulative value of the residence time, the order is: sequence C, sequence A, sequence B and sequence D, and the sequence with the smallest cumulative value of the residence time is unique, then sequence C can be used as the scheduling sequence, and the subsequent steps S24 to S30 are no longer performed.

[0139] For example, refer to Figure 6 , assuming that there are four candidate sequences, which are sequence A, sequence B, sequence C and sequence D. First, they are sorted according to the cumulative value of the residence time. Assuming that the cumulative values ​​of the residence time of sequence A, sequence B, sequence C and sequence D are 1, 1, 1, and 3 respectively, then after sorting from small to large according to the cumulative value of the residence time, the order is: sequence A, sequence B, sequence C and sequence D. The sequence with the smallest cumulative value of the residence time is not unique, then sequence A, sequence B and sequence C are sorted from large to small according to the cumulative value of the wafer waiting time. Assuming that the cumulative values ​​of the wafer waiting time of sequence A, sequence B and sequence C are 2, 3, and 1 respectively, the sorted order is sequence B, sequence A and sequence C. Sequence B can be used as the scheduling sequence, and subsequent steps S27 to S30 are no longer performed.

[0140] Taking the candidate sequence with the largest accumulated value of the wafer waiting time as the scheduling sequence can avoid excessively long waiting time for the wafer.

[0141] In some embodiments, when no residence time constraint is set, the optimal scheduling sequence can also be determined by the above method to avoid the wafer staying in the processing module 11 for too long after processing is completed, or to avoid long waiting times of the robot, or to use the longest alternative sequence as the scheduling sequence so that the scheduling sequence determined once can meet the scheduling requirements for a longer time.

[0142] Exemplary devices and apparatus

[0143] In an exemplary embodiment of the present specification, a scheduling device is also provided, for generating a scheduling sequence, comprising: a processor and a memory;

[0144] Wherein, the memory is connected to the processor, and the memory is used to store a computer program;

[0145] The processor is used to implement the scheduling method as described in any of the above embodiments by running the computer program stored in the memory.

[0146] In another exemplary embodiment of the present specification, a scheduling device is provided for generating a scheduling sequence, wherein the scheduling sequence is used to control a first robot in a semiconductor process equipment, wherein the first robot is used to schedule wafers between target modules, wherein the target modules include wafer slots of a processing module or a vacuum lock of the semiconductor process equipment, such as Figure 7 As shown, the scheduling device includes:

[0147] The state acquisition module 701 is used to determine the target wafer, and the target wafer includes: a movable wafer in the semiconductor process equipment in the current state;

[0148] The first generating module 702 is used for traversing the next target module of the target wafer to obtain a plurality of first candidate sequences if the target wafer is located on the first robot in the current state; the next target module includes a target module for executing the next process of the target wafer; the first candidate sequence includes: a step of placing the target wafer into the next target module, and if there is a wafer violating the residence time constraint in other target modules, the first candidate sequence also includes: before placing the target wafer into the next target module, inserting a step of taking out the wafer violating the residence time constraint;

[0149] The sequence evaluation module 703 is used to determine the scheduling sequence among multiple candidate sequences.

[0150] In some implementations, the scheduling device may further include a scheduling sequence output module, configured to output the scheduling sequence to the machine.

[0151] For the specific definition of the scheduling device, please refer to the definition of the scheduling method above, which will not be repeated here. Each module in the above scheduling device can be implemented in whole or in part by software, hardware and a combination thereof. The above modules can be embedded in or independent of the processor in the computer device in the form of hardware, or can be stored in the memory of the computer device in the form of software, so that the processor can call and execute the operations corresponding to the above modules.

[0152] like Figure 8 As shown, in an exemplary embodiment of the present specification, a semiconductor process equipment 100 is also provided, comprising: a first robot 10, a control module 40 and a plurality of target modules; the target module comprises a wafer slot of a processing module 11 or a vacuum lock 30;

[0153] The control module 40 is used to generate a scheduling sequence according to the scheduling method described in any of the above embodiments, and control the first robot 10 to schedule the wafer between the multiple target modules according to the scheduling sequence.

[0154] The control module 40 can collect information of the controlled module 50 and control the controlled module 50 to work in coordination. The controlled module 50 can include part or all of the above-mentioned first robot 10, control module 40, vacuum lock 30 and multiple processing modules 11. In some embodiments, the controlled module 50 can also include a second robot 20, a calibration module 22 and a wafer loading and unloading position 21, etc.

[0155] In another exemplary embodiment of the present specification, there is also provided a semiconductor process scheduling device for generating a scheduling sequence, comprising: a processor and a memory;

[0156] Wherein, the memory is connected to the processor, and the memory is used to store a computer program;

[0157] The processor is used to implement any of the scheduling methods described above by running the computer program stored in the memory.

[0158] In some implementations, the control module 40 is, for example, a lower computer of the semiconductor process equipment 100 , and this specification does not limit this, and the specific implementation depends on the actual situation.

[0159] Exemplary Electronic Devices

[0160] Another embodiment of the present application also provides an electronic device, see Fig. 9 As shown, an exemplary embodiment of the present specification also provides an electronic device, including: a memory and a processor, wherein the memory stores a computer program, and when the processor executes the computer program, it executes the steps of the scheduling method according to various embodiments of the present specification described in the above embodiments of the present specification.

[0161] The internal structure of the electronic device can be as follows Fig. 9As shown, the electronic device includes a processor, a memory, a network interface and an input device connected through a system bus. Among them, the processor of the electronic device is used to provide computing and control capabilities. The memory of the electronic device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system and a computer program. The internal memory provides an environment for the operation of the operating system and the computer program in the non-volatile storage medium. The network interface of the electronic device is used to communicate with an external terminal through a network connection. When the computer program is executed by the processor, the steps in the scheduling method according to various embodiments of the present specification described in the above embodiments of the present specification are performed.

[0162] The processor may include a main processor and may also include a baseband chip, a modem, etc.

[0163] The memory stores a program for executing the technical solution of the present invention, and may also store an operating system and other key services. Specifically, the program may include a program code, and the program code includes computer operation instructions. More specifically, the memory may include a read-only memory (ROM), other types of static storage devices that can store static information and instructions, a random access memory (RAM), other types of dynamic storage devices that can store information and instructions, a disk storage, a flash, and the like.

[0164] The processor may be a general-purpose processor, such as a general-purpose central processing unit (CPU), a microprocessor, etc., or an application-specific integrated circuit (ASIC), or one or more integrated circuits for controlling the execution of the program of the scheme of the present invention. It may also be a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic device, a discrete gate or transistor logic device, or a discrete hardware component.

[0165] The input device may include a device for receiving data and information input by a user, such as a keyboard, a mouse, a camera, a scanner, a light pen, a voice input device, a touch screen, a pedometer, or a gravity sensor.

[0166] Output devices may include means that allow information to be output to a user, such as display screens, printers, speakers, etc.

[0167] The communication interface may include using any transceiver or the like to communicate with other devices or communication networks, such as Ethernet, Radio Access Network (RAN), Wireless Local Area Network (WLAN), etc.

[0168] The processor executes the program stored in the memory and calls other devices, which can be used to implement each step of any scheduling method provided in the above embodiments of the present application.

[0169] The electronic device may also include a display component and a voice component. The display component may be a liquid crystal display or an electronic ink display. The input device of the electronic device may be a touch layer covered on the display component, or a button, trackball or touchpad provided on the housing of the electronic device, or an external keyboard, touchpad or mouse.

[0170] Those skilled in the art will understand that Fig. 9 The structure shown in the figure is only a block diagram of a part of the structure related to the scheme of this specification, and does not constitute a limitation on the electronic device to which the scheme of this specification is applied. The specific electronic device may include more or fewer components than shown in the figure, or combine certain components, or have a different arrangement of components.

[0171] Exemplary computer program products and storage media

[0172] In addition to the above-mentioned methods and devices, the scheduling method provided in the embodiments of this specification may also be a computer program product, which includes computer program instructions, which, when executed by a processor, enable the processor to execute the steps of the scheduling method according to various embodiments of this specification described in the above "Exemplary Method" section of this specification.

[0173] The computer program product may be written in any combination of one or more programming languages ​​to write program code for performing the operations of the embodiments of the present specification, including object-oriented programming languages ​​such as Java, C++, etc., and conventional procedural programming languages ​​such as "C" or similar programming languages. The program code may be executed entirely on the user computing device, partially on the user device, as a separate software package, partially on the user computing device and partially on a remote computing device, or entirely on a remote computing device or server.

[0174] In addition, an embodiment of the present specification also provides a computer-readable storage medium on which a computer program is stored, and the computer program is executed by a processor to execute the steps of the scheduling method according to various embodiments of the present specification described in the above "Exemplary Method" section of the present specification.

[0175] Those skilled in the art can understand that all or part of the processes in the above-mentioned embodiment methods can be completed by instructing the relevant hardware through a computer program, and the computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the above-mentioned methods. Among them, any reference to memory, storage, database or other media used in the embodiments provided in this specification can include non-volatile and / or volatile memory. Non-volatile memory can include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM) or flash memory. Volatile memory can include random access memory (RAM) or external cache memory. As an illustration and not limitation, RAM is available in many forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDRSDRAM), enhanced SDRAM (ESDRAM), synchronous link (Synchlink) DRAM (SLDRAM), memory bus (Rambus) direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and memory bus dynamic RAM (RDRAM).

[0176] The technical features of the above embodiments may be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0177] The above-mentioned embodiments only express several implementation methods of this specification, and the descriptions are relatively specific and detailed, but they cannot be understood as limiting the scope of the solutions provided by the embodiments of this specification. It should be pointed out that for ordinary technicians in this field, several modifications and improvements can be made without departing from the concept of this specification, which all belong to the protection scope of this specification. Therefore, the protection scope of the patent of this specification shall be based on the attached claims.

Claims

1. A scheduling method, characterized in that: The method is used to generate a scheduling sequence, wherein the scheduling sequence is used to control a first robot in a semiconductor process equipment, wherein the first robot is used to schedule wafers between target modules, wherein the target modules include processing modules of the semiconductor process equipment or wafer slots of a vacuum lock, wherein the scheduling method includes: Determining a target wafer, the target wafer comprising: a movable wafer in the semiconductor process equipment in a current state; If the target wafer is located on the first robot in the current state, the next target module of the target wafer is traversed to obtain multiple first alternative sequences; the next target module includes a target module for executing the next process of the target wafer; the first alternative sequence includes: a step of placing the target wafer into the next target module, and if there is a wafer violating the residence time constraint in other target modules, the first alternative sequence also includes: before placing the target wafer into the next target module, inserting a step of taking out the wafer violating the residence time constraint; The scheduling sequence is determined among a plurality of candidate sequences; the plurality of candidate sequences include a plurality of the first candidate sequences.

2. The method according to claim 1, characterized in that Also includes: If the target wafer is located in the target module in the current state, then when the target wafer is in the first state, the action of grabbing the target wafer is used as the second alternative sequence, and the step of traversing the next target module of the target wafer is entered; the first state includes: if the target wafer is not grabbed in the current state, the residence time constraint of the target wafer will be violated; The plurality of candidate sequences also includes the second candidate sequence.

3. The method according to claim 2, characterized in that The first alternative sequence includes: at least one step that the first robot needs to perform when the target wafer is placed into the next target module.

4. The method according to claim 1, characterized in that The next step target module of traversing the target wafer, obtaining a plurality of first candidate sequences and recording them includes: Performing simulation sequence generation on each of the next step modules of the target wafer to obtain a plurality of the first candidate sequences; The steps of generating the simulation sequence include: If there is a wafer to be picked up in the next target module, there is an empty slot in the first robot, and there is no wafer violating the residence time constraint in other target modules, then the step of taking out the wafer to be picked up and placing the target wafer in the next target module is recorded in the first candidate sequence; If the wafer to be grabbed does not exist in the next target module, then if there is a wafer violating the residence time constraint in other target modules, the wafer violating the residence time constraint will be taken out and the step of placing the target wafer into the next target module will be recorded into the first alternative sequence.

5. The method according to claim 4, characterized in that The step of generating the simulation sequence also includes: If the wafer to be grasped already exists in the next target module and there is no empty slot in the first robot, the current candidate sequence is deleted; If the wafer to be grasped is already in the next target module, there is an empty slot in the first robot, and there are wafers in the other target modules that violate the residence time constraint, the current candidate sequence is deleted.

6. The method according to claim 1, characterized in that Also includes: If in the current state, the target wafer is located in the target module and there is no empty slot on the first robot, the current candidate sequence is deleted.

7. The method according to any one of claims 1 to 6, characterized in that: Determining the scheduling sequence among multiple candidate sequences comprises: The scheduling sequence is determined according to the evaluation parameters of the candidate sequences; the evaluation parameters are used to describe the priority of the candidate sequences, and the scheduling sequence is the candidate sequence with the highest priority.

8. The method according to claim 7, characterized in that The evaluation parameters include the accumulated value of the dwell time in the candidate sequence; The determining the scheduling sequence according to the evaluation parameters of the candidate sequence comprises: Among the multiple candidate sequences, the candidate sequence with the smallest accumulated value of the dwell time is used as the scheduling sequence.

9. The method according to claim 7, characterized in that: The evaluation parameters include: the cumulative value of the dwell time, the cumulative value of the wafer waiting time, the cumulative value of the robot waiting time and the cumulative value of the number of times the robot takes the wafer; the wafer waiting time includes the difference between the time when the wafer completes the processing process in the target module and the time when the first robot grabs the wafer; the robot waiting time includes the time when the first robot waits to grab the wafer; The determining the scheduling sequence according to the evaluation parameters of the candidate sequence comprises: If there is a unique candidate sequence with the smallest cumulative value of residence time among the multiple candidate sequences, the candidate sequence with the smallest cumulative value of residence time is used as the scheduling sequence; If there are multiple candidate sequences with the smallest cumulative values ​​of the dwell times, then among the multiple candidate sequences with the smallest cumulative values ​​of the dwell times, the candidate sequence with the largest cumulative value of the wafer waiting time is used as the scheduling sequence; If there are multiple candidate sequences with the largest cumulative value of wafer waiting time, then among the multiple candidate sequences with the largest cumulative value of wafer waiting time, the candidate sequence with the smallest cumulative value of robot waiting time is used as the scheduling sequence; If there are multiple candidate sequences with the smallest cumulative value of robot waiting time, the candidate sequence with the largest cumulative value of robot fetching times among the candidate sequences with the smallest cumulative value of robot waiting time is used as the scheduling sequence.

10. A semiconductor process equipment, characterized in that: include: A first robot, a control module and a plurality of target modules; the target modules include wafer slots of a processing module or a vacuum lock; The control module is used to generate a scheduling sequence according to the scheduling method according to any one of claims 1 to 9, and control the first robot to schedule the wafer between the plurality of target modules according to the scheduling sequence.

11. A scheduling device for generating a scheduling sequence, characterized in that: include: Processor and memory; Wherein, the memory is connected to the processor, and the memory is used to store a computer program; The processor is used to implement the scheduling method according to any one of claims 1 to 9 by running the computer program stored in the memory.

12. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, and when the computer program is executed by the processor, the scheduling method according to any one of claims 1 to 9 is implemented.

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