Triode current source array, driving compensation method and digital-to-analog converter

Abstract

The invention provides a triode current source array, a driving compensation method and a digital-to-analog converter, a current source comprises an amplification module, a current compensation module and a current source array module, and the amplification module amplifies and outputs an input primary voltage and a first reference voltage; the current compensation module shunts the initial current converted from the primary voltage, carries out multiple times of mirroring processing on the shunted initial compensation current to obtain a target current equal to the initial current, and carries out N times of mirroring processing on the initial compensation current to obtain a compensation current; and the compensation current acts on the output end of the amplification module, so that N triode current source branches arranged in parallel in the current source array generate N target currents. According to the triode current source array provided by the invention, the influence of the change of the base current of the corresponding number of triodes along with the temperature is reduced by controlling the multiple of the current mirror processing in the current compensation module, the base bias voltage in the triode current source array is prevented from fluctuating along with the path, and the performance of the digital-to-analog converter is improved.

Description

Technical Field

[0001] The invention relates to a digital-to-analog converter monolithic integrated circuit design, and in particular to a triode current source array and a driving compensation method, and a digital-to-analog converter. Background Art

[0002] In the design of current output high-precision digital-to-analog converters, the function is to output a current output signal that is proportional to the digital signal input. Usually, MOS tubes or bipolar transistors are used internally to build a current source array to achieve this function. Compared with using MOS tubes to build a current source array, the advantages of using triodes to build a current source array are: first, there is less restriction on the output swing; second, when the same current flows, the noise of bipolar transistors is relatively low; third, the design is relatively simpler.

[0003] However, when actually designing a current source array using transistors, there are problems including limited driving capability and low impedance, that is, the output impedance of the transistor is small, which will affect the integral nonlinearity (INL) and spurious-free dynamic range (SFDR) of the digital-to-analog converter. At the same time, since there is a current in the base, which is 1 / β of the collector current, requirements are also put forward for the driving capability of the base voltage.

[0004] Therefore, how to provide a transistor current source array with strong base driving capability and large output impedance is a technical problem that urgently needs to be solved. Summary of the invention

[0005] In view of the above-mentioned shortcomings of the prior art, the present invention provides a triode current source array to solve at least one of the above-mentioned technical problems.

[0006] In order to achieve the above-mentioned purpose and other related purposes, the technical solution provided by this application is as follows.

[0007] According to a first aspect of an embodiment of the present application, a triode current source array is provided, comprising:

[0008] an amplification module, connected to an initial voltage and a first reference voltage, amplifying and outputting the initial voltage and the first reference voltage, and converting the initial voltage into an initial current;

[0009] A current compensation module, whose input end is connected to the amplification module, performs current shunting on the initial current, mirrors the shunted initial compensation current N times to obtain a compensation current, and mirrors the initial compensation current multiple times to obtain a target current equal to the initial current;

[0010] A current source array module, comprising N triode current source branches arranged in parallel, connected to the amplification module and the current compensation module, and applying the compensation current to the output end of the amplification module so that the N triode current source branches output N target currents;

[0011] Wherein, N≥2, and N is an integer.

[0012] In one embodiment of the present invention, the transistor current source array also includes a feedback module, the input end of the feedback module is connected to the current source array module, the target current is mirrored to obtain a feedback voltage, and the feedback voltage is fed back to the input end of the amplification module through the feedback module.

[0013] In one embodiment of the present invention, the current compensation module includes a current source adjustment unit and a compensation current generating unit, the input end of the current source adjustment unit is connected to the non-phase input end of the amplification module, the current source adjustment unit performs current shunting on the initial current to obtain the initial compensation current, and performs multiple mirroring processes on the initial compensation current to make the target current equal to the initial current; the compensation current generating unit is connected to the current source adjustment unit, performs N times mirroring process on the initial compensation current to obtain the compensation current.

[0014] In one embodiment of the present invention, the current source regulating unit includes a first NPN transistor, a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a fifth PMOS transistor, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, and a fourth NMOS transistor. The source of the first PMOS transistor is connected to a first power supply voltage, the drain of the first PMOS transistor is connected to a gate of the first PMOS transistor, the source of the second PMOS transistor is connected to the source of the first PMOS transistor, the source of the third PMOS transistor is connected to the drain of the first PMOS transistor, the drain of the third PMOS transistor is connected to the gate of the third PMOS transistor, the drain of the third PMOS transistor is also connected to the base of the first NPN transistor, the source of the fourth PMOS transistor is connected to the drain of the second PMOS transistor, the gate of the fourth PMOS tube is connected to the gate of the third PMOS tube, and the drain of the fourth PMOS tube is connected to the base of the first NPN transistor. The gate of the fifth PMOS tube is connected to the drain of the fifth PMOS tube, the drain of the fifth PMOS tube is also connected to the drain of the first NMOS tube, the drain of the first NMOS tube is also connected to the gate of the first NMOS tube, the gate of the first NMOS tube is also connected to the gate of the second NMOS tube, the drain of the third NMOS tube is connected to the source of the first NMOS tube, the drain of the third NMOS tube is also connected to the gate of the third NMOS tube, the gate of the third NMOS tube is connected to the gate of the fourth NMOS tube, the drain of the fourth NMOS tube is connected to the source of the second NMOS tube, the source of the third NMOS tube is grounded, and the source of the fourth NMOS tube is grounded, wherein the collector of the first NPN transistor and the drain of the second NMOS tube are connected to the initial current, and the emitter of the first NPN transistor outputs the target current to the outside.

[0015] In one embodiment of the present invention, the compensation current generating unit includes a sixth PMOS tube, a seventh PMOS tube, and an eighth PMOS tube, the source of the sixth PMOS tube is connected to the first power supply voltage, the gate of the sixth PMOS tube is connected to the gate of the first PMOS tube, the drain of the sixth PMOS tube is connected to the source of the seventh PMOS tube, the gate of the seventh PMOS tube is connected to the gate of the third PMOS tube, the drain of the seventh PMOS tube is connected to the source of the eighth PMOS tube, and the gate of the eighth PMOS tube is connected to the drain of the eighth PMOS tube, wherein the drain of the eighth PMOS tube outputs the compensation current.

[0016] In one embodiment of the present invention, the driving end of the transistor current source branch is connected to the output end of the amplification module, and the transistor current source branch includes a second NPN transistor and a first resistor, the base of the second NPN transistor is connected to the output end of the amplification module, and the emitter of the second NPN transistor is grounded after passing through the first resistor, wherein the collector of the second NPN transistor outputs the target current to the outside.

[0017] In one embodiment of the present invention, the amplification module includes a third NPN transistor, a fourth NPN transistor, a fifth NPN transistor, a sixth NPN transistor, a seventh NPN transistor, a ninth PMOS transistor, a tenth PMOS transistor, an eleventh PMOS transistor, a twelfth PMOS transistor, a thirteenth PMOS transistor, a fourteenth PMOS transistor, a second resistor, a third resistor, a fourth resistor, and a fifth resistor. The source of the ninth PMOS transistor is connected to the second power supply voltage, the gate of the ninth PMOS transistor is connected to the drain of the ninth PMOS transistor, the drain of the ninth PMOS transistor is connected to the collector of the third NPN transistor, and the tenth PMOS transistor is connected to the collector of the ninth PMOS transistor. The source of the first PMOS tube is connected to the source of the ninth PMOS tube, the gate of the eleventh PMOS tube is connected to the drain of the eleventh PMOS tube, the drain of the eleventh PMOS tube is connected to the collector of the fourth NPN transistor, the base of the third NPN transistor is connected to the first end of the second resistor, the emitter of the fourth NPN transistor is connected to the emitter of the third NPN transistor, the emitter of the fourth NPN transistor is also connected to the collector of the fifth NPN transistor, the emitter of the fifth NPN transistor is grounded after passing through the third resistor, the source of the tenth PMOS tube is connected to the collector of the ninth PMOS tube The source of the tenth PMOS tube is connected to the gate of the ninth PMOS tube, the drain of the tenth PMOS tube is connected to the source of the thirteenth PMOS tube, the drain of the thirteenth PMOS tube is connected to the collector of the sixth NPN transistor, the collector of the sixth NPN transistor is connected to the base of the sixth NPN transistor, the emitter of the sixth NPN transistor is grounded after passing through the fourth resistor, the source of the twelfth PMOS tube is connected to the source of the ninth PMOS tube, the gate of the twelfth PMOS tube is connected to the gate of the eleventh PMOS tube, and the drain of the twelfth PMOS tube is connected to the fourteenth PMOS tube. The source of the MOS tube is connected to the collector of the seventh NPN transistor, the drain of the fourteenth PMOS tube is connected to the collector of the seventh NPN transistor, the base of the seventh NPN transistor is connected to the base of the sixth NPN transistor, and the emitter of the seventh NPN transistor is grounded after passing through the fifth resistor, wherein the base of the fourth NPN transistor is connected to the first reference voltage, the second end of the second resistor is connected to the initial voltage, the base of the fifth NPN transistor is connected to the second reference voltage, the base of the thirteenth PMOS tube and the base of the fourteenth PMOS tube are connected to the third reference voltage, and the drain of the fourteenth PMOS tube is the output end of the amplification module.

[0018] In one embodiment of the present invention, the feedback module includes an eighth NPN transistor, a fifteenth PMOS transistor, a sixteenth PMOS transistor, a fifth NMOS transistor, a sixth NMOS transistor, a sixth resistor, and a seventh resistor. The source of the fifteenth PMOS is connected to the third power supply voltage, the gate of the fifteenth PMOS is connected to the drain of the fifteenth PMOS, the drain of the fifteenth PMOS is connected to the collector of the eighth NPN transistor, the emitter of the eighth NPN transistor is grounded after passing through the sixth resistor, and the source of the sixteenth PMOS is connected to the fifteenth PMOS The gate of the sixteenth PMOS tube is connected to the gate of the fifteenth PMOS tube, the drain of the sixteenth PMOS tube is connected to the drain of the fifth NMOS tube, the drain of the fifth NMOS tube is also connected to the gate of the fifth NMOS tube, the gate of the fifth NMOS tube is grounded, the drain of the sixth NMOS tube is connected to the third power supply voltage after passing through the seventh resistor, the gate of the sixth NMOS tube is connected to the gate of the fifth NMOS tube, and the gate of the sixth NMOS tube is grounded, wherein the drain of the sixth NMOS tube outputs the feedback voltage.

[0019] According to a second aspect of an embodiment of the present application, a driving compensation method for a triode current source array is provided. The driving compensation method is applied to the triode current source array as described above, comprising:

[0020] Amplifying the primary voltage and the first reference voltage to obtain a driving voltage, and converting the primary voltage into an initial current;

[0021] Dividing the initial current to obtain an initial compensation current, and performing multiple mirroring processes on the initial compensation current to obtain a target current equal to the initial current;

[0022] Performing N-fold mirror processing on the initial compensation current to obtain a compensation current, and compensating the driving voltage by the compensation current, so as to generate N target currents by the adjusted driving voltage;

[0023] Wherein, N≥2, and N is an integer.

[0024] According to a third aspect of an embodiment of the present application, a digital-to-analog converter is also provided, which includes the transistor current source array as described above.

[0025] The present application provides a transistor current source array and a driving compensation method, and a digital-to-analog converter. The transistor current source array includes an amplification module, a current compensation module, and a current source array module. The input primary voltage and the first reference voltage are amplified and output by the amplification module; the initial current converted by the primary voltage is shunted by the current compensation module, and the shunted initial compensation current is mirrored multiple times to obtain a target current equal to the initial current, and the initial compensation current is mirrored N times to obtain a compensation current; the compensation current is applied to the output end of the amplification module so that the N parallel transistor current source branches in the current source array generate N target currents. The transistor current source array provided by the present application controls the current mirror multiple in the current compensation module to compensate for the influence of the base current of the corresponding number of transistors changing with temperature, avoids the base bias voltage in the transistor current source array fluctuating with the path, thereby improving the matching of the transistor current source array, which is beneficial to the performance improvement of the digital-to-analog converter.

[0026] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] The drawings herein are incorporated into the specification and constitute a part of the specification, showing embodiments consistent with the present invention, and together with the specification, are used to explain the principles of the present invention. Obviously, the drawings described below are only some embodiments of the present invention, and for those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative work. In the drawings:

[0028] Figure 1 is a block diagram of a triode current source array shown in an exemplary embodiment of the present invention;

[0029] Figure 2 is a block diagram of a transistor current source array including a feedback module shown in an exemplary embodiment of the present invention;

[0030] Figure 3 is a specific circuit structure diagram of a triode current source array shown in an exemplary embodiment of the present invention;

[0031] Figure 4 It is a specific circuit structure diagram of an amplification module shown in an exemplary embodiment of the present invention. DETAILED DESCRIPTION

[0032] The following will describe the embodiments of the present invention with reference to the accompanying drawings and preferred embodiments. Those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention. It should be understood that the preferred embodiments are only for illustrating the present invention, not for limiting the scope of protection of the present invention.

[0033] It should be noted that the illustrations provided in the following embodiments are only schematic illustrations of the basic concept of the present invention, and thus the drawings only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0034] In the following description, numerous details are discussed to provide a more thorough explanation of the embodiments of the present invention. However, it is obvious to those skilled in the art that the embodiments of the present invention can be implemented without these specific details. In other embodiments, well-known structures and devices are shown in the form of block diagrams rather than in detail to avoid making the embodiments of the present invention difficult to understand.

[0035] MOS tube (MOSFET) is a voltage-controlled semiconductor device with the advantages of high input resistance, low noise, low power consumption, large dynamic range, and easy integration. It is a type of field effect tube that controls the current in the output circuit by controlling the electric field effect of the input circuit. MOS tubes are usually used for switching and amplification functions in electronic circuits.

[0036] As described in the background technology, in the design of a current output type high-precision digital-to-analog converter, the function implemented is to output a current output signal that is proportional to the digital signal input. Usually, MOS tubes or bipolar transistors are used internally to construct a current source array to achieve this function. Compared with using MOS tubes to construct a current source array, the advantages of using transistors to construct a current source array are mainly: first, the output swing is less restricted; second, when the same current flows, the noise of the transistor is relatively low; third, the design is relatively simpler.

[0037] However, the problem when using transistors as current source arrays in actual design is that the output impedance of the transistors is small, which will affect the integral nonlinearity (INL) and spurious-free dynamic range (SFDR) of the digital-to-analog converter. At the same time, since there is current in the base, which is 1 / β of the collector current, requirements are also put forward for the driving capability of the base voltage.

[0038] To solve the above problems, Figure 1 As shown, the present application provides a triode current source array, comprising:

[0039] Amplifier module, connected to the primary voltage V0 and the first reference voltage V REF1 , the primary voltage V0 and the first reference voltage V REF1 Amplify and output, and convert the initial voltage V0 into the initial current I0;

[0040] The current compensation module, whose input terminal is connected to the amplifier module, performs current shunting on the initial current I0, and performs N-fold mirroring on the shunted initial compensation current to obtain the compensation current I comp , and the initial compensation current is mirrored multiple times to obtain a target current I equal to the initial current S1 ;

[0041] The current source array module includes N parallel transistor current source branches, connected to the amplification module and the current compensation module, and applies the compensation current to the output end of the amplification module so that the N transistor current source branches output N target power supplies I S1 ~I SN ;

[0042] Wherein, N≥2, and N is an integer.

[0043] In detail, Figure 2 As shown, the transistor current source array also includes a feedback module, the input end of the feedback module is connected to the current source array module, and the target current is mirrored to obtain a feedback voltage V FB , the feedback voltage V FB Feedback to the input of the amplifier module.

[0044] In detail, the current compensation module includes a current source adjustment unit and a compensation current generating unit. The input end of the current source adjustment unit is connected to the positive phase input end of the amplification module. The current source adjustment unit performs current shunting on the initial current I0 to obtain the initial compensation current, and performs multiple mirroring processes on the initial compensation current to make the target current I S1 = equal to the initial current I0; the compensation current generating unit is connected to the current source regulating unit, and the initial compensation current is mirrored N times to obtain the compensation current Icomp .

[0045] In more detail, Figure 3 As shown, the current source regulating unit includes a first NPN transistor Q1, a first PMOS transistor M1, a second PMOS transistor M2, a third PMOS transistor M3, a fourth PMOS transistor M4, a fifth PMOS transistor M5, a first NMOS transistor N1, a second NMOS transistor N2, a third NMOS transistor N3, and a fourth NMOS transistor N4. The source of the first PMOS transistor M1 is connected to the first power supply voltage VCC1, the drain of the first PMOS transistor M1 is connected to the gate of the first PMOS transistor M1, the source of the second PMOS transistor M2 is connected to the source of the first PMOS transistor M1, the source of the third PMOS transistor M3 is connected to the drain of the first PMOS transistor M1, the drain of the third PMOS transistor M3 is connected to the gate of the third PMOS transistor M3, the drain of the third PMOS transistor M3 is also connected to the base of the first NPN transistor Q1, the source of the fourth PMOS transistor M4 is connected to the drain of the second PMOS transistor M2, the gate of the fourth PMOS transistor M4 is connected to the gate of the third PMOS transistor M3, and the fourth PMOS transistor M5 is connected to the base of the first NPN transistor Q1. The drain of the OS transistor M4 is connected to the source of the fifth PMOS transistor M5, the gate of the fifth PMOS transistor M5 is connected to the drain of the fifth PMOS transistor M5, the drain of the fifth PMOS transistor M5 is also connected to the drain of the first NMOS transistor N1, the drain of the first NMOS transistor N1 is also connected to the gate of the first NMOS transistor N1, the gate of the first NMOS transistor N1 is also connected to the gate of the second NMOS transistor N2, the drain of the third NMOS transistor N3 is connected to the source of the first NMOS transistor N1, the drain of the third NMOS transistor N3 is also connected to the gate of the third NMOS transistor N3, the gate of the third NMOS transistor N3 is connected to the gate of the fourth NMOS transistor N4, the drain of the fourth NMOS transistor N4 is connected to the source of the second NMOS transistor N2, the source of the third NMOS transistor N3 is grounded, and the source of the fourth NMOS transistor N4 is grounded, wherein the collector of the first NPN transistor Q1 and the drain of the second NMOS transistor N2 are connected to the initial current I0, and the emitter of the first NPN transistor Q1 outputs the target current I S1 .

[0046] In more detail, Figure 3 As shown, the compensation current generating unit includes a sixth PMOS tube M6, a seventh PMOS tube M7, and an eighth PMOS tube M8. The source of the sixth PMOS tube M6 is connected to the first power supply voltage VCC1, the gate of the sixth PMOS tube M6 is connected to the gate of the first PMOS tube M1, the drain of the sixth PMOS tube M6 is connected to the source of the seventh PMOS tube M7, the gate of the seventh PMOS tube M7 is connected to the gate of the third PMOS tube M3, the drain of the seventh PMOS tube M7 is connected to the source of the eighth PMOS tube M8, and the gate of the eighth PMOS tube M8 is connected to the drain of the eighth PMOS tube M8, wherein the drain of the eighth PMOS tube M8 outputs the compensation current I comp .

[0047] In detail, Figure 3 As shown, the driving end of the transistor current source branch is connected to the output end of the amplifier module, the transistor current source branch includes a second NPN transistor Q2i and a first resistor R1i, the base of the second NPN transistor Q2i is connected to the output end of the amplifier module, the emitter of the second NPN transistor Q2i is grounded after passing through the first resistor R1i, wherein the collector of the second NPN transistor Q2i outputs the target current I Si , where i is a positive integer, 1≤i≤N, and N is the number of transistor current source branches.

[0048] In detail, the amplification module includes a third NPN transistor Q3, a fourth NPN transistor Q4, a fifth NPN transistor Q5, a sixth NPN transistor Q6, a seventh NPN transistor Q7, a ninth PMOS transistor M9, a tenth PMOS transistor M10, an eleventh PMOS transistor M11, a twelfth PMOS transistor M12, a thirteenth PMOS transistor M13, a fourteenth PMOS transistor M14, a second resistor R2, a third resistor R3, a fourth resistor R4, and a fifth resistor R5. The source of the ninth PMOS transistor M9 is connected to the second power supply voltage VCC2, and the gate of the ninth PMOS transistor M9 is connected to the second power supply voltage VCC2. The drain of the ninth PMOS tube M9 is connected to the collector of the third NPN transistor Q3, the source of the eleventh PMOS tube M11 is connected to the source of the ninth PMOS tube M9, the gate of the eleventh PMOS tube M11 is connected to the drain of the eleventh PMOS tube M11, the drain of the eleventh PMOS tube M11 is connected to the collector of the fourth NPN transistor Q4, the base of the third NPN transistor Q4 is connected to the first end of the second resistor R2, the emitter of the fourth NPN transistor Q4 is connected to the emitter of the third NPN transistor, and the emitter of the fourth NPN transistor Q4 is also connected to the fifth The collector of the NPN transistor Q5, the emitter of the fifth NPN transistor Q5 is grounded after passing through the third resistor R3, the source of the tenth PMOS transistor M10 is connected to the source of the ninth PMOS transistor M9, the gate of the tenth PMOS transistor M10 is connected to the gate of the ninth PMOS transistor M9, the drain of the tenth PMOS transistor M10 is connected to the source of the thirteenth PMOS transistor M13, the drain of the thirteenth PMOS transistor M13 is connected to the collector of the sixth NPN transistor Q6, the collector of the sixth NPN transistor Q6 is connected to the base of the sixth NPN transistor Q6, and the emitter of the sixth NPN transistor Q6 is connected to the fourth resistor R 4 is connected to ground, the source of the twelfth PMOS tube M12 is connected to the source of the ninth PMOS tube M9, the gate of the twelfth PMOS tube M12 is connected to the gate of the eleventh PMOS tube M11, the drain of the twelfth PMOS tube M12 is connected to the source of the fourteenth PMOS tube M14, the drain of the fourteenth PMOS tube M14 is connected to the collector of the seventh NPN transistor Q7, the base of the seventh NPN transistor Q7 is connected to the base of the sixth NPN transistor Q6, the emitter of the seventh NPN transistor Q7 is connected to ground via the fifth resistor R5, wherein the base of the fourth NPN transistor Q3 is connected to the first reference voltage V REF1 The second end of the second resistor R2 is connected to the initial voltage V0, and the base of the fifth NPN transistor Q5 is connected to the second reference voltage V REF2 The base of the thirteenth PMOS tube M13 and the base of the fourteenth PMOS tube M14 are connected to the third reference voltage V REF3 The drain of the fourteenth PMOS tube M14 is the output end of the amplifier module, and the output end of the amplifier module outputs a driving voltage V D .

[0049] In more detail, the feedback module includes an eighth NPN transistor Q8, a fifteenth PMOS transistor M15, a sixteenth PMOS transistor M16, a fifth NMOS transistor N5, a sixth NMOS transistor N6, a sixth resistor R6, and a seventh resistor R7. The source of the fifteenth PMOS transistor M15 is connected to the third power supply voltage VCC3, the gate of the fifteenth PMOS transistor M15 is connected to the drain of the fifteenth PMOS transistor M15, the drain of the fifteenth PMOS transistor M15 is connected to the collector of the eighth NPN transistor Q8, the emitter of the eighth NPN transistor Q8 is grounded after passing through the sixth resistor R6, and the source of the sixteenth PMOS transistor M16 is connected to the tenth The source of the fifth PMOS tube M15, the gate of the sixteenth PMOS tube M16 is connected to the gate of the fifteenth PMOS tube M15, the drain of the sixteenth PMOS tube M16 is connected to the drain of the fifth NMOS tube N5, the drain of the fifth NMOS tube N5 is also connected to the gate of the fifth NMOS tube N5, the gate of the fifth NMOS tube N5 is grounded, the drain of the sixth NMOS tube N6 is connected to the third power supply voltage VCC3 through the seventh resistor R7, the gate of the sixth NMOS tube N6 is connected to the gate of the fifth NMOS tube N5, and the gate of the sixth NMOS tube N6 is grounded, wherein the drain of the sixth NMOS tube N6 outputs a feedback voltage V FB .

[0050] like Figures 1 to 4 As shown, the working principle of the triode current source array provided by the present application is as follows:

[0051] Combination Figure 1 to Figure 2 As shown, the initial voltage V0 and the first reference voltage V REF1 Amplify the drive voltage V D , the input initial voltage V0 is converted into an initial current I0, the current compensation module divides the initial current I0 into two currents, thereby obtaining an initial compensation current, and the initial compensation current is mirrored multiple times to obtain a target current I S1 Equal to the initial current I0; the initial compensation current is mirrored N times through the mirror structure to obtain the compensation current I comp , the compensation current I comp Acting on the output end of the amplifier module to increase the drive of the transistor base in the current source array module, so that the N transistor current source branches arranged in parallel in the current source array module output N target currents I S1 ~I SN The feedback module performs mirror processing on the target current to obtain the feedback voltage V FB , the feedback voltage is fed back to the non-inverting input terminal of the amplifier module to improve the stability of the transistor current source array.

[0052] like Figure 4As shown, the positive phase input terminal of the amplifier module is connected to the initial voltage V0 through the second resistor R2, and the amplifier module is a fully symmetrical structure. The base of the fifth NPN transistor Q5 is connected to the second reference voltage V REF2 , providing a current source for the operational amplifier. The input pair of tubes is a pair of bipolar transistors, whose collectors are connected to the drain terminals of another pair of PMOS tubes. The PMOS tubes form a current mirror structure, which is connected to the output terminal through the current gain. A set of current mirror structures with a gain of 2 is formed at the load part of the output terminal, thereby realizing the input initial voltage V0 and the first reference voltage V REF1 Amplification processing.

[0053] like Figure 4 As shown, the current flowing through the second resistor R2 is the initial current I0. Figure 3 As shown, the input terminal of the current source regulating unit is connected to the initial current I0, and the primary current I0 is shunted by the second NMOS transistor N2 and the first NPN transistor Q1; suppose: the collector current flowing through the first NPN transistor Q1 is I C1 , the initial compensation current of the base of the first NPN transistor Q1 is I B1 , the drain current of the second NMOS tube N2 is I D2 The initial compensation current is replicated by two 1:1 mirror structures formed by the third NMOS tube M3 and the fourth NMOS tube M4, the first NMOS tube N1 and the second NMOS tube N2, so that the current I flowing through the gate of the second NMOS tube N2 is G2 Equal to the initial compensation current I B1 , eliminating the influence of the base current of the first NPN transistor Q1, so that the target current output by the emitter of the first NPN transistor Q1 is I S1 =I C1 +I B1 =I G2 +I D2 =I0.

[0054] The current source array module has N transistor current source branches arranged in parallel, and the emitter of the second NPN transistor Q2i in each transistor current source branch is connected in series with the second resistor R2i to form feedback, so that the output impedance is increased by gmRs times.

[0055] The compensation current generating unit generates the initial compensation current I through the mirror structure formed by the third NMOS tube M3 and the seventh NMOS tube M7. B1 Perform N-fold mirror processing, the current mirror amplification multiple is the same as the number of the second NPN transistors Q2i in the current source array module, so that the drain of the eighth NMOS tube outputs the compensation current I comp .

[0056] In a second aspect of the present application, the present application further provides a compensation driving method applied to the triode current source array as described above, the method comprising:

[0057] The primary voltage V0 and the first reference voltage V REF1 Amplify the drive voltage V D , and convert the primary voltage V0 into the initial current I0;

[0058] The initial current is shunted to obtain the initial compensation current, and the initial compensation current is mirrored multiple times to obtain the target current I equal to the initial current. S1 ;

[0059] Perform N-fold mirror processing on the initial compensation current to obtain the compensation current I comp , and compensate the driving voltage V by compensating the current D , by adjusting the drive voltage V D Generate N target currents;

[0060] Wherein, N≥2, and N is an integer.

[0061] In a third aspect of the present application, the present application further provides a digital-to-analog converter, which includes the transistor current source array as described above to improve the stability of the digital-to-analog converter.

[0062] The present application provides a transistor current source array and a driving compensation method, and a digital-to-analog converter. The transistor current source array includes an amplification module, a current compensation module, and a current source array module. The input primary voltage and a first reference voltage are amplified and output by the amplification module; the initial current converted by the primary voltage is subjected to multiple mirror processing by the current compensation module to generate a target current equal to the initial current, and N times mirror processing is performed to obtain a compensation current; the compensation current is applied to the output end of the amplification module so that N parallel transistor current source branches in the current source array generate N target currents, and the transistor emitter in each transistor current source branch is connected in series with a resistor. The transistor current source array provided by the present application controls the current mirror multiple in the current compensation module to compensate for the influence of the base current of the corresponding number of transistors changing with temperature, avoids the base bias voltage in the transistor current source array fluctuating with the path, and adopts a resistor series feedback method to improve the output impedance, thereby improving the matching of the current source array, which is beneficial to the performance improvement of the digital-to-analog converter.

[0063] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the technology may modify or change the above embodiments without violating the spirit and scope of the present invention. Therefore, all equivalent modifications or changes made by a person of ordinary skill in the art without departing from the spirit and technical ideas disclosed by the present invention shall still be covered by the claims of the present invention.

Claims

1. A triode current source array, characterized in that: include: an amplification module, connected to an initial voltage and a first reference voltage, amplifying and outputting the initial voltage and the first reference voltage, and converting the initial voltage into an initial current; A current compensation module, whose input end is connected to the amplification module, performs current shunting on the initial current, mirrors the shunted initial compensation current N times to obtain a compensation current, and mirrors the initial compensation current multiple times to obtain a target current equal to the initial current; A current source array module, comprising N triode current source branches arranged in parallel, connected to the amplification module and the current compensation module, and applying the compensation current to the output end of the amplification module so that the N triode current source branches output N target currents; Wherein, N≥2, and N is an integer.

2. The transistor current source array according to claim 1, characterized in that: The transistor current source array also includes a feedback module, the input end of the feedback module is connected to the current source array module, the target current is mirrored to obtain a feedback voltage, and the feedback voltage is fed back to the input end of the amplification module through the feedback module.

3. The transistor current source array according to claim 1, characterized in that: The current compensation module includes a current source adjustment unit and a compensation current generating unit, the input end of the current source adjustment unit is connected to the non-phase input end of the amplification module, the current source adjustment unit performs current shunting on the initial current to obtain the initial compensation current, and performs multiple mirroring processes on the initial compensation current to make the target current equal to the initial current; The compensation current generating unit is connected to the current source regulating unit, and performs N-fold mirror processing on the initial compensation current to obtain the compensation current.

4. The transistor current source array according to claim 3, characterized in that: The current source regulating unit includes a first NPN transistor, a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a fifth PMOS transistor, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, and a fourth NMOS transistor. The source of the first PMOS transistor is connected to a first power supply voltage, the drain of the first PMOS transistor is connected to a gate of the first PMOS transistor, the source of the second PMOS transistor is connected to the source of the first PMOS transistor, the source of the third PMOS transistor is connected to the drain of the first PMOS transistor, the drain of the third PMOS transistor is connected to the gate of the third PMOS transistor, the drain of the third PMOS transistor is also connected to the base of the first NPN transistor, the source of the fourth PMOS transistor is connected to the drain of the second PMOS transistor, the gate of the fourth PMOS tube is connected to the gate of the third PMOS tube, and the drain of the fourth PMOS tube is connected to the base of the fifth NPN transistor. The source of the PMOS tube is connected to the gate of the fifth PMOS tube, the gate of the fifth PMOS tube is connected to the drain of the fifth PMOS tube, the drain of the fifth PMOS tube is also connected to the drain of the first NMOS tube, the drain of the first NMOS tube is also connected to the gate of the first NMOS tube, the gate of the first NMOS tube is also connected to the gate of the second NMOS tube, the drain of the third NMOS tube is connected to the source of the first NMOS tube, the drain of the third NMOS tube is also connected to the gate of the third NMOS tube, the gate of the third NMOS tube is connected to the gate of the fourth NMOS tube, the drain of the fourth NMOS tube is connected to the source of the second NMOS tube, the source of the third NMOS tube is grounded, and the source of the fourth NMOS tube is grounded, wherein the collector of the first NPN transistor and the drain of the second NMOS tube are connected to the initial current, and the emitter of the first NPN transistor outputs the target current to the outside.

5. The transistor current source array according to claim 4, characterized in that: The compensation current generating unit includes a sixth PMOS tube, a seventh PMOS tube, and an eighth PMOS tube, wherein the source of the sixth PMOS tube is connected to the first power supply voltage, the gate of the sixth PMOS tube is connected to the gate of the first PMOS tube, the drain of the sixth PMOS tube is connected to the source of the seventh PMOS tube, the gate of the seventh PMOS tube is connected to the gate of the third PMOS tube, the drain of the seventh PMOS tube is connected to the source of the eighth PMOS tube, and the gate of the eighth PMOS tube is connected to the drain of the eighth PMOS tube, wherein the drain of the eighth PMOS tube outputs the compensation current.

6. The transistor current source array according to claim 1, characterized in that: The driving end of the transistor current source branch is connected to the output end of the amplification module, and the transistor current source branch includes a second NPN transistor and a first resistor. The base of the second NPN transistor is connected to the output end of the amplification module, and the emitter of the second NPN transistor is grounded after passing through the first resistor, wherein the collector of the second NPN transistor outputs the target current to the outside.

7. The transistor current source array according to claim 1, characterized in that: The amplification module includes a third NPN transistor, a fourth NPN transistor, a fifth NPN transistor, a sixth NPN transistor, a seventh NPN transistor, a ninth PMOS transistor, a tenth PMOS transistor, an eleventh PMOS transistor, a twelfth PMOS transistor, a thirteenth PMOS transistor, a fourteenth PMOS transistor, a second resistor, a third resistor, a fourth resistor, and a fifth resistor. The source of the ninth PMOS transistor is connected to the second power supply voltage, the gate of the ninth PMOS transistor is connected to the drain of the ninth PMOS transistor, the drain of the ninth PMOS transistor is connected to the collector of the third NPN transistor, and the source of the eleventh PMOS transistor is connected to the collector of the third NPN transistor. The gate of the eleventh PMOS tube is connected to the source of the ninth PMOS tube, the gate of the eleventh PMOS tube is connected to the drain of the eleventh PMOS tube, the drain of the eleventh PMOS tube is connected to the collector of the fourth NPN transistor, the base of the third NPN transistor is connected to the first end of the second resistor, the emitter of the fourth NPN transistor is connected to the emitter of the third NPN transistor, the emitter of the fourth NPN transistor is also connected to the collector of the fifth NPN transistor, the emitter of the fifth NPN transistor is grounded after passing through the third resistor, the source of the tenth PMOS tube is connected to the source of the ninth PMOS tube, and the The gate of the tenth PMOS tube is connected to the gate of the ninth PMOS tube, the drain of the tenth PMOS tube is connected to the source of the thirteenth PMOS tube, the drain of the thirteenth PMOS tube is connected to the collector of the sixth NPN transistor, the collector of the sixth NPN transistor is connected to the base of the sixth NPN transistor, the emitter of the sixth NPN transistor is grounded after passing through the fourth resistor, the source of the twelfth PMOS tube is connected to the source of the ninth PMOS tube, the gate of the twelfth PMOS tube is connected to the gate of the eleventh PMOS tube, and the drain of the twelfth PMOS tube is connected to the fourteenth PMOS The source of the transistor is connected to the drain of the fourteenth PMOS transistor, the drain of the fourteenth PMOS transistor is connected to the collector of the seventh NPN transistor, the base of the seventh NPN transistor is connected to the base of the sixth NPN transistor, and the emitter of the seventh NPN transistor is grounded after passing through the fifth resistor, wherein the base of the fourth NPN transistor is connected to the first reference voltage, the second end of the second resistor is connected to the initial voltage, the base of the fifth NPN transistor is connected to the second reference voltage, the base of the thirteenth PMOS tube and the base of the fourteenth PMOS tube are connected to the third reference voltage, and the drain of the fourteenth PMOS tube is the output end of the amplification module.

8. The transistor current source array according to claim 2, characterized in that: The feedback module includes an eighth NPN transistor, a fifteenth PMOS transistor, a sixteenth PMOS transistor, a fifth NMOS transistor, a sixth NMOS transistor, a sixth resistor, and a seventh resistor. The source of the fifteenth PMOS transistor is connected to a third power supply voltage, the gate of the fifteenth PMOS transistor is connected to the drain of the fifteenth PMOS transistor, the drain of the fifteenth PMOS transistor is connected to the collector of the eighth NPN transistor, the emitter of the eighth NPN transistor is grounded after passing through the sixth resistor, and the source of the sixteenth PMOS transistor is connected to the source of the fifteenth PMOS transistor. The gate of the sixteenth PMOS tube is connected to the gate of the fifteenth PMOS tube, the drain of the sixteenth PMOS tube is connected to the drain of the fifth NMOS tube, the drain of the fifth NMOS tube is also connected to the gate of the fifth NMOS tube, the gate of the fifth NMOS tube is grounded, the drain of the sixth NMOS tube is connected to the third power supply voltage through the seventh resistor, the gate of the sixth NMOS tube is connected to the gate of the fifth NMOS tube, and the gate of the sixth NMOS tube is grounded, wherein the drain of the sixth NMOS tube outputs the feedback voltage.

9. A driving compensation method applied to a transistor current source array as claimed in any one of claims 1 to 8, characterized in that: include; Amplifying the primary voltage and the first reference voltage to obtain a driving voltage, and converting the primary voltage into an initial current; Dividing the initial current to obtain an initial compensation current, and performing multiple mirroring processes on the initial compensation current to obtain a target current equal to the initial current; Performing N-fold mirror processing on the initial compensation current to obtain a compensation current, and compensating the driving voltage by the compensation current, so as to generate N target currents by the adjusted driving voltage; Wherein, N≥2, and N is an integer.

10. A digital-to-analog converter, characterized in that: The digital-to-analog converter includes a transistor current source array as claimed in any one of claims 1 to 8.

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