Data storage method, data loading method, device, electronic equipment and medium

Abstract

The application provides a data storage method, a data loading method, a device, an electronic device and a medium, and relates to the technical field of data processing. The data storage method comprises the following steps: receiving a storage instruction, wherein the storage instruction is used for instructing to store data content in at least two vector registers to a storage, and any vector register has at least one data channel; in response to the storage instruction, splicing the data content in the data channels with the same channel identifier in the at least two vector registers to obtain vector data corresponding to each channel identifier; and storing the vector data to the storage. By splicing the data content in the data channels with the same channel identifier to obtain the vector data, and then storing the vector data to the storage, the number of access times of the storage can be reduced, and the storage efficiency is improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of data processing, and particularly relates to a data storage method, a data loading method, a device, an electronic device and a medium. BACKGROUND

[0002] In a Single Instruction, Multiple Threads (SIMT) architecture processor, a Vector Load / Store Unit (VLSU) is mainly responsible for moving data between a vector register and a memory. Specifically, the VLSU supports storage (writing data from a vector register to a memory) and loading (reading data from a memory to a vector register) operations of vector data.

[0003] However, in actual applications, there are often cases of storing / loading vector data across multiple vector registers. The increase in the number of vector registers affects the storage / loading efficiency of vector data. Therefore, how to improve the storage / loading efficiency of vector data has become an important technical problem. SUMMARY

[0004] The present application aims to at least solve one of the technical problems in the related art to some extent.

[0005] To this end, the present application provides a data storage method, a data loading method, a device, an electronic device and a medium to realize the storage of vector data by splicing data content in the same data channel identified by a channel, and to store the vector data into a memory, thereby reducing the access frequency of the memory and improving the storage efficiency.

[0006] An embodiment of the present application provides a data storage method, comprising:

[0007] receiving a storage instruction, the storage instruction being used to indicate the storage of data content in at least two vector registers into a memory, any of the vector registers having at least one data channel;

[0008] in response to the storage instruction, splicing the data content in the data channels identified by the same channel in the at least two vector registers to obtain vector data corresponding to each of the channels identified;

[0009] storing the vector data into the memory.

[0010] Another embodiment of the present application provides a data loading method, comprising:

[0011] receive a load instruction, the load instruction being used to indicate to load vector data in a memory into at least two vector registers, any of the vector registers having multiple data lanes;

[0012] in response to the load instruction, content split the vector data to obtain corresponding data contents;

[0013] load the vector data corresponding data contents into the at least two vector registers in data lanes with same lane identifier.

[0014] Another aspect of the present application provides a data storage device, comprising:

[0015] a receiving module, configured to receive a store instruction, the store instruction being used to indicate to store data contents in at least two vector registers into a memory, any of the vector registers having at least one data lane;

[0016] a splicing module, configured to splice the data contents in the at least two vector registers in data lanes with same lane identifier to obtain vector data corresponding to each of the lane identifiers in response to the store instruction;

[0017] a storing module, configured to store the vector data into the memory.

[0018] Another aspect of the present application provides a data loading device, comprising:

[0019] a receiving module, configured to receive a load instruction, the load instruction being used to indicate to load vector data in a memory into at least two vector registers, any of the vector registers having multiple data lanes;

[0020] a splitting module, configured to split the vector data to obtain corresponding data contents in response to the load instruction;

[0021] a loading module, configured to load the vector data corresponding data contents into the at least two vector registers in data lanes with same lane identifier.

[0022] Another aspect of the present application provides an electronic device, comprising a memory, a processor, and a computer program stored in the memory and capable of running on the processor, when the processor executes the program, the data storage method of the foregoing aspect or the data loading method of another aspect is implemented.

[0023] Another aspect of the present application provides a chip, comprising a processing circuit, the processing circuit being used to execute the data storage method of the foregoing aspect or the data loading method of another aspect.

[0024] Another aspect of the present application provides a non-transitory computer readable storage medium having stored thereon a computer program which, when executed by a processor, implements the data storage method of the preceding aspect or the data loading method of another aspect.

[0025] Another aspect of the present application provides a computer program product having stored thereon a computer program which, when executed by a processor, implements the data storage method of the preceding aspect or the data loading method of another aspect.

[0026] The data storage method, the data loading method, the device, the electronic equipment and the medium provided by the present application receive a storage instruction, the storage instruction is used to indicate to store data content in at least two vector registers to a memory, any vector register has at least one data channel; in response to the storage instruction, the data content in the data channel with the same channel identifier in the at least two vector registers is spliced to obtain the vector data corresponding to each channel identifier; and the vector data is stored to the memory. Wherein, the vector data is obtained by splicing the data content in the data channel with the same channel identifier, and then the vector data is stored to the memory, so that the access frequency of the memory can be reduced, and the storage efficiency can be improved.

[0027] Additional aspects and advantages of the present application will be in part apparent and in part pointed out hereinafter. BRIEF DESCRIPTION OF DRAWINGS

[0028] The above and / or additional aspects and advantages of the present application will become apparent and be readily appreciated from the following description, taken in conjunction with the accompanying drawings, in which:

[0029] Figure 1 A flowchart of a data storage method provided by an embodiment of the present application;

[0030] Figure 2 A flowchart of another data storage method provided by an embodiment of the present application;

[0031] Figure 3 A flowchart of another data storage method provided by an embodiment of the present application;

[0032] Figure 4 A flowchart of a data storage process provided by an embodiment of the present application;

[0033] Figure 5 Another flowchart of a data storage process provided by an embodiment of the present application;

[0034] Figure 6 A flowchart of a data loading method provided by an embodiment of the present application;

[0035] Figure 7 Another data loading method provided by an embodiment of the present application is shown in the flowchart below.

[0036] Figure 8 A flowchart of a data loading process provided by an embodiment of the present application is shown in the flowchart below.

[0037] Figure 9 Another flowchart of a data loading process provided by an embodiment of the present application is shown in the flowchart below.

[0038] Figure 10 A structural diagram of a data storage device provided by an embodiment of the present application is shown in the structural diagram below.

[0039] Figure 11 A structural diagram of a data loading device provided by an embodiment of the present application is shown in the structural diagram below.

[0040] Figure 12 A block diagram of an electronic device provided by an embodiment of the present application is shown in the block diagram below. DETAILED DESCRIPTION

[0041] Embodiments of the present application are described in detail below with reference to the accompanying drawings, in which the same or similar components have the same or similar reference numbers throughout. The embodiments described below are exemplary and are intended to explain the present application, and should not be understood as limiting the present application.

[0042] The storage layout of vector data in a vector register includes compact and fixed-length types, where the fixed-length type layout refers to a vector register being divided into a fixed number of data lanes (Lanes), such as 32 / 64, and the available bit width of each Lane is also fixed. If the data type bit width does not exceed the allocated bit width of a single Lane of the vector register, the data is stored from the lowest bit, and the high bits are idle. If the data type bit width is greater than the allocated bit width of a single Lane of the vector register, multiple vector registers are used, and the Lanes with the same number in the multiple vector registers are combined to store the data. For example, the bit width of a vector register is 1024 bits, and it is fixedly divided into 32 Lanes, and each Lane is allocated 32 bits: if the data type is 8 bits, each data only exists in the low 8 bits of each Lane of the vector register, and the high 24 bits are idle, and a total of 32 data are stored; if the data type is 64 bits, 2 vector registers are used, and the high and low 32 bits of the data are stored in the Lanes with the same number in the 2 vector registers, respectively.

[0043] For the case that the bit width of the data type is greater than the allocation bit width of a single Lane of the vector register, in the related technology, the instruction is split according to the number of vector registers, for example, a 128-bit data type, a single instruction accesses four vector registers, taking a storage process as an example, a single thread (Thread) needs to access the same number of Lanes of the four vector registers in the storage instruction, and the storage instruction is split into four sub-instructions, and the thread needs to access the memory multiple times in response to the four sub-instructions to complete the storage of the vector data. In summary, the foregoing manner is low in storage / load efficiency of the vector data.

[0044] To solve the above problems, the present application provides a data storage method, a data loading method, a device, an electronic device and a medium. The data storage method, the data loading method, the device, the electronic device and the medium of the embodiments of the present application are described below with reference to the drawings.

[0045] Figure 1 A flowchart of a data storage method provided by an embodiment of the present application is shown. It should be noted that the data storage method of the present embodiment can be applied to a data storage device. In some possible embodiments, the device can be configured in an electronic device or a chip, so that the electronic device or the chip can perform a data storage function. In addition, in some possible embodiments, the data storage device can also be software in an electronic device. For example, data storage software and the like. In addition, the data storage device can also be a VLSU in an electronic device. In the following embodiments, the execution subject is taken as an example to illustrate the VLSU.

[0046] As shown in Figure 1 The method can include the following steps:

[0047] Step 101, receiving a storage instruction, the storage instruction being used to indicate that the data content in at least two vector registers is stored to a memory, and any vector register having at least one data channel.

[0048] The storage instruction can be used to indicate the source position of the data content in the vector register and the storage position of the data content in the memory. It should be noted that after receiving the storage instruction, the storage instruction can be decoded first.

[0049] The data channel has a channel identifier, which can include a channel number, a channel code, etc.; and the data channels at the same position in the at least two vector registers have the same channel identifier.

[0050] In an embodiment of the present disclosure, the data content in the at least two vector registers can indicate the data of the same thread.

[0051] Step 102: In response to the storage instruction, the data contents of data channels with the same channel identifier in at least two vector registers are concatenated to obtain vector data corresponding to each channel identifier.

[0052] In this context, the data content in the data channels with the same channel identifier in at least two vector registers constitutes a vector data, and the data content in at least two vector registers can correspond to at least one vector data.

[0053] It should be noted that vector data is stored in at least two vector registers, which means that the bit width of vector data is greater than the allocated bit width of a single data channel in a vector register.

[0054] Step 103: Store the vector data in memory.

[0055] Specifically, the vector data and its storage location in the memory can be sent to the memory so that the memory can store the vector data according to the storage location indicated by the storage instruction.

[0056] In this embodiment, a vector data only needs to access the memory once, eliminating the need to access the memory multiple times for the data content included in the vector data, thereby improving data storage efficiency.

[0057] In the data storage method of this application embodiment, a storage instruction is received, which instructs the data contents of at least two vector registers to be stored in memory, each vector register having at least one data channel; in response to the storage instruction, the data contents of data channels with the same channel identifier in at least two vector registers are concatenated to obtain vector data corresponding to each channel identifier; and the vector data is stored in memory. By concatenating the data contents of data channels with the same channel identifier to obtain vector data, and then storing the vector data in memory, the number of memory accesses can be reduced, improving storage efficiency.

[0058] Based on the above embodiments, Figure 2 This is a flowchart illustrating another data storage method provided in an embodiment of this application. It should be noted that the data storage method of this embodiment can be applied to a data storage device. In some possible embodiments, the device can be configured in an electronic device or a chip, enabling the electronic device or chip to perform data storage functions. Additionally, in some possible embodiments, the data storage device can also be software within an electronic device. For example, data storage software. Furthermore, the data storage device can also be a VLSU within an electronic device. In the following embodiments, the execution entity is described using a VLSU as an example.

[0059] like Figure 2 As shown, the method includes the following steps:

[0060] Step 201, receiving a storage instruction.

[0061] Step 202, in response to the storage instruction, splicing data contents in data channels identified by the same channel identifier in at least two vector registers to obtain vector data corresponding to each channel identifier.

[0062] Wherein, the relevant explanations in the foregoing embodiments also apply to step 201 and step 202, and the principles are the same, which will not be repeated here.

[0063] Step 203, splicing the vector data corresponding to each channel identifier.

[0064] Wherein, in the case that the data contents in the at least two vector registers correspond to a plurality of vector data, the plurality of vector data is spliced.

[0065] In an implementation manner of the embodiment of the present application, the plurality of vector data can be spliced according to the arrangement order of the data channels in any vector register.

[0066] Step 204, according to the set bit width, the spliced vector data is divided to obtain at least one vector data group.

[0067] Wherein, the set bit width can be a pre-set bit width; any vector data group includes at least one vector data.

[0068] It should be noted that the vector data group can correspond to a data group identifier, and the data group identifier can be used to indicate the storage batch of the vector data group.

[0069] Step 205, according to the vector data group, the vector data in each vector data group is stored in the memory in batches.

[0070] In the embodiment of the present application, the vector data in each vector data group can be stored in the memory in sequence. It should be noted that in the process of storing the vector data in any group of vector data groups in each batch, the VLSU can access the memory once or multiple times until the vector data in the vector data group is stored in the memory.

[0071] The data storage method of the embodiment of the present application comprises the following steps: receiving a storage instruction, the storage instruction being used to indicate that data contents in at least two vector registers are to be stored into a memory; in response to the storage instruction, splicing the data contents in the data lanes with the same lane identifier in the at least two vector registers to obtain vector data corresponding to each lane identifier; splicing the vector data corresponding to each lane identifier; cutting the spliced vector data into at least one vector data group according to a set bit width; and storing the vector data in each vector data group into the memory in batches according to the vector data group. The spliced vector data is cut into vector data groups, and then the vector data is stored into the memory in batches, so that the data processing amount of each batch storage operation can be reduced, the storage efficiency can be improved, the burden of the memory can be reduced, and the storage congestion phenomenon can be avoided.

[0072] Based on the above embodiment, Figure 3 A flowchart of another data storage method provided by the embodiment of the present application is shown in FIG. 4. It should be noted that the data storage method of the present embodiment can be applied to a data storage device. In some possible embodiments, the device can be configured in an electronic device or a chip, so that the electronic device or the chip can perform a data storage function. In addition, in some possible embodiments, the data storage device can also be software in an electronic device. The software can be, for example, data storage software. In addition, the data storage device can also be a VLSU in an electronic device. In the following embodiments, the execution subject is taken as an example of the VLSU.

[0073] As shown in FIG. 4, the method comprises the following steps: Figure 3

[0074] Step 301: receiving a storage instruction, the storage instruction being used to indicate that data contents in at least two vector registers are to be stored into a memory.

[0075] The memory comprises at least one cache line, and the storage instruction can indicate that the data contents in the at least two vector registers are to be stored into the cache line.

[0076] Step 302: in response to the storage instruction, splicing the data contents in the data lanes with the same lane identifier in the at least two vector registers to obtain vector data corresponding to each lane identifier.

[0077] Step 303: splicing the vector data corresponding to each lane identifier.

[0078] Step 304: cutting the spliced vector data into at least one vector data group according to a set bit width.

[0079] ​The steps 301 to 304 can refer to the related explanations in the foregoing embodiments, and the principles are the same, and thus are not described herein again.

[0080] In step 305, for any vector data group, target vector data to be stored in the same cache line in the vector data group is determined according to the cache line addresses of the vector data in the vector data group in the memory.

[0081] The cache line address is used to indicate the cache line for storing the vector data; and the same cache line address indicates that the vector data is to be stored in the same cache line.

[0082] The target vector data can be the vector data in the vector data group to be stored in the same cache line, and it should be noted that the number of target vector data is multiple.

[0083] It should be noted that the target vector data to be stored in the same cache line forms a data set, and any vector data group can correspond to one or more data sets. For example, it is assumed that the vector data group includes five vector data A, B, C, D and E, A and B are to be stored in cache line a, and C, D and E are to be stored in cache line b, and thus the vector data group corresponds to two data sets.

[0084] In step 306, the target vector data to be stored in each cache line is stored in the corresponding cache line in the memory.

[0085] For the target vector data to be stored in the same cache line, the multiple target vector data to be stored in the same cache line can be stored in the corresponding cache line through one memory access operation.

[0086] Since the multiple target vector data is scattered (scattered) and stored in the corresponding cache line, in order to make the target vector data have the same offset as the target vector data in the accessed cache line, optimize the efficiency of data storage and access, in an implementation manner of the embodiment of the application, for any target vector data, the offset corresponding to the starting address of the target vector data in the corresponding cache line is determined according to the starting address of the target vector data in the corresponding cache line; based on the offset, the data of the target vector data belonging to the same cache line is rearranged through a crossbar to obtain the rearranged data of each cache line, and the rearranged positions of the target vector data belonging to the same cache line in the rearranged data are determined; based on the rearranged positions of the target vector data belonging to the same cache line, the byte mask corresponding to the rearranged data of the corresponding cache line is generated; and the rearranged data of each cache line and the corresponding byte mask are sent to the memory for storage.

[0087] The starting address of the target vector data in the corresponding cache line can be obtained according to the storage instruction, the starting address of the target vector data in the corresponding cache line is different, and the corresponding offset is different; the positions of the target vector data in the rearranged data can be non-adjacent, and the byte mask corresponding to the rearranged data is used to store the position of the target vector data in the rearranged data. For example, the byte mask can be a 0-1 sequence, 1 represents the position of the target vector data (valid data bit), and 0 represents other positions (invalid data bit).

[0088] In the embodiment of the application, the target vector data belonging to the same cache line is rearranged based on the offset to obtain rearranged data, so that the target vector data has the same offset as the target vector data in the accessed cache line, thereby improving the storage efficiency of the data; and the rearranged data and the corresponding byte mask are sent to the memory, so that the memory can quickly locate the target vector data in the rearranged data.

[0089] In an implementation manner of the embodiment of the application, the starting address of each data content corresponding to the target vector data in the cache line is determined based on the starting address of the target vector data in the corresponding cache line; and the offset corresponding to the starting address of each data content in the cache line is determined based on the starting address of each data content corresponding to the target vector data in the cache line; wherein the offset corresponding to the starting address of the target vector data in the corresponding cache line includes the offset corresponding to the starting address of each data content in the cache line.

[0090] In the embodiment of the application, since the size of the data content is fixed, the starting address of each data content corresponding to the target vector data in the cache line can be calculated based on the starting address of the target vector data in the corresponding cache line, and then the offset corresponding to the starting address of each data content in the cache line can be determined based on the starting address of each data content corresponding to the target vector data in the cache line.

[0091] In the embodiment of the application, the offset corresponding to the starting address of each data content corresponding to the target vector data in the cache line provides a more accurate positioning basis for data rearrangement, and therefore the offset corresponding to the starting address of each data content corresponding to the target vector data in the cache line can further improve the data rearrangement effect.

[0092] In an implementation manner of the embodiment of the application, the bit width is determined based on the processable bit width of the cross-point matrix.

[0093] The spliced vector data group is divided based on the processable bit width of the cross-point matrix, so that the number of times of accessing the memory can be reduced without changing the cross-point matrix, and the storage efficiency is improved.

[0094] For example, the data content of the target vector data in the cache line is rearranged based on the offset corresponding to the starting address of the target vector data in the corresponding cache line. Figure 4As shown, Figure 4 is a flowchart of a data storage process, wherein the thread identifier (Thread ID) in the figure indicates that the VLSU has T threads, and since the threads in the VLSU are one-to-one corresponding to the data channel identifiers, the thread identifier (Thread ID) in the figure can also refer to the channel identifier; 411 in the figure represents four vector registers, and each square represents a data channel, and the content in the square is the data content. The following is a specific storage process:

[0095] (1) The data contents in the data channels with the same channel identifier are spliced to obtain the corresponding vector data; for example, four D0 corresponding to the channel identifier 0 are spliced to obtain the vector data corresponding to the channel identifier 0 (the data indicated by the arrow); the vector data corresponding to each channel identifier is spliced to obtain the spliced vector data 410.

[0096] (2) According to the processable bit width of the Crossbar, the spliced vector data is divided to obtain at least one vector data group 401.

[0097] (3) For any vector data group, according to the cache line addresses of the vector data in the vector data group in the memory, a thread set 402 with the same cache line address is determined; according to the thread set, the target vector data to be stored in the same cache line in the vector data group is determined.

[0098] (4) For any target vector data, according to the starting address of the target vector data in the corresponding cache line, the offset corresponding to the starting address is determined (located in 403, which includes the offsets corresponding to each vector data in the vector data group); based on the offset, the target vector data belonging to the same cache line is data rearranged through the Crossbar 404 to obtain the rearranged data of each cache line and determine the byte mask corresponding to the rearranged data; the rearranged data of each cache line and the corresponding byte mask are sent to the memory for storage, so as to store the rearranged data into the cacheline 405.

[0099] In addition, the foregoing embodiment describes the storage process of the vector data when the vector data is stored in multiple vector registers (i.e., the bit width of the vector data is greater than the allocated bit width of the data channel). It should be noted that the present application is also applicable to the case where the bit width of the vector data is less than or equal to the allocated bit width of the data channel, which can be referred to in detail in Figure 5 , compared with Figure 4 , Figure 5 The data content does not need to be spliced and the vector data does not need to be divided, i.e., 501 is equivalent to a vector data group, and the content in each square in 501 is a vector data.

[0100] In the data storage method of the embodiment of the present application, a storage instruction is received, and in response to the storage instruction, data contents in data channels with the same channel identifier in at least two vector registers are spliced to obtain vector data corresponding to each channel identifier; the vector data corresponding to each channel identifier is spliced; the spliced vector data is divided according to a set bit width to obtain at least one vector data group; for any vector data group, target vector data to be stored in the same cache line in the vector data group is determined according to the cache line address of the vector data in the vector data group in the memory; and the target vector data to be stored in each cache line is stored in the corresponding cache line in the memory. Through accurate identification and classification of the vector data to be stored in the same cache line, the target of storing multiple target vector data at a time through a single access is achieved, the number of memory accesses is reduced, and the storage efficiency is improved.

[0101] Based on the above embodiment, Figure 6 A flowchart of a data loading method provided by the embodiment of the present application is shown. It should be noted that the data loading method of the embodiment can be applied to a data loading device. In some possible embodiments, the device can be configured in an electronic device or a chip, so that the electronic device or the chip can perform a data loading function. In addition, in some possible embodiments, the data loading device can also be software in an electronic device. For example, data loading software and the like. In addition, the data loading device can also be a VLSU in an electronic device. In the following embodiments, the execution subject is taken as an example for illustration.

[0102] As shown in Figure 6 The method includes the following steps:

[0103] Step 601, a loading instruction is received, and the loading instruction is used to indicate that vector data in a memory is loaded into at least two vector registers, and any vector register has multiple data channels.

[0104] The loading instruction can be used to indicate the source position of the vector data in the memory, the loading position of the vector data in the at least two vector registers, and the data amount of the vector data.

[0105] Step 602, in response to the loading instruction, the vector data is content-divided to obtain corresponding data contents.

[0106] After the vector data is obtained, the vector data can be content-divided according to the allocation bit width of the data channel to obtain corresponding data contents.

[0107] Step 603, the vector data corresponding to the data contents is loaded into data channels with the same channel identifier in the at least two vector registers.

[0108] The target channel identifier corresponding to the vector data can be determined according to the loading instruction, and then the data content corresponding to the vector data is loaded into the data channel corresponding to the target channel identifier in the at least two vector registers.

[0109] In the data loading method of the embodiment of the present application, a loading instruction is received, the loading instruction being used to indicate that vector data in a memory is loaded into at least two vector registers, any vector register having a plurality of data channels; in response to the loading instruction, the vector data is content-split to obtain corresponding data content; and the data content corresponding to the vector data is loaded into data channels with the same channel identifier in the at least two vector registers. Compared with the scheme in the related art in which the data content of the vector data is respectively read and then respectively loaded, the vector data is directly read in the present application, the number of reading times is reduced, and the loading efficiency is improved.

[0110] Based on the above embodiment, Figure 7 A flowchart of a data loading method provided by the embodiment of the present application is shown in FIG. 7. It should be noted that the data loading method of the embodiment can be applied to a data loading device. In some possible embodiments, the device can be configured in an electronic device or a chip, so that the electronic device or the chip can perform a data loading function. In addition, in some possible embodiments, the data loading device can also be software in the electronic device. The software can be, for example, data loading software. In addition, the data loading device can also be a VLSU in the electronic device. In the following embodiments, the execution subject is taken as the VLSU for example.

[0111] As shown in FIG. 7, the method comprises the following steps: Figure 7

[0112] Step 701, a loading instruction is received.

[0113] In one embodiment of the present disclosure, the loading instruction can be used to indicate the source location of the vector data in the memory, wherein the source location of the vector data in the memory includes a cache line address and a starting address in the cache line.

[0114] Step 702, according to any cache line address indicated by the loading instruction, the vector data stored in the cache line corresponding to the cache line address is obtained from the memory.

[0115] The same cache line address can indicate that the vector data is stored in the same cache line.

[0116] In the embodiment of the present application, the vector data stored in the cache line corresponding to the cache line address is obtained from the memory, which can achieve simultaneous loading of multiple vector data in a single reading, thereby reducing the number of memory reading times.

[0117] ​In an implementation form of the embodiment of the application, for any cache line, the storage data in the same cache line is obtained by reading the storage data from the memory according to the start address in the corresponding cache line address and the data amount information indicated by the load instruction; and the storage data in the same cache line is rearranged by the cross-point matrix based on the offset corresponding to the start address to obtain the rearranged data of the corresponding cache line, wherein the rearranged data of any cache line includes at least one vector data.

[0118] The data amount information is used to indicate the data amount of the vector data, i.e., the data bit width.

[0119] In the embodiment of the application, the storage data in the same cache line is rearranged by the cross-point matrix, which can optimize the data layout and further improve the data loading efficiency.

[0120] In step 703, the vector data is content-split to obtain corresponding data content.

[0121] In step 704, for any vector data in the rearranged data of any cache line, the target channel identifier corresponding to the vector data is determined according to the target position of the vector data in the rearranged data and the target data group identifier of the vector data group to which the vector data belongs; wherein the target data group identifier is used to indicate the storage batch when the vector data is stored in the memory.

[0122] In the vector data storage process before the vector data is loaded, the vector data has a vector data group to which it belongs, and the storage batch indicated by the data group identifier of the vector data group can be used to determine the channel identifier range corresponding to the vector data group. The target position of the vector data in the rearranged data can be used to determine the target channel identifier corresponding to the vector data in the channel identifier range. For example, the vector register has T data channels, and when the spliced vector data is split in the vector data storage process, the vector data group 1 includes the vector data corresponding to the channel identifiers 0-7, the vector data group 2 includes the vector data corresponding to the channel identifiers 8-15, and so on; if the target data group identifier of the vector data group to which the vector data belongs is 2 and the target position of the vector data in the rearranged data is the second position from right to left, it can be determined that the channel identifier range is 8-15 and the target channel identifier is 9; if the target data group identifier of the vector data group to which the vector data belongs is 1 and the target position of the vector data in the rearranged data is the second position from right to left, it can be determined that the channel identifier range is 0-7 and the target channel identifier is 1.

[0123] In step 705, the data content corresponding to the vector data is loaded into the data channel corresponding to the target channel identifier in the at least two vector registers.

[0124] The steps 701 and 703 can refer to the relevant explanations in the foregoing embodiments, and the principles are the same, which will not be repeated here.

[0125] As shown in Figure 8 , Figure 8 is a flowchart of the data loading process, and the following is a specific storage process:

[0126] (1) According to any cache line address indicated by the loading instruction, determine the thread set 802 matched with the cache line address corresponding cache line 805; read the vector data stored in the cache line 805 according to the thread set 802.

[0127] (2) Based on the offset corresponding to the starting address of the vector data in the cache line 805 (located in 803, which includes the offset corresponding to each vector data in the cache line), the data is rearranged through the Crossbar 804 to obtain 801.

[0128] (3) According to the target position of the vector data in the rearranged data 801 and the target data group identifier of the vector data group to which the vector data belongs, determine the target channel identifier.

[0129] (4) The vector data in 801 is content split, and the split data content is loaded into the data channel corresponding to the target channel identifier in the vector register 811. It should be noted that 810 is for easy understanding, and in the actual loading process, the process of 810 is not involved.

[0130] In addition, the foregoing embodiments describe the loading process of the vector data when the bit width of the vector data is greater than the allocation bit width of the data channel. It should be noted that the present application is also applicable to the case where the bit width of the vector data is less than or equal to the allocation bit width of the data channel, which can be referred to in detail Figure 9 , Figure 8 , Figure 9 It is not necessary to split the content of the vector data, that is, the content in each square in 901 is a vector data, not the data content of the vector data.

[0131] The data loading method provided in the embodiments of the present application comprises the following steps: receiving a loading instruction; obtaining vector data stored in a cache line corresponding to a cache line address indicated by the loading instruction from a memory; performing content segmentation on the vector data to obtain corresponding data content; for any vector data in rearranged data of any cache line, determining a target channel identifier corresponding to the vector data according to a target position of the vector data in the rearranged data and a target data group identifier of a vector data group to which the vector data belongs; wherein the target data group identifier is used to indicate a storage batch when the vector data is stored in the memory; and loading the data content corresponding to the vector data into a data channel corresponding to the target channel identifier in at least two vector registers. The vector data stored in the cache line corresponding to the cache line address can be obtained from the memory, so that multiple vector data can be loaded at the same time in a single reading, thereby reducing the number of memory reading times; the storage data stored in the same cache line is rearranged by using a cross-point matrix, so that the data layout can be optimized, thereby further improving the data loading efficiency.

[0132] Figure 10 A structural schematic diagram of a data storage device provided in the embodiments of the present application is shown in the figure.

[0133] As shown in Figure 10 , the device can comprise:

[0134] The receiving module 1001 is configured to receive a storage instruction, wherein the storage instruction is used to instruct to store data content in at least two vector registers to a memory, and any vector register has at least one data channel;

[0135] The splicing module 1002 is configured to splice the data content in the data channels with the same channel identifier in the at least two vector registers to obtain vector data corresponding to each channel identifier in response to the storage instruction.

[0136] The storage module 1003 is configured to store the vector data to the memory.

[0137] Further, in an implementation manner of the embodiments of the present application, the storage module 1003 is further configured to:

[0138] splice the vector data corresponding to each channel identifier;

[0139] segment the spliced vector data according to a set bit width to obtain at least one vector data group;

[0140] store the vector data in each vector data group to the memory in batches according to the vector data groups.

[0141] In an implementation manner of the embodiments of the present application, the memory comprises a cache line, and the storage module 1003 is further configured to:

[0142] For any vector data group, target vector data to be stored in the same cache line in the vector data group is determined according to the cache line address of the vector data in the vector data group in the memory;

[0143] The target vector data to be stored in each cache line is stored in the corresponding cache line in the memory.

[0144] In an implementation manner of the embodiment of the present application, the storage module 1003 is further configured to:

[0145] For any target vector data, an offset corresponding to the starting address of the target vector data in the corresponding cache line is determined according to the starting address;

[0146] Based on the offset, the target vector data belonging to the same cache line is data- rearranged by the cross-point matrix to obtain the rearranged data of each cache line, and the rearrangement positions of the target vector data belonging to the same cache line in the rearranged data are determined;

[0147] Based on the rearrangement positions of the target vector data belonging to the same cache line, a byte mask corresponding to the rearranged data of the corresponding cache line is generated;

[0148] The rearranged data of each cache line and the corresponding byte mask are sent to the memory for storage.

[0149] In an implementation manner of the embodiment of the present application, the storage module 1003 is further configured to:

[0150] Based on the starting address of the target vector data in the corresponding cache line, the starting addresses of each data content corresponding to the target vector data in the cache line are determined;

[0151] According to the starting addresses of each data content in the cache line corresponding to the target vector data, the offsets corresponding to the starting addresses of each data content in the cache line are determined; wherein the offset corresponding to the starting address of the target vector data in the corresponding cache line includes the offset corresponding to the starting address of each data content in the cache line.

[0152] In an implementation manner of the embodiment of the present application, the bit width is determined based on the processable bit width of the cross-point matrix.

[0153] It should be noted that the foregoing explanation and description of the method embodiment are also applicable to the device of this embodiment, which will not be described here.

[0154] The data storage apparatus provided in the embodiments of the present application receives a storage instruction, the storage instruction being used to indicate storage of data content in at least two vector registers to a memory, any vector register having at least one data lane; in response to the storage instruction, data content in data lanes with the same lane identifier in the at least two vector registers is spliced to obtain vector data corresponding to the lane identifier; and the vector data is stored to the memory. By splicing the data content in the data lanes with the same lane identifier to obtain the vector data, and then storing the vector data to the memory, the number of memory access times can be reduced, and the storage efficiency can be improved.

[0155] Figure 11 A structural schematic diagram of a data loading apparatus provided in the embodiments of the present application is shown.

[0156] As shown in Figure 11 , the apparatus can include:

[0157] The receiving module 1101 is configured to receive a loading instruction, the loading instruction being used to indicate loading of vector data in a memory to at least two vector registers, any vector register having a plurality of data lanes;

[0158] The splitting module 1102 is configured to, in response to the loading instruction, split the vector data in content to obtain corresponding data content.

[0159] The loading module 1103 is configured to load the data content corresponding to the vector data to data lanes with the same lane identifier in the at least two vector registers.

[0160] Further, in an implementation manner of the embodiments of the present application, the splitting module 1102 is further configured to:

[0161] According to any cache line address indicated by the loading instruction, obtain the vector data stored in a cache line corresponding to the cache line address from the memory;

[0162] Split the vector data in content to obtain corresponding data content.

[0163] In an implementation manner of the embodiments of the present application, the splitting module 1102 is further configured to:

[0164] For any cache line, according to a start address in the corresponding cache line address and data quantity information indicated by the loading instruction, perform storage data reading on the memory to obtain storage data stored in the same cache line;

[0165] Based on an offset corresponding to the start address, perform data rearrangement on the storage data stored in the same cache line through a cross-point matrix to obtain rearranged data of the corresponding cache line, wherein the rearranged data of any cache line includes at least one vector data.

[0166] In an implementation form of the embodiment of the application, the loading module 1103 is further configured to:

[0167] For any vector data in the rearranged data of any cache line, a target channel identifier corresponding to the vector data is determined according to a target position of the vector data in the rearranged data and a target data group identifier of a vector data group to which the vector data belongs; the target data group identifier is used to indicate a storage batch when the vector data is stored in the memory.

[0168] The data content corresponding to the vector data is loaded into a data channel corresponding to the target channel identifier in the at least two vector registers.

[0169] It should be noted that the foregoing explanation and description of the method embodiments are also applicable to the device of this embodiment, which will not be described here again.

[0170] The data loading device provided in the embodiment of the application receives a loading instruction, the loading instruction being used to instruct to load vector data in a memory into at least two vector registers, any vector register having a plurality of data channels; in response to the loading instruction, the vector data is content-split to obtain corresponding data content; and the data content corresponding to the vector data is loaded into data channels with the same channel identifier in the at least two vector registers. Compared with the scheme in the related art that the data content of the vector data is respectively read and then respectively loaded, the vector data is directly read in the present application, the number of reading times is reduced, and the loading efficiency is improved.

[0171] To achieve the above-mentioned embodiments, the application further provides an electronic device, comprising a memory, a processor and a computer program stored in the memory and executable on the processor, wherein the processor implements the method as described in the foregoing method embodiments when executing the program.

[0172] To achieve the above-mentioned embodiments, the embodiment of the application further provides a chip comprising a processing circuit, wherein the processing circuit is configured to implement the method as described in the foregoing method embodiments when executing.

[0173] To achieve the above-mentioned embodiments, the application further provides a non-transitory computer-readable storage medium having a computer program stored thereon, wherein the program is executable by a processor to implement the method as described in the foregoing method embodiments.

[0174] To achieve the above-mentioned embodiments, the application further provides a computer program product having a computer program stored thereon, wherein the computer program is executable by a processor to implement the method as described in the foregoing method embodiments.

[0175] Figure 12A block diagram of an electronic device provided for embodiments of this application. For example, the electronic device 1200 can be a mobile phone, a computer, a digital broadcast terminal, a messaging device, a game console, a tablet device, a medical device, a fitness device, a personal digital assistant, and the like.

[0176] Referring to Figure 12 The electronic device 1200 can include one or more of the following components: a processing component 1202, a memory 1204, a power component 1206, a multimedia component 1208, an audio component 1210, an input / output (I / O) interface 1212, a sensor component 1214, and a communication component 1216.

[0177] The processing component 1202 usually controls overall operations of the electronic device 1200, such as operations associated with displaying, making phone calls, data communications, camera operations, and recording operations. The processing component 1202 can include one or more processors 1220 to execute instructions to complete all or part of steps of the methods described above. In addition, the processing component 1202 can include one or more modules to facilitate the interaction between the processing component 1202 and other components. For example, the processing component 1202 can include a multimedia module to facilitate the interaction between the multimedia component 1208 and the processing component 1202.

[0178] The memory 1204 is configured to store various types of data to support operations of the electronic device 1200. Examples of these data include instructions for any application or method operating on the electronic device 1200, contact data, phonebook data, messages, pictures, videos, and the like. The memory 1204 can be implemented by any type of volatile or non-volatile storage devices or a combination thereof, such as static random access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic storage, flash memory, magnetic disk or optical disk.

[0179] The power component 1206 provides power to various components of the electronic device 1200. The power component 1206 can include a power management system, one or more power sources, and other components associated with generating, managing and distributing power for the electronic device 1200.

[0180] The multimedia component 1208 includes a screen to provide an output interface between the electronic device 1200 and a user. In some embodiments, the screen can include a liquid crystal display (LCD) and a touch panel (TP). If the screen includes a touch panel, the screen can be implemented as a touch screen to receive an input signal from a user. The touch panel includes one or more touch sensors to sense a touch, a slide and a gesture on the touch panel. The touch sensor can not only sense a boundary of a touching or a sliding action, but also detect duration and pressure related to the touching or sliding action. In some embodiments, the multimedia component 1208 includes a front camera and / or a rear camera. When the electronic device 1200 is in an operating mode, such as a capturing mode or a video mode, the front camera and / or the rear camera can receive external multimedia data. Each of the front camera and the rear camera can be a fixed optical lens system or have a focal length and optical zooming capability.

[0181] The audio component 1210 is configured to output and / or input an audio signal. For example, the audio component 1210 includes a microphone (MIC) to receive an external audio signal when the electronic device 1200 is in an operating mode, such as a call mode, a recording mode, and a voice recognition mode. The received audio signal can be further stored in the memory 1204 or transmitted via the communication component 1216. In some embodiments, the audio component 1210 further includes a speaker to output an audio signal.

[0182] The I / O interface 1212 provides an interface between the processing component 1202 and peripheral interface modules, which can be a keypad, a click wheel, buttons, and the like. The buttons can include, but are not limited to, a home button, a volume button, a start button, and a lock button.

[0183] The sensor component 1214 includes one or more sensors for providing status assessments for various aspects of the electronic device 1200. For example, the sensor component 1214 can detect an open / closed position of the electronic device 1200, relative positioning of components of the electronic device 1200, such as a display and a keypad of the electronic device 1200, a change in position of the electronic device 1200 or a component of the electronic device 1200, presence or absence of user contact with the electronic device 1200, orientation or acceleration / deceleration / g-force and temperature changes of the electronic device 1200. The sensor component 1214 can include an optical sensor for detecting ambient light, a proximity sensor for detecting nearby objects without any physical touch, a CMOS or CCD image sensor for use in imaging applications, and / or a gyroscope sensor, a magnetometer sensor, a pressure sensor, or a temperature sensor in some embodiments.

[0184] The communication component 1216 is configured to facilitate wired or wireless communication between the electronic device 1200 and other devices. The electronic device 1200 can access a wireless network based on a communication standard, such as WiFi, 4G, or 5G, or a combination thereof. In an example embodiment, the communication component 1216 receives broadcast signals or broadcast-related information from an external broadcast management system via a broadcast channel. In an example embodiment, the communication component 1216 further includes a Near Field Communication (NFC) module to facilitate short-range communication. For example, the NFC module can be implemented based on Radio Frequency Identification (RFID) technology, infrared data association (IrDA) technology, ultra-wideband (UWB) technology, Bluetooth (BT) technology and other technology.

[0185] In an example embodiment, the electronic device 1200 can be implemented using one or more application-specific integrated circuits (ASICs), digital signal processors (DSPs), digital signal processing devices (DSPDs), programmable logic devices (PLDs), field programmable gate arrays (FPGAs), controllers, micro-controllers, microprocessors, or other electronic elements for performing the above-described methods.

[0186] In an example embodiment, a non-transitory computer-readable storage medium including instructions, such as the memory 1204 including instructions, is also provided. The instructions can be executable by the processor 1220 of the electronic device 1200 to implement the above-described methods. For example, the non-transitory computer-readable storage medium can be a ROM, a random access memory (RAM), a CD-ROM, a magnetic tape, a floppy disc, and an optical data storage device, etc.

[0187] In the description of the application, reference to "one embodiment", "some embodiments", "an example", "a specific example", or "some examples" means that a particular feature, structure, material, or characteristic being described is included in at least one embodiment or example of the application. The appearances of the phrase in various places in the specification are not necessarily all referring to the same embodiment or example. Furthermore, the described specific features, structures, materials, or characteristics can be combined in any suitable manner in one or more embodiments or examples. Moreover, the usage of the terms "first", "second" or "third" does not limit the quantity or order of the specific features, structures, materials or characteristics, but rather the term "first", "second" or "third" can be used to distinguish the specific features, structures, materials or characteristics from one another. In addition, the particular features, structures, materials, or characteristics can be combined in any suitable manner in one or more embodiments or examples, without changing the scope of the application.

[0188] Furthermore, the terms "first", "second", or the like do not denote any quantity or order, but rather serve as labels to distinguish between different instances of an element. Thus, a feature labeled "first" can imply or be understood to mean that there is at least one such feature, either explicitly or implicitly. In the description of the application, the meaning of "a plurality" is at least two, for example two, three or more, unless otherwise expressly specified.

[0189] Any process or method descriptions or blocks in flow charts or otherwise described herein represent embodiments of modules, segments, or portions of code which include one or more executable instructions for implementing specific logical functions or steps, or combinations of tasks or steps. Alternate implementations are included within the scope of the preferred embodiments of the application in which additional functionality can be added or where functions can be implemented out of the order or in reverse order of the described or illustrated implementations, as will be understood by those skilled in the art. Further, interactions between different described or illustrated functional blocks or modules can be implemented in the opposite order or in reverse order, or in an out of order manner, as will be understood by those skilled in the art.

[0190] The logic and / or steps represented in flow diagrams or otherwise described herein, for example, can be considered as a sequence of executable instructions, and can be embodied in any computer-readable medium for use by or in connection with an instruction execution system, apparatus, or device, such as a computer-based system, processor-containing system, or other system that can fetch the instructions from the instruction execution system, apparatus, or device and execute the instructions. For purposes of this specification, a "computer-readable medium" can be any apparatus that can contain, store, communicate, propagate, or transport the program for use by or in connection with the instruction execution system, apparatus, or device. The computer-readable medium can be a product of the manufacturing and / or processing. The computer-readable medium can include, but is not limited to, the following: an electronic connection (an electronic device having one or more wires), a portable computer diskette (a magnetic device), a RAM (random access memory), a ROM (read-only memory), an EPROM (erasable programmable ROM) or a Flash memory, an optical fiber, and a portable CD ROM. In addition, the computer-readable medium can even be paper or another suitable medium upon which the program is printed, as the program can be electronically captured, for example via the optical scanner of the paper or other medium, then compiled, interpreted, or otherwise processed in a suitable manner, if necessary, and stored in a computer memory.

[0191] It should be understood that aspects of the application can be implemented in hardware, software, firmware or combinations thereof. In the above embodiments, various steps or methods can be implemented in software or firmware that is stored in memory and executed by a suitable instruction execution system. As such, in some embodiments, the steps or methods can be implemented in a combination of hardware and software. If implemented in hardware, as in another embodiment, any of the above techniques can be implemented with or without the use of the following technologies, which technologies are well known in the art: discrete logic circuitry having logic gates for implementing logic functions upon an application of data signals, application specific integrated circuits having appropriate combinational logic gates, programmable gate arrays (PGA), field programmable gate arrays (FPGA), and other implementations which are known in the art.

[0192] Those of skill in the art would understand that information and signals can be represented using any of a variety of technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that can be referenced throughout the above description can be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof.

[0193] In addition, each of the functional units in the various embodiments of the present application can be integrated in one processing module, or each of the units can be physically present separately, or two or more units can be integrated in one module. The integrated module can be implemented in the form of hardware or in the form of a software functional module. When the integrated module is implemented in the form of a software functional module and sold or used as an independent product, it can also be stored in a computer readable storage medium.

[0194] The storage medium mentioned above can be a read-only memory, a magnetic disk or an optical disk, etc. Although the embodiments of the present application have been shown and described above, it should be understood that the above embodiments are exemplary and should not be construed as limiting the present application, and those skilled in the art can make changes, modifications, replacements and variations to the above embodiments within the scope of the present application.

Claims

1. A data storage method, characterized in that, include: Receive a storage instruction, the storage instruction being used to instruct the data contents of at least two vector registers to be stored into memory, each of the vector registers having at least one data channel; In response to the storage instruction, the data contents of the data channels with the same channel identifier in the at least two vector registers are concatenated to obtain vector data corresponding to each channel identifier; Concatenate the vector data corresponding to each of the channel identifiers; Based on the set bit width, the concatenated vector data is segmented to obtain at least one vector data group; Based on the vector data group, the vector data in each vector data group is stored in the memory in batches.

2. The method according to claim 1, characterized in that, The memory includes cache lines, and the step of storing vector data within each vector data group into the memory in batches according to the vector data group includes: For any of the vector data groups, the target vector data to be stored in the same cache line in the vector data group is determined according to the cache line address of the vector data in the memory. The target vector data to be stored in each of the cache lines is stored in the corresponding cache line in the memory.

3. The method according to claim 2, characterized in that, The step of storing the target vector data to be stored in each of the cache lines into the corresponding cache line in the memory includes: For any of the target vector data, determine the offset corresponding to the starting address based on the starting address of the target vector data in the corresponding cache line; Based on the offset, the target vector data belonging to the same cache line are rearranged using the intersection matrix to obtain the rearranged data of each cache line, and the rearranged position of each target vector data belonging to the same cache line in the rearranged data is determined. Based on the rearranged positions of the target vector data in the same cache line, generate the byte mask corresponding to the rearranged data of the corresponding cache line; The rearranged data of each cache line and the corresponding byte mask are sent to the memory for storage.

4. The method according to claim 3, characterized in that, The step of determining the offset corresponding to the starting address based on the starting address of the target vector data in the corresponding cache line includes: Based on the starting address of the target vector data in the corresponding cache line, determine the starting address of each data content corresponding to the target vector data in the cache line; Based on the starting address of each data content corresponding to the target vector data in the cache line, determine the offset corresponding to the starting address of each data content in the cache line; wherein, the offset corresponding to the starting address of the target vector data in the corresponding cache line includes the offset corresponding to the starting address of each data content in the cache line.

5. The method according to claim 3, characterized in that, The set bit width is determined based on the processable bit width of the intersection matrix.

6. A data loading method, characterized in that, include: Receive a load instruction, the load instruction being used to instruct the loading of vector data in memory into at least two vector registers, each of the vector registers having multiple data channels; According to any cache line address indicated by the loading instruction, retrieve the vector data stored in the cache line corresponding to the cache line address from the memory; The vector data is segmented to obtain the corresponding data content; The data content corresponding to the vector data is loaded into the data channel with the same channel identifier in the at least two vector registers.

7. The method according to claim 6, characterized in that, The step of retrieving vector data stored in the cache line corresponding to any cache line address indicated by the load instruction from the memory includes: For any cache line, based on the starting address in the corresponding cache line address and the data volume information indicated by the load instruction, the memory is read to obtain the stored data stored in the same cache line; Based on the offset corresponding to the starting address, the stored data in the same cache line is rearranged using the intersection matrix to obtain the rearranged data of the corresponding cache line. The rearranged data of any cache line includes at least one of the vector data.

8. The method according to claim 7, characterized in that, The step of loading the data content corresponding to the vector data into the data channel with the same channel identifier in the at least two vector registers includes: For any vector data in the reordered data of any cache line, the target channel identifier corresponding to the vector data is determined according to the target position of the vector data in the reordered data and the target data group identifier of the vector data group to which the vector data belongs; wherein, the target data group identifier is used to indicate the storage batch when the vector data is stored in the memory; The data content corresponding to the vector data is loaded into the data channel corresponding to the target channel identifier in the at least two vector registers.

9. A data storage device, characterized in that, include: A receiving module is configured to receive a storage instruction, the storage instruction being configured to instruct the data contents of at least two vector registers to be stored in memory, each of the vector registers having at least one data channel; A splicing module is used to, in response to the storage instruction, splice the data contents of data channels with the same channel identifier in at least two vector registers to obtain vector data corresponding to each channel identifier; The storage module is used to concatenate the vector data corresponding to each of the channel identifiers; According to the set bit width, the concatenated vector data is segmented to obtain at least one vector data group; based on the vector data group, the vector data in each vector data group is stored in the memory in batches.

10. A data loading device, characterized in that, include: A receiving module is used to receive a loading instruction, which instructs that vector data in memory be loaded into at least two vector registers, each of which has multiple data channels; The segmentation module is used to retrieve vector data stored in the cache line corresponding to the cache line address from the memory according to any cache line address indicated by the loading instruction; and to segment the vector data to obtain the corresponding data content. The loading module is used to load the data content corresponding to the vector data into the data channel with the same channel identifier in the at least two vector registers.

11. An electronic device, characterized in that, include: processor; Memory used to store processor-executable instructions; The processor is configured as follows: The steps of implementing the method according to any one of claims 1 to 5 or 6-8.

12. A chip, characterized in that, It includes processing circuitry, which, when executed, implements the method of any one of claims 1 to 5 or 6-8.

13. A non-transitory computer-readable storage medium, wherein when instructions in the storage medium are executed by a processor of a mobile terminal, the mobile terminal is enabled to perform the steps of the method according to any one of claims 1 to 5 or 6-8.

14. A computer program product, characterized in that, Includes a computer program, which, when executed by a processor, implements the method of any one of claims 1 to 5 or 6-8.

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