A data block cache updating method, device, equipment and storage medium

Abstract

The application discloses a data block cache updating method and device, equipment and a storage medium, and relates to the technical field of processor cores. The method comprises the following steps: obtaining a data access request for a target chip, and performing data matching in a target cache line based on an access address in the data access request to determine whether the data access request hits the memory; if the data access request does not hit the memory, determining a data cache running state based on the number of hit identifiers in a target memory access identifier signal; if the data cache running state is a normal running state, determining a first target cache data block based on the lowest hit identifier in the target memory access identifier signal; if the distance between the hit identifiers in the first target cache data block is less than a preset distance threshold, performing data replacement on the first target cache data block to complete cache data block updating, and refreshing the cache identifiers of each group of the target chip. In this way, the cache hit rate of the data block can be improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of processor core, and in particular to a data block cache updating method and device, equipment and storage medium. BACKGROUND

[0002] In the field of chip technology development, the performance of a processor is affected by two core factors: one is the clock frequency and computing throughput of the processor, and the other is the data access speed. The clock frequency and computing throughput of the processor benefit from the continuous evolution of Moore's Law, so that the core frequency of a modern microprocessor can reach 3GHz. However, the data access speed is limited by the timing requirements of memory access, and usually requires multiple processor clock cycles to complete data reading from the memory. Therefore, memory access delay has become a key bottleneck restricting the performance improvement of the processor. In order to enhance the memory reading performance of the processor and alleviate the performance limitation caused thereby, a multi-level cache architecture has become a commonly used storage technology in microprocessor design. This architecture integrates multiple groups of high-speed low-capacity storage units on the chip, and preloads part of the external memory data into these caches, thereby reducing the access demand of the processor core to the external memory, and further improving the overall processing performance. However, due to the limitation of physical resources on the chip, the cache storage capacity that can be integrated on the chip is limited. Therefore, how to optimize the selection and replacement strategy of data in the on-chip cache, and improve the cache hit rate of data is a problem to be solved. SUMMARY

[0003] Therefore, the purpose of the present application is to provide a data block cache updating method, device, equipment and storage medium, which can improve the cache hit rate of data blocks. The specific scheme is as follows:

[0004] In a first aspect, the present application discloses a data block cache updating method, comprising:

[0005] obtaining a data access request for a target chip, and entering a target cache line based on the access address in the data access request to perform data matching, so as to determine whether the data access request is a memory access hit according to the data matching result;

[0006] If the data access request does not hit the memory, the target memory access identification signal of the target cache line is determined, and the running state of the data cache is determined to be an initial filling state or a normal running state according to the number of hit identification signals in the target memory access identification signal;

[0007] If the running state of the data cache is a normal running state, the first target cache data block is determined based on the hit identification signal of the lowest bit in the target memory access identification signal, and the distance between the hit identification signals in the first target cache data block is obtained;

[0008] If the distance is less than a preset distance threshold, data replacement is performed on the first target cache data block by using a current data block in the data access request to complete cache data block updating, and each group of cache identifiers of the target chip is refreshed based on a preset shift register mechanism.

[0009] Optionally, after the data access request is determined to be a memory access hit based on the data matching, the method further includes:

[0010] If the data access request is a memory access hit, the cache identifiers corresponding to the cache data blocks with successful data matching are left shifted and filled with a hit identifier at the last bit, and the cache identifiers corresponding to other cache data blocks are left shifted and filled with a hit identifier at the last bit.

[0011] Optionally, the target memory access identifier signal of the target cache line is determined, and whether the data cache running state is an initial filling state or a normal running state is determined according to a number of hit identifiers in the target memory access identifier signal, and the method includes:

[0012] The cache identifiers corresponding to each cache data block of the target cache line are subjected to a bitwise OR operation to obtain a target memory access identifier signal;

[0013] The number of hit identifiers in the target memory access identifier signal is obtained, and a proportion of the number of hit identifiers to a number of all identifiers in the target memory access identifier signal is determined;

[0014] Whether the proportion is greater than a preset proportion threshold is determined to determine whether the data cache running state is an initial filling state or a normal running state.

[0015] Optionally, after whether the data cache running state is an initial filling state or a normal running state is determined according to the number of hit identifiers in the target memory access identifier signal, the method further includes:

[0016] If the data cache running state is a preset initial filling state, a current data block in the data access request is stored to a target position based on a preset data filling sequence, and each group of cache identifiers of the target chip is refreshed based on a preset shift register mechanism.

[0017] Optionally, after the distance between the hit identifiers in the first target cache data block is obtained, the method further includes:

[0018] If the distance is greater than or equal to a preset distance threshold, a cache data block with a highest identifier bit of a hit identifier in the cache identifiers is selected from each cache data block of the target cache line to obtain a second target cache data block;

[0019] replacing the second target cache data block with the current data block in the data access request to complete cache data block updating.

[0020] Optionally, the selecting, from the cache data blocks in the target cache line, a cache data block with a highest bit position of a hit-identified identifier in the cache identifier to obtain a second target cache data block comprises:

[0021] determining, from the cache data blocks in the target cache line, a cache data block with a highest bit position of a hit-identified identifier in the cache identifier as a candidate data block, and judging whether there is a cache data block without a hit-identified identifier in the cache identifier in the cache data blocks in the target cache line;

[0022] if there is no cache data block without a hit-identified identifier in the cache identifier in the cache data blocks, determining the candidate data block as the second target cache data block.

[0023] Optionally, after the cache identifier refreshing of the cache identifiers in each group of the target chip based on the preset shift register mechanism, the method further comprises:

[0024] reacquiring the data access request, and performing data matching on the target cache line with an access address in the data access request;

[0025] performing left shift on a cache identifier corresponding to a cache data block with successful data matching and filling a hit-identified identifier at the end, and performing left shift on cache identifiers corresponding to other cache data blocks and filling hit-identified identifiers at the end.

[0026] In a second aspect, the application discloses a data block cache updating device, comprising:

[0027] an access request judging module, configured to acquire a data access request for a target chip, perform data matching on a target cache line with an access address in the data access request, and judge whether the data access request is a memory hit according to a data matching result;

[0028] a cache state determining module, configured to determine a target memory identifier signal of the target cache line if the data access request is not a memory hit, and judge whether a data cache running state is an initial filling state or a normal running state according to a number of hit-identified identifiers in the target memory identifier signal;

[0029] a hit-identified identifier acquiring module, configured to determine a first target cache data block based on a hit-identified identifier at a lowest bit position in the target memory identifier signal if the data cache running state is the normal running state, and acquire a distance between hit-identified identifiers in the first target cache data block;

[0030] The cache refreshing module is configured to, if the distance is less than a preset distance threshold, perform data replacement on the first target cache data block by using a current data block in the data access request to complete cache data block updating, and perform cache identification refreshing on each group of cache identifications of the target chip based on a preset shift register mechanism.

[0031] In a third aspect, the present application discloses an electronic device, comprising:

[0032] A memory is configured to save a computer program.

[0033] A processor is configured to execute the computer program to implement the data block cache updating method.

[0034] In a fourth aspect, the present application discloses a computer readable storage medium configured to save a computer program, and the computer program is executed by a processor to implement the data block cache updating method.

[0035] It can be seen that, in the present application, a data access request for a target chip is acquired, and data matching is performed in a target cache line based on an access address in the data access request to determine whether the data access request is a memory access hit according to a data matching result. If the data access request is not a memory access hit, a target memory access identification signal of the target cache line is determined, and a data cache running state is determined to be an initial filling state or a normal running state according to a number of hit identifications in the target memory access identification signal. If the data cache running state is a normal running state, a first target cache data block is determined based on a lowest bit hit identification in the target memory access identification signal, and a distance between hit identifications in the first target cache data block is acquired. If the distance is less than a preset distance threshold, data replacement is performed on the first target cache data block by using a current data block in the data access request to complete cache data block updating, and cache identification refreshing is performed on each group of cache identifications of the target chip based on a preset shift register mechanism. In this way, cache identifications are constructed for each cache group in the cache module, data access probability of data in the cache identifications is analyzed based on the cache identifications, and data is updated and replaced in a targeted manner, so that data with a higher memory hit rate, i.e., data-intensive data, can be reserved, and cache hit rates for data-intensive and non-data-intensive computing tasks can be effectively improved. BRIEF DESCRIPTION OF DRAWINGS

[0036] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings needed to be used in the embodiments or prior art description. Obviously, the drawings in the following description are only embodiments of the present application, and for those skilled in the art, other drawings can be obtained without creative labor based on the provided drawings.

[0037] Figure 1 A data block cache update method flowchart disclosed by the present application;

[0038] Figure 2 A specific data block cache update architecture diagram disclosed by the present application;

[0039] Figure 3 A specific data block cache update method flowchart disclosed by the present application;

[0040] Figure 4 A data block cache update device structure diagram disclosed by the present application;

[0041] Figure 5 An electronic device structure diagram disclosed by the present application. DETAILED DESCRIPTION

[0042] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor fall within the scope of protection of the present application.

[0043] In the existing cache replacement strategy, the core idea of the LRU (Least Recently Used, i.e. least recently used) replacement mechanism is to replace the data block with the longest unused time in the cache module first, so as to tend to retain the data recently accessed. This strategy conforms to the principle of locality in computer science, i.e. the probability of the data recently accessed being accessed again in the future is higher. However, for computing tasks that continuously process new data, the LRU replacement mechanism will cause the cache hit rate to decrease significantly, because these tasks frequently access new data, and the invalid data that the LRU replacement mechanism prefers to retain will occupy too much cache space. On the other hand, the FIFO (First Input First Output, which is a first-in first-out data structure) replacement strategy and the random replacement strategy do not consider the influence of cache hit history on replacement decision when selecting replacement data. The FIFO algorithm is based on the principle of first-in first-out, and simply replaces the data block that enters the cache earliest, while the random replacement strategy randomly selects a data block for replacement. These two strategies fail to effectively improve the cache hit rate for data-intensive and non-data-intensive computing tasks. Therefore, the present application will specifically introduce a data block cache update method that can effectively improve the cache hit rate for data-intensive and non-data-intensive computing tasks.

[0044] Reference is made to Figure 1As shown, the embodiment of the present application discloses a data block cache updating method, comprising:

[0045] Step S11: obtaining a data access request for a target chip, and entering a target cache line based on an access address in the data access request to perform data matching, so as to determine whether the data access request is a memory hit according to a data matching result.

[0046] In the embodiment, first of all, it needs to be pointed out that an independent cache identifier set is constructed for each cache group in the cache module, and these identifiers record the behavior mode of the cache line in the previous n times of access in detail, including hit, miss and refresh events. Through this mechanism, the access history of the cache line can be accurately captured, providing a basis for subsequent data analysis, and the specific architecture is as shown in Figure 2 In the traditional group-connection cache structure, the cache data is distinguished according to a plurality of cache lines, and a plurality of groups of cache data are stored in each cache line. When the access signal arrives, first of all, the corresponding cache line is entered according to the access address to perform data matching, so as to determine whether the access signal matches the plurality of groups of data in the access line. If the data matching is successful, it is a memory hit, and the data of the corresponding group in the access line is read. If the data matching is not successful, it is a memory miss, and the memory miss information is stored and a data request signal is sent to the high-level cache. When the high-level cache sends back a response signal, the corresponding cache line is entered according to the access address to perform a refresh operation. At this time, according to the corresponding cache replacement policy, one of the plurality of groups of cache data in the cache line is selected to be refreshed. After the data refresh is completed, the stored memory miss signal is re-sent to enter the corresponding cache line to perform secondary data matching and reading.

[0047] In the embodiment, the traditional group-connection cache structure is adapted and optimized, the cache module is divided into a cache data module and a cache identifier module, and a data updating mechanism of the cache identifier is added. That is, a data access request for a target chip is obtained, and a target cache line is entered based on an access address in the data access request to perform data matching, so as to determine whether the data access request is a memory hit according to a data matching result. Specifically, when the access signal arrives and enters the corresponding cache line according to the access address, the cache data module sends an identifier refresh signal to each group of access identifiers of the corresponding cache line in the cache identifier module; and when the access signal completes data matching in the corresponding cache line, the cache data module sends identifier refresh data to each group of access identifiers of the corresponding cache line in the cache identifier module. When the matching result is a memory hit, the group of the memory hit in the identifier refresh data is 1, and the other groups are 0; and when the matching result is a memory miss, the identifier refresh data is all 0. It needs to be pointed out here that the hit identifier is 1 in the present application. In the embodiment, the cache identifier set is divided into a plurality of groups according to the cache line, and each group of cache identifiers records the behavior mode of the cache line in the previous n times of access in detail. Figure 2Taking the cache structure of the 4-way set-associative as an example, when the cache line 3 receives the access signal, the cache data module sends an identification refresh signal to the cache line 3 in the cache identification module; subsequently, the cache data module cache line 3 completes the data matching work and obtains a data matching result: if the matching result is access miss, the cache data module sends the cache identification module an identification refresh data 4bit of 0000; if the matching result is access hit and the hit group identification is 1, the cache data module sends the cache identification module an identification refresh data 4bit of 0100.

[0048] In the embodiment, after the data matching based on the access address in the data access request into the target cache line to determine whether the data access request is access hit according to the data matching result, the method further comprises: if the data access request is access hit, left shifting the cache identification corresponding to the cache data block with successful data matching and filling the hit identification at the last bit, and left shifting the cache identification corresponding to other cache data blocks and filling the hit identification at the last bit. Specifically, the access identification refresh mechanism is a shift register mechanism, that is, the original access identification is left shifted by one bit and the highest bit is discarded, and the newly received identification refresh data is filled into the lowest bit of each group of access identification. Through this mechanism, it can be ensured that sufficient cache hit information is retained with the least identification bits, that is, when one bit of each group of access identification of the corresponding cache line is 1, it indicates that the corresponding group of the access line has access hit, and if one bit of each group of access identification of the corresponding cache line is 0, it indicates that the access line has access miss.

[0049] Step S12: If the data access request is not access hit, determining the target access identification signal of the target cache line, and determining whether the data cache running state is an initial filling state or a normal running state according to the number of hit identifications in the target access identification signal.

[0050] In the embodiment, the target access identification signal of the target cache line is determined, and whether the data cache running state is an initial filling state or a normal running state is determined according to a number of hit identifications in the target access identification signal, including: performing a bitwise OR operation on cache identifications corresponding to each cache data block of the target cache line to obtain a target access identification signal; obtaining the number of hit identifications in the target access identification signal, and determining a proportion of the number of hit identifications in the number of all identifications in the target access identification signal; and determining whether the proportion is greater than a preset number proportion threshold to determine whether the data cache running state is an initial filling state or a normal running state. In the embodiment, through identification processing of each group of access identification information maintained in the cache identification module, whether the current data access mode is inclined to a data-intensive or a non-data-intensive computing task is determined, and then a suitable cache replacement strategy is selected accordingly. Specifically, assuming that the cache identification module maintains n times of access information, the bit width of each access identification corresponding to each cache line in the cache identification module is n, and a bitwise OR operation is performed on each group of cache identifications in the same cache line, so that a comprehensive access identification signal of n-bit width is obtained at the granularity of a cache line. Then, by identifying the number of 1s in the comprehensive access identification signal of n-bit width, whether the current cache module is in an initial filling state or a normal running state is determined.

[0051] In the embodiment, after determining whether the data cache running state is an initial filling state or a normal running state according to the number of hit identifications in the target access identification signal, the method further includes: if the data cache running state is a preset initial filling state, storing a current data block in the data access request to a target position based on a preset data filling sequence, and refreshing each group of cache identifications of the target chip based on a preset shift register mechanism. Specifically, if the number of 1s in the comprehensive access identification signal of n-bit width is less than n / 2, it indicates that the current cache module is in an initial filling state, at this time, the cache module has just started to work, and there are cache groups that have not been filled with valid data, therefore, at this time, the dynamic data refresh mechanism is preferably a sequential refresh, that is, each group is sequentially filled from low to high, so as to ensure that each group in the cache module is preferentially filled with valid data, and the on-chip resource utilization rate is improved.

[0052] Step S13: If the data cache running state is a normal running state, a first target cache data block is determined based on a hit identification of the lowest bit in the target access identification signal, and a distance between hit identifications in the first target cache data block is obtained.

[0053] In the embodiment, after the distance between the hit identifiers in the first target cache data block is obtained, if the distance is greater than or equal to a preset distance threshold, a cache data block with the highest bit position of the hit identifier in the cache identifier is selected from each cache data block of the target cache line to obtain a second target cache data block; and the second target cache data block is replaced with the current data block in the data access request to complete cache data block updating. Specifically, the selection of the cache data block with the highest bit position of the hit identifier in the cache identifier from each cache data block of the target cache line to obtain the second target cache data block includes: determining the cache data block with the highest bit position of the hit identifier in the cache identifier in each cache data block of the target cache line as a candidate data block, and determining whether there is a cache data block without the hit identifier in the cache identifier in each cache data of the target cache line; if there is no cache data block without the hit identifier in the cache identifier in each cache data, the candidate data block is determined as the second target cache data block. In actual operation, if the number of 1s in the n-bit-wide comprehensive memory access identifier signal is greater than or equal to n / 2, it indicates that the current cache module is in a normal running state, and each group in the cache module has valid data at this time. When cache miss occurs, the corresponding memory access identifier group is found according to the lowest bit position of 1 in the comprehensive memory access identifier signal, the distance relationship of two 1s in the corresponding memory access identifier group is determined, if the distance is less than n / 2, the dynamic refresh mechanism prefers the new data retention system, and if the distance is greater than or equal to n / 2, the dynamic refresh mechanism prefers the new data refresh system.

[0054] Step S14: if the distance is less than the preset distance threshold, the first target cache data block is replaced with the current data block in the data access request to complete cache data block updating, and each group of cache identifiers of the target chip is refreshed based on a preset shift register mechanism.

[0055] In the embodiment, if the distance is less than the preset distance threshold, when the dynamic refresh mechanism prefers the new data retention system, the group for data replacement selects the group with the highest bit position of the 1 signal in the corresponding memory access identifier; and if the dynamic refresh mechanism prefers the new data refresh system, the group for data replacement selects the group with the lowest bit position of the 1 signal in the corresponding memory access identifier.

[0056] In the embodiment, after the cache tag refreshing of each group of cache tags of the target chip based on the preset shift register mechanism, the method further comprises: reacquiring the data access request, and the access address in the data access request enters a target cache line for data matching; left shifting the cache tag corresponding to the cache data block with successful data matching and filling a hit tag at the last position, while left shifting the cache tags corresponding to other cache data blocks and filling a hit tag at the last position. In actual operation, after the data refreshing, the last memory access miss signal is received again, and this time must be a memory access hit. Since the last data refreshing selects group 0, each memory access tag is left shifted by one bit, and the last position is filled with 1000.

[0057] Next, a cache line with a four-way group connected cache structure and a cache tag module saving 8 memory access information will be taken as a specific implementation case to illustrate the above situation, and the specific implementation case is as follows: Figure 3shown. First, the first access request comes, since the cache module has not yet worked and there is no valid data, so the access miss must occur, and since each access identifier in the cache identifier module has not yet worked is 0, the comprehensive access identifier signal calculated is 0000_0000, wherein the number of 1s is less than 8 / 2=4, so the cache module is in the initial filling state, and the data refresh preferred order filling. So the group selection of data refresh is group 0, and each access identifier is left shifted by one bit, and the last bit is filled with 0000. After the data refresh is completed, the last access miss signal is received again, and this time must be access hit. Since the last data refresh selected is group 0, each access identifier is left shifted by one bit, and the last bit is filled with 1000. The second access request comes, if this time the access request is access miss, since the comprehensive access identifier signal calculated at present is 0000_0001, wherein the number of 1s is less than 8 / 2=4, so the cache module is still in the initial filling state, and the data refresh preferred order filling. So the group selection of data refresh is group 1, and each access identifier is left shifted by one bit, and the last bit is filled with 0000. If the access request is all access miss in the initial filling state, then the data is sequentially refreshed to group 3. Next, if group 0 gets an access hit signal, the cache identifier module receives the refresh data 1000, and each access identifier is left shifted by one bit, and the last bit is filled with 1000. Next, if the cache line has a cache miss, since the comprehensive access identifier signal calculated at present is 1010_1011, wherein the number of 1s is 5, which is greater than 8 / 2=4, so the cache module is in the normal running state, and the lowest 1 is from group 0, so the distance between the two 1s in the access identifier in group 0 is judged. Since the access identifier in group 0 is 1000_0001, the distance between the two 1s is 6, which is greater than 8 / 2=4, so the dynamic refresh mechanism prefers new data refresh. Since the bit of the 1 signal in the access identifier in groups 0-3 is the lowest 0, 5, 4 and 1 respectively, the group 0 with the lowest value is preferentially refreshed. Since it is access miss, each access identifier is left shifted by one bit, and the last bit is filled with 0000. After the data refresh is completed, the last access miss signal is received again, and this time must be access hit. Since the last data refresh selected is group 0, each access identifier is left shifted by one bit, and the last bit is filled with 1000. Next, if group 0 gets an access hit signal, the cache identifier module receives the refresh data 1000, and each access identifier is left shifted by one bit, and the last bit is filled with 1000.Next if the cache line again cache miss occurs, since the current calculation of the comprehensive access identification signal is 0101_1011, the number of 1 is 5 greater than 8 / 2=4, so the cache module is in normal operation state at this time, and the lowest bit of 1 is from group 0, so the distance of two 1s in the access identification in group 0 is judged, since the access identification in group 0 is 0000_1011, the distance of two 1s is 0, which is less than 8 / 2=4, so the dynamic refresh mechanism optimizes the new data retention system. Because the bit of 1 signal in groups 0-3 is the 0th, no 1, the 6th and the 4th respectively, the group 2 with the highest value is preferentially refreshed, but it is worth noting that the priority of group 1 is higher than that of group 2 because group 1 has no 1 directly, so the final refresh group is group 1. At the same time, since it is a memory access miss, each access identification is left shifted by one bit, and the last bit is filled with 0000. After the data is refreshed, the last memory access miss signal is received again, and this time the memory access hit is certain, since the last data refresh selects group 1, each access identification is left shifted by one bit, and the last bit is filled with 0100. The following is also performed in turn.

[0058] It can be seen that in the embodiment, the data access request for the target chip is obtained, and data matching is performed in the target cache line based on the access address in the data access request to determine whether the data access request is a memory access hit according to the data matching result; if the data access request is not a memory access hit, a target access identification signal of the target cache line is determined, and whether the data cache running state is an initial filling state or a normal running state is determined according to the number of hit identification in the target access identification signal; if the data cache running state is a normal running state, a first target cache data block is determined based on the lowest hit identification in the target access identification signal, and the distance between the hit identifications in the first target cache data block is obtained; if the distance is less than a preset distance threshold, the first target cache data block is replaced with the current data block in the data access request to complete cache data block updating, and each group of cache identifications of the target chip is refreshed based on a preset shift register mechanism. In this way, by constructing cache identification for each cache group in the cache module, the data access probability of the data in the cache identification is analyzed and updated and replaced, the data with high memory hit rate, that is, data-intensive data, can be reserved, and the cache hit rate of data-intensive and non-data-intensive computing tasks can be effectively improved.

[0059] Reference Figure 4 The embodiment of the present application also discloses a data block cache updating device, which comprises:

[0060] The access request judging module 11 is configured to acquire a data access request for a target chip, and perform data matching based on an access address in the data access request to enter a target cache line, so as to judge whether the data access request is a memory access hit according to a data matching result.

[0061] The cache state determining module 12 is configured to determine a target memory access identification signal of the target cache line if the data access request is not a memory access hit, and judge whether a data cache running state is an initial filling state or a normal running state according to a number of hit identifications in the target memory access identification signal.

[0062] The hit identification acquiring module 13 is configured to determine a first target cache data block based on a hit identification of a lowest bit in the target memory access identification signal if the data cache running state is the normal running state, and acquire a distance between hit identifications in the first target cache data block.

[0063] The cache refreshing module 14 is configured to perform data replacement on the first target cache data block by using a current data block in the data access request to complete cache data block updating if the distance is less than a preset distance threshold, and refresh cache identifications of each group of caches of the target chip based on a preset shift register mechanism.

[0064] It can be seen that by separately constructing cache identifications for each cache group in a cache module, and performing data targeted updating and replacement based on data access probability of data in the cache identifications identified and analyzed, data with a higher memory access hit rate, that is, data-intensive data, can be reserved to effectively improve cache hit rates of data-intensive and non-data-intensive computing tasks.

[0065] In some specific embodiments, the data block cache updating apparatus can further include:

[0066] The first identification filling module is configured to left shift a cache identification corresponding to a cache data block with a successful data matching and fill a hit identification at a last bit, and left shift cache identifications corresponding to other cache data blocks and fill hit identifications at last bits if the data access request is a memory access hit.

[0067] In some specific embodiments, the cache state determining module 12 can specifically include:

[0068] The identification calculating unit is configured to perform a bitwise OR operation on cache identifications corresponding to each cache data block of the target cache line to obtain a target memory access identification signal.

[0069] An identifier quantity determination unit is configured to acquire a quantity of hit identifiers in the target access identifier signal and determine a proportion of the quantity of hit identifiers in a total quantity of identifiers in the target access identifier signal.

[0070] A running state determination unit is configured to determine whether the proportion is greater than a preset proportion threshold to determine whether the data cache running state is an initial filling state or a normal running state.

[0071] In some specific embodiments, the data block cache updating apparatus can further include:

[0072] A second identifier filling module is configured to, if the data cache running state is a preset initial filling state, store a current data block in the data access request to a target location based on a preset data filling sequence and refresh cache identifiers of each group of caches of the target chip based on a preset shift register mechanism.

[0073] In some specific embodiments, the data block cache updating apparatus can further include:

[0074] A distance determination module is configured to, if the distance is greater than or equal to a preset distance threshold, select a cache data block with a highest identifier bit of a hit identifier in cache identifiers from each cache data block of the target cache line to obtain a second target cache data block.

[0075] A data replacement module is configured to replace the second target cache data block with a current data block in the data access request to complete cache data block updating.

[0076] In some specific embodiments, the distance determination module can specifically include:

[0077] A data block determination unit is configured to determine a cache data block with a highest identifier bit of a hit identifier in cache identifiers of each cache data block of the target cache line as a candidate data block and determine whether there is a cache data block without a hit identifier in cache identifiers in each cache data of the target cache line.

[0078] A data block determination unit is configured to, if there is no cache data block without a hit identifier in cache identifiers in each cache data, determine the candidate data block as a second target cache data block.

[0079] In some specific embodiments, the data block cache updating apparatus can further include:

[0080] A data matching module is configured to reacquire the data access request and perform data matching on a target cache line with an access address in the data access request.

[0081] The third identifier filling module is configured to left shift the cache identifier corresponding to the cache data block matched successfully and fill a hit identifier at the end, and left shift the cache identifier corresponding to other cache data blocks and fill a hit identifier at the end.

[0082] Further, the embodiment of the application further discloses an electronic device, Figure 5 is an electronic device 20 structure diagram shown according to an exemplary embodiment, the contents in the figure cannot be considered as any limitation on the use range of the application.

[0083] Figure 5 An electronic device 20 structure diagram is provided for the embodiment of the application. The electronic device 20 can specifically include at least one processor 21, at least one memory 22, a power supply 23, a communication interface 24, an input / output interface 25 and a communication bus 26. Wherein, the memory 22 is used for storing computer programs, the computer programs are loaded and executed by the processor 21, to realize the related steps in the data block cache updating method disclosed in any of the preceding embodiments. In addition, the electronic device 20 in the embodiment can be an electronic computer.

[0084] In the embodiment, the power supply 23 is used for providing working voltage for each hardware device on the electronic device 20; the communication interface 24 can create a data transmission channel between the electronic device 20 and the external device, and the communication protocol followed by the communication interface 24 can be any communication protocol applicable to the technical solution of the application, which is not limited here; the input / output interface 25 is used for obtaining external input data or outputting data to the outside world, and the specific interface type can be selected according to the specific application needs, which is not limited here.

[0085] In addition, the memory 22 as a resource storage carrier can be a read-only memory, a random access memory, a magnetic disk or an optical disk, etc., and the resources stored thereon can include an operating system 221, a computer program 222, etc., and the storage mode can be temporary storage or permanent storage.

[0086] Wherein, the operating system 221 is used for managing and controlling each hardware device on the electronic device 20 and the computer program 222, which can be Windows Server, Netware, Unix, Linux, etc. In addition to the computer program capable of completing the data block cache updating method executed by the electronic device 20 disclosed in any of the preceding embodiments, the computer program 222 can further include a computer program capable of completing other specific work.

[0087] Further, the application also discloses a computer readable storage medium for storing a computer program; wherein the computer program is executed by a processor to realize the data block cache updating method disclosed above. For the specific steps of the method, refer to the corresponding content disclosed in the foregoing embodiments, which will not be repeated here.

[0088] The various embodiments are described in the specification by progressive stages, and each embodiment focuses on the difference from other embodiments. For the device disclosed in the embodiments, since it corresponds to the method disclosed in the embodiments, the description is relatively simple, and the relevant parts refer to the method part.

[0089] The skilled person can further realize that the units and algorithm steps of the examples described in combination with the embodiments disclosed herein can be realized by electronic hardware, computer software or a combination of both. In order to clearly illustrate the interchangeability of hardware and software, the components and steps of the examples have been described in the above description in general terms. Whether the functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. The skilled person can use different methods to realize the described functions for each specific application, but such implementation should not be considered beyond the scope of the application.

[0090] The steps of the method or algorithm described in combination with the embodiments disclosed herein can be directly implemented by hardware, a software module executed by a processor, or a combination of both. The software module can be placed in a random access memory (RAM), a memory, a read-only memory (ROM), an electrically programmable ROM, an electrically erasable programmable ROM, a register, a hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art.

[0091] Finally, it should be noted that in this document, relational terms such as first and second are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any such actual relationship or order between such entities or actions. Moreover, the terms "comprises", "comprising", or any other variations thereof are intended to cover non-exclusive inclusions, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but can also include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without more limitations, an element defined by the phrase "comprising a" does not exclude the existence of additional identical elements in the process, method, article, or apparatus that includes the element.

[0092] The technical solutions provided by the present application are described in detail above, and the principles and implementation manners of the present application are described by using specific examples. The above description of the examples is only used to help understand the method of the present application and its core idea; meanwhile, for those skilled in the art, according to the idea of the present application, the specific implementation manners and application ranges will be changed, and the above description of the content of the specification should not be understood as a limitation on the present application.

Claims

1. A data block cache update method, characterized in that: include: Obtaining a data access request for a target chip, and entering a target cache line to perform data matching based on an access address in the data access request, so as to determine whether the data access request is a memory hit according to a data matching result; If the data access request does not result in a memory hit, determining a target memory access identification signal of the target cache line, and judging whether the data cache operation state is an initial filling state or a normal operation state according to the number of hit identifications in the target memory access identification signal; If the data cache operation state is a normal operation state, determining a first target cache data block based on the hit flag of the lowest bit in the target memory access identification signal, and obtaining a distance between the hit flags in the first target cache data block; If the distance is less than a preset distance threshold, the current data block in the data access request is used to replace the first target cache data block to complete the cache data block update, and the cache identifiers of each group of cache identifiers of the target chip are refreshed based on a preset shift register mechanism.

2. The data block cache update method according to claim 1, characterized in that: After entering the target cache line to perform data matching based on the access address in the data access request and determining whether the data access request is a memory hit according to the data matching result, the method further includes: If the data access request is a memory hit, the cache identifier corresponding to the cache data block with successful data matching is shifted left and the hit identifier is filled at the end. At the same time, the cache identifiers corresponding to other cache data blocks are shifted left and the hit identifiers are filled at the end.

3. The data block cache update method according to claim 1, characterized in that: The determining of the target memory access identification signal of the target cache line and judging whether the data cache operation state is an initial filling state or a normal operation state according to the number of hit identifications in the target memory access identification signal includes: Performing a bitwise OR operation on cache identifiers corresponding to cache data blocks of the target cache line to obtain a target memory access identification signal; Obtaining the number of hit identifiers in the target memory access identification signal, and determining the ratio of the number of hit identifiers to the number of all identifiers in the target memory access identification signal; It is determined whether the quantity ratio is greater than a preset quantity ratio threshold to determine whether the data cache operation state is an initial filling state or a normal operation state.

4. The data block cache update method according to claim 1, characterized in that: After determining whether the data cache operation state is an initial filling state or a normal operation state according to the number of hit identifiers in the target memory access identification signal, the method further includes: If the data cache operation state is a preset initial filling state, the current data block in the data access request is stored in the target location based on a preset data filling order, and the cache identifiers of each group of cache identifiers of the target chip are refreshed based on a preset shift register mechanism.

5. The data block cache update method according to claim 1, characterized in that: After obtaining the distance between the hit identifiers in the first target cache data block, the method further includes: If the distance is greater than or equal to a preset distance threshold, selecting a cache data block with a highest identification bit of a hit identifier in a cache identifier from the cache data blocks of the target cache line to obtain a second target cache data block; The second target cache data block is replaced with the current data block in the data access request to complete the cache data block update.

6. The data block cache update method according to claim 5, characterized in that: The step of selecting, from the cache data blocks of the target cache line, a cache data block having a hit identifier with the highest bit in the cache identifier to obtain a second target cache data block comprises: Determine, among the cache data blocks of the target cache line, a cache data block having a highest identification bit of a hit identification in a cache identification as a candidate data block, and determine whether there is a cache data block in the cache data of the target cache line whose cache identification does not contain a hit identification; If there is no cache data block in each cache data whose cache identifier does not include a hit identifier, the to-be-selected data block is determined as the second target cache data block.

7. The data block cache update method according to any one of claims 1 to 6, characterized in that: After refreshing the cache identifiers of each group of cache identifiers of the target chip based on the preset shift register mechanism, the method further includes: Reacquiring the data access request, and entering the access address in the data access request into the target cache line for data matching; The cache identifier corresponding to the cache data block with successful data matching is shifted left and the hit identifier is filled at the end. At the same time, the cache identifiers corresponding to other cache data blocks are shifted left and the hit identifier is filled at the end.

8. A data block cache update device, characterized in that: include: An access request judgment module is used to obtain a data access request for a target chip, and enter a target cache line to perform data matching based on an access address in the data access request, so as to judge whether the data access request is a memory hit according to the data matching result; a cache state determination module, configured to determine a target memory access identification signal of the target cache line if the data access request does not result in a memory access hit, and determine whether the data cache operation state is an initial filling state or a normal operation state according to the number of hit identifications in the target memory access identification signal; a hit identifier acquisition module, configured to determine a first target cache data block based on the hit identifier of the lowest bit in the target memory access identifier signal if the data cache operation state is a normal operation state, and obtain a distance between hit identifiers in the first target cache data block; A cache refresh module is used to replace the first target cache data block with the current data block in the data access request to complete the cache data block update if the distance is less than a preset distance threshold, and to refresh the cache identifiers of each group of cache identifiers of the target chip based on a preset shift register mechanism.

9. An electronic device, characterized in that: include: Memory, used to store computer programs; A processor, configured to execute the computer program to implement the data block cache updating method according to any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that Used to store a computer program, which, when executed by a processor, implements the data block cache update method according to any one of claims 1 to 7.

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