Pseudo-random sequence generation circuit and pseudo-random sequence generation method for processor

Abstract

The present application relates to a pseudo-random sequence generation circuit and a pseudo-random sequence generation method for a processor. Based on the present application, a shift deduction circuit of the processor can deduce the shift deduction results of multiple single-bit registers subjected to linear feedback shifting for a specified number of shifts. The shift deduction circuit can use the shift deduction results to complete the shift jump of the multiple single-bit registers after the linear feedback shifting for the specified number of shifts at one time. In addition, the shift deduction results can also include the output register values of the output bit registers configured in the multiple single-bit registers during the linear feedback shifting for the specified number of shifts. Therefore, the output register values of the output bit registers obtained at one time in the shift deduction results can be output in parallel as the corresponding bits of the pseudo-random sequence, thereby achieving parallel output of the pseudo-random sequence, which in turn helps to reduce the operating frequency required to generate the pseudo-random sequence in the processor.

Description

Technical Field

[0001] The present application relates to the field of integrated circuits, and in particular to a pseudo-random sequence generation circuit for a processor, a pseudo-random sequence generation method for a processor, and a processor. Background Art

[0002] A processor can use a linear feedback shift register (LFSR) to generate a pseudo-random sequence. The pseudo-random sequence has multiple bits, and the multiple bits of the pseudo-random sequence are generated serially by the LFSR. That is, the LFSR can only generate one bit of the pseudo-random sequence in one operating clock cycle.

[0003] The operating frequency of the linear feedback shift register used to generate the pseudo-random sequence must match the data rate at which the processor transmits the pseudo-random sequence. If the processor's transmission rate is high, the operating frequency of the linear feedback shift register used to generate the pseudo-random sequence for the processor will inevitably increase accordingly, potentially even exceeding a level that is difficult to achieve with the processor's manufacturing process. For example, if the processor's transmission rate is 16 Gbps and the pseudo-random sequence consists of 16 bits, the operating frequency of the linear feedback shift register used to serially generate the pseudo-random sequence for the processor must reach 16 GHz, and the processor's manufacturing process is difficult to meet such a high operating frequency.

[0004] Therefore, how to reduce the operating frequency required to generate a pseudo-random sequence in a processor has become a technical problem to be solved in related technologies. Summary of the Invention

[0005] Embodiments of the present application provide a pseudo-random sequence generation circuit for a processor, a pseudo-random sequence generation method for a processor, and a processor, which help reduce the operating frequency required to generate a pseudo-random sequence in the processor.

[0006] In one embodiment of the present application, a pseudo-random sequence generation circuit for a processor is provided, comprising:

[0007] A register group, comprising a plurality of single-bit registers; wherein one of the plurality of single-bit registers is designated as an output bit register in a set linear feedback shift topology;

[0008] Shift deduction circuit for:

[0009] Determining, based on pre-configured shift prediction information, shift deduction results of the multiple single-bit registers after completing a specified number of linear feedback shifts; wherein the shift prediction information is determined based on the linear feedback shift topology, the specified number of shifts is determined by a set number of bits in a pseudo-random sequence, and the shift deduction results include: the update register value of the last linear feedback shift of each single-bit register in the multiple single-bit registers within the specified number of shifts, and each output register value of the output bit register for each linear feedback shift within the specified number of shifts;

[0010] Based on the shift deduction result, synchronous updating of the multiple single-bit registers and parallel output of the pseudo-random sequence are achieved; wherein the synchronous updating is used to synchronously update the multiple single-bit registers to the updated register value of the last linear feedback shift in the specified number of shifts, and the parallel output of the pseudo-random sequence includes: outputting the output register value of each linear feedback shift of the output bit register in the specified number of shifts in parallel as the corresponding bit of the pseudo-random sequence.

[0011] In some examples, optionally, the shift prediction information is used to characterize: an iterative logical relationship between an updated register value of each single-bit register in the multiple single-bit registers in any number of linear feedback shifts and an initial register value of at least one associated single-bit register; wherein the at least one associated single-bit register is predetermined among the multiple single-bit registers by performing shift deduction of the arbitrary number of linear feedback shifts based on the linear feedback shift topology; the shift deduction circuit is specifically used to determine the shift deduction result in the following manner: determining the shift deduction result based on the shift prediction information and the initial register value of the at least one associated single-bit register.

[0012] In some examples, optionally, the shift prediction information includes multiple iterative logical relationship tables corresponding to different numbers of linear feedback shifts; wherein each iterative logical relationship table in the multiple iterative logical relationship tables is used to characterize: the iterative logical relationship between the updated register value of each single-bit register in the multiple single-bit registers corresponding to the number of linear feedback shifts in the iterative logical relationship table and the initial register value of at least one associated single-bit register; the at least one associated single-bit register is predetermined among the multiple single-bit registers by using the shift deduction of the arbitrary number of linear feedback shifts based on the linear feedback shift topology; the shift deduction circuit is specifically used to determine the shift deduction result in the following manner: based on the lookup table operation of the multiple iterative logical relationship tables and the initial register value of the at least one associated single-bit register, determine the shift deduction result.

[0013] In some examples, optionally, the first lookup table hit object of the lookup table operation with the specified number of shifts as the index includes: the iterative logical relationship table corresponding to the last linear feedback shift in the specified number of shifts in the multiple iterative logical relationship tables; the first lookup table result of the lookup table operation on the first lookup table hit object includes: the iterative logical relationship between the updated register value of each linear feedback shift of the output bit register except the last one in the specified number of shifts and the initial register value of the at least one associated single-bit register; the process of the shift deduction circuit determining the shift deduction result includes: determining the updated register value of each single-bit register in the multiple single-bit registers after completing the last linear feedback shift in the specified number of shifts based on the first lookup table result and the initial register value of the at least one associated single-bit register.

[0014] In some examples, optionally, each output register value of the output bit register includes, in sequence: the initial register value of the output bit register, and the updated register value of each linear feedback shift of the output bit register except the last one in the specified number of shifts; the second lookup table hit object of the lookup table operation with the specified number of shifts as the index includes: the iterative logical relationship table of each linear feedback shift except the last one in the multiple iterative logical relationship tables corresponding in sequence to the specified number of shifts; the second lookup table result of the lookup table operation on the first lookup table hit object includes: the iterative logical relationship between the initial register value of the output bit register and the updated register value of each linear feedback shift of the output bit register except the last one in the specified number of shifts; the process of the shift deduction circuit determining the shift deduction result includes: determining each output register value of the output bit register based on the second lookup table result and the initial register value of the at least one associated single-bit register.

[0015] In some examples, optionally, each iterative logical relationship table in the multiple iterative logical relationship tables includes: an operational polynomial corresponding to each single-bit register in the multiple single-bit registers; wherein, any operational polynomial included in each iterative logical relationship table in the multiple iterative logical relationship tables is used to characterize: the iterative logical relationship between the updated register value of the single-bit register corresponding to the operational polynomial at the linear feedback shift number corresponding to the iterative logical relationship table and the initial register value of the at least one associated single-bit register.

[0016] In some examples, optionally, the cycle period of the linear feedback shift of the plurality of single-bit registers is 2 M -1 , M represents the total number of registers of the plurality of single-bit registers, and the total number of the plurality of iterative logical relationship tables is less than or equal to 2 M-1 .

[0017] In some examples, optionally, an information storage circuit is further included to store the shift prediction information.

[0018] In some examples, optionally, the shift deduction circuit is further used to receive a pseudo-random sequence generation instruction; wherein the pseudo-random sequence generation instruction is used to indicate the set number of bits of the pseudo-random sequence.

[0019] In another embodiment of the present application, a pseudo-random sequence generation method for a processor is provided. The processor includes a register group, the register group includes a plurality of single-bit registers, one of the plurality of single-bit registers is designated as an output bit register in a set linear feedback shift topology, and the pseudo-random sequence generation method includes:

[0020] Determining, based on pre-configured shift prediction information, shift deduction results of the multiple single-bit registers after completing linear feedback shifts for a specified number of shifts; wherein the shift prediction information is determined based on the linear feedback shift topology, the specified number of shifts is determined by a set number of bits in a pseudo-random sequence, and the shift deduction results include: the update register value of the last linear feedback shift of each single-bit register in the multiple single-bit registers for the specified number of shifts, and each output register value of the output bit register for each linear feedback shift for the specified number of shifts;

[0021] Based on the shift deduction result, synchronous updating of the multiple single-bit registers and parallel output of the pseudo-random sequence are achieved; wherein the synchronous updating is used to synchronously update the multiple single-bit registers to the updated register value of the last linear feedback shift in the specified number of shifts, and the parallel output of the pseudo-random sequence includes: outputting the output register value of each linear feedback shift of the output bit register in the specified number of shifts in parallel as the corresponding bit of the pseudo-random sequence.

[0022] In some examples, optionally, the shift prediction information is used to characterize: an iterative logical relationship between an updated register value of each single-bit register in the multiple single-bit registers in any number of linear feedback shifts and an initial register value of at least one associated single-bit register; wherein the at least one associated single-bit register is predetermined among the multiple single-bit registers by performing shift deduction of the arbitrary number of linear feedback shifts based on the linear feedback shift topology; determining the shift deduction results of the multiple single-bit registers after completing the linear feedback shift for a specified number of shifts based on the pre-configured shift prediction information includes: determining the shift deduction result based on the shift prediction information and the initial register value of the at least one associated single-bit register.

[0023] In some examples, optionally, the shift prediction information includes multiple iterative logical relationship tables corresponding to different numbers of linear feedback shifts; wherein each iterative logical relationship table in the multiple iterative logical relationship tables is used to characterize: an iterative logical relationship between an updated register value of each single-bit register in the multiple single-bit registers corresponding to the number of linear feedback shifts in the iterative logical relationship table and an initial register value of the at least one associated single-bit register; the at least one associated single-bit register is predetermined among the multiple single-bit registers by performing shift deduction of the arbitrary number of linear feedback shifts based on the linear feedback shift topology; the determining, based on the pre-configured shift prediction information, shift deduction results of the multiple single-bit registers after completing the linear feedback shift of the specified number of shifts includes: determining the shift deduction result based on a lookup table operation on the multiple iterative logical relationship tables and the initial register value of the at least one associated single-bit register.

[0024] In some examples, optionally, the first lookup table hit object indexed by the lookup table operation with the specified number of shifts as the index includes: an iterative logical relationship table corresponding to the last linear feedback shift in the specified number of shifts in the multiple iterative logical relationship tables; the first lookup table result of the lookup table operation on the first lookup table hit object includes: an iterative logical relationship between the updated register value of the last linear feedback shift of each single-bit register in the multiple single-bit registers in the specified number of shifts and the initial register value of the at least one associated single-bit register; the shift deduction result is determined based on the lookup table operation on the multiple iterative logical relationship tables and the initial register value of the at least one associated single-bit register, including: determining the updated register value of the last linear feedback shift of each single-bit register in the multiple single-bit registers in the specified number of shifts based on the first lookup table result and the initial register value of the at least one associated single-bit register.

[0025] In some examples, optionally, each output register value of the output bit register includes, in sequence: the initial register value of the output bit register, and the updated register value of each linear feedback shift of the output bit register except the last one in the specified number of shifts; a second lookup table hit object indexed by the lookup table operation with the specified number of shifts as an index includes: iterative logical relationship tables in the multiple iterative logical relationship tables that correspond in sequence to each linear feedback shift except the last one in the specified number of shifts; a second lookup table result of the lookup table operation on the second lookup table hit object includes: an iterative logical relationship between the updated register value of each linear feedback shift of the output bit register except the last one in the specified number of shifts and the initial register value of the at least one associated single-bit register; and determining the shift deduction result based on the lookup table operation on the multiple iterative logical relationship tables and the initial register value of the at least one associated single-bit register includes: determining each output register value of the output bit register based on the second lookup table result and the initial register value of the at least one associated single-bit register.

[0026] In some examples, optionally, each iterative logical relationship table in the multiple iterative logical relationship tables includes: an operational polynomial corresponding to each single-bit register in the multiple single-bit registers; wherein, any operational polynomial included in each iterative logical relationship table in the multiple iterative logical relationship tables is used to characterize: the iterative logical relationship between the updated register value of the single-bit register corresponding to the operational polynomial at the linear feedback shift number corresponding to the iterative logical relationship table and the initial register value of the at least one associated single-bit register.

[0027] In some examples, optionally, the cycle period of the linear feedback shift of the plurality of single-bit registers is 2 M -1 , M represents the total number of registers of the plurality of single-bit registers, and the total number of the plurality of iterative logical relationship tables is less than or equal to 2 M-1 .

[0028] In another embodiment of the present application, a processor is provided, comprising the pseudo-random sequence generation circuit as described above.

[0029] According to an embodiment of the present application, a processor may include a register group and a shift deduction circuit. Multiple single-bit registers in the register group may have a shift relationship based on a preset linear feedback shift topology. The shift deduction circuit may deduce shift deduction results of the multiple single-bit registers subjected to linear feedback shifting for a specified number of shifts. The shift deduction circuit may use the shift deduction results to simultaneously complete shift jumps of the multiple single-bit registers after the linear feedback shifting for the specified number of shifts. Furthermore, the shift deduction results may further include output register values of output bit registers configured in the multiple single-bit registers during the linear feedback shifting for the specified number of shifts. Since the specified number of shifts in the linear feedback shifting corresponds to a set number of bits in a pseudo-random sequence, the output register values of the output bit registers obtained in the shift deduction results may be output in parallel as corresponding bits of the pseudo-random sequence, thereby achieving parallel output of the pseudo-random sequence. Furthermore, compared to a linear feedback shift register that generates a pseudo-random sequence serially, the scheme of generating a pseudo-random sequence in parallel based on shift deduction in the embodiment of the present application helps to reduce the operating frequency required to generate a pseudo-random sequence in a processor. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] The following drawings are only provided for schematic illustration and explanation of the present application and do not limit the scope of the present application:

[0031] Figure 1 Schematic diagram of an exemplary structure of a pseudo-random sequence generation circuit for a processor in an embodiment of the present application;

[0032] Figure 2 Schematic diagram of the principle of a linear feedback shift topology applicable to a register group in an embodiment of the present application;

[0033] Figure 3 Schematic diagram of another linear feedback shift topology applicable to a register group in an embodiment of the present application;

[0034] Figure 4 Schematic diagram of the deduction principle of the pseudo-random sequence generation circuit for the processor in an embodiment of the present application;

[0035] Figure 5 Schematic diagram of the deduction principle of the pseudo-random sequence generation circuit for the processor based on the lookup table in an embodiment of the present application;

[0036] Figure 6 A schematic diagram of an example of a linear feedback shift topology set for a register group in an embodiment of the present application;

[0037] Figure 7 Schematic diagram of an exemplary flow chart of a pseudo-random sequence generation method for a processor in an embodiment of the present application. DETAILED DESCRIPTION

[0038] In order to make the objectives, technical solutions and advantages of this application more clear, the application is further described in detail below with reference to the accompanying drawings and examples.

[0039] Figure 1 This is an exemplary structural diagram of a pseudo-random sequence generation circuit for a processor in an embodiment of the present application. Figure 1 In an embodiment of the present application, a pseudo-random sequence generation circuit for a processor may include a register group 10, an information storage circuit 20, and a shift deduction circuit 30.

[0040] Illustratively, in an embodiment of the present application, the register group 10 may include a plurality (eg, M) of single-bit registers Reg_1 to Reg_M, where M is a positive integer greater than 1.

[0041] For example, in an embodiment of the present application, register values of multiple single-bit registers Reg_1 through Reg_M may have a shift relationship based on a preset linear feedback shift topology, and one of the multiple single-bit registers Reg_1 through Reg_M (e.g., single-bit register Reg_M) may be designated as the output bit register in the preset linear feedback shift topology. The shift relationship based on the linear feedback shift topology may mean that the updated changes in the register values of the multiple single-bit registers Reg_1 through Reg_M and the output register value of the output bit register Reg_M resulting from the linear feedback shift all conform to the shift change rules of the linear feedback shift topology, and the multiple single-bit registers Reg_1 through Reg_M do not need to actually undergo multiple shift iterations of the register values according to the operating frequency. For example, it is not necessary to establish a real electrical connection between the multiple single-bit registers Reg_1 to Reg_M according to the linear feedback shift topology, and the multiple single-bit registers Reg_1 to Reg_M can each be independently electrically connected to the shift deduction circuit 30. In this case, it can be considered that the register group 10 (i.e., the multiple single-bit registers Reg_1 to Reg_M) and the shift deduction circuit 30 are connected via a parallel bus.

[0042] Figure 2 This is a schematic diagram of the principle of a linear feedback shift topology applicable to the register group in the embodiment of this application. Figure 2In an embodiment of the present application, it is assumed that one register Reg_1 among the multiple single-bit registers Reg_1 to Reg_M is designated as the input bit register in the linear feedback shift topology, and another register Reg_M is designated as the output bit register in the linear feedback shift topology. In this case, the multiple single-bit registers Reg_1 to Reg_M can be connected in series in a step-by-step arrangement direction from the input bit register Reg_1 to the output bit register Reg_M, and each single-bit register Reg_k (k is a positive integer greater than or equal to 1 and less than or equal to M) among the multiple single-bit registers Reg_1 to Reg_M is also connected to a function operation circuit. The function operation circuit is used to perform logical operations such as exclusive OR operations on the register values D_1 to D_M of the multiple single-bit registers Reg_1 to Reg_M based on a preset logical operation function F(D_1, D_2, ..., D_M), and the output end of the function operation circuit for generating the operation result can be connected to the input bit register Reg_1. For example, Figure 2 The linear feedback shift topology shown is similar to a Galois topology model applied to a linear feedback shift register in the related art.

[0043] If based on Figure 2 The linear feedback shift topology shown is applied to a linear feedback shift register. The actual shift process that occurs in any working clock cycle includes:

[0044] A result of a logic operation performed on register values D_1 to D_M of multiple single-bit registers Reg_1 to Reg_M in a previous working clock cycle using a logic operation function F(D_1, D_2, ..., D_M) can be used as the register value V1 of the input bit register Reg_1 in the current working clock cycle;

[0045] The register value D_k of each single-bit register Reg_k among the multiple single-bit registers Reg_1 to Reg_M, excluding the output bit register Reg_M, can be shifted to the subsequent single-bit register Reg_k+1 on the side where the output bit register Reg_M is located, where k is a positive integer greater than or equal to 1 and less than or equal to M-1. That is, the register values of the single-bit registers Reg_2 to Reg_M are updated so that "D_k+1=D_k";

[0046] The register value D_M of the output bit register Reg_M in the previous working clock cycle can be output as the output register value D_out.

[0047] In the embodiments of the present application, Figure 2The function operation circuit in FIG1 and the connections between the multiple single-bit registers Reg_1 to Reg_M are all represented by dotted lines, which means that the pseudo-random sequence generation circuit for the processor may not include Figure 2 The function operation circuit shown in FIG. 1 is shown in FIG. 2 , and the multiple single-bit registers Reg_1 to Reg_M may not be connected in series in a sequential manner. In this case, the update changes of the register values D_1 to D_M of the multiple single-bit registers Reg_1 to Reg_M, and the output register value D_out generated by the output bit register Reg_M due to the linear feedback shift, can still meet the following conditions: Figure 2 The shift change rules in the linear feedback shift topology shown in FIG. 3 , and based on the shift deduction of the shift deduction circuit 30 , the update changes of the register values D_1 to D_M of the multiple single-bit registers Reg_1 to Reg_M after multiple shifts, and the multiple outputs of the output register value D_out of the output bit register Reg_M due to the multiple linear feedback shifts, can be completed all at once in one working clock cycle, rather than being completed successively over multiple working clock cycles as in the case of a linear feedback shift register.

[0048] Figure 3 This is a schematic diagram of another linear feedback shift topology applicable to the register group in the embodiment of the present application. Figure 3 In the embodiment of the present application, it is assumed that one register Reg_1 among the multiple single-bit registers Reg_1~Reg_M is designated as the input bit register in the linear feedback shift topology, and another register Reg_M is designated as the output bit register in the linear feedback shift topology. In this case, in the direction of stepwise arrangement from the input bit register Reg_1 to the output bit register Reg_M, any two adjacent single-bit registers Reg_k to Reg_k+1 among the multiple single-bit registers Reg_1 to Reg_M can be connected via an exclusive OR operation circuit (indicated by the symbol “⊕” marked with the character “XOR” in the figure), and the output bit register Reg_M is also connected to the exclusive OR operation circuit between any two adjacent single-bit registers Reg_k to Reg_k+1. The exclusive OR operation circuit between any two adjacent single-bit registers Reg_k to Reg_k+1 is used to perform an exclusive OR operation using the register value D_k of the previous stage single-bit register Reg_k and the register value D_M of the output bit register Reg_M, and the operation result of the exclusive OR operation circuit between any two adjacent single-bit registers Reg_k to Reg_k+1 is used to output to the next stage single-bit register Reg_k+1. For example, Figure 3 The linear feedback shift topology shown is similar to an Xorshift (exclusive OR shift) topology model applied to a linear feedback shift register in the related art.

[0049] If based on Figure 3 The linear feedback shift topology shown is applied to a linear feedback shift register. The actual shift process that occurs in any working clock cycle includes:

[0050] The register value D_M of the output bit register Reg_M in the previous working clock cycle can be used as the register value V1 of the input bit register Reg_1 in the current working clock cycle;

[0051] The register value D_k of each single-bit register Reg_k among the multiple single-bit registers Reg_1 to Reg_M, excluding the output bit register Reg_M, can be shifted to the subsequent single-bit register Reg_k+1 on the side where the output bit register Reg_M is located through an exclusive-OR operation circuit, where k is a positive integer greater than or equal to 1 and less than or equal to M-1. That is, the register value of the single-bit registers Reg_2 to Reg_M is updated to "D_k+1=D_k XOR D_M".

[0052] The register value D_M of the output bit register Reg_M in the previous working clock cycle can be output as the output register value D_out.

[0053] In the embodiments of the present application, Figure 3 The XOR operation circuit and the connections between the multiple single-bit registers Reg_1 to Reg_M are all represented by dotted lines, which means that the pseudo-random sequence generation circuit for the processor may not include Figure 3 The XOR operation circuit shown in FIG, and the multiple single-bit registers Reg_1 to Reg_M may not be connected through the XOR operation circuit. In this case, the update changes of the register values D_1 to D_M of the multiple single-bit registers Reg_1 to Reg_M and the output register value D_out generated by the output bit register Reg_M due to the linear feedback shift can still meet the following conditions: Figure 3 The shift change rules in the linear feedback shift topology shown in FIG. 3 , and based on the shift deduction of the shift deduction circuit 30 , the update changes of the register values D_1 to D_M of the multiple single-bit registers Reg_1 to Reg_M after multiple shifts, and the multiple outputs of the output register value D_out of the output bit register Reg_M due to the multiple linear feedback shifts, can be completed all at once in one working clock cycle, rather than being completed successively over multiple working clock cycles as in the case of a linear feedback shift register.

[0054] In the embodiments of the present application, Figure 2 and Figure 3The illustrated linear feedback shift topology is intended to facilitate understanding of the shift relationship between the register values of multiple single-bit registers Reg_1 through Reg_M based on the linear feedback shift topology, and is not intended to unnecessarily limit the rules governing the updates of the register values D_1 through D_M of the multiple single-bit registers Reg_1 through Reg_M, or the output register value D_out generated by the output bit register Reg_M due to the linear feedback shift. For example, any linear feedback shift topology that meets the following conditions may be applicable to the embodiments of the present application: the feedback source in the linear feedback shift includes the register value D_M of the output bit register Reg_M, and the update of the register value D_1 of the input bit register Reg_1 is associated with the register value D_M of the output bit register Reg_M.

[0055] For example, in an embodiment of the present application, the information storage circuit 20 can be used to store pre-configured shift prediction information. The shift prediction information is determined based on a linear feedback shift topology set for multiple single-bit registers Reg_1 to Reg_M, and the shift prediction information can be used to characterize: updates and changes in register values D_1 to D_M of the multiple single-bit registers Reg_1 to Reg_M based on the linear feedback shift topology, and the rules for the output register value D_out generated by the output bit register Reg_M due to the linear feedback shift based on the linear feedback shift topology.

[0056] For example, in an embodiment of the present application, pre-configured shift prediction information can be used to specifically represent: an iterative logical relationship between an updated register value D_i_j of each single-bit register Reg_i among the plurality of single-bit registers Reg_1 to Reg_M during any number of linear feedback shifts (i.e., the j-th linear feedback shift of the single-bit register Reg_i starting from its initial register value D_i_0) and the initial register value of at least one associated single-bit register among the plurality of single-bit registers Reg_1 to Reg_M (i.e., an iterative logical relationship between the updated register value D_i_j of the single-bit register Reg_i and the initial register value of at least one associated single-bit register). Where i is a positive integer greater than or equal to 1 and less than or equal to M, and j is a positive integer greater than or equal to 1 and used to represent any number of times.

[0057] Illustratively, in an embodiment of the present application, at least one associated single-bit register among the multiple single-bit registers Reg_1 to Reg_M can be predetermined among the multiple single-bit registers Reg_1 to Reg_M by using a shift deduction of any number of linear feedback shifts starting from an initial register value D_i_0 based on a pre-set linear feedback shift topology.

[0058] Illustratively, in an embodiment of the present application, the value range of any number represented by j may be less than or equal to the maximum number of shifts that can be supported by the shift deduction of the shift deduction circuit 30 .

[0059] For example, in the embodiment of the present application, the cycle period of the linear feedback shift of the plurality of single-bit registers Reg_1 to Reg_M (ie, the cycle period in which the output register value D_out of the output bit register Reg_M is not repeated) may be 2 M-1 , and the maximum number of shifts supported by the shift deduction circuit 30 can be less than or equal to the cycle period 2 M -1 .

[0060] Exemplarily, in an embodiment of the present application, the specified number of shifts N may be determined by a set number of bits Q of the pseudo-random sequence to be generated, the specified number of shifts N and the set number of bits Q are both positive integers greater than 1, the set number of bits Q may be P times the specified number of shifts N, and P is a positive integer greater than or equal to 1. For example, the specified number of shifts N may be equal to the set number of bits Q, or may be half of the set number of bits Q.

[0061] For example, in an embodiment of the present application, the set bit number Q of the pseudo-random sequence indicated by the pseudo-random sequence generation instruction may be limited to be less than the cycle period 2 M-1 , and the specified number of shifts N may be limited to be less than or equal to the maximum number of shifts that can be supported by the shift deduction of the shift deduction circuit 30 .

[0062] Exemplarily, in an embodiment of the present application, the shift deduction circuit 30 can be used to implement shift deduction in the following manner: based on the pre-configured shift prediction information stored in the information storage circuit 20, determine the shift deduction results after multiple single-bit registers Reg_1~Reg_M complete the linear feedback shift of a specified number of shifts N.

[0063] For example, in an embodiment of the present application, the shift deduction circuit 30 may be configured to receive a pseudo-random sequence generation instruction. The pseudo-random sequence generation instruction may be configured to indicate a set number of bits, Q, of the pseudo-random sequence. Furthermore, the pseudo-random sequence generation instruction may be configured to trigger the shift deduction circuit 30 to perform a shift deduction on the register group 10 (i.e., the plurality of single-bit registers Reg_1 to Reg_M) to determine a shift deduction result. Specifically, the shift deduction circuit 30 may trigger a shift deduction on the register group 10 (i.e., the plurality of single-bit registers Reg_1 to Reg_M) in response to the pseudo-random sequence generation instruction, and determine a specified number of linear feedback shifts, N, required for the shift deduction triggered in response to the pseudo-random sequence generation instruction.

[0064] For example, in an embodiment of the present application, the initial register value D_i_0 of each single-bit register Reg_i among the multiple single-bit registers Reg_1~Reg_M before the start of the first linear feedback shift in the specified shift number N can also be considered as the register value when the shift deduction circuit 30 is triggered to perform shift deduction (that is, it is triggered to perform the determination of the shift deduction result).

[0065] For example, in an embodiment of the present application, the shift deduction circuit 30 can be specifically used to determine the shift deduction result in the following manner: based on pre-configured shift prediction information (for example, shift prediction information stored in the information storage circuit 20) and the initial register value of at least one associated single-bit register predetermined among the multiple single-bit registers Reg_1~Reg_M, determine the shift deduction result for the register group 10 (that is, the multiple single-bit registers Reg_1~Reg_M).

[0066] Figure 4 This is a schematic diagram of the deduction principle of the pseudo-random sequence generation circuit used in the processor in the embodiment of the present application. Figure 4 In an embodiment of the present application, when the shift deduction circuit 30 is triggered to perform shift deduction on the register group 10 (i.e., the multiple single-bit registers Reg_1 through Reg_M), it can concurrently (or synchronously) read the current register values of the multiple single-bit registers Reg_1 through Reg_M as the initial register values D_1_0 through D_M_0 of the multiple single-bit registers Reg_1 through Reg_M. Furthermore, in an embodiment of the present application, when concurrently (or synchronously) reading the initial register values D_1_0 through D_M_0 of the multiple single-bit registers Reg_1 through Reg_M, the shift deduction circuit 30 can query the information storage circuit 20 for pre-configured shift prediction information.

[0067] For example, in the embodiments of the present application, Figure 4 As shown, based on the concurrently (or synchronously) read initial register values D_1_0 to D_M_0 of the multiple single-bit registers Reg_1 to Reg_M and the query result of the shift prediction information (such as the iterative logical relationship described above), the shift deduction result determined by the shift deduction circuit 30 may specifically include:

[0068] update register values {D_1_N, D_2_N, ..., D_M_N} of the multiple single-bit registers Reg_1 to Reg_M in the last (i.e., Nth) linear feedback shift within a specified number of shifts (i.e., N times), including update register value D_i_N of the last (i.e., Nth) linear feedback shift of each single-bit register Reg_i in the multiple single-bit registers Reg_1 to Reg_M; and,

[0069] The output register values {D_out_1, D_out_2, ..., D_out_N} of the output bit register Reg_M in each linear feedback shift (i.e., N linear feedback shifts, from the 1st to the Nth) within a specified number of shifts (i.e., N times) are as follows: wherein the output register value D_out_j of any linear feedback shift (i.e., the jth) within the specified number of shifts (i.e., N times) may be the previous register value of the output bit register Reg_M before the linear feedback shift (i.e., the jth) time.

[0070] For example, in an embodiment of the present application, the previous register value of the output bit register Reg_M before the first (i.e., when j is equal to 1) linear feedback shift of the output bit register Reg_M within a specified number of shifts (i.e., N times) may be the initial register value D_M_0 of the output bit register Reg_M before the start of the first linear feedback shift of the output bit register Reg_M within the specified number of shifts (i.e., N times) (i.e., when the shift deduction circuit 30 is triggered to perform shift deduction); the previous register value of the output bit register Reg_M before each linear feedback shift starting from the second (i.e., when j is greater than 1) within the specified number of shifts (i.e., N times) may be the updated register values D_M_1 to D_M_N-1 of each linear feedback shift of the output bit register Reg_M except the last (i.e., Nth) within the specified number of shifts (i.e., N times) (i.e., the 1st to N-1st linear feedback shifts). Thus, the output register values {D_out_1, D_out_2, ..., D_out_N} of the output bit register Reg_M may sequentially include: the initial register value D_M_0 of the output bit register Reg_M before the first linear feedback shift in a specified number of shifts (i.e., N times) begins (i.e., when the shift deduction circuit 30 is triggered to perform shift deduction); and the updated register values D_M_1 to D_M_N-1 of each linear feedback shift (i.e., the 1st to N-1st linear feedback shifts) of the output bit register Reg_M in the specified number of shifts (i.e., N times) except for the last (i.e., the Nth time).

[0071] Illustratively, in an embodiment of the present application, the shift deduction circuit 30 may also be used to: based on the determined shift deduction result, realize synchronous update of multiple single-bit registers Reg_1 to Reg_M and parallel output of the pseudo-random sequence PRS.

[0072] For example, in the embodiments of the present application, Figure 4 As shown, the shift deduction circuit 30 synchronously updates the multiple single-bit registers Reg_1 to Reg_M, which can be used to: synchronously update (or synchronously assign values) the multiple single-bit registers Reg_1 to Reg_M to the updated register values D_1_N to D_M_N of the last (i.e., Nth) linear feedback shift of each single-bit register Reg_1 to Reg_M in a specified number of shifts (i.e., N times); that is, synchronously update the initial register values D_1_0 to D_M_0 of the multiple single-bit registers Reg_1 to Reg_M directly (or once) to the updated register values D_1_N to D_M_N of the last (i.e., Nth) linear feedback shift of each single-bit register Reg_1 to Reg_M in a specified number of shifts (i.e., N times). That is, each single-bit register Reg_i among the multiple single-bit registers Reg_1 to Reg_M can directly (or all at once) jump from the initial register value D_i_0 to the updated register value D_i_N of the last (i.e., Nth) linear feedback shift of the single-bit register Reg_i in the specified number of shifts (i.e., N times).

[0073] For example, in the embodiments of the present application, Figure 4 As shown, the parallel output process of the pseudo-random sequence PRS implemented by the shift deduction circuit 30 may include: using the output register values {D_out_1, D_out_2, ..., D_out_N} (i.e., D_M_0 and D_M_1 to D_M_N-1) of each linear feedback shift of the output bit register Reg_M in a specified number of shifts (i.e., N times) as Q bits of the pseudo-random sequence PRS ( Figure 4 The corresponding bits are output in parallel, taking the example of specifying the shift number N equal to the set bit Q as an example.

[0074] Based on an embodiment of the present application, a processor may include a register group 10 and a shift deduction circuit 30. A shift relationship based on a preset linear feedback shift topology may exist between the multiple single-bit registers Reg_1 to Reg_M in the register group 10, and the shift deduction circuit 30 may directly deduce the shift deduction results of the linear feedback shift of the multiple single-bit registers Reg_1 to Reg_M after a specified number of shifts. Wherein: multiple single-bit registers Reg_1 to Reg_M can be synchronously updated to updated register values D_1_N to D_M_N after linear feedback shifting for a specified number of shifts (i.e., N times) using the shift deduction result, so that the multiple single-bit registers can complete the shift jump of the linear feedback shift for the specified number of shifts at one time (e.g., within one working clock cycle); the specified number of linear feedback shifts (i.e., N times) corresponds to the set number of bits Q of the pseudo-random sequence, and the shift deduction result can also include the output register values D_out_1 to D_out_N (i.e., D_M_0 and D_M_1 to D_M_N-1) of the output bit register Reg_M configured in the multiple single-bit registers Reg_1 to Reg_M during the linear feedback shift for the specified number of shifts. Therefore, the output register values D_out_1 to D_out_N (i.e., D_M_0 and D_M_1 to D_M_N-1) of the output bit register Reg_M are D_M_N-1) can be output in parallel as corresponding bits of a pseudo-random sequence (e.g., output in parallel within a single operating clock cycle), thereby enabling parallel output of the pseudo-random sequence PRS. Furthermore, compared to a linear feedback shift register that serially generates a pseudo-random sequence, the shift-deduction-based parallel pseudo-random sequence generation scheme in the embodiments of the present application helps reduce the operating frequency required to generate the pseudo-random sequence in the processor.

[0075] For example, if the transmission rate of the processor can be 16 Gbps, the pseudo-random sequence includes 16 bits, and the specified number of shifts of the shift deduction is 16 times, then the pseudo-random sequence generation circuit in the embodiment of the present application can generate a 16-bit pseudo-random sequence in parallel in one working clock cycle. In this case, the operating frequency of the pseudo-random sequence generation circuit in the embodiment of the present application for generating pseudo-random sequences in parallel for the processor may only require 1 GHz, which is lower than the 16 GHz required by the linear feedback shift register.

[0076] For another example, if the transmission rate of the processor can be 16 Gbps, the pseudo-random sequence includes 16 bits, and the specified number of shift deductions is 8 times, then the pseudo-random sequence generation circuit in the embodiment of the present application can successively generate two groups of 8-bit sequence segments of the pseudo-random sequence in parallel through two working clock cycles. In this case, the operating frequency of the pseudo-random sequence generation circuit in the embodiment of the present application for generating pseudo-random sequences in parallel for the processor may only need 2 GHz, which is still lower than the 16 GHz required by the linear feedback shift register.

[0077] Figure 5 This is a schematic diagram of the deduction principle of the pseudo-random sequence generation circuit for the processor based on the lookup table in the embodiment of the present application. Figure 5 In an embodiment of the present application, the preconfigured shift prediction information stored in the information storage circuit 20 may include multiple iterative logical relationship tables {TBL} corresponding to linear feedback shifts of different shift orders j. Each of the multiple iterative logical relationship tables {TBL} is used to represent: an iterative logical relationship between the updated register value D_i_j of each single-bit register Reg_i among the multiple single-bit registers Reg_1 to Reg_M at the linear feedback shift order j corresponding to the iterative logical relationship table (i.e., the jth time for the single-bit register Reg_i starting from its initial register value D_i_0) and the initial register value of at least one predetermined associated single-bit register among the multiple single-bit registers Reg_1 to Reg_M (i.e., the iterative logical relationship between the updated register value D_i_j of the single-bit register Reg_i and the initial register value of at least one associated single-bit register).

[0078] Illustratively, in an embodiment of the present application, each iterative logical relationship table TBL_j in the multiple iterative logical relationship tables {TBL} includes: an arithmetic polynomial F(i, j) corresponding to each single-bit register Reg_i in the multiple single-bit registers Reg_1 to Reg_M; wherein, the arbitrary arithmetic polynomial F(i, j) included in each iterative logical relationship table TBL_j in the multiple iterative logical relationship tables {TBL} is used to represent: the iterative logical relationship between the updated register value D_i_j of the single-bit register Reg_i corresponding to the arithmetic polynomial F(i, j) in the multiple single-bit registers Reg_1 to Reg_M at the linear feedback shift number j corresponding to the iterative logical relationship table (i.e., the jth time of the single-bit register Reg_i starting from its initial register value D_i_0) and the initial register value of at least one predetermined associated single-bit register in the multiple single-bit registers Reg_1 to Reg_M (i.e., the iterative logical relationship between the updated register value D_i_j of the single-bit register Reg_i and the initial register value of at least one associated single-bit register).

[0079] For example, in an embodiment of the present application, any arithmetic polynomial F(i, j) included in each iterative logical relationship table TBL_j in the plurality of iterative logical relationship tables {TBL} includes an operand that represents the initial register value of at least one predetermined associated single-bit register among the plurality of single-bit registers Reg_1 to Reg_M. Therefore, any arithmetic polynomial F(i, j) included in each iterative logical relationship table TBL_j in the plurality of iterative logical relationship tables {TBL} can be used to indicate the initial register value of at least one predetermined associated single-bit register among the plurality of single-bit registers Reg_1 to Reg_M.

[0080] For example, in the embodiment of the present application, as described above, the cycle period of the linear feedback shift of the plurality of single-bit registers Reg_1 to Reg_M (ie, the cycle period in which the output register value D_out of the output bit register Reg_M is not repeated) can be 2 M-1 Therefore, the total number T of multiple iterative logical relationship tables {TBL} can be less than or equal to 2 M-1 .

[0081] For example, in an embodiment of the present application, the total number T of the multiple iterative logical relationship tables {TBL} can represent the maximum number of shifts that can be supported by the shift deduction circuit 30, and the specified number of shifts N can be limited to be less than or equal to the total number T of the multiple iterative logical relationship tables {TBL}. In this case, the value range of the linear feedback shift number j can be expressed as a positive integer greater than or equal to 1 and less than or equal to T.

[0082] Exemplarily, in an embodiment of the present application, the shift deduction circuit 30 can be specifically used to determine the shift deduction result in the following manner: based on a lookup-table operation on multiple iterative logical relationship tables {TBL} and an initial register value of at least one associated single-bit register predetermined among multiple single-bit registers Reg_1~Reg_M, the shift deduction result is determined.

[0083] For example, in an embodiment of the present application, in order to determine the updated register values D_1_N~D_M_N of the last (i.e., Nth) linear feedback shift of each single-bit register Reg_1~Reg_M in the shift deduction result in a specified number of shifts (i.e., N times), the first lookup table hit object indexed by the specified number N of times in the shift deduction circuit 30 may include: an iterative logical relationship table TBL_N corresponding to the last (i.e., Nth) linear feedback shift in the specified number of shifts (i.e., N times) in multiple iterative logical relationship tables {TBL}.

[0084] For example, in an embodiment of the present application, the first lookup table result of the lookup table operation performed by the shift deduction circuit 30 for a first lookup table hit object may include: an iterative logical relationship between the updated register value D_i_N of the last (i.e., Nth) linear feedback shift of each single-bit register Reg_i among the plurality of single-bit registers Reg_1 to Reg_M within a specified number of shifts (i.e., N times) and the initial register value of at least one predetermined associated single-bit register among the plurality of single-bit registers Reg_1 to Reg_M (i.e., the iterative logical relationship between the updated register value D_i_N of the single-bit register Reg_i and the initial register value of at least one associated single-bit register). For example, this iterative logical relationship may be represented by the operational polynomials F(1, N) to F(M, N) in the iterative logical relationship table TBL_N.

[0085] For example, in an embodiment of the present application, the process of the shift deduction circuit 30 determining the shift deduction result using the first lookup table result may include: determining, based on the first lookup table result and the initial register value of at least one predetermined associated single-bit register among the plurality of single-bit registers Reg_1 to Reg_M, an updated register value D_1_N to D_M_N for the last (i.e., Nth) linear feedback shift of each of the single-bit registers Reg_1 to Reg_M within a specified number of shifts (i.e., N times). Specifically, the updated register value D_1_N to D_M_N for the last (i.e., Nth) linear feedback shift of each of the single-bit registers Reg_1 to Reg_M within the specified number of shifts (i.e., N times) may be determined by substituting the initial register value of at least one predetermined associated single-bit register among the plurality of single-bit registers Reg_1 to Reg_M into the operational polynomials F(1, N)_1 to F(M, N) representing the iterative logical relationships corresponding to each of the single-bit registers Reg_1 to Reg_M, respectively, as shown in the first lookup table result.

[0086] Illustratively, in an embodiment of the present application, in order to determine the output register values {D_out_1, D_out_2, ..., D_out_N} (i.e., D_M_0 and D_M_1 to D_M_N-1) of each linear feedback shift of the output bit register Reg_M in a specified number of shifts (i.e., N times), the shift deduction circuit 30 may obtain a second lookup table hit object indexed by the specified number N, which may include: multiple iterative logical relationship tables {TBL} that correspond in sequence to each (i.e., the 1st to N-1th) linear feedback shift except the last one in the specified number of shifts (i.e., N times) TBL_1 to TBL_N-1.

[0087] For example, in an embodiment of the present application, the second lookup table result for the lookup table operation performed by the shift deduction circuit 30 for the second lookup table hit object may include: an iterative logical relationship between the updated register values D_M_1 to D_M_N-1 of each linear feedback shift of the output bit register Reg_M except the last one (i.e., the 1st to N-1st times) within a specified number of shifts (i.e., N times) and the initial register value of at least one predetermined associated single-bit register among the plurality of single-bit registers Reg_1 to Reg_M (i.e., an iterative logical relationship between each of the updated register values D_M_1 to D_M_N-1 of the output bit register Reg_M and the initial register value of at least one associated single-bit register). For example, these iterative logical relationships may be represented by the operational polynomials F(M, 1) to F(M, N-1) in the iterative logical relationship tables TBL_1 to TBL_N-1, respectively.

[0088] For example, in an embodiment of the present application, the process of the shift deduction circuit 30 determining the shift deduction result using the second lookup table result may include: determining, based on the second lookup table result and the initial register value of at least one predetermined associated single-bit register among the plurality of single-bit registers Reg_1 to Reg_M, the output register values {D_out_1, D_out_2, ..., D_out_N} of each linear feedback shift of the output bit register Reg_M for a specified number of shifts (i.e., N times). The first output register value D_out_1 of the output bit register Reg_M is the initial register value D_M_0 of the output bit register Reg_M, and the subsequent output register values D_out_2 to D_out_N of the output bit register Reg_M can be determined by sequentially substituting the initial register value of at least one predetermined associated single-bit register among the plurality of single-bit registers Reg_1 to Reg_M into the operational polynomials F(M, 1) to F(M, N-1) representing the iterative logical relationship in the second lookup table result.

[0089] Figure 6 Schematic diagram of an example of a linear feedback shift topology set for a register group in an embodiment of the present application. Figure 6 In the linear feedback shift topology example shown in FIG, the total number of registers M of the multiple single-bit registers Reg_1 to Reg_M is 23. In this case, Figure 6 In the linear feedback shift topology example shown, among the multiple single-bit registers Reg_1 to Reg_23, the single-bit registers Reg_2 and Reg_3, Reg_5 and Reg_6, Reg_8 and Reg_9, Reg_16 and Reg_17, and Reg_21 and Reg_22 are connected via an exclusive-OR circuit (indicated by the symbol "⊕" with the character "XOR" in the figure). The output bit register Reg_23 is also connected to the exclusive-OR circuit. The remaining adjacent single-bit registers among the multiple single-bit registers Reg_1 to Reg_23 are all directly connected.

[0090] For example, in the embodiment of the present application, taking the maximum number of shifts supported by the shift deduction circuit 30 as 16 as an example, the multiple single-bit registers Reg_1 to Reg_23 are based on the following formula: Figure 6 The shifting rules of the linear feedback shifting topology example shown can be found in Tables 1 to 16 listed below. Tables 1 to 16 correspond to the 1st to 16th linear feedback shifting times, respectively, and each of Tables 1 to 16 includes three table items.

[0091] Illustratively, in the embodiments of the present application, the first column of each table in Table 1 to Table 16 represents: the updated register value D_i_j of the plurality of single-bit registers Reg_1 to Reg_23 corresponding to the linear shift number j in the table.

[0092] For example, in an embodiment of the present application, the second column of each of Tables 1 to 16 represents the shift logic relationship between the update register value D_i_j of multiple single-bit registers Reg_1 to Reg_23 at the corresponding linear shift number j in that table and the previous register value of the associated single-bit register before the corresponding linear shift number j (i.e., j-1 times). The second column of each of Tables 1 to 16 may include an arithmetic polynomial G(i, j) for the previous register value of the associated single-bit register, which has an equivalent relationship with the update register value D_i_j of the corresponding single-bit register Reg_i. Thus, the equivalent relationship between the arithmetic polynomial G(i, j) in the second column and the update register value D_i_j can represent the shift logic relationship between the update register value D_i_j and the previous register value of the associated single-bit register. Furthermore, the symbol "^" in the arithmetic polynomial G(i, j) in the second column of each of Tables 1 to 16 represents an exclusive-OR operation.

[0093] For example, in an embodiment of the present application, the third column of each of Tables 1 to 16 represents the iterative logical relationship between the updated register value D_i_j of a plurality of single-bit registers Reg_1 to Reg_23 at the corresponding linear shift number j in that table and the initial register value of the associated single-bit register before the first linear feedback shift. The third column of each of Tables 1 to 16 may include an arithmetic polynomial F(i, j) for the initial register value of the associated single-bit register, which has an equivalent relationship with the updated register value D_i_j of the corresponding single-bit register Reg_i. Thus, the equivalent relationship between the arithmetic polynomial in the third column and the updated register value D_i_j represents the iterative logical relationship between the updated register value D_i_j and the initial register value of the associated single-bit register. Furthermore, the symbol "^" is used in the arithmetic polynomial in the third column of each of Tables 1 to 16 to represent an exclusive-OR operation.

[0094] For example, in an embodiment of the present application, the operational polynomial F(i, j) corresponding to each single-bit register Reg_i in the third column of each table in Tables 1 to 16 can be determined by iterating step by step with the operational polynomial G(i, j) corresponding to each single-bit register Reg_i in the second column of the preceding table. For example, the operational polynomial F(i, 8) corresponding to each single-bit register Reg_i in the third column of Table 8 can be determined by substituting the operational polynomial G(i, 1) corresponding to the single-bit register Reg_i in the second column of Table 1 into the operational polynomial G(i, 2) corresponding to the single-bit register Reg_i in the second column of Table 2, and then substituting the result into the operational polynomial G(i, 3) corresponding to the single-bit register Reg_i in the second column of Table 3, and then step by step substituting the result into the operational polynomial G(i, 8) corresponding to the single-bit register Reg_i in the second column of Table 8, thereby obtaining the operational polynomial F(i, j) corresponding to the single-bit register Reg_i in the second column of Table 8. That is, the operational polynomial G(i, j) in the second column of each of Tables 1 to 16 is intended to represent the shift logic relationship between the register values of the multiple single-bit registers Reg_1 to Reg_23 in the current and previous linear feedback shifts. Thus, by iterating step by step on the shift logic relationship between the register values in the current and previous linear feedback shifts, the operational polynomial F(i, j) in the third column, which is used to represent the iterative logical relationship between the last linear feedback shift and the initial register value, can be obtained.

[0095] For example, in an embodiment of the present application, 16 iterative logic relationship tables TBL_1 to TBL_16 in the plurality of iterative logic relationship tables {TBL} may include the third columns of Tables 1 to 16 in sequence.

[0096] Table 1:

[0097]

[0098] Table 2:

[0099]

[0100] Table 3:

[0101]

[0102] Table 4:

[0103]

[0104] Table 5:

[0105]

[0106] Table 6:

[0107]

[0108] Table 7:

[0109]

[0110] Table 8:

[0111]

[0112] For example, in an embodiment of the present application, if the specified shift count N is 8, then the multiple single-bit registers Reg_1 to Reg_23 can be synchronously updated according to the corresponding operation polynomials F(1, 8) to F(23, 8) in the third column of Table 8. At the same time (for example, within one working clock cycle), among the 8 bits of the pseudo-random sequence output in parallel:

[0113] Bit 1: Initial register value D_23_0 of output bit register Reg_23;

[0114] 2nd digit: Operation polynomial F(23, 1)=D_22_0 in Table 1;

[0115] 3rd digit: Operation polynomial F(23, 2)=D_21_0^D_23_0 in Table 2;

[0116] 4th digit: the operational polynomial F(23, 3)=D_20_0^D_22_0 in Table 3;

[0117] 5th digit: Operation polynomial F(23, 4)=D_19_0^D_21_0^D_23_0 in Table 4;

[0118] 6th digit: Operation polynomial F(23, 5)=D_18_0^D_20_0^D_22_0 in Table 5;

[0119] 7th digit: Operation polynomial F(23, 6)=D_17_0^D_19_0^D_21_0^D_23_0 in Table 6;

[0120] Bit 8: Operation polynomial F(23, 7) = D_16_0^D_23_0^D_18_0^D_20_0^D_22_0 in Table 7.

[0121] Table 9:

[0122]

[0123] Table 10:

[0124]

[0125] Table 11:

[0126]

[0127] Table 12:

[0128]

[0129] Table 13:

[0130]

[0131] Table 14:

[0132]

[0133] Table 15:

[0134]

[0135] Table 16:

[0136]

[0137] For example, in an embodiment of the present application, if the specified shift count N is 16, then the multiple single-bit registers Reg_1 to Reg_23 can be synchronously updated according to the corresponding operational polynomials F(1, 16) to F(23, 16) in the third column of Table 16. At the same time (for example, within one working clock cycle), among the 16 bits of the pseudo-random sequence output in parallel:

[0138] Bit 1: Initial register value D_23_0 of output bit register Reg_23;

[0139] 2nd digit: Operation polynomial F(23, 1)=D_22_0 in Table 1;

[0140] 3rd digit: Operation polynomial F(23, 2)=D_21_0^D_23_0 in Table 2;

[0141] 4th digit: the operational polynomial F(23, 3)=D_20_0^D_22_0 in Table 3;

[0142] 5th digit: Operation polynomial F(23, 4)=D_19_0^D_21_0^D_23_0 in Table 4;

[0143] 6th digit: Operation polynomial F(23, 5)=D_18_0^D_20_0^D_22_0 in Table 5;

[0144] 7th digit: Operation polynomial F(23, 6)=D_17_0^D_19_0^D_21_0^D_23_0 in Table 6;

[0145] Bit 8: Operation polynomial F(23, 7) = D_16_0^D_23_0^D_18_0^D_20_0^D_22_0 in Table 7;

[0146] The ninth digit is the operation polynomial F(23, 8) in Table 8, that is:

[0147] D_15_0^D_22_0^D_17_0^D_19_0^D_21_0^D_23_0;

[0148] The 10th digit: the operation polynomial F(23, 9) in Table 9, that is:

[0149] D_14_0^D_21_0^D_16_0^D_18_0^D_20_0^D_22_0;

[0150] 11th digit: The operation polynomial F(23, 10) in Table 10, that is:

[0151] D_13_0^D_20_0^D_15_0^D_17_0^D_19_0^D_21_0^D_23_0;

[0152] Bit 12: The operation polynomial F(23, 11) in Table 11, that is:

[0153] D_12_0^D_19_0^D_14_0^D_16_0^D_23_0^D_18_0^D_20_0^D_22_0;

[0154] The 13th bit: The operation polynomial F(23, 12) in Table 12, that is:

[0155] D_11_0^D_18_0^D_13_0^D_15_0^D_22_0^D_17_0^D_19_0^D_21_0^D_23_0;

[0156] 14th digit: The operation polynomial F(23, 13) in Table 13, that is:

[0157] D_10_0^D_17_0^D_12_0^D_14_0^D_21_0^D_16_0^D_18_0^D_20_0^D_22_0;

[0158] 15th digit: The operation polynomial F(23, 14) in Table 14, that is:

[0159] D_9_0^D_16_0^D_11_0^D_13_0^D_20_0^D_15_0^D_17_0^D_19_0^D_21_0;

[0160] 16th bit: The operation polynomial F(23, 15) in Table 15, that is:

[0161] D_8_0^D_15_0^D_10_0^D_12_0^D_19_0^D_14_0^D_16_0^D_18_0^D_20_0.

[0162] It should be understood that the above examples are merely intended to provide a more intuitive understanding of the deduction principle implemented by the shift deduction circuit 30 based on the lookup table operation of the shift prediction information, and are not intended to unnecessarily limit the specific definition of the iterative logical relationship represented by the shift prediction information. In other words, the iterative logical relationship represented by the shift prediction information can be represented using an arithmetic polynomial whose operation is not limited to an exclusive-OR operation, or using other forms not limited to arithmetic polynomials.

[0163] In an embodiment of the present application, a pseudo-random sequence generation method for a processor is also provided, and a processor applicable to the pseudo-random sequence generation method may include a register group, which may include multiple single-bit registers, and one of the multiple single-bit registers may be designated as an output bit register in a set linear feedback shift topology.

[0164] Figure 7 This is an exemplary flow chart of a pseudo-random sequence generation method for a processor in an embodiment of the present application. Figure 7 In an embodiment of the present application, the pseudo-random sequence generation method may include:

[0165] S710: Determine, based on pre-configured shift prediction information, shift deduction results of multiple single-bit registers of the processor after completing a specified number of linear feedback shifts; wherein the shift prediction information is determined based on a linear feedback shift topology set for the multiple single-bit shift registers, the specified number of linear feedback shifts is determined by a set number of bits of a pseudo-random sequence, and the determined shift deduction results include: an updated register value of the last linear feedback shift of each single-bit register in the multiple single-bit registers within the specified number of shifts, and each output register value of the output bit register for each linear feedback shift within the specified number of shifts;

[0166] S730: Based on the determined shift deduction result, realize the synchronous update of multiple single-bit registers and the parallel output of the pseudo-random sequence; wherein, the synchronous update of multiple single-bit registers is used to synchronously update the multiple single-bit registers to the updated register value of the last linear feedback shift in the specified number of shifts, and the parallel output of the pseudo-random sequence includes: outputting the output register value of each linear feedback shift of the output bit register in the specified number of shifts in parallel as the corresponding bit of the pseudo-random sequence.

[0167] Based on the above-described process of the embodiment of the present application, a shift deduction result of linear feedback shifting of multiple single-bit registers of a processor by a specified number of shifts can be directly deduced. Specifically, the multiple single-bit registers can be synchronously updated to updated register values after the linear feedback shifting by the specified number of shifts using the shift deduction result, so that the multiple single-bit registers can complete the shift jump of the linear feedback shifting by the specified number of shifts in one go (e.g., within one working clock cycle). The specified number of linear feedback shifts (i.e., N times) corresponds to a set number of bits in a pseudo-random sequence. Furthermore, the shift deduction result can also include the output register values of the output bit registers configured in the multiple single-bit registers during the linear feedback shifting by the specified number of shifts. Therefore, the output register values of the output bit registers can be output in parallel as corresponding bits of the pseudo-random sequence (e.g., output in parallel within one working clock cycle), thereby achieving parallel output of the pseudo-random sequence. Furthermore, compared to a linear feedback shift register that generates a pseudo-random sequence serially, the scheme of generating a pseudo-random sequence in parallel based on shift deduction in the embodiment of the present application helps to reduce the operating frequency required to generate a pseudo-random sequence in a processor.

[0168] For example, in an embodiment of the present application, the shift prediction information based on which S710 performs shift deduction can be used to represent: an iterative logical relationship between the updated register value of each single-bit register in a plurality of single-bit registers after any number of linear feedback shifts (i.e., any number of times starting from its initial register value) and the initial register value of at least one associated single-bit register; wherein the at least one associated single-bit register can be pre-determined among the plurality of single-bit registers using shift deduction based on a linear feedback shift topology to perform any number of linear feedback shifts. In this case, S710 can specifically include: determining, based on the pre-configured shift prediction information and the initial register value of the at least one associated single-bit register, a shift deduction result after the plurality of single-bit registers of the processor complete a specified number of linear feedback shifts.

[0169] For example, in an embodiment of the present application, the shift prediction information based on which S710 performs shift deduction may include multiple iterative logical relationship tables corresponding to different linear feedback shift times; wherein each iterative logical relationship table in the multiple iterative logical relationship tables can be used to represent: the iterative logical relationship between the updated register value of each single-bit register in the multiple single-bit registers for the linear feedback shift times corresponding to the iterative logical relationship table and the initial register value of at least one associated single-bit register. In this case, S710 may specifically include: determining the shift deduction results of the multiple single-bit registers of the processor after completing the linear feedback shift of the specified shift times based on the lookup table operation of the multiple iterative logical relationship tables and the initial register value of the at least one associated single-bit register.

[0170] For example, in an embodiment of the present application, the first lookup table hit object indexed by the specified shift count in the lookup table operation performed by S710 may include an iterative logical relationship table corresponding to the last linear feedback shift within the specified shift count in multiple iterative logical relationship tables. In this case, the first lookup table result of the lookup table operation for the first lookup table hit object may include an iterative logical relationship between the updated register value of the last linear feedback shift of each of the multiple single-bit registers within the specified shift count and the initial register value of at least one associated single-bit register. Furthermore, the process of determining the shift deduction result based on the lookup table operation on the multiple iterative logical relationship tables and the initial register value of the at least one associated single-bit register in S710 may include determining the updated register value of the last linear feedback shift of each of the multiple single-bit registers within the specified shift count based on the first lookup table result and the initial register value of the at least one associated single-bit register.

[0171] For example, in an embodiment of the present application, each output register value of the output bit register may sequentially include: the initial register value of the output bit register, and the updated register value of each linear feedback shift of the output bit register, except for the last one, within a specified number of shifts. Therefore, in an embodiment of the present application, the second lookup table hit object indexed by the specified shift number in the lookup table operation performed in S710 may include: the iterative logical relationship tables corresponding to each linear feedback shift of the specified number of shifts, except for the last one, in a plurality of iterative logical relationship tables. In this case, the second lookup table result of the lookup table operation for the second lookup table hit object may include: the iterative logical relationship between the updated register value of each linear feedback shift of the output bit register, except for the last one, within the specified number of shifts, and the initial register value of at least one associated single-bit register. Furthermore, the process of determining the shift deduction result in S710 based on the lookup table operation on the plurality of iterative logical relationship tables and the initial register value of at least one associated single-bit register may include: determining each output register value of the output bit register based on the second lookup table result and the initial register value of at least one associated single-bit register.

[0172] Exemplarily, in an embodiment of the present application, each iterative logical relationship table in a plurality of iterative logical relationship tables may include: an operational polynomial corresponding to each single-bit register in a plurality of single-bit registers; wherein, any operational polynomial included in each iterative logical relationship table in a plurality of iterative logical relationship tables may be used to characterize: an iterative logical relationship between an updated register value of the single-bit register corresponding to the operational polynomial at the number of linear feedback shifts corresponding to the iterative logical relationship table and an initial register value of at least one associated single-bit register.

[0173] For example, in the embodiment of the present application, the cycle period of the linear feedback shift of the plurality of single-bit registers is 2 M-1 , M represents the total number of registers of the plurality of single-bit registers, and the total number of the plurality of iterative logical relationship tables is less than or equal to 2 M-1 Moreover, the total number of multiple iterative logic relationship tables can be used to represent the maximum number of shifts that the pseudo-random sequence can support based on the lookup table method.

[0174] In an embodiment of the present application, a processor is further provided. The processor may include the pseudo-random sequence generation circuit as described in the above embodiment.

[0175] Exemplarily, in the embodiments of the present application, the processor may refer to any device with processing capabilities, for example, the processor may be any one of a CPU (Central Processing Unit), a GPU (Graphics Processing Unit), a TPU (Tensor Processing Unit), an NPU (Neural Network Processing Unit), a DPU (Deep Learning Processing Unit), an APU (Accelerated Processing Unit), and a GPGPU (General-Purpose computing on Graphics Processing Units).

[0176] Illustratively, in an embodiment of the present application, a processor may include at least two chiplets, and the pseudo-random sequences generated in parallel by the pseudo-random sequence generation circuit may be used for verification of transmission communications between the chiplets.

[0177] For example, in an embodiment of the present application, at least two cores of a processor may transmit communication data packets via a physical layer channel. Any core of the at least two cores that is the sender of the communication data packets includes a pseudo-random sequence generation circuit. Another core of the at least two cores that is the receiver of the communication data packets may include an analog receiving circuit. The analog receiving circuit is configured to receive the communication data packets by sampling the physical layer channel based on analog deskew, and the pseudo-random sequence concurrently output by the pseudo-random sequence generation circuit is used to verify the analog deskew. For example, the core of the at least two cores that is the receiver of the communication data packets may use the pseudo-random sequence transmitted via the physical layer channel and received using sampling based on analog deskew to determine whether it has residual bias that has not been corrected by analog deskew.

[0178] It can be understood that, in the embodiments of the present application, the various parts of the content exemplified can be in an "and / or" relationship. In this article, the meaning of "and / or" refers to the context in which it is connected, which can be a common limiting relationship of "and", or can also be an alternative limiting relationship of "or". Therefore, the various parts of the content with an "and / or" relationship can be understood as including different combinations of situations in which "and / or" between each two parts of the content respectively represents a common limiting relationship of "and" or an alternative limiting relationship of "or", and this combination of different situations can be considered to be basically equivalent to the limiting scope of "at least one of the parts".

[0179] The above description is only a preferred embodiment of the present application and is not intended to limit the present application. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present application shall be included in the scope of protection of the present application.

Claims

1. A pseudo-random sequence generating circuit for a processor, characterized in that: include: A register group, comprising a plurality of single-bit registers; wherein one of the plurality of single-bit registers is designated as an output bit register in a set linear feedback shift topology; Shift deduction circuit for: Based on pre-configured shift prediction information, shift deduction results of the multiple single-bit registers after completing the linear feedback shift of the specified shift times are determined; wherein the shift prediction information is determined based on the linear feedback shift topology, and the specified shift times are determined by the set number of bits of the pseudo-random sequence; the shift prediction information includes multiple iterative logical relationship tables corresponding to different linear feedback shift times, each of the multiple iterative logical relationship tables is used to represent: the iterative logical relationship between the updated register value of each single-bit register in the multiple single-bit registers corresponding to the linear feedback shift times in the iterative logical relationship table and the initial register value of at least one associated single-bit register; the at least one The associated single-bit registers are predetermined among the plurality of single-bit registers by utilizing shift deduction of any number of linear feedback shifts based on the linear feedback shift topology; the shift deduction circuit is specifically configured to determine the shift deduction result by: determining the shift deduction result based on a lookup table operation on the plurality of iterative logical relationship tables and the initial register value of the at least one associated single-bit register; and the shift deduction result includes: an updated register value of the last linear feedback shift of each single-bit register in the plurality of single-bit registers in the specified number of shifts, and each output register value of each linear feedback shift of the output bit register in the specified number of shifts; Based on the shift deduction result, synchronous updating of the multiple single-bit registers and parallel output of the pseudo-random sequence are achieved; wherein the synchronous updating is used to synchronously update the multiple single-bit registers to the updated register value of the last linear feedback shift in the specified number of shifts, and the parallel output of the pseudo-random sequence includes: outputting the output register value of each linear feedback shift of the output bit register in the specified number of shifts in parallel as the corresponding bit of the pseudo-random sequence.

2. The pseudo-random sequence generating circuit according to claim 1, wherein: The first lookup table hit object indexed by the lookup table operation includes: an iterative logic relationship table corresponding to the last linear feedback shift in the specified shift number among the multiple iterative logic relationship tables; a first lookup table result of the lookup table operation for a hit object in the first lookup table comprising: an iterative logical relationship between an updated register value of a last linear feedback shift of each of the plurality of single-bit registers in the specified number of shifts and the initial register value of the at least one associated single-bit register; The process of the shift deduction circuit determining the shift deduction result includes: determining, based on the first lookup table result and the initial register value of the at least one associated single-bit register, an updated register value of each single-bit register in the multiple single-bit registers after completing the last linear feedback shift in the specified number of shifts.

3. The pseudo-random sequence generating circuit according to claim 1, wherein: Each output register value of the output bit register includes, in sequence: the initial register value of the output bit register, and the updated register value of each linear feedback shift of the output bit register except the last one in the specified number of shifts; The second lookup table hit object indexed by the lookup table operation includes: the iterative logic relationship tables of the multiple iterative logic relationship tables that sequentially correspond to each linear feedback shift except the last one in the specified shift number; A second lookup table result of the lookup table operation for a hit object in the second lookup table includes: an iterative logical relationship between an updated register value of each linear feedback shift of the output bit register except for the last one in the specified number of shifts and the initial register value of the at least one associated single-bit register; The process of the shift deduction circuit determining the shift deduction result includes: determining each output register value of the output bit register based on the second lookup table result and the initial register value of the at least one associated single-bit register.

4. The pseudo-random sequence generating circuit according to claim 1, wherein: Each of the multiple iterative logical relationship tables includes: an operation polynomial corresponding to each single-bit register of the multiple single-bit registers; wherein, any operation polynomial included in each of the multiple iterative logical relationship tables is used to represent: an iterative logical relationship between an updated register value of the single-bit register corresponding to the operation polynomial at a corresponding number of linear feedback shifts and the initial register value of the at least one associated single-bit register.

5. The pseudo-random sequence generating circuit according to claim 1, wherein: The cycle period of the linear feedback shift of the plurality of single-bit registers is 2 M-1 , M represents the total number of registers of the plurality of single-bit registers, and the total number of the plurality of iterative logical relationship tables is less than or equal to 2 M-1 .

6. A pseudo-random sequence generation method for a processor, characterized in that: The processor includes a register group, the register group includes a plurality of single-bit registers, one of the plurality of single-bit registers is designated as an output bit register in a set linear feedback shift topology, and the pseudo-random sequence generation method includes: Based on pre-configured shift prediction information, shift deduction results of the multiple single-bit registers after completing the linear feedback shift of the specified shift times are determined; wherein the shift prediction information is determined based on the linear feedback shift topology, and the specified shift times are determined by the set number of bits of the pseudo-random sequence; the shift prediction information includes multiple iterative logical relationship tables corresponding to different linear feedback shift times, each of the multiple iterative logical relationship tables is used to represent: the iterative logical relationship between the updated register value of each single-bit register in the multiple single-bit registers corresponding to the linear feedback shift times in the iterative logical relationship table and the initial register value of at least one associated single-bit register; the at least one associated single-bit register is based on the basic Shift deduction of performing any number of linear feedback shifts in the linear feedback shift topology is pre-determined in the plurality of single-bit registers; determining shift deduction results of the plurality of single-bit registers after completing the linear feedback shift for a specified number of shifts based on pre-configured shift prediction information, comprising: determining the shift deduction results based on a lookup table operation of the plurality of iterative logical relationship tables and the initial register value of the at least one associated single-bit register; and the shift deduction results include: an updated register value of the last linear feedback shift of each single-bit register in the plurality of single-bit registers in the specified number of shifts, and each output register value of the output bit register for each linear feedback shift in the specified number of shifts; Based on the shift deduction result, synchronous updating of the multiple single-bit registers and parallel output of the pseudo-random sequence are achieved; wherein the synchronous updating is used to synchronously update the multiple single-bit registers to the updated register value of the last linear feedback shift in the specified number of shifts, and the parallel output of the pseudo-random sequence includes: outputting the output register value of each linear feedback shift of the output bit register in the specified number of shifts in parallel as the corresponding bit of the pseudo-random sequence.

7. A processor, characterized in that: The method comprises the pseudo-random sequence generating circuit according to any one of claims 1 to 5.

Images