Instruction processing method, electronic equipment, storage medium and program product

Abstract

The invention relates to the technical field of micro-architecture, and discloses an instruction processing method, electronic equipment, a storage medium and a program product. The instruction processing method comprises the steps that when a processor obtains two instructions, if one instruction is a branch instruction and the other instruction is any instruction except the branch instruction, the processor can transmit the two instructions to the same assembly line, so that the two instructions are processed at the same time through resources in the same assembly line. In this way, the processor can process the two instructions in one assembly line at the same time, and therefore the instruction execution efficiency of the processor is improved. For example, for a dual-emission pipeline structure, a processor can process three or four instructions at the same time through the instruction processing method, and the instruction processing efficiency is high.

Description

Technical Field

[0001] The present application relates to the field of micro-architecture technology, and in particular to an instruction processing method, an electronic device, a storage medium and a program product. Background Art

[0002] With the rapid development of computer technology, the multi-issue pipeline structure is a key technology to improve the processing performance of the processor. It processes multiple instructions in parallel in the same clock cycle to improve the instruction execution efficiency of the processor. Figure 1 In the dual-issue pipeline structure for processing two instructions in parallel, the processor can issue instruction inst1 and instruction inst2 to pipeline Pipe1 and pipeline Pipe2, so as to simultaneously implement instruction fetch, decoding, execution, memory access, write back and other processes for instruction inst1 and instruction inst2 in the time period t1 to t5.

[0003] However, in each instruction processing pipeline in the multi-issue pipeline structure, only one instruction can be processed, so that the processor still has a low instruction execution efficiency. Figure 1 In the dual-issue pipeline structure shown, pipeline Pipe1 and pipeline Pipe2 can only process instruction inst1 and instruction inst2 respectively, and cannot process more instructions at the same time, resulting in that the instruction execution efficiency of the processor is still low. Summary of the invention

[0004] In order to solve the above problems, the present application provides an instruction processing method, an electronic device, a storage medium and a program product.

[0005] In a first aspect, the present application provides an instruction processing method, applied to a processor, the method comprising: acquiring a first instruction and a second instruction; when it is determined that the instruction type of the first instruction is a branch instruction, and the instruction types of the first instruction and the second instruction are different, processing the first instruction and the second instruction by each execution unit in the first instruction processing pipeline of the processor.

[0006] In the present application, the first instruction may be a branch instruction; the second instruction may be other types of instructions; and the first instruction processing pipeline may be any instruction processing pipeline in the processor.

[0007] In some embodiments, inside the processor, the processor only needs to use the branch resolved unit (BRU) when processing branch instructions, without occupying other arithmetic logic units. The BRU is also only used to process branch instructions, that is, the processor does not occupy BRU resources when processing other types of instructions (such as arithmetic logic instructions such as addition). In addition, when the processor processes other arithmetic logic instructions (such as addition instructions and subtraction instructions), it is necessary to read the operands required for the arithmetic logic instructions from the memory through the read port, but the processor does not need to use the read port when processing branch instructions. Therefore, there is no conflict between the resources required by the processor when processing branch instructions and the resources required when processing other types of instructions.

[0008] Therefore, through the above method, the processor can process two instructions simultaneously in one pipeline, thereby improving the instruction execution efficiency of the processor. For example, for a dual-issue pipeline structure, the processor can process three or four instructions simultaneously through the above instruction processing method, with high instruction processing efficiency.

[0009] In a possible implementation of the first aspect above, when it is determined that the instruction type of the first instruction is a branch instruction, and the instruction types of the first instruction and the second instruction are different, the first instruction and the second instruction are processed by each execution unit in the first instruction processing pipeline of the processor, including: in the instruction fetch stage of the first instruction processing pipeline, the instruction acquisition unit of the processor determines that the instruction type of the first instruction is a branch instruction, and the instruction types of the first instruction and the second instruction are different; a flag field is generated by the instruction acquisition unit, and the flag field is used to indicate that the first instruction processing pipeline processes two instructions; the flag field, the first instruction, and the second instruction are passed to the decoding stage of the first instruction processing pipeline to obtain a decoded first instruction and a decoded second instruction; based on the flag field, the operations corresponding to each stage in the execution stage, the memory access stage, and the write back stage of the first instruction processing pipeline are executed on the decoded first instruction and the decoded second instruction respectively.

[0010] In some embodiments, after fetching two instructions, the instruction fetch unit (IFU) may first determine whether the two instructions are branch instructions and other types of instructions, so as to determine whether the two instructions can be fused (i.e., whether they can be processed through one pipeline). Moreover, the IFU may determine that the two instructions can be fused when it is determined that the two instructions are a branch instruction and another type of instruction, thereby adding a flag field at the end of the two instructions. Next, the IFU may pass the two fused instructions to the core of the central computer unit (CPU) for operations in the decoding, execution, memory access, write-back and other stages. In this way, the first instruction and the second instruction can be processed simultaneously through the first instruction processing pipeline.

[0011] In a possible implementation of the first aspect above, the branch mode corresponding to the first instruction is any one of the following modes: a direct branch, which refers to a branch mode of directly jumping to a specified address in the program for execution; a conditional branch, which refers to a branch mode of determining whether it is necessary to jump to a specified address in the program for execution based on the state of the program during execution; a no-operation instruction, which refers to an instruction that does not change the program state when executed and is used to fill bytes or delays.

[0012] It can be understood that the branching method of the first instruction mentioned in the present application can be any of the above methods, and the present application does not limit it.

[0013] In a possible implementation of the first aspect above, the field content of the flag field includes: a fusion flag, used to indicate the presence of two instructions; a fusion type, used to indicate the branch mode corresponding to the first instruction and the instruction type of the second instruction; and a fusion order, used to indicate the position of the first instruction and / or the second instruction in the two instructions.

[0014] In some embodiments, the processor can determine through a fusion flag that two instructions need to be processed simultaneously through an instruction processing pipeline; determine through a fusion type the branch mode (e.g., direct branch, conditional branch, or no-operation instruction) corresponding to the first instruction and the instruction type (e.g., addition instruction, subtraction instruction, etc.) of the second instruction; determine through a fusion order the position of the first instruction and / or the second instruction in the two instructions. For example, if the two instructions are sent to the CPU core in the form of (instruction inst1, instruction inst2), the CPU core can determine through the fusion order whether the first instruction inst1 or the second instruction inst2 is a branch instruction among the two instructions.

[0015] In a possible implementation of the first aspect above, the above-mentioned flag field-based execution of operations corresponding to each stage in the execution stage, memory access stage, and write-back stage of the first instruction processing pipeline for the decoded first instruction and the decoded second instruction, respectively, includes: based on the fusion order in the flag field, distinguishing the decoded first instruction and the decoded second instruction in the two decoded instructions; based on the fusion type in the flag field, executing the operations corresponding to each stage in the execution stage, memory access stage, and write-back stage corresponding to the branch mode of the first instruction for the decoded first instruction; based on the fusion type in the flag field, executing the operations corresponding to each stage in the execution stage, memory access stage, and write-back stage corresponding to the instruction type of the second instruction for the decoded second instruction.

[0016] In some embodiments, the processor can distinguish the decoded first instruction and the decoded second instruction in the two decoded instructions by the fusion order in the flag field. For example, if the fusion order is "branch instruction first", the processor can determine that the first instruction is the first instruction of the branch instruction type and the second instruction is the second instruction of other instruction types in the two decoded instructions based on the fusion order.

[0017] In addition, the processor can also perform operations corresponding to the execution, memory access, write-back, etc. stages corresponding to the branch mode of the first instruction on the decoded first instruction based on the fusion type in the flag field. For example, if the fusion type contains the content "the branch mode is a direct branch", the processor can pass the first instruction to the branch resolution unit for processing, thereby implementing the execution, memory access, write-back, etc. operations on the first instruction based on the operation process corresponding to the direct branch. At the same time, the processor can also perform operations corresponding to the execution, memory access, write-back, etc. stages of the instruction type of the second instruction on the decoded second instruction based on the fusion type in the flag field. For example, if the fusion type contains the content "the instruction type is an addition instruction", the processor can pass the second instruction to the addition arithmetic logic unit for processing, thereby implementing the execution, memory access, write-back, etc. operations on the second instruction based on the operation process corresponding to the addition instruction.

[0018] In this way, the processor can process two instructions simultaneously in the first instruction processing pipeline without any data conflict or resource conflict, thereby improving the instruction processing efficiency of the processor.

[0019] In a possible implementation of the first aspect above, the processor also includes a second instruction processing pipeline, and the method includes: acquiring a first instruction, a second instruction, and a third instruction; when it is determined that the instruction type of the first instruction is a branch instruction, and the instruction types of the first instruction and the second instruction are different, processing the first instruction and the second instruction by each execution unit in the first instruction processing pipeline, and processing the third instruction by each execution unit in the second instruction processing pipeline.

[0020] In the present application, the first instruction may be a branch instruction; the second instruction may be an instruction other than a branch instruction; and the third instruction may be any type of instruction.

[0021] It can be understood that, among the three instructions obtained, the first instruction (ie, the branch instruction) can be any one of them, and the present application does not limit the position of the first instruction.

[0022] In a possible implementation of the first aspect above, the processor also includes a second instruction processing pipeline, and the method includes: acquiring a first instruction, a second instruction, a third instruction, and a fourth instruction; when it is determined that the instruction type of the first instruction is a branch instruction, and the instruction types of the first instruction and the second instruction are different, processing the first instruction and the second instruction by each execution unit in the first instruction processing pipeline; and when it is determined that the instruction type of the third instruction is a branch instruction, and the instruction types of the third instruction and the fourth instruction are different, processing the third instruction and the fourth instruction by each execution unit in the second instruction processing pipeline.

[0023] In the present application, the first instruction may be a branch instruction; the second instruction may be an instruction other than a branch instruction; the third instruction may be a branch instruction; and the fourth instruction may be an instruction other than a branch instruction.

[0024] It can be understood that, among the four instructions obtained, the first instruction (ie, branch instruction) and the third instruction (ie, branch instruction) can be any two instructions, and the present application does not limit the positions of the first instruction and the third instruction.

[0025] In this way, the processor can process two instructions simultaneously in one pipeline without data conflict or resource conflict, thereby improving the instruction execution efficiency of the processor.

[0026] It can be understood that the instruction processing method provided in the present application can be applied to a single-issue pipeline structure and a dual-issue pipeline structure as well as a multi-issue pipeline structure including at least three pipelines. Moreover, in each pipeline of the multi-issue pipeline structure, the processor can also process one or two instructions at the same time, which is not limited in the present application.

[0027] In a possible implementation of the first aspect above, the processor includes a program counter, and the method includes: after each instruction is executed, updating the program counter (PC) based on the number of completed instructions so that the program counter points to the next instruction to be processed.

[0028] In some embodiments, in a single-issue pipeline structure, when the processor processes two instructions simultaneously, after the two instructions are executed, the processor can control the PC to point to the third instruction, indicating that the processor can start processing from the third instruction the next time it processes instructions.

[0029] For another example, in a dual-issue pipeline structure, when the processor processes three instructions simultaneously, after the three instructions are executed, the processor can control the PC to point to the fourth instruction, indicating that the processor can start processing from the fourth instruction the next time it processes instructions.

[0030] For another example, in a dual-issue pipeline structure, when the processor processes four instructions at the same time, after the four instructions are executed, the processor can control the PC to point to the fifth instruction, indicating that the processor can start processing from the fifth instruction when processing instructions next time. Similarly, when the processor processes multiple instructions at the same time, the processor can update the PC based on the number of completed instructions after each instruction is executed so that the PC can successfully point to the next instruction to be processed, which will not be repeated here.

[0031] In a second aspect, the present application provides an electronic device, comprising: a memory and a processor, the memory being coupled to the processor; the memory being used to store computer program code / instructions; when the computer program code / instructions are executed by the processor, the processor implements the instruction processing method mentioned in the present application.

[0032] In a third aspect, the present application provides a readable storage medium, on which instructions are stored. When the instructions are executed on a processor, the processor enables the processor to implement the instruction processing method mentioned in the present application.

[0033] In a fourth aspect, the present application provides a computer program product, comprising: computer instructions, which, when executed on a processor, enable the processor to implement the instruction processing method mentioned in the present application.

[0034] The beneficial effects of the second to fourth aspects mentioned above can be referred to the relevant descriptions in the first aspect mentioned above and various possible implementations of the first aspect, and will not be elaborated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] Figure 1 According to some embodiments of the present application, a schematic diagram of a dual-issue pipeline structure is shown;

[0036] Figure 2 According to some embodiments of the present application, a schematic diagram of an instruction processing process is shown;

[0037] Figure 3A According to some embodiments of the present application, a schematic diagram of a first instruction processing pipeline structure is shown;

[0038] Figure 3B According to some embodiments of the present application, a schematic diagram of a second instruction processing pipeline structure is shown;

[0039] Figure 3C According to some embodiments of the present application, a third instruction processing pipeline structure schematic diagram is shown;

[0040] Figure 4 According to some embodiments of the present application, a specific flow chart of an instruction processing method is shown;

[0041] Figure 5 According to some embodiments of the present application, a schematic diagram of the hardware structure of an electronic device is shown. DETAILED DESCRIPTION

[0042] Illustrative embodiments of the present application include, but are not limited to, instruction processing methods, electronic devices, storage media, and program products.

[0043] Currently, the multi-issue pipeline structure has become a key technology to improve the processing performance of the processor. It can improve the instruction execution efficiency of the processor by processing multiple instructions in parallel in the same clock cycle. For example, in a dual-issue pipeline structure with two instruction processing pipelines, the processor can process two instructions at the same time; or, if there is a three-issue pipeline structure with three instruction processing pipelines, the processor can process three instructions at the same time through the three-issue pipeline structure. However, in each instruction processing pipeline in the multi-issue pipeline structure, only one instruction can be processed, so that the processor still has a low instruction execution efficiency. For example, in the above Figure 1 In the dual-issue pipeline structure shown, pipeline Pipe1 and pipeline Pipe2 can only process instruction inst1 and instruction inst2 respectively, and cannot process more instructions at the same time, resulting in that the instruction execution efficiency of the processor is still low.

[0044] It can be understood that among the various types of instructions that can be executed by the processor, there is a branch instruction. The branch instruction can be an instruction with conditional judgment logic (such as an if instruction in the program code), which can make the program jump to different parts of the code for execution, thereby realizing more complex logic control and process management. For example, the branch instruction can be: if a>2, then jump to execute code block A; if a<2, then jump to execute code block B.

[0045] Among them, inside the processor, the processor only needs to use BRU when processing branch instructions, and does not need to occupy other arithmetic logic units. BRU is also only used to process branch instructions, that is, the processor will not occupy BRU resources when processing other types of instructions (such as arithmetic logic instructions such as addition). In addition, when the processor processes other arithmetic logic instructions (such as addition instructions and subtraction instructions), it needs to read the operands required for the arithmetic logic instructions from the memory through the read port. For example, for the addition arithmetic logic instruction c+d, the processor needs to read the values ​​of operand c and operand d from the memory at the same time through two read ports. Among them, although the number of read ports is limited, the processor does not need to use the read port when processing branch instructions. Therefore, there is no conflict between the resources required by the processor when processing branch instructions and the resources required when processing other types of instructions.

[0046] Therefore, the present application provides an instruction processing method. In the present application, when the processor obtains two instructions, if one of the instructions is a branch instruction (as an example of the first instruction) and the other instruction is any instruction other than the branch instruction (as an example of the second instruction), the processor can emit the two instructions to the same pipeline (as an example of the first instruction processing pipeline) to process the two instructions simultaneously through the resources in the same pipeline. In this way, the processor can process two instructions simultaneously in one pipeline, thereby improving the instruction execution efficiency of the processor. For example, for a dual-issue pipeline structure, the processor can process three or four instructions simultaneously through the above-mentioned instruction processing method, thereby having a higher instruction processing efficiency.

[0047] It should be understood that the instruction processing pipeline may include stages such as instruction fetch, decoding, execution, memory access, and writeback. In the instruction fetch stage of the first instruction processing pipeline, the processor may first determine through the internal IFU that the instruction type of the first instruction is a branch instruction, and that the first instruction and the second instruction are two instructions of different instruction types. Then, the processor may generate a flag field through the IFU to instruct the first instruction processing pipeline to process the two instructions through the flag field. For example, refer to Figure 2As shown, after obtaining two instructions, the IFU first needs to perform a fusion judgment. Specifically, it can first determine whether the two instructions are a branch instruction and an instruction of another type, so as to determine whether the two instructions can be fused (that is, whether they can be processed through a pipeline). Among them, when the IFU determines that the two instructions are a branch instruction and an instruction of another type, it means that it is determined that the two instructions can be fused, so that a flag field can be added at the end of the two instructions.

[0048] Next, the processor can pass the flag field, the first instruction, and the second instruction to the decoding stage of the first instruction processing pipeline, thereby obtaining the decoded first instruction and the decoded second instruction. Finally, the processor can perform operations corresponding to the execution stage, memory access stage, write-back stage, etc. of the first instruction processing pipeline on the decoded first instruction and the decoded second instruction based on the flag field. For example, Figure 2 In the process, the IFU can pass the two fused instructions to the CPU core for operations in the decoding, execution, memory access, write-back and other stages. In this way, the first instruction and the second instruction can be processed simultaneously through the first instruction processing pipeline.

[0049] It can be understood that the instruction processing method provided by the present application can be applied to any pipeline structure, for example, a single-issue pipeline structure including only one pipeline, or a multi-issue pipeline structure including at least two pipelines. Moreover, in each pipeline of the multi-issue pipeline structure, the processor can also process one instruction or two instructions at the same time, which is not limited by the present application.

[0050] Let's first combine Figure 3A The pipeline structure schematic diagram shown describes the process of a processor with a single-issue pipeline structure executing the above instruction processing method.

[0051] In the embodiments of the present application, Figure 3A As shown, when the pipeline structure of the processor is a single-issue pipeline structure, if instruction inst1 is a branch instruction and instruction inst2 is an instruction of another type other than a branch instruction, the processor can simultaneously process instruction inst1 and instruction inst2 through each execution unit in a pipeline (e.g., pipeline Pipe1). For example, the processor can process instruction inst1 through the BRU and process instruction inst2 through other arithmetic logic processing units; and the processor will not occupy the read port when processing instruction inst1, thereby not causing the processor to be unable to read the operand of instruction inst2 from the memory through the read port. Therefore, the processor can process two instructions simultaneously in the time period t1 to t5 without data conflict or resource conflict, thereby improving the instruction processing efficiency of the single-issue pipeline structure.

[0052] Combine the following Figure 3B and Figure 3C The pipeline structure schematic diagram shown describes the process of a processor with a dual-issue pipeline structure executing the above instruction processing method.

[0053] In the embodiments of the present application, Figure 3B As shown, when the multi-issue pipeline structure of the processor is a dual-issue pipeline structure, when the processor obtains instruction inst1 (as an example of the first instruction), instruction inst2 (as an example of the second instruction), and instruction inst3 (as an example of the third instruction), if the processor determines that instruction inst1 is a branch instruction and another instruction (such as instruction inst2) is an instruction of another type other than the branch instruction, the processor can simultaneously process instruction inst1 and instruction inst2 through each execution unit in pipeline Pipe1 (as an example of the first instruction processing pipeline), and process instruction inst3 (instruction inst3 can be any type of instruction) through each execution unit in pipeline Pipe2 (as an example of the second instruction processing pipeline). For example, the processor can process instruction inst1 through the BRU in pipeline Pipe1, process instruction inst2 through other arithmetic logic processing units in pipeline Pipe1, and process instruction inst3 through each execution unit in pipeline Pipe2.

[0054] In this way, the processor can process three instructions simultaneously in the time period t1 to t5 without data conflict or resource conflict. Figure 1 Compared with the dual-issue pipeline structure shown in the figure, which can only process two instructions at the same time, the instruction processing method provided by the present application can significantly improve the instruction processing efficiency of the dual-issue pipeline structure.

[0055] It can be understood that in the above embodiment, among the three instructions obtained, when instruction inst1 is the first instruction (i.e., a branch instruction), instruction inst1 can be fused with another instruction of other types (e.g., instruction inst2 or inst3) so that the processor can process instruction inst1 and another instruction at the same time through one instruction processing pipeline. However, the present application is not limited to this. For example, in other embodiments, among the three instructions obtained, instruction inst2 can be the first instruction (i.e., a branch instruction), and the processor can process instruction inst2 and another instruction at the same time through one instruction processing pipeline. For another example, in other embodiments, among the three instructions obtained, instruction inst3 can be the first instruction (i.e., a branch instruction), and the processor can process instruction inst3 and another instruction at the same time through one instruction processing pipeline. The present application does not limit this.

[0056] For example, refer to Figure 3C As shown, when the multi-issue pipeline structure of the processor is a dual-issue pipeline structure, when instruction inst1 (as an example of the first instruction), instruction inst2 (as an example of the second instruction), instruction inst3 (as an example of the third instruction), and instruction inst4 (as an example of the fourth instruction) are obtained, if the processor determines that instruction inst1 is a branch instruction and instruction inst2 is an instruction of another type other than the branch instruction, and determines that instruction inst3 is a branch instruction and instruction inst4 is an instruction of another type other than the branch instruction. Then the processor can simultaneously process instruction inst1 and instruction inst2 through each execution unit in pipeline Pipe1 (as an example of the first instruction processing pipeline), and simultaneously process instruction inst3 and instruction inst4 through each execution unit in pipeline Pipe2 (as an example of the second instruction processing pipeline). For example, the processor may process instruction inst1 through the BRU in pipeline Pipe1 and instruction inst2 through other ALUs in pipeline Pipe1; and process instruction inst3 through the BRU in pipeline Pipe2 and instruction inst4 through other ALUs in pipeline Pipe2.

[0057] In this way, the processor can process four instructions simultaneously in the time period t1 to t5 without data conflict or resource conflict. Figure 1 Compared with the dual-issue pipeline structure shown in the figure, which can only process two instructions at the same time, the instruction processing method provided by the present application can significantly improve the instruction processing efficiency of the dual-issue pipeline structure.

[0058] It can be understood that in the above embodiment, among the four instructions obtained, when instruction inst1 is the first instruction (i.e., branch instruction) and instruction inst3 is the third instruction (i.e., branch instruction), instruction inst1 can be fused with another instruction of other type (e.g., instruction inst2), and instruction inst3 can be fused with another instruction of other type (e.g., instruction inst4), so that the processor can process a branch instruction and an instruction of other type at the same time through one instruction processing pipeline. However, the present application is not limited to this. For example, in other embodiments, among the four instructions obtained, instruction inst2 can be the first instruction (i.e., branch instruction), instruction inst4 can be the third instruction (i.e., branch instruction), etc., and the processor can process a branch instruction and another instruction of other type at the same time through one instruction processing pipeline. The present application does not limit this.

[0059] In addition, for any multi-issue pipeline structure such as a three-issue pipeline structure and a four-issue pipeline structure, the processor can control each pipeline to process one instruction or two instructions at the same time, and this application does not limit this.

[0060] It can be understood that the above instruction processing method of the present application can be applied to processor performance optimization. In addition, the processor can also be a processor in any electronic device, for example, the electronic device includes but is not limited to a mobile station (MS), a mobile terminal (MT), etc. For example, the electronic device can be a vehicle-mounted computer, a computer, a mobile phone, a smart TV, a wearable device, a tablet computer (Pad), a desktop computer, a laptop computer, a virtual reality (VR) device, an augmented reality (AR) device, a terminal in industrial control, a terminal in self-driving, a terminal in remote medical surgery, a terminal in smart grid, a terminal in transportation safety, a terminal in smart city, a terminal in smart home, etc. The embodiment of the present application does not limit the specific form of the electronic device.

[0061] Combine the following Figure 4 The flowchart shown in the figure describes the instruction processing method provided by the present application. It can be understood that in the embodiment of the present application, Figure 4 The execution subject of each process of the method shown can be a processor, and the execution subject of each process will not be repeatedly described when describing each process of the instruction processing method below. Specifically, the specific process of the instruction processing method is as follows:

[0062] S401: Obtain a first instruction and a second instruction.

[0063] In the present application, the first instruction may be a branch instruction; the second instruction may be any type of instruction except a branch instruction, such as an addition instruction, a division instruction, a subtraction instruction, a multiplication instruction, etc.

[0064] In some embodiments, the branching mode of the first branch instruction can be any one of the following branching modes: (1) Direct branch, which refers to a branching mode that directly jumps to a specified address in the program for execution. For example, as long as the processor can directly jump to execute the program's code block B without any conditions when executing instruction A1 in the program's code block A, then instruction A1 can be a direct branch instruction. (2) Conditional branch, which refers to a branching mode that determines whether it is necessary to jump to the specified address in the program for execution based on the state of the program during execution. For example, when the processor executes instruction A1 in the program's code block A, if the data in instruction A1 meets the judgment condition (e.g., instruction A1 is: a>2), the processor can jump to execute the program's code block B, then instruction A1 can be a conditional branch instruction. (3) No operation instruction (NOP), which refers to an instruction that does not change the program state when executed and is used to fill bytes or delay. For example, some processor architectures require that instructions must be aligned according to specific byte boundaries, and the processor can use NOP instructions to fill in excess bytes to ensure that subsequent instructions can be correctly aligned. Alternatively, a meaningless instruction (ie, a NOP instruction) is directly used as a placeholder, thereby delaying the execution time of the next instruction.

[0065] Among them, in the above branching mode, the processor does not need to perform any operation when processing NOP instructions. Alternatively, when the processor processes direct branches or conditional branches, it needs to process them through an internal branch resolution unit (the branch resolution unit can only be used to process branch instructions), and does not need to use limited read ports to read data from the memory. Therefore, when the processor processes the first instruction, it will not occupy the resources required for other types of instructions, that is, there will be no resource conflict between the first instruction and the second instruction.

[0066] S402: When it is determined that the instruction type of the first instruction is a branch instruction, and the instruction types of the first instruction and the second instruction are different, the first instruction and the second instruction are processed by each execution unit in the first instruction processing pipeline of the processor.

[0067] In some embodiments, during the instruction fetching stage of the first instruction processing pipeline, when the processor determines in the IFU that the two instructions obtained include branch instructions and other types of instructions, the IFU can add a flag field at the end of the two instructions to indicate that the first instruction processing pipeline processes the two instructions through the flag field. The contents of each field in the flag field may include the following: (1) a fusion flag, used to indicate that there are two instructions. (2) a fusion type, used to indicate the branching method corresponding to the first instruction (e.g., direct branch, conditional branch, or no-operation instruction) and the instruction type of the second instruction (e.g., addition instruction, subtraction instruction, etc.). (3) a fusion order, used to indicate the position of the first instruction and / or the second instruction in the two instructions. For example, if the two instructions are sent to the CPU core in the form of (instruction inst1, instruction inst2), the CPU core can determine whether the first instruction inst1 is a branch instruction or the second instruction inst2 is a branch instruction through the fusion order.

[0068] Next, the IFU can pass the flag field, the first instruction, and the second instruction to the decoding stage of the first instruction processing pipeline, so as to obtain the decoded first instruction and the decoded second instruction. For example, the IFU can pass the flag field, the first instruction, and the second instruction to the CPU core, and the CPU core can decode the first instruction and the second instruction through the decoder to obtain the two decoded instructions. Then, the processor can distinguish the decoded first instruction and the decoded second instruction from the two decoded instructions through the fusion order in the flag field. For example, if the fusion order is "branch instruction first", the processor can determine that the first instruction is a first instruction of a branch instruction type and the second instruction is a second instruction of other instruction types based on the fusion order.

[0069] Finally, the processor can also perform the operations of the execution, memory access, write-back and other stages corresponding to the branch mode of the first instruction on the decoded first instruction based on the fusion type in the flag field. For example, if the fusion type contains the content "the branch mode is a direct branch", the processor can pass the first instruction to the branch resolution unit for processing, thereby implementing the execution, memory access, write-back and other operations on the first instruction based on the operation process corresponding to the direct branch. At the same time, the processor can also perform the operations of the execution, memory access, write-back and other stages corresponding to the instruction type of the second instruction on the decoded second instruction based on the fusion type in the flag field. For example, if the fusion type contains the content "the instruction type is an addition instruction", the processor can pass the second instruction to the addition arithmetic logic unit for processing, thereby implementing the execution, memory access, write-back and other operations on the second instruction based on the operation process corresponding to the addition instruction.

[0070] In this way, the processor can process two instructions simultaneously in the first instruction processing pipeline without any data conflict or resource conflict, thereby improving the instruction processing efficiency of the processor.

[0071] In addition, there is a PC in the processor, which can point to the next instruction when the instruction is executed. Therefore, in this application, after each instruction is executed, the processor can update the PC based on the number of instructions completed, so that the PC can successfully point to the next instruction to be processed. For example, as mentioned above Figure 3A As shown, when the processor processes two instructions at the same time, after the two instructions are executed, the processor can control the PC to point to the third instruction, indicating that the processor can start processing from the third instruction when processing instructions next time. Figure 3B As shown, when the processor processes three instructions at the same time, after the three instructions are executed, the processor can control the PC to point to the fourth instruction, indicating that the processor can start processing from the fourth instruction when processing instructions next time. Figure 3C As shown, when the processor processes four instructions at the same time, after the four instructions are executed, the processor can control the PC to point to the fifth instruction, indicating that the processor can start processing from the fifth instruction when processing instructions next time. Similarly, when the processor processes multiple instructions at the same time, the processor can update the PC based on the number of completed instructions after each instruction is executed so that the PC can successfully point to the next instruction to be processed, which will not be repeated here.

[0072] Thus, through the instruction processing method provided by the present application, the processor can process two instructions simultaneously in one pipeline, thereby improving the instruction execution efficiency of the processor. For example, for a dual-issue pipeline structure, the processor can process three or four instructions simultaneously through the above instruction processing method, with high instruction processing efficiency.

[0073] In some embodiments, the present application provides a readable storage medium, on which instructions are stored, wherein when the instructions are executed on a processor, the processor implements the instruction processing method mentioned in the present application.

[0074] In some other embodiments, the present application further provides a computer program product, wherein the computer program product includes computer instructions. When the computer instructions are executed on a processor, the processor implements the instruction processing method mentioned in the present application.

[0075] In other embodiments, the present application further provides an electronic device, the electronic device comprising a memory and a processor, wherein the memory is coupled to the processor, wherein the memory is used to store computer program code / instructions, and when the computer program code / instructions are executed by the processor, the processor can implement the instruction processing method mentioned in the present application.

[0076] like Figure 5 As shown, a hardware structure diagram of an electronic device 1200 according to an embodiment of the present application is exemplified. Figure 5 As shown, the electronic device 1200 may include one or more processors 1202, a system control logic 1201 connected to at least one of the processors 1202, a system memory 1205 connected to the system control logic 1201, a storage 1203 connected to the system control logic 1201, and a network interface 1207 connected to the system control logic 1201.

[0077] It is to be understood that the structure illustrated in the embodiment of the present application does not constitute the only possible implementation method for the electronic device 1200. In other embodiments of the present application, the electronic device 1200 may include more or fewer components than shown in the figure, or combine some components, or split some components, or arrange the components differently. The components shown in the figure may be implemented in hardware, software, or a combination of software and hardware.

[0078] The processor 1202 may include one or more single-core or multi-core processors. In some embodiments, the processor 1202 may include any combination of a general-purpose processor and a dedicated processor (e.g., an application processor, a baseband processor, etc.). It is understood that in the embodiment of the present application, the processor 1202 may be configured to execute the executable instructions 1204 stored in the memory 1203 to implement the instruction processing method of the embodiment of the present application. When at least one of the processors 1202 executes the instruction, the electronic device 1200 implements the instruction processing method of the embodiment of the present application.

[0079] The system control logic 1201 may include any suitable interface controller to provide any suitable interface to at least one of the processors 1202 and / or any suitable device or component in communication with the system control logic 1201. The system control logic 1201 may include one or more memory controllers to provide an interface to the system memory 1205. The system memory 1205 may be used to load and store data and / or instructions. In some embodiments, the system memory 1205 of the electronic device 1200 may include any suitable volatile memory, such as a suitable dynamic random access memory.

[0080] The memory 1203 may include one or more tangible, non-transitory computer-readable media for storing data and / or instructions. In some embodiments, the memory 1203 may include any suitable volatile memory and / or any suitable non-volatile storage device, for example, the memory 1203 may include: a random access memory (RAM) and / or a cache memory unit, and may further include a read-only memory (ROM).

[0081] The memory 1203 may include a portion of storage resources on a device on which the electronic device 1200 is installed, or it may be accessible by the device but is not necessarily a portion of the device. For example, the memory 1203 may be accessed over a network via the network interface 1207 .

[0082] In particular, the system memory 1205 and the storage 1203 may respectively include: a temporary copy and a permanent copy of the instruction 1204. The instruction 1204 may include: when executed by at least one of the processors 1202, causing the electronic device 1200 to implement the instruction processing method of the embodiment of the present application. In some embodiments, the instruction 1204, hardware, firmware and / or its software components may be additionally / alternatively placed in the system control logic 1201, the network interface 1207 and / or the processor 1202.

[0083] The network interface 1207 may include a transceiver for providing a radio interface for the electronic device 1200, thereby communicating with any other suitable device (such as a front-end module, an antenna, etc.) through one or more networks. In some embodiments, the network interface 1207 may be integrated with other components of the electronic device 1200. For example, the network interface 1207 may be integrated with at least one of the processor 1202, the system memory 1205, the storage 1203, and a firmware device (not shown) having instructions.

[0084] The network interface 1207 may further include any suitable hardware and / or firmware to provide a multiple-input multiple-output radio interface. For example, the network interface 1207 may be a network adapter, a wireless network adapter, a telephone modem and / or a wireless modem.

[0085] The electronic device 1200 may further include an input / output (I / O) device 1206. The I / O device 1206 may include a user interface to enable a user to interact with the electronic device 1200; the design of the peripheral component interface enables the peripheral components to interact with the electronic device 1200. In some embodiments, the electronic device 1200 further includes a sensor for determining at least one of an environmental condition and location information related to the electronic device 1200.

[0086] In some embodiments, the user interface may include, but is not limited to, a display (e.g., an LCD display, a touch screen display, etc.), a speaker, a microphone, one or more cameras (e.g., a still image camera and / or a video camera), a flashlight (e.g., an LED flash), and a keyboard.

[0087] In some embodiments, the peripheral component interface may include, but is not limited to, a non-volatile memory port, an audio jack, and a power interface.

[0088] In some embodiments, the sensors may include, but are not limited to, gyroscope sensors, accelerometers, proximity sensors, ambient light sensors, and positioning units. The positioning unit may also be part of or interact with the network interface 1207 to communicate with components of a positioning network (e.g., global positioning system (GPS) satellites).

[0089] The various embodiments disclosed in the present application may be implemented in hardware, software, firmware, or a combination of these implementation methods. The embodiments of the present application may be implemented as a computer program or program code executed on a programmable system, the programmable system including at least one processor, a storage system (including volatile and non-volatile memory and / or storage elements), at least one input device, and at least one output device.

[0090] Program code can be applied to input instructions to perform the functions described in this application and generate output information. The output information can be applied to one or more output devices in a known manner. For the purposes of this application, a processing system includes any system having a processor such as, for example, a digital signal processor, a microcontroller, an application specific integrated circuit, or a microprocessor.

[0091] Program code can be implemented with high-level programming language or object-oriented programming language to communicate with the processing system. When necessary, program code can also be implemented with assembly language or machine language. In fact, the mechanism described in this application is not limited to the scope of any specific programming language. In either case, the language can be a compiled language or an interpreted language.

[0092] In some cases, the disclosed embodiments may be implemented in hardware, firmware, software, or any combination thereof. The disclosed embodiments may also be implemented as instructions carried or stored on one or more temporary or non-temporary machine-readable (e.g., computer-readable) storage media, which may be read and executed by one or more processors. For example, instructions may be distributed over a network or through other computer-readable media. Therefore, a machine-readable medium may include any mechanism for storing or transmitting information in a machine (e.g., computer) readable form, including, but not limited to, a floppy disk, an optical disk, an optical disk, a magneto-optical disk, a read-only memory (ROM), a random access memory (RAM), a magnetic card or an optical card, or a tangible machine-readable memory for transmitting information (e.g., carrier wave, infrared signal digital signal, etc.) using the Internet in an electrical, optical, acoustic or other form of propagation signal. Therefore, a machine-readable medium includes any type of machine-readable medium suitable for storing or transmitting electronic instructions or information in a machine (e.g., computer) readable form.

[0093] In the accompanying drawings, some structural or method features may be shown in a specific arrangement and / or order. However, it should be understood that such a specific arrangement and / or order may not be required. Instead, in some embodiments, these features may be arranged in a manner and / or order different from that shown in the illustrative drawings. In addition, the inclusion of structural or method features in a particular figure does not mean that such features are required in all embodiments, and in some embodiments, these features may not be included or may be combined with other features.

[0094] It should be noted that the units / modules mentioned in the various device embodiments of the present application are all logical units / modules. Physically, a logical unit / module can be a physical unit / module, or a part of a physical unit / module, or can be implemented as a combination of multiple physical units / modules. The physical implementation method of these logical units / modules themselves is not the most important. The combination of functions implemented by these logical units / modules is the key to solving the technical problems proposed by the present application. In addition, in order to highlight the innovative part of the present application, the above-mentioned device embodiments of the present application do not introduce units / modules that are not closely related to solving the technical problems proposed by the present application, which does not mean that there are no other units / modules in the above-mentioned device embodiments.

[0095] It should be noted that, in the examples and description of the present application, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply that there is any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that the process, method, article or equipment including a series of elements includes not only those elements, but also includes other elements not explicitly listed, or also includes elements inherent to such process, method, article or equipment. In the absence of more restrictions, the elements limited by the statement "include one" do not exclude the existence of other identical elements in the process, method, article or equipment including the elements.

[0096] Although the present application has been illustrated and described with reference to certain preferred embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the scope of the present application.

Claims

1. An instruction processing method, applied to a processor, characterized in that: The method comprises: Obtain the first instruction and the second instruction; When it is determined that the instruction type of the first instruction is a branch instruction, and the instruction types of the first instruction and the second instruction are different, the first instruction and the second instruction are processed by each execution unit in the first instruction processing pipeline of the processor.

2. The method according to claim 1, characterized in that When it is determined that the instruction type of the first instruction is a branch instruction and the instruction types of the first instruction and the second instruction are different, processing the first instruction and the second instruction by each execution unit in the first instruction processing pipeline of the processor includes: In the instruction fetch stage of the first instruction processing pipeline, determining, by the instruction fetch unit of the processor, that the instruction type of the first instruction is a branch instruction, and the instruction types of the first instruction and the second instruction are different; generating a flag field by the instruction fetch unit, the flag field being used to indicate that the first instruction processing pipeline processes two instructions; Passing the flag field, the first instruction, and the second instruction to a decoding stage of the first instruction processing pipeline to obtain a decoded first instruction and a decoded second instruction; Based on the flag field, operations corresponding to each stage of the execution stage, the memory access stage, and the write-back stage of the first instruction processing pipeline are performed on the decoded first instruction and the decoded second instruction respectively.

3. The method according to claim 2, characterized in that The branch mode corresponding to the first instruction is any one of the following modes: Direct branch refers to the branch method that directly jumps to the specified address in the program; Conditional branching refers to a branching method that determines whether to jump to a specified address in the program for execution based on the status of the program during runtime; No-operation instructions are instructions that do not change the program state when executed and are used to fill bytes or delays.

4. The method according to claim 3, characterized in that The field content of the flag field includes: The fusion flag is used to indicate the presence of two instructions; a fusion type, used to indicate a branch mode corresponding to the first instruction and an instruction type of the second instruction; and The fusion order is used to indicate the position of the first instruction and / or the second instruction in two instructions.

5. The method according to claim 4, characterized in that The performing operations corresponding to the execution phase, the memory access phase, and the write-back phase of the first instruction processing pipeline on the decoded first instruction and the decoded second instruction based on the flag field respectively includes: Distinguishing a decoded first instruction and a decoded second instruction from the two decoded instructions based on a fusion order in the flag field; Based on the fusion type in the flag field, for the decoded first instruction, perform operations corresponding to each stage of the execution stage, the memory access stage, and the write-back stage corresponding to the branch mode of the first instruction; Based on the fusion type in the flag field, the operations corresponding to the execution phase, the memory access phase, and the write-back phase corresponding to the instruction type of the second instruction are performed on the decoded second instruction.

6. The method according to claim 1, characterized in that The processor also includes a second instruction processing pipeline, and the method includes: The first instruction, the second instruction and the third instruction are obtained; When it is determined that the instruction type of the first instruction is a branch instruction, and the instruction types of the first instruction and the second instruction are different, the first instruction and the second instruction are processed by each execution unit in the first instruction processing pipeline, and the third instruction is processed by each execution unit in the second instruction processing pipeline.

7. The method according to claim 1, characterized in that The processor also includes a second instruction processing pipeline, and the method includes: Obtaining the first instruction, the second instruction, the third instruction, and the fourth instruction; When it is determined that the instruction type of the first instruction is a branch instruction, and the instruction types of the first instruction and the second instruction are different, the first instruction and the second instruction are processed by each execution unit in the first instruction processing pipeline; and When it is determined that the instruction type of the third instruction is a branch instruction, and the instruction types of the third instruction and the fourth instruction are different, the third instruction and the fourth instruction are processed by each execution unit in the second instruction processing pipeline.

8. The method according to any one of claims 1 to 7, characterized in that The processor includes a program counter, and the method includes: After each instruction is executed, the program counter is updated based on the number of instructions completed, so that the program counter points to the next instruction to be processed.

9. An electronic device, characterized in that: include: A memory and a processor, wherein the memory is coupled to the processor; the memory is used to store computer program code / instructions; when the computer program code / instructions are executed by the processor, the processor implements the instruction processing method according to any one of claims 1 to 8.

10. A readable storage medium, characterized in that: The readable storage medium stores instructions, and when the instructions are executed on a processor, the processor implements the instruction processing method according to any one of claims 1 to 8.

11. A computer program product, characterized in that include: A computer instruction, when the computer instruction is executed on a processor, causes the processor to implement the instruction processing method according to any one of claims 1 to 8.

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