A reset test method, apparatus and equipment

Abstract

This application provides a reset testing method, apparatus, and device, relating to the field of computer technology, aiming to solve the problems of high cost and low efficiency in RAID card reset testing for reset scenarios in related technologies. The method includes: obtaining a target reset type number, and determining the target reset information corresponding to the target reset type number based on the correspondence between the reset type number and reset information; if the reset type in the target reset information is a hard disk reset, sending the target reset information to the disk array to trigger the disk array to execute a hard disk reset process; if the reset type in the target reset information is a host reset, determining whether it needs to be executed in an I / O scenario, and sending the target reset information to the disk array to trigger the disk array to execute a host reset process or execute a host reset process in I / O processing.

Description

Technical Field

[0001] This application relates to the field of computer technology, and in particular to a reset test method, apparatus, and device. Background Technology

[0002] In chip design, reset operations are widely used in various scenarios as an important mechanism to ensure system stability and recovery capabilities. RAID (Disk Array) cards support NVMe SSD mounting, enabling normal interactions such as NVMe command execution and disk operations. During this process, there may be scenarios that require reset operations. Therefore, during the R&D and testing phase, it is necessary to test for possible reset scenarios.

[0003] Methods for testing reset scenarios in related RAID cards typically include: constructing reset scenarios and writing reset scenario and trigger code; and artificially constructing different reset scenarios from both hardware and software logic perspectives. However, these methods have limitations. For example, constructing different reset scenarios involves complex software logic, requiring extensive reset test logic coding, resulting in high costs, long processing times, and low efficiency. Reset scenarios involving hardware processing require artificially constructed defects, which are also costly. Summary of the Invention

[0004] This application provides a reset test method, apparatus, and device to address the issues of high cost and low efficiency in RAID card reset tests for reset scenarios in related technologies.

[0005] A first aspect of this application provides a reset test method applied to a host computer, the method comprising:

[0006] Obtain the target reset type number, and determine the target reset information corresponding to the target reset type number based on the correspondence between the reset type number and the reset information;

[0007] If the reset type in the target reset information is hard disk reset, the target reset information is sent to the disk array to trigger the disk array to execute the hard disk reset process;

[0008] If the reset type in the target reset information is host reset, determine whether it needs to be executed in an I / O scenario;

[0009] When execution is not required in an I / O scenario, the target reset information is sent to the disk array to trigger the disk array to execute the host reset process;

[0010] When execution is required in an I / O scenario, the I / O execution logic is triggered, the I / O execution process is recorded, and the target reset information is sent to the disk array during the I / O execution process to trigger the host reset process in the I / O processing of the disk array.

[0011] In an optional implementation, the method further includes:

[0012] Multiple reset types are numbered separately to obtain multiple reset type numbers;

[0013] The reset description, the I / O operations involved, and the disk operations involved for each of the multiple reset types are used as the reset information for each of the multiple reset types.

[0014] Based on the reset type number and reset information of each of the multiple reset types, establish a correspondence between the reset type number and the reset information.

[0015] In one optional implementation, obtaining the target reset type number includes:

[0016] The type of reset test is determined, including: manually entered and randomly generated;

[0017] When the type of the reset test is manual input, output a prompt message indicating the range of reset type numbers, obtain the first reset type number input by the user, and determine whether the first reset type number is within the range of the type numbers;

[0018] If the first reset type number is not within the range of reset type numbers, the first reset type number is determined to be invalid, and a prompt message to re-enter the reset type number is output.

[0019] If the first reset type number is within the range of the reset type numbers, the first reset type number is determined as the target reset type number;

[0020] When the type of the reset test is randomly generated, a second reset type number is randomly generated according to the range of the reset type number, and the second reset type number is determined as the target reset type number.

[0021] A second aspect of this application provides a reset test method applied to a disk array, the method comprising:

[0022] Receive target reset information sent by the host;

[0023] If the reset type in the target reset information is hard disk reset, the hard disk reset procedure is executed;

[0024] If the reset type in the target reset information is host reset, and the host reset process is not required to be executed in an I / O scenario, then the host reset process will be executed.

[0025] If the reset type in the target reset information is host reset, and it needs to be executed in an I / O scenario, then the host reset process in the I / O processing will be executed.

[0026] In an optional implementation, the method further includes:

[0027] Add the target reset information to the message queue;

[0028] The host reset process includes:

[0029] When the target reset information is detected in the message queue, the reset processing thread is woken up by the interrupt handler.

[0030] The target reset information is retrieved from the message queue by the reset processing thread;

[0031] The reset processing thread parses the target reset information to obtain the parsing result;

[0032] If the resolution result is that the reset type in the target reset information is host reset, and it does not need to be executed in an I / O scenario, then execute the host reset process;

[0033] If the parsing result indicates that the reset type in the target reset information is host reset, and the process needs to be executed in an I / O scenario, then the host reset process in the I / O handling is executed.

[0034] In one alternative implementation, at least one of the following is further included before executing the host reset procedure, or before executing the host reset procedure in I / O processing:

[0035] If the IO operation involved in the target reset information is a stop IO, the IO sent by the host is stopped to achieve reset preprocessing;

[0036] If the disk operation involved in the target reset information is a disk reset, the lower disk is reset to achieve reset preprocessing;

[0037] If the disk operation involved in the target reset information is a cache flush, the cache of the lower disk is flushed to achieve reset preprocessing;

[0038] The target module is notified to save the currently stored data. The target module is the module whose stored data is lost after a power failure.

[0039] In one optional implementation, if the parsed result is a host reset in the target reset information and needs to be executed in an I / O scenario, the host reset process in the I / O processing is executed, including:

[0040] Receive I / O requests sent by the host;

[0041] In response to the parsing result indicating that the reset type in the target reset information is host reset and needs to be executed in an I / O scenario, the host reset process in the I / O processing is executed;

[0042] After the host reset process in IO processing is completed, an IO response to the IO request is generated and sent to the host.

[0043] A third aspect of this application provides a reset test device applied to a host computer, the device comprising:

[0044] The acquisition module is used to acquire the target reset type number and determine the target reset information corresponding to the target reset type number based on the correspondence between the reset type number and the reset information.

[0045] The first triggering module is used to send the target reset information to the disk array when the reset type in the target reset information is hard disk reset, so as to trigger the disk array to execute the hard disk reset process;

[0046] The determination module is used to determine whether it is necessary to execute in an I / O scenario if the reset type in the target reset information is host reset;

[0047] The second triggering module is used to send the target reset information to the disk array when it is not necessary to execute in an I / O scenario, so as to trigger the disk array to execute the host reset process.

[0048] The third triggering module is used to trigger the IO execution logic when it is required to be executed in an IO scenario, record the IO execution process, and send the target reset information to the disk array during the IO execution process to trigger the host reset process in the IO processing of the disk array.

[0049] A fourth aspect of this application provides a reset testing device applied to a disk array, the device comprising:

[0050] The receiving module is used to receive target reset information sent by the host;

[0051] The first execution module is used to execute the hard disk reset process when the reset type in the target reset information is hard disk reset;

[0052] The second execution module is used to execute the host reset process when the reset type in the target reset information is host reset and it is not required to be executed in an I / O scenario.

[0053] The third execution module is used to execute the host reset process in the IO process when the reset type in the target reset information is host reset and needs to be executed in an IO scenario.

[0054] A fifth aspect of this application provides an electronic device, comprising:

[0055] A processor, a memory, and a computer program stored in the memory and executable on the processor, wherein the processor executes the computer program to implement the reset test method of the first or second aspect of the embodiments of this application.

[0056] In this embodiment, by obtaining the target reset type number and determining the target reset information corresponding to the target reset type number based on the correspondence between the reset type number and reset information, the target reset information is sent to the disk array. Based on the reset type in the target reset information, different reset procedures are triggered on the disk array. This approach replaces the specific reset scenario construction process with reset type encoding and injection, significantly reducing costs and improving testing efficiency. Attached Figure Description

[0057] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the accompanying drawings used in the description of the embodiments of this disclosure will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0058] Figure 1 This is a flowchart of the host-side steps of a reset test method proposed in an embodiment of this application;

[0059] Figure 2 This is a flowchart of the disk array side steps of the reset test method proposed in one embodiment of this application;

[0060] Figure 3 This is a common processing flowchart of a reset test method proposed in an embodiment of this application;

[0061] Figure 4 This is a flowchart of the reset injection process for a reset test method proposed in one embodiment of this application;

[0062] Figure 5 This is a schematic diagram of the structure of a reset test system proposed in an embodiment of this application;

[0063] Figure 6 This is a schematic diagram of an electronic device according to this application. Detailed Implementation

[0064] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0065] The following technical terms appearing in this application are explained:

[0066] Redundant Arrays of Independent Disks (RAID) is a large-capacity disk group composed of many independent disks, designed to provide data redundancy and performance enhancement. RAID distributes data across multiple hard drives in a specific way and provides fault tolerance at certain levels, thereby improving data reliability and access speed.

[0067] PCIe (Peripheral Component Interconnect Express) is a high-speed serial computer expansion bus standard, primarily used to expand the data throughput of computer system buses and improve device communication speed. It has corresponding hardware interfaces for hosts and peripherals, and enables data interaction between the host and peripherals through the PCIe bus protocol implemented internally within the PCIe hardware link and the host PCIe interface. It features high-speed transmission, link failure recovery, and power management.

[0068] NVMe (Peripheral Component Interconnect Express) is a host software application layer protocol that runs on top of the hardware PCIe protocol. It defines a set of interfaces for managing and responding to I / O requests, enabling the host to submit I / O request commands to the device and process I / O responses in a high-concurrency, asynchronous manner.

[0069] IO (Input Output) refers to input and output streams.

[0070] SSD (Solid State Drive) is a hard drive made of solid-state electronic storage chip arrays.

[0071] Reference Figure 1 , Figure 1 This is a flowchart of the host-side steps of a reset test method proposed in an embodiment of this application, including the following steps S11 to S15:

[0072] Step S11: Obtain the target reset type number, and determine the target reset information corresponding to the target reset type number according to the correspondence between the reset type number and the reset information.

[0073] Establishing the correspondence between reset type numbers and reset information can be achieved through data structures or similar data storage methods. The target reset type number is obtained from user input or other data sources; this number is a unique identifier for the executed reset type. The target reset information corresponding to this target reset type number can be determined by looking up the correspondence.

[0074] Further, obtaining the target reset type number includes:

[0075] The type of reset test is determined, including: manually entered and randomly generated;

[0076] When the type of the reset test is manual input, output a prompt message indicating the range of reset type numbers, obtain the first reset type number input by the user, and determine whether the first reset type number is within the range of the type numbers;

[0077] If the first reset type number is not within the range of reset type numbers, the first reset type number is determined to be invalid, and a prompt message to re-enter the reset type number is output.

[0078] If the first reset type number is within the range of the reset type numbers, the first reset type number is determined as the target reset type number;

[0079] When the type of the reset test is randomly generated, a second reset type number is randomly generated according to the range of the reset type number, and the second reset type number is determined as the target reset type number.

[0080] By executing the test script, the user selects the type of reset test, for example, 0: manual input, 1: random generation. When 0 is selected for manual input, a prompt message indicating the range of reset type numbers is displayed, such as requiring a number from 0 to 7. The system then obtains the first reset type number entered by the user. If the first reset type number is within the range of reset type numbers, then the entered first reset type number is correct and is determined as the target reset type number; otherwise, if the entered first reset type number is invalid, a prompt message to re-enter the reset type number is displayed.

[0081] When inputting option 1 and selecting random generation, the second reset type number is generated according to the random algorithm formula: Second Reset Type Number = random.randint(x, y), where x and y represent the upper and lower limits of the reset type number range. x = 0, and y = the total number of reset types. The second reset type number randomly generated by the random algorithm is the determined target reset type number. Reset triggering is supported through manual input and random generation, increasing the flexibility of reset testing.

[0082] Step S12: If the reset type in the target reset information is hard disk reset, send the target reset information to the disk array to trigger the disk array to execute the hard disk reset process.

[0083] The system parses the identified target reset information and executes different procedures based on the reset type. If the reset type is a hard disk reset, the system triggers and sends the target reset information to the disk array side via a standard transmission interface such as a serial port, thus executing the hard disk reset procedure.

[0084] Step S13: If the reset type in the target reset information is host reset, determine whether it needs to be executed in an I / O scenario.

[0085] The system parses the identified target reset information and executes different procedures based on the reset type. If the reset type is a host reset, it selects whether to perform a reset test during the I / O process. This helps simulate complex situations that may be encountered in real-world applications, especially when a reset request occurs while the system is performing critical I / O operations.

[0086] Step S14: If execution is not required in an I / O scenario, send the target reset information to the disk array to trigger the disk array to execute the host reset process.

[0087] If you choose not to perform a reset test in an I / O scenario, you can directly trigger a reset by writing to a register and send the target reset information to the disk array side to trigger the disk array to execute the host reset process.

[0088] Step S15: When execution is required in an IO scenario, trigger the IO execution logic, record the IO execution process, and send the target reset information to the disk array during the IO execution process to trigger the host reset process in the IO processing of the disk array.

[0089] If a reset test is required in an I / O scenario, the I / O execution logic will be triggered, recording the I / O execution process and key metrics such as data flow, response time, and error rate. During the I / O execution, a reset will be triggered, and the target reset information will be sent to the disk array side to trigger the host reset process within the disk array's I / O handling.

[0090] Furthermore, the method also includes:

[0091] Multiple reset types are numbered separately to obtain multiple reset type numbers;

[0092] The reset description, the I / O operations involved, and the disk operations involved for each of the multiple reset types are used as the reset information for each of the multiple reset types.

[0093] Based on the reset type number and reset information of each of the multiple reset types, establish a correspondence between the reset type number and the reset information.

[0094] According to the NVMe protocol and PCIe manual standards, RAID cards have multiple reset types. Different resets involve different related information such as I / O and disk operations. Therefore, all reset types and related information are categorized and numbered, resulting in multiple reset type numbers. A summary of the reset types is shown in Table 1.

[0095] Table 1 Summary of Reset Types

[0096]

[0097] The reset descriptions, involved I / O operations, and disk operations for each of the multiple reset types are stored as reset information for each type, which can be stored in arrays. A mapping relationship is established by associating the reset type number with its corresponding reset information using program code or other methods. When needed, the reset information can be quickly retrieved by inputting the reset type number.

[0098] On the host side, by executing test scripts, reset type information is first recorded, summarized, and saved according to the NVMe and PCIe standard protocol interfaces. Then, the target reset type number is obtained for testing. Targeted reset tests can be performed by manually entering the reset type number, or a random algorithm can be used to generate the reset type number for reset testing. These two methods can be freely selected via a switch, and different processes are executed according to different reset types. Stress testing is also supported. Reset injection follows the standard NVMe protocol and PCIe manual, resulting in good system adaptability and portability. It allows for the free selection of reset types and scenarios for automated testing, supports stress testing, and is highly efficient.

[0099] In this embodiment, by obtaining the target reset type number and determining the target reset information corresponding to the target reset type number based on the correspondence between the reset type number and reset information, the target reset information is sent to the disk array. Based on the reset type in the target reset information, different reset procedures are triggered on the disk array. This approach replaces the specific reset scenario construction process with reset type encoding and injection, significantly reducing costs and improving testing efficiency.

[0100] Reference Figure 2 , Figure 2 This is a flowchart of the disk array side steps of the reset test method proposed in an embodiment of this application, including the following steps S21 to S24:

[0101] Step S21: Receive target reset information sent by the host.

[0102] The disk array receives target reset information sent by the host. This target reset information is determined by the host through the target reset type number and is usually sent to the disk array in the form of a data packet or command.

[0103] Step S22: If the reset type in the target reset information is hard disk reset, execute the hard disk reset procedure.

[0104] Parsing the received target reset information reveals the reset type and related information, including at least the reset type, reset description, involved I / O operations, and involved disk operations. If the reset type in the target reset information is a hard disk reset, the hard disk reset procedure is executed, directly resetting the SSD through disk reset logic.

[0105] Step S23: If the reset type in the target reset information is host reset and it does not need to be executed in an I / O scenario, execute the host reset process.

[0106] If the reset type in the target reset information is host reset, and it does not need to be executed in an I / O scenario, the host reset process is executed through the reset handling logic. In this case, the reset operation is unrelated to I / O operations and can be performed directly.

[0107] Step S24: If the reset type in the target reset information is host reset and needs to be executed in an IO scenario, execute the host reset process in the IO process.

[0108] If the reset type in the target reset information is host reset, and it needs to be executed in an I / O scenario, then the host reset procedure within the I / O processing should be executed. The reset operation should be performed as safely as possible without affecting the current I / O operation. This could involve pausing or completing the current I / O operation before the reset, or maintaining monitoring of the I / O operation during the reset process to ensure that the reset operation does not compromise data consistency.

[0109] Furthermore, the method also includes:

[0110] Add the target reset information to the message queue;

[0111] The host reset process includes:

[0112] When the target reset information is detected in the message queue, the reset processing thread is woken up by the interrupt handler.

[0113] The target reset information is retrieved from the message queue by the reset processing thread;

[0114] The reset processing thread parses the target reset information to obtain the parsing result;

[0115] If the resolution result is that the reset type in the target reset information is host reset, and it does not need to be executed in an I / O scenario, then execute the host reset process;

[0116] If the parsing result indicates that the reset type in the target reset information is host reset, and the process needs to be executed in an I / O scenario, then the host reset process in the I / O handling is executed.

[0117] A message queue is a mechanism for passing messages between different threads or processes. It allows one thread (or process) to put a message into the queue, while another thread (or process) can retrieve the message from the queue for processing. The process involves adding the target reset information to the message queue, waking up the reset processing thread via an interrupt handler, retrieving the target reset information (message) from the message queue, parsing the message content to obtain the reset type and related information, and then invoking the corresponding reset processing logic based on this information. Figure 3 As shown. Specifically, if the reset type is host reset and does not need to be executed in an I / O scenario, the host reset procedure is executed; if the reset type is host reset and needs to be executed in an I / O scenario, the host reset procedure within the I / O processing is executed.

[0118] Furthermore, before executing the host reset procedure, or before executing the host reset procedure during I / O processing, at least one of the following is also included:

[0119] If the IO operation involved in the target reset information is a stop IO, the IO sent by the host is stopped to achieve reset preprocessing;

[0120] If the disk operation involved in the target reset information is a disk reset, the lower disk is reset to achieve reset preprocessing;

[0121] If the disk operation involved in the target reset information is a cache flush, the cache of the lower disk is flushed to achieve reset preprocessing;

[0122] The target module is notified to save the currently stored data. The target module is the module whose stored data is lost after a power failure.

[0123] After the reset thread is woken up, it will call the corresponding reset processing logic according to the corresponding reset type and information. Before executing the host reset process, or before executing the host reset process in IO processing, reset preprocessing and reset notification will be performed.

[0124] The main tasks of the preprocessing stage include the following: based on the reset type, determining whether to stop the I / O sent by the host, and determining whether to reset the downstream disk or flush the cache. If the I / O operation involved in the target reset information is to stop I / O, stop the I / O sent by the host; if the disk operation involved in the target reset information is a disk reset, reset the downstream disk; if the disk operation involved in the target reset information is to flush the cache, flush the cache of the downstream disk, thus achieving reset preprocessing.

[0125] After preprocessing, a reset notification can be sent to important modules in the system to save important variables. During a system reset, internal storage spaces such as the LMU and OCB generally do not lose power and data is not lost, but data in the heap and stack will be lost, so it is necessary to save relevant data. Then, the reset execution is performed, implementing the execution process for different reset scenarios, as described in Table 1.

[0126] Furthermore, if the parsed result indicates that the reset type in the target reset information is host reset, and this needs to be executed in an I / O scenario, the host reset process in the I / O processing is executed, including:

[0127] Receive I / O requests sent by the host;

[0128] In response to the parsing result indicating that the reset type in the target reset information is host reset and needs to be executed in an I / O scenario, the host reset process in the I / O processing is executed;

[0129] After the host reset process in IO processing is completed, an IO response to the IO request is generated and sent to the host.

[0130] Upon receiving an IO request from the host, and in cases where the parsed result indicates a host reset in the target reset information and requires execution within an IO scenario, the host reset process within the IO handling is executed. The current IO operation can be paused or completed before the reset, and the host reset operation is executed according to the specific requirements of the target reset information. After the host reset is complete, a corresponding IO response is generated based on the IO request and sent to the host. Combining host reset with IO handling improves the reliability of reset testing.

[0131] In this embodiment, the target reset information sent by the host, determined by the target reset type number, is received and parsed. Based on the reset type in the target reset information, different reset procedures are executed. This allows for free selection of reset types and scenarios for testing, enables automated testing, supports stress testing, and is highly efficient.

[0132] Reference Figure 4 , Figure 4 This is a flowchart illustrating the reset injection process of a reset test method proposed in one embodiment of this application. Figure 4 As shown, the reset injection process is as follows:

[0133] The test script executes, prompting the user to enter reset information. The user enters the reset type, number, and operation information, saving them to the same array, with the number corresponding to the array index. The script checks if all information has been entered. If not, it continues entering information. When all information has been entered, the user is prompted to enter the reset test type: 0 for manual input, 1 for random generation. After entering the reset test type, the script checks if it is randomly generated. If it is, it executes a random algorithm to generate a reset type number = random.randint(x, y), where x and y represent the upper and lower limits of the range. x = 0, y = the total number of reset types. Based on the reset type number, the script finds the corresponding reset information array and retrieves the corresponding reset information. If it is not randomly generated, the user manually enters the reset type number. The script checks if the reset type number is correct. If the reset type number is incorrect, the user manually re-enters the reset type number. If the reset type number is correct, the script finds the corresponding reset information array and retrieves the corresponding reset information. After obtaining the corresponding reset information, it is determined whether it is a direct hard disk reset. If it is a direct hard disk reset, the reset information is transmitted via serial port and triggered; the reset information is then transmitted to the RAID-side disk reset logic. If it is not a direct hard disk reset, it is determined whether it needs to be executed in an I / O scenario. If it needs to be executed in an I / O scenario, the I / O execution logic is triggered, the I / O execution process is recorded, and a reset is performed during the I / O execution process; the reset is executed, and the corresponding triggering method, such as writing to a register, is executed according to the reset information; if it does not need to be executed in an I / O scenario, the reset is executed, and the corresponding triggering method, such as writing to a register, is executed according to the reset information; the reset trigger is then transmitted to the RAID side for processing.

[0134] In this embodiment, the reset injection mechanism supports manual input and random generation for reset triggering, which can be selected according to needs. It also supports stress testing, realizes automated testing, and increases the flexibility of reset testing.

[0135] refer to Figure 5 , Figure 5 This is a schematic diagram of the structure of a reset test system proposed in one embodiment of this application. Figure 5 As shown, the reset test system includes a reset injector and a RAID card.

[0136] The reset injector is primarily responsible for inputting, summarizing, and saving all reset type information according to the standard NVMe protocol and PCIe manual, following the NVMe and PCIe standard protocol interfaces. It then triggers and transmits reset information to the RAID card using different reset trigger methods based on the reset type, supporting both manual input and random generation of reset types. Specifically, it is controlled by a switch, allowing users to input type codes such as 0 (manual input) and 1 (random generation) for arbitrary selection. Afterward, different reset trigger methods are used based on the reset type. For example, in a host reset process, a reset scenario is triggered on the host side by executing scripts, ultimately transmitting the reset type to the RAID-side reset processing logic. This allows for testing of specific reset scenarios and reset stress tests. Another method involves a direct hard drive reset process, where the reset type is triggered and transmitted to the RAID-side disk reset logic via a standard transmission interface such as a serial port, directly resetting the SSD. This also supports stress testing.

[0137] The RAID card is primarily responsible for receiving reset information from the host-side reset injector and executing corresponding reset scenario processing logic based on different reset types. Specifically, for host resets, the common processing logic can be triggered via interrupts. This logic uses message queues to transmit information according to different reset types, ultimately waking up the reset processing logic thread to perform reset preprocessing, reset notification, and reset execution. During this process, different operations are performed based on the reset type, such as stopping I / O, resetting the SSD, or flushing the cache. For hard drive resets, the reset is performed directly according to the disk reset logic. For host reset testing, the RAID side also records each different reset type and related information, and registers relevant interrupt handling functions and reset threads during the initialization phase to create a closed-loop reset processing mechanism.

[0138] The reset testing system supports standalone reset test scenarios, scenarios involving resets during NVMe IO processing, and disk-specific reset scenarios. Host reset testing includes... Figure 1 As shown in the flow ①->②->③, reset scenario testing can also be performed on the host side during the IO business process, as shown in the flow ④->⑤->⑥->①->②->③->⑦. Direct reset testing for the hard drive is as follows... Figure 1 The process is shown in the diagram: ①->⑧->⑨->⑩.

[0139] In this embodiment, based on the standard NVMe protocol and PCIe manual, different reset test scenarios such as NVMeCLR and PCIe FLR are statistically analyzed. Simultaneously, a reset type encoding and injection method is used to replace the specific reset scenario construction process, significantly reducing costs and improving efficiency. Reset triggering is supported through manual input and random generation, and both can be executed in parallel. Stress testing is also supported, achieving automated testing and increasing the flexibility of reset testing.

[0140] Based on the same inventive concept in steps S11-S15, a reset test device is applied to a host computer, the device comprising:

[0141] The acquisition module is used to acquire the target reset type number and determine the target reset information corresponding to the target reset type number based on the correspondence between the reset type number and the reset information.

[0142] The first triggering module is used to send the target reset information to the disk array when the reset type in the target reset information is hard disk reset, so as to trigger the disk array to execute the hard disk reset process;

[0143] The determination module is used to determine whether it is necessary to execute in an I / O scenario if the reset type in the target reset information is host reset;

[0144] The second triggering module is used to send the target reset information to the disk array when it is not necessary to execute in an I / O scenario, so as to trigger the disk array to execute the host reset process.

[0145] The third triggering module is used to trigger the IO execution logic when it is required to be executed in an IO scenario, record the IO execution process, and send the target reset information to the disk array during the IO execution process to trigger the host reset process in the IO processing of the disk array.

[0146] In one alternative embodiment, the device further includes:

[0147] A module is built to number multiple reset types, resulting in multiple reset type numbers;

[0148] The reset description, I / O operations, and disk operations involved in each of the multiple reset types are used as the reset information for each reset type. Based on the reset type number and reset information of each of the multiple reset types, a correspondence between the reset type number and the reset information is established.

[0149] In one optional implementation, the acquisition module is specifically used for:

[0150] The type of reset test is determined, including: manually entered and randomly generated;

[0151] When the type of the reset test is manual input, output a prompt message indicating the range of reset type numbers, obtain the first reset type number input by the user, and determine whether the first reset type number is within the range of the type numbers;

[0152] If the first reset type number is not within the range of reset type numbers, the first reset type number is determined to be invalid, and a prompt message to re-enter the reset type number is output.

[0153] If the first reset type number is within the range of the reset type numbers, the first reset type number is determined as the target reset type number;

[0154] When the type of the reset test is randomly generated, a second reset type number is randomly generated according to the range of the reset type number, and the second reset type number is determined as the target reset type number.

[0155] Based on the same inventive concept in steps S21-S24, a reset test device is applied to a disk array, the device comprising:

[0156] The receiving module is used to receive target reset information sent by the host;

[0157] The first execution module is used to execute the hard disk reset process when the reset type in the target reset information is hard disk reset;

[0158] The second execution module is used to execute the host reset process when the reset type in the target reset information is host reset and it is not required to be executed in an I / O scenario.

[0159] The third execution module is used to execute the host reset process in the IO process when the reset type in the target reset information is host reset and needs to be executed in an IO scenario.

[0160] In one alternative embodiment, the device further includes:

[0161] The first processing module is used to add target reset information to a message queue; when the target reset information is detected in the message queue, the reset processing thread is woken up by an interrupt handler; the reset processing thread retrieves the target reset information from the message queue; the reset processing thread parses the target reset information to obtain a parsing result; if the parsing result indicates that the reset type in the target reset information is host reset and does not need to be executed in an I / O scenario, the host reset process is executed; if the parsing result indicates that the reset type in the target reset information is host reset and needs to be executed in an I / O scenario, the host reset process in the I / O processing is executed.

[0162] In one alternative embodiment, the device further includes:

[0163] The second processing module is used to: stop the I / O sent by the host when the I / O operation involved in the target reset information is stop I / O, so as to achieve reset preprocessing; reset the connected disk when the disk operation involved in the target reset information is disk reset, so as to achieve reset preprocessing; and flush the cache of the connected disk when the disk operation involved in the target reset information is flush cache, so as to achieve reset preprocessing; and notify the target module to save the currently stored data, wherein the target module is the module whose stored data is lost after power failure.

[0164] As the device embodiment is basically similar to the method embodiment, the description is relatively simple, and relevant parts can be found in the description of the method embodiment.

[0165] Based on the same inventive concept, another embodiment of this application provides an electronic device, referring to... Figure 6 , Figure 6 This is a schematic diagram illustrating an electronic device according to an embodiment of this application. For example... Figure 6 As shown, the electronic device 100 includes a memory 110 and a processor 120. The memory 110 and the processor 120 are connected via a bus for communication. The memory 110 stores a computer program that can run on the processor 120 to implement the steps in the reset test method disclosed in this embodiment.

[0166] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. The same or similar parts between the various embodiments can be referred to each other.

[0167] Those skilled in the art will understand that embodiments of this application can be provided as methods, apparatus, or computer program products. Therefore, embodiments of this application can take the form of entirely hardware embodiments, entirely software embodiments, or embodiments combining software and hardware aspects. Furthermore, embodiments of this application can take the form of computer program products implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0168] This application describes embodiments with reference to flowchart illustrations and / or block diagrams of methods, terminal devices (systems), and computer program products according to embodiments of this application. It should be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing terminal device to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing terminal device, generate instructions for implementing the flowchart illustrations. Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0169] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing terminal device to operate in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0170] These computer program instructions can also be loaded onto a computer or other programmable data processing terminal equipment, causing a series of operational steps to be performed on the computer or other programmable terminal equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable terminal equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0171] Although preferred embodiments of the present application have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of the embodiments of the present application.

[0172] Finally, it should be noted that in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or terminal device that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or terminal device. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or terminal device that includes said element.

[0173] The above provides a detailed description of the reset test method, apparatus, and device provided in this application. Specific examples have been used to illustrate the principles and implementation methods of this application. The description of the above embodiments is only for the purpose of helping to understand the method and core ideas of this application. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of this application. Therefore, the content of this specification should not be construed as a limitation of this application.

Claims

1. A reset test method, characterized by, The method applied to a host comprises: obtaining a target reset type number and determining target reset information corresponding to the target reset type number according to a corresponding relationship between the reset type number and the reset information; in the case that the reset type in the target reset information is a hard disk reset, sending the target reset information to a disk array to trigger the disk array to execute a hard disk reset process; in the case that the reset type in the target reset information is a host reset, determining whether it is necessary to execute in an IO scenario; in the case that it is not necessary to execute in the IO scenario, sending the target reset information to the disk array to trigger the disk array to execute a host reset process; in the case that it is necessary to execute in the IO scenario, triggering IO execution logic, recording an IO execution process, and sending the target reset information to the disk array in the IO execution process to trigger the disk array to execute a host reset process in the IO process; wherein the host reset comprises NVMe CLR, NVMe shut down, PCIe FLR, PCIe hot reset, and PCIe cold reset; the hard disk reset comprises NVMe CLR, NVMe shut down, and cold reset.

2. The reset test method of claim 1, wherein, The method further comprises: numbering a plurality of reset types to obtain a plurality of reset type numbers; taking reset descriptions, IO operations involved, and disk operations involved of the plurality of reset types as reset information of the plurality of reset types respectively; establishing a corresponding relationship between the reset type numbers and the reset information according to the reset type numbers and the reset information of the plurality of reset types respectively.

3. The reset test method according to claim 1 or 2, characterized in that, The method further comprises: obtaining a reset test type, wherein the reset test type comprises manual input and random generation; in the case that the reset test type is the manual input, outputting prompt information of a range of reset type numbers and obtaining a first reset type number input by a user to determine whether the first reset type number is within the range of the type numbers; in the case that the first reset type number is not within the range of the reset type numbers, determining that the first reset type number is invalid and outputting prompt information of re-inputting a reset type number; in the case that the first reset type number is within the range of the reset type numbers, determining the first reset type number as the target reset type number; in the case that the reset test type is the random generation, randomly generating a second reset type number according to the range of the reset type numbers and determining the second reset type number as the target reset type number.

4. A reset test method, characterized by, The method applied to a disk array comprises: receiving target reset information sent by a host; in the case that the reset type in the target reset information is a hard disk reset, executing a hard disk reset process; in the case that the reset type in the target reset information is a host reset and it is not necessary to execute in an IO scenario, executing a host reset process; In a case where the reset type in the target reset information is host reset and needs to be executed in an IO scenario, a host reset procedure in IO processing is executed. The host reset includes an NVMe CLR, an NVMe shut down, a PCIe FLR, a PCIe hot reset, and a PCIe cold reset. The hard disk reset includes an NVMe CLR, an NVMe shut down, and a cold reset.

5. The reset test method of claim 4, wherein, The method further includes: adding the target reset information into a message queue; the host reset procedure includes: when the target reset information is detected in the message queue, waking up a reset processing thread through an interrupt processing program; taking out the target reset information from the message queue through the reset processing thread; analyzing the target reset information through the reset processing thread to obtain an analysis result; in a case where the analysis result is that the reset type in the target reset information is host reset and does not need to be executed in an IO scenario, executing a host reset procedure; in a case where the analysis result is that the reset type in the target reset information is host reset and needs to be executed in an IO scenario, executing a host reset procedure in IO processing.

6. The reset test method of claim 5, wherein, Before executing the host reset procedure, or before executing the host reset procedure in IO processing, at least one of the following is further included: in a case where an IO operation involved in the target reset information is stopping IO, stopping IO issued by a host to achieve reset preprocessing; in a case where a disk operation involved in the target reset information is disk reset, resetting a disk hung down to achieve reset preprocessing; in a case where a disk operation involved in the target reset information is cache flushing, flushing the cache of the disk hung down to achieve reset preprocessing; informing a target module to save currently stored data, the target module being a module whose stored data is lost after power failure.

7. The reset test method of any of claims 5-6, wherein, In a case where the analysis result is that the reset type in the target reset information is host reset and needs to be executed in an IO scenario, executing a host reset procedure in IO processing includes: receiving an IO request sent by a host; in response to the analysis result being that the reset type in the target reset information is host reset and needs to be executed in an IO scenario, executing a host reset procedure in IO processing; after the host reset procedure in IO processing is executed, generating an IO response to the IO request and sending the IO response to the host.

8. A reset testing apparatus, characterized by comprising: The device applied to a host includes: an obtaining module configured to obtain a target reset type number and determine target reset information corresponding to the target reset type number according to a correspondence between reset type numbers and reset information; a first triggering module configured to, in a case where the reset type in the target reset information is hard disk reset, send the target reset information to a disk array to trigger the disk array to execute a hard disk reset procedure; The determining module is configured to determine whether it is necessary to perform in an IO scenario in a case that the reset type in the target reset information is a host reset; The second triggering module is configured to send the target reset information to the disk array to trigger the disk array to perform a host reset process in a case that it is not necessary to perform in an IO scenario; The third triggering module is configured to trigger IO execution logic, record an IO execution process, and send the target reset information to the disk array to trigger the disk array to perform a host reset process in an IO process in a case that it is necessary to perform in an IO scenario; The host reset includes NVMe CLR, NVMe shut down, PCIe FLR, PCIe hot reset, and PCIe cold reset. The hard disk reset includes NVMe CLR, NVMe shut down, and cold reset.

9. A reset testing apparatus, characterized by, The device is applied to a disk array and includes: A receiving module is configured to receive target reset information sent by a host; A first execution module is configured to perform a hard disk reset process in a case that the reset type in the target reset information is a hard disk reset; A second execution module is configured to perform a host reset process in a case that the reset type in the target reset information is a host reset and it is not necessary to perform in an IO scenario; A third execution module is configured to perform a host reset process in an IO process in a case that the reset type in the target reset information is a host reset and it is necessary to perform in an IO scenario; The host reset includes NVMe CLR, NVMe shut down, PCIe FLR, PCIe hot reset, and PCIe cold reset. The hard disk reset includes NVMe CLR, NVMe shut down, and cold reset.

10. An electronic device, comprising: The device includes: A processor, a memory, and a computer program stored on the memory and executable on the processor, wherein the processor executes the computer program to implement the reset test method in any one of claims 1-3 or 4-7.

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