Chip debugging system and method for multiplexing MIPI (Mobile Industry Processor Interface), and computer readable medium

Abstract

The invention provides a chip debugging system and method for multiplexing an MIPI (Mobile Industry Processor Interface) and a computer readable medium, and the chip debugging system comprises a PG, an FPC (Flexible Printed Circuit), a DDIC (Double Data Integrated Circuit) chip PG and a control end used for a debugging mode and a transmission mode; the DDIC chip is connected with the PG through the FPC (Flexible Printed Circuit); the DDIC chip comprises an MIPI (Mobile Industry Processor Interface) module, and the MIPI module comprises N data channels and a clock channel; wherein part of the data channels are multiplexed as debugging channels in the debugging mode. According to the method and the device, the function of multiplexing the MIPI interface as the debugging interface can be realized without changing and simplifying the design of the mass-production FPC, and the problem of debugging difficulty caused by the fact that the mass-production FPC does not lead out a debugging module interface IO is effectively solved.

Description

Technical Field

[0001] The present application relates to the field of integrated circuit design, and in particular to the field of chip debugging technology. Background Art

[0002] MIPI is a high-performance, low-power, low-cost serial communication interface. Its purpose is to standardize the interfaces inside devices, such as cameras, display interfaces, and RF / baseband interfaces, thereby reducing the complexity of device design and increasing design flexibility. The advantage of a unified interface standard is that manufacturers can flexibly choose different chips and modules according to their needs, and it is very quick and convenient to change the design and function. MIPI is mainly used in mobile devices and embedded devices, such as mobile phones, computers, car entertainment systems, wearable devices, and IoT devices.

[0003] In the AMOLED display module solutions on the market, the mass production version FPC that encapsulates the DDIC chip is often designed to be the simplest state. For example, in the mass production version FPC design, the DDIC chip interface IO is minimized, and only the essential communication interface is retained, such as the MIPI interface, which maintains the interface IO for the mobile phone AP or debugging device PG (Programmable Generator) and the module DDIC (Display Driver IC) chip to send and receive images. This is to reduce costs as much as possible on the one hand, and on the other hand, it can also reduce the complexity of the mass production version FPC design. The fewer DDIC IO interfaces are brought out, the higher the yield of the mass production version FPC (Flexible Printed Circuit). In the design of mass production FPCs for large-scale mass production, for cost control considerations, the debugging IO interfaces of the DDIC chips on these mass production FPCs are not brought out. Only the essential interface IO, such as the MIPI interface IO, is retained when designing the mass production FPC.

[0004] When problems occur with mass-produced FPC modules using these streamlined designs, the DDIC chip debugging IO interface is not brought out on the mass-produced FPC, making it impossible to observe the internal working state of the DDIC chip on the mass-produced FPC module (observing the state machine jump inside the IC, key indicator signals that identify the internal state of the IC, etc.), which seriously affects the efficiency of debugging the DDIC chip of the mass-produced FPC module. If R&D cannot quickly locate the problem, it will often affect the speed of product launch, thus having a more extensive negative impact on the macro level of company operations and marketing.

[0005] In order to solve the debugging dilemma, the DDIC chip on the mass production version of the FPC module is often stripped and repackaged on the COB or engineering board FPC module for debugging. In this way, although the convenience of debugging is obtained at the cost of time and money, the working environment of the COB or engineering board FPC module is not essentially the same working environment as the mass production version of the FPC module. There is a possibility that the problems of the mass production version of the FPC module cannot be reproduced in the COB working environment or the engineering board FPC module working environment. Often some tricky problems appear only on the mass production version of the FPC module, but cannot be reproduced on the COB or the engineering version of the FPC. When faced with these problems, R&D needs to spend more time analyzing through other methods, such as simulation verification, which is a method that takes a lot of time and energy but may not be effective. Therefore, the best strategy is still to reproduce the problem on the mass production version of the FPC module and try to analyze the problem directly.

[0006] In view of this, this application is filed. Summary of the invention

[0007] The present invention provides a chip debugging system and method for multiplexing a MIPI interface, and a computer-readable medium, which can directly observe the internal state of a DDIC chip by multiplexing the MIPI interface as a debugging interface.

[0008] On the one hand, this embodiment provides a chip debugging system for multiplexing a MIPI interface, including:

[0009] PG, FPC and DDIC chips;

[0010] PG, the control terminal for debug mode and transfer mode;

[0011] A DDIC chip connected to the PG via the FPC; the DDIC chip includes a MIPI module, and the MIPI module includes N data channels and one clock channel;

[0012] Among them, the clock channel is used by PG to transmit clock signals to DDIC chip;

[0013] One of the N data channels is used by the PG to transmit high-speed image data packets or low-speed command packets to the DDIC chip, which is recorded as the control channel;

[0014] M data channels among the (N-1) data channels are used in the debugging mode for the test signal collection module to transmit the detection signal to the detection unit, or, in the transmission mode, for the PG to transmit the high-speed image data packet to the DDIC chip, and are recorded as multiplexing channels;

[0015] Wherein, N is an integer greater than or equal to 2, and M is an integer less than or equal to (N-1).

[0016] Furthermore, the DDIC chip further comprises a channel processing module, a test signal collection module and a debugging module; the MIPI module, the channel processing module, the test signal collection module and the debugging module are connected in sequence;

[0017] The test signal collection module is also connected to the MIPI module;

[0018] The test signal collection module transmits the detection signal to the detection unit through the multiplexing channel in the MIPI module.

[0019] Furthermore, in the debugging mode, the multiplexing channel is used as the GPIO IO of the DDIC chip and is configured as the GPIO OUTPUT output mode.

[0020] Furthermore, the detection unit is an oscilloscope or a logic analyzer.

[0021] Furthermore, the path processing module includes IP0, IP1, IP2 and IP3 connected in sequence.

[0022] On the other hand, based on the above chip debugging system, the present application also provides a chip debugging method, comprising the following steps:

[0023] Step 1: Send a low-speed command packet through the control channel to enter the debug mode, and the multiplexed channel is configured as the GPIOOUTPUT output mode;

[0024] Step 2: input a first signal to the unit to be debugged, and the unit to be debugged outputs a second signal;

[0025] Step 3: The first signal and the second signal are output as GPIO signal waveforms via a multiplexing channel;

[0026] Step 4: The detection unit captures the GPIO signal waveform output by the multiplexing channel and observes it.

[0027] Furthermore, the first signal includes a vertical synchronization signal, a horizontal synchronization signal and data enable data.

[0028] Furthermore, the second signal includes a vertical synchronization signal, a horizontal synchronization signal and data enable data.

[0029] On the other hand, the present application also provides a computer-readable medium storing a computer program, wherein the computer program executes the above-mentioned chip debugging method when running on a computer.

[0030] Compared with the prior art, the present invention has the following beneficial effects:

[0031] 1) The present invention reuses the MIPI interface as a debugging interface, and can easily capture the internal signals of the DDIC on the streamlined mass production version of the FPC module through the MIPI interface for mass production problem analysis and rapid problem location. This effectively solves the debugging difficulty caused by the mass production version of the FPC due to the lack of a debugging module interface IO.

[0032] 2) The present invention can realize the function of reusing the MIPI interface as a debugging interface without changing the streamlined mass production version FPC design, and does not increase additional mass production version FPC design overhead and cost. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0034] Figure 1 It is a structural diagram of a general DDIC chip;

[0035] Figure 2 Schematic diagram of the DDIC chip structure of this embodiment;

[0036] Figure 3 This is a schematic diagram of the transmission mode of this embodiment;

[0037] Figure 4 This is a schematic diagram of the debugging mode of this embodiment;

[0038] Figure 5 It is a debugging diagram of the path processing module of this embodiment. DETAILED DESCRIPTION

[0039] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0040] Figure 1 Figure 2 shows a schematic diagram of the internal structure of a currently common DDIC chip. Figure 1 As shown, the PG 10 , the FPC 20 , the DDIC chip 30 and the display screen are connected in sequence, wherein the DDIC chip 30 includes a MIPI module 301 , a channel processing module 302 , a debugging signal collection module 303 and a debugging module 304 .

[0041] In the initial stage of chip debugging, such as the CP test stage and COB test stage of the DDIC chip, and the FPC module test stage of the engineering board, the debugging module 304 of the DDIC chip, such as the Debug_SPI IO interface or the Debug_GPIOIO interface, is brought out to facilitate debugging. Figure 1 As shown by arrow a in the middle. Generally, the engineering board FPC is only used by R&D personnel of chip design companies in the laboratory, and generally only a small batch of engineering version FPC is prepared for in-factory debugging and verification; when the product plan is determined, the mass production version FPC will be used for large-scale product applications, so most of the product problems exposed in the mass production process are almost all modules using the mass production version FPC. In the mass production version, the interface in the debugging module 304 is usually closed, so it is difficult to debug the chip.

[0042] This embodiment provides a system that directly reuses the MIPI interface as a chip debugging interface. Figure 2 As shown, the DDIC chip of this embodiment has almost no difference from the internal modules of the general DDIC chip, the only difference is that the debug signal collection module 303 is also connected to the MIPI module 301 ( Figure 2 As shown by arrow b), and the MIPI module 301 also sends a signal to the detection unit ( Figure 2 Not shown) transmits a detection signal ( Figure 2 That is to say, in the mass production version of this embodiment, the DDIC chip can be debugged through the MIPI module 301.

[0043] The principle of this embodiment is to realize the debugging of DDIC chip by reusing part of the data channels in MIPI module 301 as the debugging interface. When faced with the need to debug the problem of the streamlined mass production version FPC module, because the MIPI interface is also necessarily present on the mass production version FPC, at this time, by reusing the MIPI interface as the debugging interface, the internal state of the DDIC chip can be directly observed.

[0044] The principle of multiplexing some data lanes in the MIPI module 301 as the MIPI debug interface is based on retaining the functions of the MIPIPHY layer unchanged. Generally, the MIPI module 301 has N data lanes (MIPI Data Lanes) and one clock lane (MIPI Clock Lane);

[0045] Among them, the clock channel is used by PG to transmit clock signals to DDIC chip;

[0046] One of the N data channels is used by the PG to transmit high-speed image data packets or low-speed command packets to the DDIC chip, which is recorded as the control channel (MIPIData Lane0);

[0047] M data channels among the (N-1) data channels are used in the debugging mode for the test signal collection module to transmit the detection signal to the detection unit, or, in the transmission mode, for the PG to transmit the high-speed image data packet to the DDIC chip, which are recorded as multiplexing channels;

[0048] Wherein, N is an integer greater than or equal to 3, and M is a positive integer;

[0049] like Figure 3-4 As shown, the MIPI module 301 has 4 MIPI Data Lanes and 1 MIPI Clock Lane, each Data Lane and Clock Lane has 2 differential signal pairs, and a total of 10 IO Pads. Whether it is a MIPI conventional application or a MIPI debugging application of the present invention, the function of the MIPI Clock Lane remains unchanged, and only the functions of the 4 MIPI Data Lanes are changed.

[0050] When the MIPI module 301 is in the receiving mode, Figure 3 As shown, all four MIPIData Lanes are used to send high-speed image data packets, and one MIPIData Lane0 is used to send low-speed command packets in addition to high-speed image data packets. The mobile phone AP or debugging device PG can send commands to DDIC or read certain specific status bits through MIPIData Lane0.

[0051] When the MIPI module 302 is in debug mode, Figure 4 As shown in the figure, only MIPIData Lane0 is reserved among the four MIPIData Lanes to send high-speed image data packets and low-speed command packets, and the other three MIPIData Lanes 1 / 2 / 3 are used as GPIO IOs of the DDIC chip, configured as 6 GPIO OUTPUT output mode. In this way, image data is sent to DDIC through MIPIData Lane0 and the internal configuration of DDIC is configured. The preset state machine signals inside DDIC and the key indication signals that identify the internal status of IC can be observed through the 6 GPIO OUTPUT Pads multiplexed from MIPIData Lane1 / 2 / 3.

[0052] It should be noted that in the above embodiment, only three MIPI Data Lanes are multiplexed as debug interfaces, which is only for illustration, and the specific number is not limited thereto and can be flexibly adjusted according to actual conditions.

[0053] On the other hand, based on the above chip debugging system, this embodiment also provides a chip debugging method, including the following steps:

[0054] Step 1: Send a low-speed command packet through the control channel to enter the debug mode, and the multiplexed channel is configured as the GPIOOUTPUT output mode;

[0055] Step 2, inputting a first signal to the unit to be debugged, and the unit to be debugged outputs a second signal;

[0056] Step 3: The first signal and the second signal are output as GPIO signal waveforms via a multiplexing channel;

[0057] Step 4: The detection unit captures the GPIO signal waveform output by the multiplexing channel and observes it.

[0058] Preferably, the first signal includes a vertical synchronization signal, a horizontal synchronization signal and data enable data.

[0059] Preferably, the second signal includes a vertical synchronization signal, a horizontal synchronization signal and data enable data.

[0060] Figure 5 FIG. 4 shows a schematic diagram of debugging a channel processing module. Figure 5 As shown, the path processing module 302 includes IP0, IP1, IP2 and IP3 connected in sequence.

[0061] Now Figure 5 The path processing module shown is a unit to be debugged and is combined with Figure 4 Provide detailed explanation.

[0062] The first step is to debug IP0.

[0063] Send low-speed command packets through MIPIData Lane0 to control the output of MIPIData Lane1 / 2 / 3 multiplexed GPIO. The command packet configures DDIC to: multiplex GPIO 0,1,2 output Vsync[0],Hsync[0],DE[0], multiplex GPIO 3,4,5 output Vsync[1],Hsync[1],DE[1]. Use an oscilloscope or logic analyzer to capture the signal waveforms of the above multiplexed GPIOs and observe them. If all signals are displayed normally, it means that IP0 is working properly; otherwise, if the timing of Vsync[0],Hsync[0],DE[0] is normal, but the timing of Vsync[1],Hsync[1],DE[1] is wrong, it means that IP0 is working abnormally.

[0064] The second step is to debug IP1.

[0065] Send low-speed command packets through MIPIData Lane0 to control the output of MIPIData Lane1 / 2 / 3 multiplexed GPIO. The command packet configures DDIC to: multiplex GPIO 0,1,2 output Vsync[1],Hsync[1],DE[1], multiplex GPIO 3,4,5 output Vsync[2],Hsync[2],DE[2]. Use an oscilloscope or logic analyzer to capture the signal waveforms of the above multiplexed GPIOs and observe them. If all signals are displayed normally, it means that IP1 is working properly; otherwise, if the timing of Vsync[1],Hsync[1],DE[1] is normal, but the timing of Vsync[2],Hsync[2],DE[2] is wrong, it means that IP1 is working abnormally.

[0066] The third step is to debug IP2.

[0067] Send low-speed command packets through MIPIData Lane0 to control the output of MIPIData Lane1 / 2 / 3 multiplexed GPIO. The command packet configures DDIC to: multiplex GPIO 0,1,2 output Vsync[2],Hsync[2],DE[2], multiplex GPIO 3,4,5 output Vsync[3],Hsync[3],DE[3]. Use an oscilloscope or logic analyzer to capture the signal waveforms of the above multiplexed GPIOs and observe them. If all signals are displayed normally, it means that IP2 is working properly; otherwise, if the timing of Vsync[2],Hsync[2],DE[2] is normal, but the timing of Vsync[3],Hsync[3],DE[3] is wrong, it means that IP2 is working abnormally.

[0068] The fourth step is to debug IP3.

[0069] Send low-speed command packets through MIPIData Lane0 to control the output of MIPIData Lane1 / 2 / 3 multiplexed GPIO. The command packet configures DDIC to: multiplex GPIO 0,1,2 output Vsync[3],Hsync[3],DE[3], multiplex GPIO 3,4,5 output Vsync[4],Hsync[4],DE[4]. Use an oscilloscope or logic analyzer to capture the signal waveforms of the above multiplexed GPIOs and observe them. If all signals are displayed normally, it means that IP3 is working properly; otherwise, if the timing of Vsync[3],Hsync[3],DE[3] is normal, but the timing of Vsync[4],Hsync[4],DE[4] is wrong, it means that IP3 is working abnormally.

[0070] From the above, it can be seen that the chip debugging method and system using the multiplexed MIPI interface proposed in this article can more conveniently complete the analysis and debugging of product problems based on such FPC modules without changing the design of the streamlined mass production version of FPC.

[0071] In summary, the chip debugging method and system for reusing the MIPI interface proposed in this article can complete the analysis and debugging of product problems based on such FPC modules without changing the streamlined mass-produced version of the FPC design, which can ensure that the FPC design is sufficiently streamlined while maintaining sufficient debugging and analysis means.

[0072] The "equal" or "same" or "equal" disclosed in the present invention must take into account the distribution of engineering parameters, and the error distribution is within ±30%; the definition of "parallel" of two line segments or two straight lines is that the angle between the two line segments or two straight lines is less than or equal to 45 degrees; the definition of "perpendicular" of two line segments or two straight lines is that the angle between the two line segments or two straight lines is within the range of [60, 120] degrees; the definition of "phase mismatch" also needs to take into account the distribution of engineering parameters, and the error distribution of the degree of mismatch is within ±30%. In addition, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also includes other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. Without more constraints, an element defined by the phrase "comprising a ..." does not exclude the existence of other identical elements in the process, method, article or apparatus comprising the element.

[0073] The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0074] The above description of the disclosed embodiments enables one skilled in the art to implement or use the present invention. Various modifications to these embodiments will be apparent to one skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention will not be limited to the embodiments shown herein, but rather to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A chip debugging system for multiplexing MIPI interface, comprising: PG, FPC and DDIC chips; PG, the control terminal for debug mode and transfer mode; A DDIC chip connected to the PG via the FPC; the DDIC chip includes a MIPI module, and the MIPI module includes N data channels and one clock channel; Among them, the clock channel is used by PG to transmit clock signals to DDIC chip; One of the N data channels is used by the PG to transmit high-speed image data packets or low-speed command packets to the DDIC chip, which is recorded as the control channel; M data channels among the (N-1) data channels are used in the debugging mode for the test signal collection module to transmit the detection signal to the detection unit, or, in the transmission mode, for the PG to transmit the high-speed image data packet to the DDIC chip, and are recorded as multiplexing channels; Wherein, N is an integer greater than or equal to 2, and M is an integer less than or equal to (N-1).

2. The chip debugging system according to claim 1, characterized in that: The DDIC chip also includes a channel processing module, a test signal collection module and a debugging module; the MIPI module, the channel processing module, the test signal collection module and the debugging module are connected in sequence; The test signal collection module is also connected to the MIPI module; The test signal collection module transmits the detection signal to the detection unit through the multiplexing channel in the MIPI module.

3. The chip debugging system according to claim 1, characterized in that: In the debug mode, the multiplexed channel is used as the GPIOIO of the DDIC chip and is configured as the GPIO OUTPUT output mode.

4. The chip debugging system according to claim 1, characterized in that: The detection unit is an oscilloscope or a logic analyzer.

5. The chip debugging system according to claim 2, characterized in that: The path processing module includes IP0, IP1, IP2 and IP3 which are connected in sequence.

6. A chip debugging method based on the chip debugging system according to any one of claims 1 to 5, characterized in that: The following steps are involved: Step 1: Send a low-speed command packet through the control channel to enter the debug mode, and the multiplexed channel is configured as the GPIO OUTPUT output mode; Step 2: input a first signal to the unit to be debugged, and the unit to be debugged outputs a second signal; Step 3: The first signal and the second signal are output as GPIO signal waveforms via a multiplexing channel; Step 4: The detection unit captures the GPIO signal waveform output by the multiplexing channel and observes it.

7. The chip debugging method as claimed in claim 6, characterized in that: The first signal includes a vertical synchronization signal, a horizontal synchronization signal and data enable data.

8. The chip debugging method according to claim 6, characterized in that: The second signal includes a vertical synchronization signal, a horizontal synchronization signal and data enable data.

9. A computer-readable medium, characterized in that A computer program is stored, and when the computer program is run on a computer, the chip debugging method according to any one of claims 6 to 8 is executed.

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