A cache management method, device and equipment for memory access and storage medium

Abstract

The application discloses a cache management method and device for memory access, equipment and a storage medium, and relates to the technical field of storage. The method comprises the following steps: acquiring a data read-write message of a central processing unit; detecting the data heat type of an access address of the data read-write message; searching for cache data corresponding to the access address from a target cache area; if the cache data is not found from the target cache area, sending a corresponding read-write request to the memory to search for memory data corresponding to the access address from the memory; through the setting of the preset cache area corresponding to the cold data and the hot data, the cache can be partitioned according to the heat of the data, the cache resources can be reasonably allocated, the cost is reduced, the efficiency and speed of memory access are improved, more precise consistency control can be realized, the cache hit rate and system performance are improved, and therefore, the required data can be searched for from the corresponding preset cache area according to the heat of the data, and the speed of memory access is improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of storage, in particular to a cache management method and device for memory access, equipment and a storage medium. BACKGROUND

[0002] Generally, with the improvement of CPU (Central Processing Unit) performance, the CPU speed is getting faster and faster, while the memory reading speed is slower than the CPU, the memory delay close to the CPU is low, but the size is limited, and the implementation cost is high. Generally, a larger memory block needs to be implemented, but these memory blocks increase the delay. In order to optimize the overall performance, the memory system can contain multiple levels of cache in a hierarchical memory system, thereby making a trade-off between size and delay.

[0003] The cache is a high-speed memory block, which is usually composed of static random access memory (SRAM), which is faster than the main memory (such as DRAM, i.e. memory), but the cost is higher. Modern computers usually have a multi-level cache structure, such as L1, L2 and L3 cache. The closer to the CPU, such as L1 cache is the fastest, but the capacity is the smallest; L3 cache has the largest capacity and relatively slow speed. When the CPU reads and writes memory data, it will first search in the cache, if it hits, it will use the data in the cache, otherwise it will read in the memory.

[0004] At present, with the development of artificial intelligence and information industry, the amount of data is growing, and the speed requirement of memory access is getting higher and higher. In the process of memory access, some frequently read data or a large amount of access to the same data in a short time often occurs. The traditional cache management system does not distinguish the heat of the data when processing data access, resulting in the mixing storage of hot data and cold data, thereby reducing the cache hit rate and system performance, and causing the waste of cache resources. As the key technology to alleviate the speed difference between CPU and memory, the design and management mode of cache directly affects the performance of the whole system. Therefore, how to improve the speed of memory access, improve the cache hit rate and system performance is a problem that needs to be solved urgently. SUMMARY

[0005] The purpose of the present application is to provide a cache management method and device for memory access, equipment and a computer readable storage medium, to improve the speed of memory access, improve the cache hit rate and system performance.

[0006] To solve the above technical problems, the present application provides a cache management method for memory access, comprising:

[0007] Obtaining the data read-write message of the central processing unit;

[0008] detect a data hotness type of an access address of the data read-write message; wherein the data hotness type comprises cold data and hot data;

[0009] find cache data corresponding to the access address from a target cache area; wherein the target cache area is a preset cache area corresponding to the data hotness type, the preset cache area corresponding to the hot data comprises a hot data cache layer, a hot data area in a first common cache layer, and a second common cache layer, the preset cache area corresponding to the cold data comprises a cold data area in the first common cache layer and the second common cache layer, a granularity of the hot data cache layer and the hot data area is smaller than a granularity of the cold data area and the second common cache layer, a distance between the hot data cache layer and the central processing unit is smaller than a distance between the first common cache layer and the central processing unit, and the distance between the first common cache layer and the central processing unit is smaller than a distance between the second common cache layer and the central processing unit;

[0010] if the cache data is not found from the target cache area, send a corresponding read-write request to a memory to find memory data corresponding to the access address from the memory.

[0011] In another aspect, the finding of the cache block corresponding to the access address from the target cache area comprises:

[0012] in order from near to far from the central processing unit, find the cache data corresponding to the access address from each cache layer in the target cache area in turn.

[0013] In another aspect, the hot data cache layer comprises a first cache layer, the first common cache layer comprises a second cache layer, and the second common cache layer comprises a third cache layer and a fourth cache layer; and the finding of the cache data corresponding to the access address from each cache layer in the target cache area in turn in order from near to far from the central processing unit comprises:

[0014] if the data hotness type is the hot data, find the cache data from the first cache layer;

[0015] if the cache data is not found from the first cache layer, find the cache data from a hot data area in the second cache layer;

[0016] if the cache data is not found from the hot data area in the second cache layer, find the cache data from the third cache layer;

[0017] if the cache data is not found from the third cache layer, find the cache data from the fourth cache layer;

[0018] when the cache data is not found in the fourth cache layer, sending a corresponding read-write request to the memory to find the memory data corresponding to the access address in the memory;

[0019] if the data hotness type is the cold data, finding the cache data in the cold data area in the second cache layer;

[0020] when the cache data is not found in the cold data area in the second cache layer, finding the cache data in the third cache layer;

[0021] when the cache data is not found in the third cache layer, finding the cache data in the fourth cache layer;

[0022] when the cache data is not found in the fourth cache layer, sending a corresponding read-write request to the memory to find the memory data corresponding to the access address in the memory.

[0023] In another aspect, the method further comprises:

[0024] determining a respective prefetch strategy for each memory data according to a data hotness type of each memory data in the memory; wherein the prefetch strategy comprises a cold data prefetch strategy and a hot data prefetch strategy; a prefetch trigger condition of the hot data prefetch strategy is lower than a prefetch trigger condition of the cold data prefetch strategy, and / or a prefetch window of the hot data prefetch strategy is greater than a prefetch window of the cold data prefetch strategy;

[0025] storing, according to the prefetch strategy, the memory data triggering the corresponding prefetch trigger condition to a corresponding preset cache area.

[0026] In another aspect, the detecting the data hotness type of the access address of the data read-write packet comprises:

[0027] determining the data hotness type according to a data hotness value flag bit of the access address in a preset memory management mapping table; wherein the preset memory management mapping table comprises each address information and a respective data hotness value flag bit.

[0028] In another aspect, the method further comprises:

[0029] monitoring an access frequency of each historical access address by the central processing unit;

[0030] determining a latest data hotness value flag bit of each historical access address according to the access frequency;

[0031] updating the data hotness value flag bit of the corresponding address information in the preset memory management mapping table according to the latest data hotness value flag bit.

[0032] In another aspect, the method further comprises:

[0033] determining key hotspot data according to the access frequency;

[0034] storing and locking the key hotspot data in each cache layer in a preset cache area corresponding to the hot data.

[0035] The application further provides a cache management device for memory access, comprising:

[0036] an acquisition module for acquiring data read-write messages of a central processor;

[0037] a detection module for detecting a data heat type of an access address of the data read-write messages; wherein the data heat type comprises cold data and hot data;

[0038] a prefetch lookup module for looking up cache data corresponding to the access address from a target cache area; wherein the target cache area is a preset cache area corresponding to the data heat type, the preset cache area corresponding to the hot data comprises a hot data cache layer, a hot data area in a first common cache layer and a second common cache layer, the preset cache area corresponding to the cold data comprises a cold data area in the first common cache layer and the second common cache layer, the granularity of the hot data cache layer and the hot data area is smaller than that of the cold data area and the second common cache layer, and the distance between the hot data cache layer and the central processor is smaller than that between the first common cache layer and the central processor, and that between the second common cache layer and the central processor;

[0039] a memory lookup module for sending a corresponding read-write request to a memory to look up memory data corresponding to the access address from the memory if the cache data is not found from the target cache area.

[0040] The application further provides a cache management device for memory access, comprising:

[0041] a memory for storing a computer program;

[0042] a processor for executing the computer program to realize the steps of the cache management method for memory access as described above.

[0043] In addition, the application further provides a computer readable storage medium, wherein the computer readable storage medium stores a computer program, and the computer program is executed by a processor to realize the steps of the cache management method for memory access as described above.

[0044] The memory access cache management method provided by the application comprises the following steps: obtaining data read-write messages of a central processor; detecting the data hotness type of the access address of the data read-write messages; wherein the data hotness type comprises cold data and hot data; searching for the cache data corresponding to the access address from a target cache area; wherein the target cache area is a preset cache area corresponding to the data hotness type, the preset cache area corresponding to the hot data comprises a hot data cache layer, a hot data area in a first common cache layer and a second common cache layer, the preset cache area corresponding to the cold data comprises a cold data area in the first common cache layer and the second common cache layer, the granularity of the hot data cache layer and the hot data area is smaller than that of the cold data area and the second common cache layer; the distance between the hot data cache layer and the central processor is smaller than that between the first common cache layer and the central processor, and smaller than that between the second common cache layer and the central processor; if the cache data is not searched from the target cache area, a corresponding read-write request is sent to the memory to search for the memory data corresponding to the access address from the memory.

[0045] It can be seen that, by setting the preset cache areas corresponding to the cold data and the hot data respectively, the application can partition the cache according to the data hotness, reasonably allocate the cache resources, reduce the cost, improve the efficiency and speed of memory access, and by setting the hot data cache layer and the hot data area with smaller granularity, more precise consistency control can be realized, the cache hit rate and system performance are improved; by searching for the cache data corresponding to the access address from the target cache area, the required data can be searched from the corresponding preset cache area according to the data hotness, and the speed of memory access is improved. In addition, the application also provides a memory access cache management device, equipment and computer readable storage medium, which also have the above beneficial effects. BRIEF DESCRIPTION OF DRAWINGS

[0046] In order to more clearly illustrate the technical solutions in the embodiments of the application or the prior art, the following will briefly introduce the drawings needed to be used in the embodiments or the prior art description. Obviously, the drawings in the following description only constitute the embodiments of the application, and for those skilled in the art, other drawings can also be obtained without creative labor on the basis of the provided drawings.

[0047] Figure 1 The flow chart of the memory access cache management method provided by the embodiment of the application;

[0048] Figure 2 The system architecture schematic diagram of the memory access cache management method provided by the embodiment of the application;

[0049] Figure 3 The schematic diagram of the mapping table updating process of another memory access cache management method provided by the embodiment of the application;

[0050] Figure 4 FIG. 1 is a flowchart of another cache management method for memory access according to an embodiment of the present application;

[0051] Figure 5 FIG. 2 is a structural block diagram of a cache management device for memory access according to an embodiment of the present application;

[0052] Figure 6 FIG. 3 is a structural diagram of a cache management apparatus for memory access according to an embodiment of the present application. DETAILED DESCRIPTION

[0053] In order to make the objects, technical solutions and advantages of the embodiments of the present application clearer, the following will clearly and completely describe the technical solutions in the embodiments of the present application with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are some but not all of the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative work fall within the scope of protection of the present application.

[0054] For the purpose of Figure 1 , Figure 1 FIG. 1 is a flowchart of a cache management method for memory access according to an embodiment of the present application. The method can include the following steps.

[0055] Step 101: obtaining a data read-write message of a central processing unit.

[0056] In the embodiment, the data read-write message can be a read-write data message of the CPU, such as a data read message. The method provided by the embodiment can be applied to a memory management unit in a processor (such as a CPU core) in a CPU chip, for example, the memory management unit in the step can receive a data read-write message sent by the CPU (i.e. the CPU core). Figure 2

[0057] Step 102: detecting a data hotness type of an access address of the data read-write message; wherein the data hotness type includes cold data and hot data.

[0058] It can be understood that the access address of the data read-write message in the step can be an address to be accessed by the CPU, such as a virtual address or a physical address; and the data hotness type in the step can be a hotness type of data stored in the access address, such as hot data with a high access frequency or cold data with a low access frequency.

[0059] ​Correspondingly, for the specific number and type division of the data hotness types in this embodiment, the designer can set it according to the use scene and user demand, for example, the data hotness types can only include hot data and cold data, or the cold data and / or hot data can be further classified to adopt more types to partition the cache more carefully. This embodiment does not make any limitation on this.

[0060] It should be noted that this embodiment is an example of the processor (such as the memory management unit) processing a data read-write message of the central processor. For the processor processing other data read-write messages of the central processor, the same or similar method as provided in this embodiment can be used to achieve it, and this embodiment does not make any limitation on this.

[0061] Correspondingly, for the specific way of detecting the data hotness type of the access address of the data read-write message in this step, the designer can set it according to the use scene and user demand, for example, the processor (such as the memory management unit) can determine the data hotness type of the access address according to the historical access times of the access address in the preset time period, for example, when the historical access times are greater than the hotness threshold, the data hotness type is determined as hot data, and when the historical access times are greater than the hotness threshold, the data hotness type is determined as cold data. The processor can also determine the data hotness type according to the data hotness value flag of the access address in the preset memory management mapping table; wherein the preset memory management mapping table includes each address information and its respective data hotness value flag; that is, in this embodiment, the respective data hotness value flag (such as the default cold data identifier) of each address information in the pre-set memory management mapping table (i.e. the preset memory management mapping table) can be directly matched to the data hotness value flag corresponding to the access address, so as to determine the data hotness type of the access address according to the identifier (such as the identifier of hot data or cold data) on the data hotness value flag.

[0062] Among them, the address information in the preset memory management mapping table can include the mapping relationship between the virtual address and the physical address. For example, in this step, the memory control unit can use the preset memory management mapping table to convert the virtual address (i.e. the access address of the data read-write message) to be queried by the CPU into a physical address, and simultaneously query the corresponding data hotness value flag recorded in the mapping table to determine the corresponding data hotness type.

[0063] Correspondingly, the method provided in the embodiment can also include a configuration updating process of the data hotness value flag bit corresponding to each address information in the preset memory management mapping table. For example, the method provided in the embodiment can also include monitoring the access frequency of the central processing unit to each historical access address; determining the latest data hotness value flag bit of each historical access address according to the access frequency; and updating the data hotness value flag bit of the corresponding address information in the preset memory management mapping table according to the latest data hotness value flag bit. For example, in some embodiments, a pre-written script software can be used to dynamically and real-time monitor the memory physical address information (such as the access data in Figure 3 ) accessed by the CPU, so as to monitor the access frequency of the CPU to each access address (i.e. historical access address), and thus determine the latest data hotness value flag bit of each access address according to the access frequency and dynamically evaluate the address access hotness. Then, as shown in Figure 3 , the script software can send a command to the CPU to control the CPU to send a corresponding command (such as a flag bit updating command) to the memory control unit to update the data hotness value flag bit of the corresponding address information in the preset memory management mapping table.

[0064] Correspondingly, the embodiment is not limited to the specific way of determining the latest data hotness value flag bit of each historical access address according to the access frequency, such as using a hotness threshold value set according to the system performance requirement and the historical access address to determine whether the access frequency of the current historical access address in a preset time period reaches the hotness threshold value; wherein the current historical access address is any historical access address; if yes, the latest data hotness value flag bit of the current historical access address is determined as the identification of hot data; if no, the latest data hotness value flag bit of the current historical access address is determined as the identification of cold data. For example, when the access frequency of a certain address suddenly increases, if the access frequency of a data item of a certain historical access address exceeds the hotness threshold value in a preset time period, the data item can be determined as hot data.

[0065] Further, in some embodiments, the hotness threshold value can be adjusted according to the access records of each historical access address, such as determining and updating the hotness threshold value according to the access records of all historical access addresses at a preset time interval.

[0066] Step 103: searching for the cache data corresponding to the access address from the target cache area.

[0067] The target cache area is a preset cache area corresponding to the data hotness type, the preset cache area corresponding to the hot data includes a hot data cache layer, a hot data area in a first common cache layer, and a second common cache layer, the preset cache area corresponding to the cold data includes a cold data area in the first common cache layer and the second common cache layer, the granularity of the hot data cache layer and the hot data area is smaller than the granularity of the cold data area and the second common cache layer, the distance between the hot data cache layer and the central processing unit is smaller than the distance between the first common cache layer and the central processing unit, and the distance between the second common cache layer and the central processing unit.

[0068] It can be understood that the target cache area in the embodiment can be a preset cache area corresponding to the data hotness type of the access address; that is, in the embodiment, by pre-setting the cache area (i.e., the preset cache area) corresponding to each data hotness type (such as hot data and cold data), the cache of the CPU can be partitioned according to the hotness of the data, so as to reasonably allocate cache resources and reduce costs.

[0069] Correspondingly, the preset cache area corresponding to the hot data in the embodiment can include a hot data cache layer, a hot data area in a first common cache layer, and a second common cache layer; the preset cache area corresponding to the cold data can include a cold data area in the first common cache layer and the second common cache layer. The hot data cache layer can be a cache layer (such as an L0 hot data layer in Figure 2 ) specially used for storing hot data; the first common cache layer and the second common cache layer can be cache layers used for storing hot data and cold data, the first common cache layer can be divided into a cold data area used for storing cold data and a hot data area used for storing hot data; and the second common cache layer can not be partitioned. That is, in the embodiment, a hot data cache layer can be added to the hardware architecture, a high-speed memory block with better performance such as a static random access memory (SRAM) or a non-volatile memory technology is used, a fine granularity is used, and the cache area is used for storing hot data; the first common cache layer is divided into a hot data area (such as an L1 hot data area in Figure 2 ) and a cold data area (such as an L1 cold data area in Figure 2 ), the hot data area uses a fine granularity, and the cold data area uses a coarse granularity; and the second common cache layer (such as an L2 cache layer and an L3 cache layer in Figure 2 ) can not be partitioned and uses a coarse granularity; so as to reasonably allocate cache resources, so that the hot data cache granularity is smaller, finer consistency control is achieved, the problem of small granularity misses can be reduced because the data access frequency is controlled to be high, and the cold data uses a larger granularity to load more data each time.

[0070] Correspondingly, for the specific manner of searching the cache data corresponding to the access address from the target cache area in this embodiment, the designer can set it by himself, for example, the memory management unit can search the cache data corresponding to the access address from each cache layer in the target cache area in turn according to the order from the closest to the farthest distance from the central processor; the memory management unit can also search the cache data corresponding to the access address from the target cache area simultaneously and in parallel. This embodiment does not make any limitation on this.

[0071] Similarly, this embodiment does not limit the specific data of the hot data cache layer, the first common cache layer and the second common cache layer, for example, the number of the hot data cache layer, the first common cache layer and the second common cache layer can be 1 or greater than 1; for example, Figure 2 As shown in the figure, the number of the hot data cache layer and the first common cache layer can be 1, and the number of the second common cache layer can be 2.

[0072] For example, as shown in the figure, Figure 2 The hot data cache layer includes the first cache layer (L0 cache layer), the first common cache layer includes the second cache layer (L1 cache layer), and the second common cache layer includes the third cache layer (L2 cache layer) and the fourth cache layer (L3 cache layer); the above process of searching the cache data corresponding to the access address from each cache layer in the target cache area in turn according to the order from the closest to the farthest distance from the central processor can include: if the data hotness type is hot data, searching the cache data from the first cache layer; when the cache data is not found in the first cache layer (i.e. miss), searching the cache data from the hot data area in the second cache layer; when the cache data is not found in the hot data area in the second cache layer, searching the cache data from the third cache layer; when the cache data is not found in the third cache layer, searching the cache data from the fourth cache layer; when the cache data is not found in the fourth cache layer, entering step 104 to send the corresponding read / write request to the memory to search the memory data corresponding to the access address from the memory;

[0073] Correspondingly, if the data hotness type is cold data, searching the cache data from the cold data area in the second cache layer; when the cache data is not found in the cold data area in the second cache layer, searching the cache data from the third cache layer; when the cache data is not found in the third cache layer, searching the cache data from the fourth cache layer; when the cache data is not found in the fourth cache layer, entering step 104 to send the corresponding read / write request to the memory to search the memory data corresponding to the access address from the memory.

[0074] For example, as shown in the figure, Figure 4As shown, when the CPU sends a read-write data packet (i.e., a data read-write packet), the memory control unit can query the mapping table of virtual address to physical address, and at the same time obtain the corresponding data hotness value flag recorded in the mapping table; if the data to be read and written is hot data, the corresponding cache block is viewed using index (index) to the L0 cache layer, and then the cache group of the hot data cache area is reached, and it is queried whether the tag (high part of the cache address) of each cache group hits and whether there is a backup in the cache block. If it hits, the data in the cache is read and written according to the protocol consistency policy; if it does not hit, the next layer L1 cache layer hot data area is indexed, and if it hits, the data is read and written; if it does not hit, the L2 cache layer is queried whether it hits, and if it hits, the data in the cache is read and written according to the protocol consistency policy; if it does not hit, the L3 is queried whether it hits, and if it hits, the backup data in the cache is read and written; if it does not hit, the memory (such as Figure 2 the main memory) is requested to load data into the cache. If the data to be read and written is cold data, the corresponding cache block is viewed using index (index) to the cold data area of the L1 cache layer, and then it is queried whether the tag of each cache group corresponding to the cold data area hits and whether there is a backup in the cache block. If it hits, the backup data in the cache is read and written; if it does not hit, the L2 cache layer is queried whether it hits, and if it hits, the data in the cache is read and written according to the protocol consistency policy; if it does not hit, the L3 is queried whether it hits, and if it hits, the backup data in the cache is read and written; if it does not hit, the memory is requested to load data into the cache, and if it still does not hit, the memory is requested to read and write, and the data is loaded into the cache.

[0075] Correspondingly, the method provided in the embodiment can also include a data prefetching process in the cache, i.e., a storage process of corresponding hot data and cold data in the respective preset cache areas of hot data and cold data. For example, in order to improve the accuracy and efficiency of prefetching, the prefetching technology according to hotness can be used in the embodiment, such as different prefetching strategies for cold data and hot data; that is, the respective prefetching strategies of each memory data (i.e., the memory data corresponding to each address information) in the memory can be determined according to the data hotness type of each memory data in the memory; wherein the prefetching strategy includes a cold data prefetching strategy and a hot data prefetching strategy; according to the prefetching strategy, the memory data triggering the corresponding prefetching trigger condition is stored in the corresponding preset cache area.

[0076] Correspondingly, to avoid the additional delay caused by prefetching, the hot data can have a higher prefetching frequency because of the high frequency of expected access, and the expected trigger condition for cold data can be relatively increased to reduce the prefetching frequency of cold data; that is, in some embodiments, the prefetching trigger condition of the hot data prefetching strategy is lower than that of the cold data prefetching strategy. In other embodiments, the prefetching window of the hot data prefetching strategy can be greater than that of the cold data prefetching strategy to achieve dynamic adjustment of the prefetching window size.

[0077] In the embodiment, the related data of the hot data to be currently prefetched is determined as hot data and stored in the preset cache area corresponding to the hot data when the hot data is stored in the corresponding preset cache area.

[0078] Further, the method provided in the embodiment can also copy very hot key data (i.e., key hot data) to multiple cache layers to ensure cache hit rate and temporarily lock the data to prevent replacement during high concurrency access; for example, the key hot data is determined according to the access frequency; the key hot data is distributed and stored in each cache layer in the preset cache area corresponding to the hot data and locked; wherein the access frequency of the key hot data (such as the historical access frequency in a preset time period) can be greater than a key hot threshold, and the key hot threshold can be greater than the hotness threshold.

[0079] Correspondingly, based on the multi-level cache structure in the embodiment, the cache priority can be set according to the hotness of the data, and a cache replacement strategy based on the cache priority can be set to upgrade the priority of the hot data and downgrade the data of the cold data to be deleted from the cache layer close to the CPU, thereby improving the efficiency of memory access. For example, the method provided in the embodiment can also include determining the latest cache priority of each historical access address according to the monitored access frequency of the CPU to each historical access address, i.e., determining the latest cache priority corresponding to each data in the cache; adjusting the data in the cache according to the latest cache priority corresponding to each data in the cache; for example, when the latest cache priority corresponding to the current hot data in the cache is higher than the cache priority corresponding to the cache layer, the current hot data is moved to the cache layer corresponding to the latest cache priority for storage; when the latest cache priority corresponding to the current cold data in the cache is lower than the cache priority corresponding to the cache layer, the current cold data is moved to the cache layer corresponding to the latest cache priority for storage.

[0080] Step 104: If the cache data corresponding to the access address is not found in the target cache area, a corresponding read-write request is sent to the memory to find the memory data corresponding to the access address from the memory.

[0081] In this step, when the data corresponding to the access address is not found in the cache, a corresponding read-write request is sent to the memory to find the corresponding data from the memory.

[0082] In this embodiment, the cache is partitioned according to the heat of the data by setting the preset cache area corresponding to the cold data and the hot data, so as to reasonably allocate the cache resources, reduce the cost, improve the efficiency and speed of memory access, and realize more fine consistency control by setting the hot data cache layer and the hot data area with smaller granularity, thereby improving the cache hit rate and system performance. By finding the cache data corresponding to the access address from the target cache area, the required data can be found in the corresponding preset cache area according to the heat of the data, thereby improving the speed of memory access.

[0083] Corresponding to the above method embodiment, the present embodiment also provides a cache management device for memory access. The cache management device for memory access described below can be referred to in conjunction with the cache management method for memory access described above.

[0084] Please refer to Figure 5 , Figure 5 The structure block diagram of the cache management device for memory access provided by the present embodiment. The device can include:

[0085] The acquisition module 10 is configured to acquire the data read-write message of the central processing unit.

[0086] The detection module 20 is configured to detect the data heat type of the access address of the data read-write message. The data heat type includes cold data and hot data.

[0087] The prefetching and finding module 30 is configured to find the cache data corresponding to the access address from the target cache area. The target cache area is the preset cache area corresponding to the data heat type. The preset cache area corresponding to the hot data includes the hot data cache layer, the hot data area in the first common cache layer, and the second common cache layer. The preset cache area corresponding to the cold data includes the cold data area in the first common cache layer and the second common cache layer. The granularity of the hot data cache layer and the hot data area is smaller than the granularity of the cold data area and the second common cache layer. The distance between the hot data cache layer and the central processing unit is smaller than the distance between the first common cache layer and the central processing unit, which is smaller than the distance between the second common cache layer and the central processing unit.

[0088] The memory lookup module 40 is configured to send a corresponding read-write request to the memory to find the memory data corresponding to the access address from the memory if the cache data is not found from the target cache area.

[0089] In some embodiments, the prefetch lookup module 30 can be specifically configured to find the cache data corresponding to the access address from each cache layer in the target cache area in turn according to the order from the closest to the farthest distance from the central processor.

[0090] In some embodiments, the hot data cache layer includes a first cache layer, the first common cache layer includes a second cache layer, the second common cache layer includes a third cache layer and a fourth cache layer; and the prefetch lookup module 30 can include:

[0091] The first hot lookup submodule is configured to find the cache data from the first cache layer if the data hotness type is hot data.

[0092] The second hot lookup submodule is configured to find the cache data from the hot data area in the second cache layer if the cache data is not found from the first cache layer.

[0093] The third hot lookup submodule is configured to find the cache data from the third cache layer if the cache data is not found from the hot data area in the second cache layer.

[0094] The fourth hot lookup submodule is configured to find the cache data from the fourth cache layer if the cache data is not found from the third cache layer; and send a start signal to the memory lookup module 40 if the cache data is not found from the fourth cache layer.

[0095] The first cold lookup submodule is configured to find the cache data from the cold data area in the second cache layer if the data hotness type is cold data.

[0096] The second cold lookup submodule is configured to find the cache data from the third cache layer if the cache data is not found from the cold data area in the second cache layer.

[0097] The third cold lookup submodule is configured to find the cache data from the fourth cache layer if the cache data is not found from the third cache layer; and send a start signal to the memory lookup module 40 if the cache data is not found from the fourth cache layer.

[0098] In some embodiments, the apparatus can further include:

[0099] The strategy determining module is configured to determine a respective prefetch strategy of each memory data according to a data hotness type of each memory data in the memory, wherein the prefetch strategy comprises a cold data prefetch strategy and a hot data prefetch strategy, and a prefetch trigger condition of the hot data prefetch strategy is lower than a prefetch trigger condition of the cold data prefetch strategy, and / or a prefetch window of the hot data prefetch strategy is greater than a prefetch window of the cold data prefetch strategy.

[0100] The prefetch module is configured to store, according to the prefetch strategy, the memory data triggering the respective prefetch trigger condition into a corresponding preset cache area.

[0101] In some embodiments, the detection module 20 can be specifically configured to determine the data hotness type according to a data hotness value flag bit of the access address in the preset memory management mapping table, wherein the preset memory management mapping table comprises respective address information and respective data hotness value flag bits.

[0102] In some embodiments, the apparatus can further comprise:

[0103] The monitoring module is configured to monitor an access frequency of the central processing unit to each historical access address.

[0104] The hotness determining module is configured to determine a latest data hotness value flag bit of each historical access address according to the access frequency.

[0105] The flag updating module is configured to update the data hotness value flag bit of the corresponding address information in the preset memory management mapping table according to the latest data hotness value flag bit.

[0106] In some embodiments, the apparatus can further comprise:

[0107] The data determining module is configured to determine the key hotspot data according to the access frequency.

[0108] The locking module is configured to store and lock the key hotspot data into each cache layer in the preset cache area corresponding to the hot data.

[0109] In the embodiment, the preset cache area corresponding to the cold data and the hot data is set, the cache is partitioned according to the data hotness, the cache resources are reasonably allocated, the cost is reduced, the efficiency and speed of memory access are improved, the more fine consistency control is realized through the setting of the hot data cache layer and the hot data area with smaller granularity, the cache hit rate and system performance are improved, the cache data corresponding to the access address is found from the target cache area through the prefetch finding module 30, the required data is found in the preset cache area according to the data hotness, and the speed of memory access is improved.

[0110] Corresponding to the above method embodiments, the embodiments of the present application also provide a cache management device for memory access. The cache management device for memory access described below can be mutually corresponding with reference to the cache management method for memory access described above.

[0111] Please refer to Figure 6 , Figure 6 A structure diagram of a cache management device for memory access provided by the embodiments of the present application. The device can include:

[0112] A memory D1 for storing a computer program;

[0113] A processor D2 for implementing the steps of the cache management method for memory access provided by the above method embodiments when executing the computer program.

[0114] Among them, the cache management device for memory access provided by the embodiments of the present application can be a CPU chip or a memory management unit in the CPU chip.

[0115] Corresponding to the above method embodiments, the embodiments of the present application also provide a computer program product. The computer program product described below can be mutually corresponding with reference to the cache management method for memory access described above.

[0116] A computer program product, including a computer program / instruction, which implements the steps of the cache management method for memory access provided by the above method embodiments when executed by a processor.

[0117] Corresponding to the above method embodiments, the embodiments of the present application also provide a computer readable storage medium. The computer readable storage medium described below can be mutually corresponding with reference to the cache management method for memory access described above.

[0118] A computer readable storage medium, and the computer program is stored on the readable storage medium, and the computer program is executed by a processor to implement the steps of the cache management method for memory access of the above method embodiments.

[0119] The computer readable storage medium can be a U disk, a mobile hard disk, a read-only memory (Read-Only Memory, ROM), a random access memory (Random Access Memory, RAM), a magnetic disk or an optical disk, and various readable storage media that can store program codes.

[0120] The various embodiments described in the specification are presented for purposes of illustration and description. Each of the embodiments highlight a different aspect of the application. The embodiments are not mutually exclusive, and aspects of each embodiment can be combined with aspects of other embodiments. The embodiments disclosed herein are not exhaustive of the ways in which the application can be practiced. The present devices, apparatus, computer program products, and computer-readable storage media disclosed by the embodiments correspond to the methods disclosed by the embodiments, and are described more simply.

[0121] The memory access cache management method, device, apparatus, and storage medium provided by the application are described in detail above. The principles and implementation manners of the application are described by applying specific examples in this paper. The above description of the embodiments is only used to help understand the method of the application and its core idea. It should be pointed out that for ordinary skilled persons in the technical field, without departing from the principles of the application, the application can be improved and modified in several ways, and these improvements and modifications also fall within the protection scope of the application.

Claims

1. A cache management method of memory access, characterized by, The method comprises the following steps: acquiring a data read-write message of a central processing unit; detecting a data hotness type of an access address of the data read-write message; wherein the data hotness type comprises cold data and hot data; finding cache data corresponding to the access address from a target cache area; wherein the target cache area is a preset cache area corresponding to the data hotness type, the preset cache area corresponding to the hot data comprises a hot data cache layer, a hot data area in a first common cache layer, and a second common cache layer, the preset cache area corresponding to the cold data comprises a cold data area in the first common cache layer and the second common cache layer, the granularity of the hot data cache layer and the hot data area is smaller than the granularity of the cold data area and the second common cache layer, and the distance between the hot data cache layer and the central processing unit is smaller than the distance between the first common cache layer and the central processing unit, which is smaller than the distance between the second common cache layer and the central processing unit; if the cache data is not found in the target cache area, sending a corresponding read-write request to a memory to find memory data corresponding to the access address in the memory.

2. The cache management method of memory access according to claim 1, wherein, The step of finding the cache data corresponding to the access address from the target cache area comprises the following steps: in order from near to far from the central processing unit, sequentially finding the cache data corresponding to the access address from each cache layer in the target cache area.

3. The cache management method of memory access according to claim 2, wherein, The hot data cache layer comprises a first cache layer, the first common cache layer comprises a second cache layer, the second common cache layer comprises a third cache layer and a fourth cache layer; and the step of sequentially finding the cache data corresponding to the access address from each cache layer in the target cache area in order from near to far from the central processing unit comprises the following steps: if the data hotness type is the hot data, finding the cache data from the first cache layer; if the cache data is not found in the first cache layer, finding the cache data from a hot data area in the second cache layer; if the cache data is not found in the hot data area in the second cache layer, finding the cache data from the third cache layer; if the cache data is not found in the third cache layer, finding the cache data from the fourth cache layer; if the cache data is not found in the fourth cache layer, performing the step of sending a corresponding read-write request to the memory to find memory data corresponding to the access address in the memory; if the data hotness type is the cold data, finding the cache data from a cold data area in the second cache layer; if the cache data is not found in the cold data area in the second cache layer, finding the cache data from the third cache layer; if the cache data is not found in the third cache layer, finding the cache data from the fourth cache layer; if the cache data is not found in the fourth cache layer, performing the step of sending a corresponding read-write request to the memory to find memory data corresponding to the access address in the memory.

4. The cache management method of memory access according to claim 1, wherein, The method further comprises the following steps: According to the data hotness type of each memory data in the memory, determine the respective prefetch strategy of each memory data; wherein, the prefetch strategy includes cold data prefetch strategy and hot data prefetch strategy; the prefetch trigger condition of the hot data prefetch strategy is lower than the prefetch trigger condition of the cold data prefetch strategy, and / or the prefetch window of the hot data prefetch strategy is greater than the prefetch window of the cold data prefetch strategy; According to the prefetch strategy, the memory data triggering the corresponding prefetch trigger condition is stored in the corresponding preset cache area.

5. The cache management method of memory access according to any one of claims 1 to 4, characterized in that, The data hotness type of the access address of the data read-write message is detected, including: According to the data hotness value flag bit of the access address in the preset memory management mapping table, determine the data hotness type; wherein, the preset memory management mapping table includes each address information and the respective data hotness value flag bit.

6. The cache management method of memory access according to claim 5, wherein, Also includes: Monitoring the access frequency of the central processing unit to each historical access address; According to the access frequency, determine the latest data hotness value flag bit of each historical access address; According to the latest data hotness value flag bit, update the data hotness value flag bit of the corresponding address information in the preset memory management mapping table.

7. The cache management method of memory access according to claim 6, wherein, Also includes: According to the access frequency, determine the key hot data; The key hot data is distributed to each cache layer in the hot data corresponding preset cache area for storage and locking.

8. A cache management apparatus of memory access, characterized by, Including: An acquisition module is configured to acquire a data read-write message of a central processing unit; A detection module is configured to detect a data hotness type of an access address of the data read-write message; wherein, the data hotness type includes cold data and hot data; A prefetch lookup module is configured to find cache data corresponding to the access address from a target cache area; wherein, the target cache area is a preset cache area corresponding to the data hotness type, the preset cache area corresponding to the hot data includes a hot data cache layer, a hot data area in a first common cache layer, and a second common cache layer, the preset cache area corresponding to the cold data includes a cold data area in the first common cache layer and the second common cache layer, the granularity of the hot data cache layer and the hot data area is smaller than the granularity of the cold data area and the second common cache layer; the distance between the hot data cache layer and the central processing unit is smaller than the distance between the first common cache layer and the central processing unit, which is smaller than the distance between the second common cache layer and the central processing unit; A memory lookup module is configured to send a corresponding read-write request to a memory to find memory data corresponding to the access address from the memory if the cache data is not found in the target cache area.

9. A cache management device for memory access, characterized by, Including: A memory is configured to store a computer program; A processor is configured to execute the computer program to implement the steps of the cache management method for memory access according to any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that, The computer readable storage medium stores a computer program, and the computer program is executed by the processor to implement the steps of the cache management method for memory access according to any one of claims 1 to 7.

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