Data transmission method and device based on enhanced serial peripheral interface, equipment and medium

Abstract

The invention discloses a data transmission method and device based on an enhanced serial peripheral interface, equipment and a medium, relates to the technical field of data transmission, and is applied to a target functional component. The target functional component is a functional component which is determined from a first functional component, a second functional component, a third functional component and a fourth functional component according to the type of the to-be-transmitted data and is used for executing a data transmission task, and writing first data carried by a write request sent by a preset host into a local first preset cache, generating a first interrupt signal to the target processor, so that the target processor writes the data in the first preset cache into the substrate management controller; and receiving second data sent by the substrate management controller by using a local second preset cache, and sending the target message to the preset host, so as to respond to a read request sent by the preset host based on the target message, and send the second data in the second preset cache to the preset host. And transmission of special information between the host and the baseboard management controller is realized.

Description

Technical Field

[0001] The present invention relates to the technical field of data transmission, and in particular to a data transmission method, device, equipment and medium based on an enhanced serial peripheral interface. Background Art

[0002] Currently, the eSPI (Enhanced Serial Peripheral Interface) bus is mainly used as a dedicated interface between low-speed peripherals and the host. The eSPI bus borrows and reuses the electrical clock specification of the SPI (Serial Peripheral Interface) bus, but uses a new definition at the protocol layer. In addition to being fully compatible with the role and function of the LPC (Low Pin Count) bus, the eSPI bus also converts the SMBUS (System Management Bus) (out of band) and the GPIO (General-Purpose Input / Output) (Sideband) of OOB (out of band) to in-band information that can be transmitted on the eSPI bus. In addition, it can also share cache with the chipset in real time.

[0003] However, the related art only implements the functions of the eSPI protocol, and does not extend the transmission of some dedicated information between the host and the baseboard management controller.

[0004] In summary, how to expand the functionality of the eSPI protocol to enable the transmission of some dedicated information between the host and the baseboard management controller is a problem that needs to be solved. Summary of the invention

[0005] In view of this, the purpose of the present invention is to provide a data transmission method, device, equipment and medium based on an enhanced serial peripheral interface, which can expand the function of the eSPI protocol to realize the transmission of some special information between the host and the baseboard management controller. The specific scheme is as follows:

[0006] In a first aspect, the present application discloses a data transmission method based on an enhanced serial peripheral interface, which is applied to a target functional component, where the target functional component is a functional component for performing a data transmission task determined from a first functional component, a second functional component, a third functional component, and a fourth functional component according to the type of data to be transmitted, and the method comprises:

[0007] When a write request sent by a preset host is obtained, first data carried in the write request is written into a local first preset cache, and a first interrupt signal is generated to a target processor so that the target processor writes the data in the first preset cache into a baseboard management controller;

[0008] The second data sent by the baseboard management controller is received by using the local second preset cache, and a target message is sent to the preset host, so as to respond to a read request sent by the preset host based on the target message and send the second data in the second preset cache to the preset host.

[0009] Optionally, determining a functional component for performing a data transmission task from the first functional component, the second functional component, the third functional component, and the fourth functional component according to the type of data to be transmitted includes:

[0010] If the data to be transmitted is a command and data corresponding to the system management software, determining the first functional component as a functional component for performing a data transmission task;

[0011] If the total amount of data to be transmitted is greater than a preset threshold, determining the second functional component as a functional component for performing the data transmission task;

[0012] If the data to be transmitted is preset information data, the third functional component is determined as a functional component for performing the data transmission task;

[0013] If the data to be transmitted is interaction data corresponding to the preset host and the external device, the fourth functional component is determined as a functional component for executing the data transmission task.

[0014] Optionally, if the target functional component is the first functional component, the first preset cache is the first register, and the second preset cache is the second register;

[0015] Accordingly, writing the first data carried by the write request into a local first preset cache, and generating a first interrupt signal to the target processor so that the target processor writes the data in the first preset cache into the baseboard management controller, including:

[0016] Writing the first data carried by the write request into the first register;

[0017] Setting the level state of the first flag signal corresponding to the first register to a high level to generate a first interrupt signal to the target processor so that the target processor writes the first data stored in the first register to the baseboard management controller;

[0018] Correspondingly, using the local second preset cache to receive the second data sent by the baseboard management controller, and sending a target message to the preset host, so as to respond to the read request sent by the preset host based on the target message, and sending the second data in the second preset cache to the preset host, including:

[0019] The second register is used to receive the second data sent by the baseboard management controller, and the level state of the second flag signal corresponding to the second register is set to a high level, so as to respond to the read request sent by the preset host based on the high level signal and send the second data in the second register to the preset host.

[0020] Optionally, if the target functional component is the second functional component, the first preset cache is a first random access memory, and the second preset cache is a second random access memory;

[0021] Accordingly, writing the first data carried by the write request into a local first preset cache, and generating a first interrupt signal to the target processor so that the target processor writes the data in the first preset cache into the baseboard management controller, including:

[0022] Writing the first data carried by the write request to the first position in the first random access memory according to the current first write pointer, and performing an increment operation on the current first write pointer to update the current first write pointer;

[0023] When the first data is written, a first interrupt signal is generated to the target processor, so that the target processor generates a read enable signal and writes the data in the first random access memory to the baseboard management controller;

[0024] Correspondingly, using the local second preset cache to receive the second data sent by the baseboard management controller, and sending a target message to the preset host, so as to respond to the read request sent by the preset host based on the target message, and sending the second data in the second preset cache to the preset host, including:

[0025] Receive second data sent by the baseboard management controller using a second position in the second random access memory according to the current second write pointer;

[0026] After the second data is received, a target message is sent to the preset host so that the preset host generates a read enable signal and reads the second data from the second random access memory.

[0027] Optionally, if the target functional component is the third functional component, the first preset cache is any first data register in the data register set, and the second preset cache is any second data register in the data register set;

[0028] Accordingly, writing the first data carried by the write request into a local first preset cache, and generating a first interrupt signal to the target processor so that the target processor writes the data in the first preset cache into the baseboard management controller, including:

[0029] Writing the first data carried by the write request into the first data register, and setting the flag bit corresponding to the first data register in the preset state register to the target value; wherein the preset state register is used to record the storage state of each data register;

[0030] Generate a first interrupt signal to a target processor so that the target processor reads first data from a corresponding first data register to a baseboard management controller based on a flag bit of a preset status register that is a target value;

[0031] Correspondingly, using the local second preset cache to receive the second data sent by the baseboard management controller, and sending a target message to the preset host, so as to respond to the read request sent by the preset host based on the target message, and sending the second data in the second preset cache to the preset host, including:

[0032] Using the second data register to receive the second data sent by the baseboard management controller, and setting the flag bit corresponding to the second data register in the preset status register to the target value;

[0033] A target message is sent to the preset host so that the preset host sends a read request based on the target message to read the second data from the corresponding second data register based on the flag bit of the preset status register that is the target value.

[0034] Optionally, if the target functional component is the fourth functional component, the data transmission method based on the enhanced serial peripheral interface of the present application further includes:

[0035] A target external device interacting with a preset host is determined based on a preset state machine, so that first data is forwarded to the target external device through a baseboard management controller, and second data sent by the target external device is received through the baseboard management controller.

[0036] Optionally, the preset state machine includes a first state for characterizing that the fourth functional component is in an idle state, a second state for characterizing that the fourth functional component is in a state to be unlocked, a third state for characterizing that the fourth functional component is in a state to select an external device, and a fourth state for characterizing that the fourth functional component is in a state to determine an external device;

[0037] Accordingly, determining a target external device to interact with a preset host based on a preset state machine includes:

[0038] When the signal input by the preset host is the first preset signal, the preset state machine is controlled to enter the second state from the first state;

[0039] When the signal input by the preset host is the second preset signal, the preset state machine is controlled to enter the third state from the second state;

[0040] When the signal input by the preset host is the third preset signal, the preset state machine is controlled to enter the fourth state from the third state;

[0041] The device number input by the preset host is obtained to determine the external device corresponding to the device number as the target external device for interacting with the preset host.

[0042] In a second aspect, the present application discloses a data transmission device based on an enhanced serial peripheral interface, which is applied to a target functional component, where the target functional component is a functional component for performing a data transmission task determined from a first functional component, a second functional component, a third functional component, and a fourth functional component according to the type of data to be transmitted, and the device includes:

[0043] A data writing module, configured to, when a write request sent by a preset host is obtained, write first data carried in the write request into a local first preset cache, and generate a first interrupt signal to a target processor, so that the target processor writes the data in the first preset cache into a baseboard management controller;

[0044] A data reading module, configured to receive second data sent by the baseboard management controller using a local second preset cache, and send a target message to the preset host, so as to respond to a read request sent by the preset host based on the target message, and send the second data in the second preset cache to the preset host;

[0045] Among them, the first functional component is a functional component set based on the keyboard controller interface, the second functional component is a functional component set based on the IPMI block transmission interface, the third functional component is a functional component set based on the mailbox message, and the fourth functional component is a functional component set based on the input and output interface.

[0046] In a third aspect, the present application discloses an electronic device, comprising:

[0047] Memory, used to store computer programs;

[0048] The processor is used to execute a computer program to implement the steps of the aforementioned disclosed data transmission method based on the enhanced serial peripheral interface.

[0049] In a fourth aspect, the present application discloses a computer-readable storage medium for storing a computer program; wherein, when the computer program is executed by a processor, the steps of the aforementioned disclosed data transmission method based on an enhanced serial peripheral interface are implemented.

[0050] It can be seen that the present application discloses a data transmission method based on an enhanced serial peripheral interface applied to a target functional component, wherein the target functional component is a functional component for performing a data transmission task determined from a first functional component, a second functional component, a third functional component and a fourth functional component according to the type of data to be transmitted, and the method includes: when a write request sent by a preset host is obtained, the first data carried by the write request is written into a local first preset cache, and a first interrupt signal is generated to a target processor so that the target processor writes the data in the first preset cache to a baseboard management controller; the second data sent by the baseboard management controller is received by using a local second preset cache, and a target message is sent to the preset host so as to respond to a read request sent by the preset host based on the target message, and the second data in the second preset cache is sent to the preset host; wherein the first functional component is a functional component set based on a keyboard controller interface, the second functional component is a functional component set based on an IPMI block transfer interface, the third functional component is a functional component set based on a mailbox message, and the fourth functional component is a functional component set based on an input / output interface.

[0051] Beneficial effects: The present application further expands the functions of the eSPI protocol, and specifically sets four functional components, the first functional component is a functional component set based on the keyboard controller interface, the second functional component is a functional component set based on the IPMI block transmission interface, the third functional component is a functional component set based on the mailbox message, and the fourth functional component is a functional component set based on the input and output interface. When data transmission is required, it is first necessary to determine the target functional component for performing the data transmission task from the first functional component, the second functional component, the third functional component and the fourth functional component according to the type of data to be transmitted. When the target functional component obtains a write request sent by the preset host, the first data carried by the write request is written into the local first preset cache, and a first interrupt signal is generated to the target processor, so that the target processor writes the data in the first preset cache to the baseboard management controller, thereby realizing the host write operation. Further, the target functional component uses the local second preset cache to receive the second data sent by the baseboard management controller, and sends a target message to the preset host, so as to respond to the read request sent by the preset host based on the target message, and send the second data in the second preset cache to the preset host, thereby realizing the host read operation. The above solution realizes the transmission of some special information data between the host and the baseboard management controller, and increases the function of the baseboard management controller. BRIEF DESCRIPTION OF THE DRAWINGS

[0052] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without paying creative work.

[0053] Figure 1 A flow chart of a data transmission method based on an enhanced serial peripheral interface disclosed in this application;

[0054] Figure 2 A system architecture diagram of a data transmission method based on an enhanced serial peripheral interface disclosed in the present application;

[0055] Figure 3 A schematic diagram of state changes of a state machine disclosed in this application;

[0056] Figure 4 A schematic diagram of the structure of a data transmission device based on an enhanced serial peripheral interface disclosed in this application;

[0057] Figure 5 This is a structural diagram of an electronic device disclosed in this application. DETAILED DESCRIPTION

[0058] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present invention.

[0059] Currently, the eSPI bus is mainly used as a dedicated interface between low-speed peripherals and the host. However, the related art only implements the functions of the eSPI protocol, and does not extend it for the transmission of some dedicated information between the host and the baseboard management controller. To this end, the embodiment of the present application discloses a data transmission method, device, equipment and medium based on an enhanced serial peripheral interface, which can extend the functions of the eSPI protocol to realize the transmission of some dedicated information between the host and the baseboard management controller.

[0060] See also Figure 1 As shown, the embodiment of the present application discloses a data transmission method based on an enhanced serial peripheral interface, which is applied to a target functional component, where the target functional component is a functional component for performing a data transmission task determined from a first functional component, a second functional component, a third functional component, and a fourth functional component according to the type of data to be transmitted. The method includes:

[0061] Step S11: when a write request sent by a preset host is obtained, first data carried in the write request is written into a local first preset cache, and a first interrupt signal is generated to a target processor so that the target processor writes the data in the first preset cache into the baseboard management controller.

[0062] In this embodiment, the function of the eSPI protocol is further expanded, and four functional components are specifically set. The first functional component is a functional component set based on the keyboard controller interface, the second functional component is a functional component set based on the IPMI (Intelligent Platform Management Interface) block transmission interface, the third functional component is a functional component set based on the mailbox message, and the fourth functional component is a functional component set based on the input and output interface. When data transmission is required, it is first necessary to determine the target functional component for executing the data transmission task from the first functional component, the second functional component, the third functional component and the fourth functional component according to the type of data to be transmitted.

[0063] Specifically, when the target functional component obtains a write request sent by a preset host, the first data carried by the write request is written into a local first preset cache, and a first interrupt signal is generated to the target processor, so that the target processor writes the data in the first preset cache to the baseboard management controller, thereby realizing the host write operation.

[0064] In a specific implementation, the above-mentioned determining the functional component for executing the data transmission task from the first functional component, the second functional component, the third functional component and the fourth functional component according to the type of data to be transmitted includes: if the data to be transmitted is a command and data corresponding to the system management software, the first functional component is determined as the functional component for executing the data transmission task; if the total amount of the data to be transmitted is greater than a preset threshold, the second functional component is determined as the functional component for executing the data transmission task; if the data to be transmitted is preset information data, the third functional component is determined as the functional component for executing the data transmission task; if the data to be transmitted is interactive data corresponding to a preset host and an external device, the fourth functional component is determined as the functional component for executing the data transmission task.

[0065] Specific as Figure 2As shown in the figure, the first functional component is specifically kcs (keyboard controller style interface). Kcs is a communication protocol used to transmit information between BMC and BIOS (Basic Input Output System). The kcs interface is the interface from BMC to system management software (System Management Software, SMS). The kcs interface is mainly used to transmit SMS messages, that is, to transmit commands and data corresponding to system management software. The second functional component is specifically ibt (IPMI block transferinterface, IPMI block transfer interface, IPMI is the intelligent platform management interface), kcs can only transfer 1 byte at a time, which is used for transmission of small data volume, while ibt is mainly used for large-volume data transmission, that is, if the total amount of data to be transmitted is greater than the preset threshold, the second functional component is used to perform the data transmission task; the third functional component is specifically mbox (mailbox, mailbox message), which is mainly used to transmit message information between the host and the baseboard management controller, that is, used to transmit preset information data; the fourth functional component is superio (super input / output), which is mainly used to transmit the preset host and the corresponding interactive data of the external device, that is, to realize the information interaction between the host and the low-speed peripherals, mainly including uart (universal asynchronous receiver and transmitter), gpio (general input and output port), system wake-up controller, mailbox (mailbox), etc. However, the relevant technology only realizes the function of the espi protocol, and has not been expanded, and the functions of kcs, ibt, mbox, superio, etc. are implemented based on LPC (Low PinCount, low pin count), and only a simple read and write design is performed, and no control signal is involved. This application extends the functions of the espi protocol, uses espi to implement functions such as kcs, ibt, mbox, superio, etc., realizes the transmission of some special information between the host and bmc, and increases the functions of bmc.

[0066] Step S12: using the local second preset cache to receive the second data sent by the baseboard management controller, and sending a target message to the preset host, so as to respond to the read request sent by the preset host based on the target message, and send the second data in the second preset cache to the preset host.

[0067] In this embodiment, the target functional component uses the local second preset cache to receive the second data sent by the baseboard management controller, and sends a target message to the preset host, so as to respond to the read request sent by the preset host based on the target message, and send the second data in the second preset cache to the preset host, thereby realizing the host read operation. The above scheme realizes the transmission of some special information data between the host and the baseboard management controller, and increases the function of the baseboard management controller.

[0068] It should be further pointed out that in order to optimize the data transmission mechanism between the host and the baseboard management controller, data compression and decompression algorithms can also be introduced in the target functional component, that is, the data transmitter compresses the data to be transmitted before transmitting it, and correspondingly, the receiving end needs to decompress the data after receiving it, so as to reduce the amount of transmitted data and improve the transmission efficiency. The specific compression algorithm and decompression algorithm are not restricted here. For example, in the host write operation stage, before the host sends the data, it first compresses the data using the selected compression algorithm, and then transmits the data to the BMC after compression. After the BMC receives the compressed data, it uses the corresponding decompression algorithm to restore the data. In this way, the data transmission time can be reduced, the system response speed can be improved, and more data can be transmitted under limited bandwidth.

[0069] In a specific embodiment, if the target functional component is the first functional component, the first preset cache is the first register, and the second preset cache is the second register; accordingly, the first data carried by the write request is written into the local first preset cache, and a first interrupt signal is generated to the target processor, so that the target processor writes the data in the first preset cache to the baseboard management controller, including: writing the first data carried by the write request into the first register; setting the level state of the first flag signal corresponding to the first register to a high level, so as to generate a first interrupt signal to the target processor, so that the target processor writes the first data stored in the first register to the baseboard management controller; accordingly, using the local second preset cache to receive the second data sent by the baseboard management controller, and sending a target message to the preset host, so as to respond to the read request sent by the preset host based on the target message, and send the second data in the second preset cache to the preset host, including: using the second register to receive the second data sent by the baseboard management controller, and setting the level state of the second flag signal corresponding to the second register to a high level, so as to respond to the read request sent by the preset host based on the high level signal, and send the second data in the second register to the preset host.

[0070] That is, in the kcs module, the two preset caches are the first register and the second register, where the first register is specifically the IBR register (Input Buffer Register) and the second register is specifically the OBR register (Output Buffer Register). The IBR register is used to receive data sent by the host for BMC to read, while the OBR register is used to receive data sent by the BMC for the host to read. These two registers each have a flag signal. As long as there is data in the register, the corresponding flag signal is pulled high, and if there is no data, it is pulled low. The IBR register size is 9 bits, of which the highest 1 bit is used to distinguish whether the host sends a command or data, and the other 8 bits are the content of the transmission; while the OBR register is 8 bits, and only transmits data read by the host from the BMC.

[0071] The host write process of the kcs module is as follows: the host is preset to first query whether there is data in the IBR register. Only when there is no data in this register can the host send data or commands, otherwise the host will keep querying. When it is possible to send, the host sends a write request carrying the data and address to be written. The kcs module judges the sent address. If the sent address is a command address, it means that the data transmitted this time is a command, then the data is placed in the lower 8 bits of the IBR register, and its 9th bit is set to 1, indicating that it is a command, and the corresponding first flag signal is pulled high, and a corresponding first interrupt signal is generated and sent to the target processor; the target processor in this embodiment is specifically an ARM (Advanced RISC-Machines) processor. After the ARM processor receives the first interrupt signal, it obtains the data written by the host to the BMC by reading the IBR register; in addition, if the sent address is a data address, then the data is transmitted this time, and the data is directly placed in the lower 8 bits of the KCS IBR register, and its 9th bit is set to 0, indicating that it is data, and the corresponding first flag signal is pulled high, and the first interrupt signal is generated and sent to the ARM processor. After receiving the interrupt, the ARM processor reads the data, and after reading, the flag signal of the IBF register is automatically pulled low.

[0072] The host read process of the kcs module is as follows: the host must first check whether there is data in the OBR register. If there is data, it means that ARM has written the data into the OBR register. Only then can the host perform a read operation. Otherwise, the host cannot initiate a read operation. When there is no data in the OBR register in the kcs module, ARM can write data to this register, that is, use the OBR register to receive the data written by the BMC. When the write is successful, the second flag signal corresponding to this register will be pulled high, indicating that there is data in this register. At this time, the preset host can initiate a read operation, send the address of the OBR register, and read the data in the OBR register. After the data is read, the flag signal of the OBF register is automatically pulled low.

[0073] In a specific embodiment, if the target functional component is the second functional component, the first preset cache is the first random access memory, and the second preset cache is the second random access memory; accordingly, the first data carried by the write request is written into the local first preset cache, and a first interrupt signal is generated to the target processor, so that the target processor writes the data in the first preset cache to the baseboard management controller, including: writing the first data carried by the write request to the first position in the first random access memory according to the current first write pointer, and performing an increment operation on the current first write pointer to update the current first write pointer; when the first data is written, a first interrupt signal is generated to the target processor, so that the target processor generates a read enable signal and writes the data in the first random access memory to the baseboard management controller; accordingly, the second data sent by the baseboard management controller is received by using the local second preset cache, and a target message is sent to the preset host, so that in response to the read request sent by the preset host based on the target message, the second data in the second preset cache is sent to the preset host, including: receiving the second data sent by the baseboard management controller by using the second position in the second random access memory according to the current second write pointer; after the second data is received, a target message is sent to the preset host, so that the preset host generates a read enable signal and reads the second data from the second random access memory.

[0074] That is, the kcs module has two RAM (Random Access Memory) cache spaces, namely host2bmc buffer (i.e. the first random access memory) and bmc2host buffer (i.e. the second random access memory), and the size of each is 256 bytes. When the host intends to perform a write operation, the host sends a write enable and write data. The kcs module stores the data in the corresponding first position in the host2bmc buffer according to the current position of the first write pointer, and at the same time increases the corresponding current first write pointer by one for the next write operation. When the host has written all the data to be transmitted, the kcs module will generate a first interrupt signal to the target processor (i.e. ARM). After receiving the interrupt signal, ARM will read the data in the host2bmc buffer, generate a read enable for reading, and increase the read pointer by one for each read until all the data are read away, and then all pointers are cleared. The host's read operation is the same. First, ARM writes the corresponding data to the bmc2host buffer. When the data is written, the kcs module notifies the host of the information. Then the host initiates a read operation, generates a read enable signal, and reads the data in the bmc2host buffer. Each time one is read, the corresponding read pointer is increased by one. After all are read, the pointer is cleared.

[0075] In a specific embodiment, if the target functional component is the third functional component, the first preset cache is any first data register in the data register set, and the second preset cache is any second data register in the data register set; accordingly, the first data carried by the write request is written into the local first preset cache, and a first interrupt signal is generated to the target processor so that the target processor writes the data in the first preset cache to the baseboard management controller, including: writing the first data carried by the write request into the first data register, and setting the flag bit corresponding to the first data register in the preset status register to the target value; wherein the preset status register is used to record the storage status of each data register; generating a first interrupt signal to the target processor so that the target processor can write the data in the first preset cache to the baseboard management controller based on the preset status register. The flag bit in the status register with the target value reads the first data from the corresponding first data register to the baseboard management controller; accordingly, the local second preset cache is used to receive the second data sent by the baseboard management controller, and a target message is sent to the preset host, so as to respond to the read request sent by the preset host based on the target message, and send the second data in the second preset cache to the preset host, including: using the second data register to receive the second data sent by the baseboard management controller, and setting the flag bit corresponding to the second data register in the preset status register to the target value; sending the target message to the preset host so that the preset host sends a read request based on the target message to read the second data from the corresponding second data register based on the flag bit in the preset status register with the target value.

[0076] It should be pointed out that the mbox module has 32 data registers, each of which can cache 8 bits of data. At the same time, the mbox module has 4 status registers, each of which is 8 bits, totaling 32 bits, so that each 1-bit status register corresponds to a data register. When the host performs a write operation, the host writes the first data carried by the write request into the corresponding first data register, and sets the flag bit corresponding to the first data register in the preset status register to the target value. After receiving the first data, the mbox module generates an interrupt signal to the target processor ARM. After receiving the interrupt signal, ARM reads the preset status register to check the corresponding state change, finds the data register corresponding to this state register according to the change of the state register, and then reads the data away, and finally clears the interrupt. The mbox module mainly implements the data cache on the hardware, as well as the correspondence between the data register and the status register. The process of the host read operation is the same as that of the write operation. First, ARM writes the data into the second data register of the mbox module, and the corresponding status register is set high. The mbox module notifies the host that it can read the data, and then the host reads the status register first, reads the data from the corresponding second data register according to the status of the status register, and finally clears the interrupt.

[0077] In a specific embodiment, if the target functional component is the fourth functional component, the data transmission method based on the enhanced serial peripheral interface of the present application also includes: determining the target external device to interact with the preset host based on a preset state machine, so as to forward the first data to the target external device through the baseboard management controller, and receive the second data sent by the target external device through the baseboard management controller.

[0078] That is, the superio module mainly implements the function of parsing logical devices through the state machine. Specifically, it is necessary to determine the currently selected target external device to interact with the preset host based on the preset state machine to realize data transmission between the baseboard management controller and the target external device.

[0079] Specifically, the preset state machine includes a first state for characterizing that the fourth functional component is idle, a second state for characterizing that the fourth functional component is to be unlocked, a third state for characterizing that the fourth functional component is to be selected as an external device, and a fourth state for characterizing that the fourth functional component is to determine an external device; accordingly, determining the target external device for interacting with the preset host based on the preset state machine includes: when the signal input by the preset host is a first preset signal, controlling the preset state machine to enter the second state from the first state; when the signal input by the preset host is a second preset signal, controlling the preset state machine to enter the third state from the second state; when the signal input by the preset host is a third preset signal, controlling the preset state machine to enter the fourth state from the third state; obtaining the device number input by the preset host to determine the external device corresponding to the device number as the target external device for interacting with the preset host.

[0080] That is, if Figure 3As shown, the preset state machine in the superio module mainly includes four states, namely the first state SIOR_IDLE, the second state SIOR_UNLOCK, the third state SIOR_X, and the fourth state SIOR_LDN. The SIOR_IDLE state is the idle state. When no operation is performed, this module is in this state. If the host wants to operate any logical device under superio, first write the first preset signal 0xA5, then the state machine will enter the SIOR_UNLOCK state from the idle state, which is equivalent to entering the password stage, that is, the unlocking state. To continue, you need to unlock , in this state, continue to write the second preset signal 0xA5, then the state machine enters the stage of selecting an external logical device from the password stage, that is, enters the SIOR_X state. In this state, the host writes the third preset signal 0x07, then the state machine continues to jump and enters the SIOR_LDN state, which means that the logical device register is selected. This register is the device number of the external logical device (external device for short), which represents which external device the host will select for data transmission next. In this state, the host wants to select which one, and writes the device number of which external device into the register, and then the corresponding register in the selected external device can be operated. When the host operation is completed, send 0xAA directly to exit this state and return to the idle state, and the host can operate the next logical device. Each state in the state machine will remain in the current state as long as the jump condition is not met. Each time the selected logical device is transmitted, it needs to be operated in the SIOR_LDN state.

[0081] It can be seen that the present application further expands the function of the eSPI protocol, and specifically sets four functional components. The first functional component is a functional component set based on the keyboard controller interface, the second functional component is a functional component set based on the IPMI block transmission interface, the third functional component is a functional component set based on the mailbox message, and the fourth functional component is a functional component set based on the input and output interface. When data transmission is required, it is first necessary to determine the target functional component for performing the data transmission task from the first functional component, the second functional component, the third functional component and the fourth functional component according to the type of data to be transmitted. When the target functional component obtains the write request sent by the preset host, the first data carried by the write request is written into the local first preset cache, and a first interrupt signal is generated to the target processor, so that the target processor writes the data in the first preset cache to the baseboard management controller, thereby realizing the host write operation. Further, the target functional component uses the local second preset cache to receive the second data sent by the baseboard management controller, and sends a target message to the preset host, so as to respond to the read request sent by the preset host based on the target message, and send the second data in the second preset cache to the preset host, thereby realizing the host read operation. The above scheme realizes the transmission of some special information data between the host and the baseboard management controller, and increases the function of the baseboard management controller.

[0082] See also Figure 4 As shown, the embodiment of the present application discloses a data transmission device based on an enhanced serial peripheral interface, which is applied to a target functional component, and the target functional component is a functional component for performing a data transmission task determined from a first functional component, a second functional component, a third functional component, and a fourth functional component according to the type of data to be transmitted. The device includes:

[0083] The data writing module 11 is used for, when obtaining a write request sent by a preset host, writing the first data carried in the write request into a local first preset cache, and generating a first interrupt signal to a target processor, so that the target processor writes the data in the first preset cache into the baseboard management controller;

[0084] The data reading module 12 is used to receive the second data sent by the baseboard management controller by using the local second preset cache, and send a target message to the preset host, so as to respond to the read request sent by the preset host based on the target message, and send the second data in the second preset cache to the preset host;

[0085] Among them, the first functional component is a functional component set based on the keyboard controller interface, the second functional component is a functional component set based on the IPMI block transmission interface, the third functional component is a functional component set based on the mailbox message, and the fourth functional component is a functional component set based on the input and output interface.

[0086] It can be seen that the present application further expands the function of the eSPI protocol, and specifically sets four functional components. The first functional component is a functional component set based on the keyboard controller interface, the second functional component is a functional component set based on the IPMI block transmission interface, the third functional component is a functional component set based on the mailbox message, and the fourth functional component is a functional component set based on the input and output interface. When data transmission is required, it is first necessary to determine the target functional component for performing the data transmission task from the first functional component, the second functional component, the third functional component and the fourth functional component according to the type of data to be transmitted. When the target functional component obtains the write request sent by the preset host, the first data carried by the write request is written into the local first preset cache, and a first interrupt signal is generated to the target processor, so that the target processor writes the data in the first preset cache to the baseboard management controller, thereby realizing the host write operation. Further, the target functional component uses the local second preset cache to receive the second data sent by the baseboard management controller, and sends a target message to the preset host, so as to respond to the read request sent by the preset host based on the target message, and send the second data in the second preset cache to the preset host, thereby realizing the host read operation. The above scheme realizes the transmission of some special information data between the host and the baseboard management controller, and increases the function of the baseboard management controller.

[0087] Since the embodiments of the device part correspond to the embodiments of the method part, the embodiments of the device part refer to the embodiments of the method part, which will not be described here. In addition, the invention has the same beneficial effects as the data transmission method based on the enhanced serial peripheral interface mentioned above.

[0088] Figure 5 A schematic diagram of the structure of an electronic device provided in an embodiment of the present application. Specifically, it may include: at least one processor 21, at least one memory 22, a power supply 23, a communication interface 24, an input / output interface 25, and a communication bus 26. Among them, the memory 22 is used to store a computer program, and the computer program is loaded and executed by the processor 21 to implement the relevant steps in the data transmission method based on the enhanced serial peripheral interface performed by the electronic device disclosed in any of the aforementioned embodiments.

[0089] In this embodiment, the power supply 23 is used to provide working voltage for each hardware device on the electronic device 20; the communication interface 24 can create a data transmission channel between the electronic device 20 and the external device, and the communication protocol it follows is any communication protocol that can be applied to the technical solution of the present application, and is not specifically limited here; the input and output interface 25 is used to obtain external input data or output data to the outside world, and its specific interface type can be selected according to specific application needs and is not specifically limited here.

[0090] Among them, the processor 21 may include one or more processing cores, such as a 4-core processor, an 8-core processor, etc. The processor 21 can be implemented in at least one hardware form of DSP (Digital Signal Processing), FPGA (Field-Programmable Gate Array), and PLA (Programmable Logic Array). The processor 21 may also include a main processor and a coprocessor. The main processor is a processor for processing data in the awake state, also known as a CPU (Central Processing Unit); the coprocessor is a low-power processor for processing data in the standby state. In some embodiments, the processor 21 may be integrated with a GPU (Graphics Processing Unit), which is responsible for rendering and drawing the content to be displayed on the display screen. In some embodiments, the processor 21 may also include an AI (Artificial Intelligence) processor, which is used to process computing operations related to machine learning.

[0091] In addition, the memory 22, as a carrier for storing resources, can be a read-only memory, a random access memory, a disk or an optical disk, etc. The resources stored thereon include an operating system 221, a computer program 222 and data 223, etc. The storage method can be temporary storage or permanent storage.

[0092] Among them, the operating system 221 is used to manage and control the hardware devices and computer programs 222 on the electronic device 20, so as to realize the operation and processing of the massive data 223 in the memory 22 by the processor 21, which can be Windows, Unix, Linux, etc. In addition to including a computer program that can be used to complete the data transmission method based on the enhanced serial peripheral interface performed by the electronic device 20 disclosed in any of the aforementioned embodiments, the computer program 222 can also further include a computer program that can be used to complete other specific tasks. In addition to data transmitted from an external device received by the electronic device, the data 223 can also include data collected by its own input and output interface 25, etc.

[0093] Furthermore, an embodiment of the present application also discloses a computer-readable storage medium, in which a computer program is stored. When the computer program is loaded and executed by a processor, the steps of the data transmission method based on the enhanced serial peripheral interface disclosed in any of the aforementioned embodiments are implemented.

[0094] Furthermore, an embodiment of the present application also discloses a computer program product, including a computer program / instruction, which, when executed by a processor, implements the steps of the data transmission method based on an enhanced serial peripheral interface disclosed in any of the aforementioned embodiments.

[0095] In this specification, each embodiment is described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the embodiments can be referred to each other. For the device disclosed in the embodiment, since it corresponds to the method disclosed in the embodiment, the description is relatively simple, and the relevant parts can be referred to the method part.

[0096] Those skilled in the art may further appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented with electronic hardware, computer software, or a combination of the two. In order to clearly illustrate the interchangeability of hardware and software, the composition and steps of each example have been generally described in terms of function in the above description. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art may use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of this application.

[0097] The steps of the method or algorithm described in conjunction with the embodiments disclosed herein may be implemented directly using hardware, a software module executed by a processor, or a combination of the two. The software module may be placed in a random access memory (RAM), a memory, a read-only memory (ROM), an electrically programmable ROM, an electrically erasable programmable ROM, a register, a hard disk, a removable disk, a compact disc read-only memory (CD-ROM), or any other form of storage medium known in the art.

[0098] Finally, it should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the presence of other identical elements in the process, method, article or device including the elements.

[0099] The above is a detailed introduction to a data transmission method, device, equipment and storage medium based on an enhanced serial peripheral interface provided by the present invention. Specific examples are used in this article to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only used to help understand the method of the present invention and its core idea; at the same time, for a person skilled in the art, according to the idea of ​​the present invention, there will be changes in the specific implementation method and application scope. In summary, the content of this specification should not be understood as a limitation on the present invention.

Claims

1. A data transmission method based on an enhanced serial peripheral interface, characterized in that: Applied to a target functional component, the target functional component being a functional component for performing a data transmission task determined from a first functional component, a second functional component, a third functional component, and a fourth functional component according to a type of data to be transmitted, the method comprising: When a write request sent by a preset host is obtained, first data carried by the write request is written into a local first preset cache, and a first interrupt signal is generated to a target processor so that the target processor writes the data in the first preset cache into a baseboard management controller; Using a local second preset cache to receive the second data sent by the baseboard management controller, and sending a target message to the preset host, so as to respond to a read request sent by the preset host based on the target message, and send the second data in the second preset cache to the preset host; Among them, the first functional component is a functional component set based on the keyboard controller interface, the second functional component is a functional component set based on the IPMI block transfer interface, the third functional component is a functional component set based on the mailbox message, and the fourth functional component is a functional component set based on the input and output interface.

2. The data transmission method based on the enhanced serial peripheral interface according to claim 1, characterized in that: Determining a functional component for performing a data transmission task from the first functional component, the second functional component, the third functional component, and the fourth functional component according to the type of data to be transmitted, including: If the data to be transmitted is a command and data corresponding to the system management software, determining the first functional component as a functional component for performing a data transmission task; If the total amount of data to be transmitted is greater than a preset threshold, determining the second functional component as a functional component for performing a data transmission task; If the data to be transmitted is preset information data, determining the third functional component as a functional component for performing a data transmission task; If the data to be transmitted is interaction data corresponding to the preset host and the external device, the fourth functional component is determined as a functional component for performing a data transmission task.

3. The data transmission method based on enhanced serial peripheral interface according to claim 2, characterized in that: If the target functional component is the first functional component, the first preset cache is a first register, and the second preset cache is a second register; Correspondingly, writing the first data carried by the write request into a local first preset cache and generating a first interrupt signal to a target processor so that the target processor writes the data in the first preset cache into a baseboard management controller includes: Writing the first data carried by the write request into the first register; Setting the level state of the first flag signal corresponding to the first register to a high level to generate a first interrupt signal to a target processor, so that the target processor writes the first data stored in the first register to a baseboard management controller; Correspondingly, the using of the local second preset cache to receive the second data sent by the baseboard management controller, and sending a target message to the preset host, so as to respond to the read request sent by the preset host based on the target message, and sending the second data in the second preset cache to the preset host, includes: The second register is used to receive the second data sent by the baseboard management controller, and the level state of the second flag signal corresponding to the second register is set to a high level, so as to respond to the read request sent by the preset host based on the high level signal, and send the second data in the second register to the preset host.

4. The data transmission method based on enhanced serial peripheral interface according to claim 2, characterized in that: If the target functional component is the second functional component, the first preset cache is a first random access memory, and the second preset cache is a second random access memory; Correspondingly, writing the first data carried by the write request into a local first preset cache and generating a first interrupt signal to a target processor so that the target processor writes the data in the first preset cache into a baseboard management controller includes: Writing the first data carried by the write request to a first position in the first random access memory according to the current first write pointer, and performing an increment operation on the current first write pointer to update the current first write pointer; When the first data is written, a first interrupt signal is generated to a target processor, so that the target processor generates a read enable signal and writes the data in the first random access memory to a baseboard management controller; Correspondingly, the using of the local second preset cache to receive the second data sent by the baseboard management controller, and sending a target message to the preset host, so as to respond to the read request sent by the preset host based on the target message, and sending the second data in the second preset cache to the preset host, includes: Receive second data sent by the baseboard management controller using a second position in the second random access memory according to the current second write pointer; After the second data is received, a target message is sent to the preset host so that the preset host generates a read enable signal and reads the second data from the second random access memory.

5. The data transmission method based on enhanced serial peripheral interface according to claim 2, characterized in that: If the target functional component is the third functional component, the first preset cache is any first data register in the data register set, and the second preset cache is any second data register in the data register set; Correspondingly, writing the first data carried by the write request into a local first preset cache and generating a first interrupt signal to a target processor so that the target processor writes the data in the first preset cache into a baseboard management controller includes: Writing the first data carried by the write request into the first data register, and setting the flag bit corresponding to the first data register in the preset state register to a target value; wherein the preset state register is used to record the storage state of each data register; Generate a first interrupt signal to a target processor, so that the target processor reads the first data from the corresponding first data register to a baseboard management controller based on a flag bit of the preset status register that is the target value; Correspondingly, the using of the local second preset cache to receive the second data sent by the baseboard management controller, and sending a target message to the preset host, so as to respond to the read request sent by the preset host based on the target message, and sending the second data in the second preset cache to the preset host, includes: Using the second data register to receive the second data sent by the baseboard management controller, and setting the flag bit corresponding to the second data register in the preset status register to the target value; A target message is sent to the preset host so that the preset host sends a read request based on the target message to read the second data from the corresponding second data register based on the flag bit of the preset status register that is the target value.

6. The data transmission method based on enhanced serial peripheral interface according to claim 2, characterized in that: If the target functional component is the fourth functional component, the method further includes: A target external device interacting with the preset host is determined based on a preset state machine, so that the first data is forwarded to the target external device through the baseboard management controller, and the second data sent by the target external device is received through the baseboard management controller.

7. The data transmission method based on enhanced serial peripheral interface according to claim 6, characterized in that: The preset state machine includes a first state for representing that the fourth functional component is in an idle state, a second state for representing that the fourth functional component is in a state to be unlocked, a third state for representing that the fourth functional component is in a state to select an external device, and a fourth state for representing that the fourth functional component is in a state to determine an external device; Accordingly, the step of determining a target external device to interact with the preset host based on a preset state machine includes: When the signal input by the preset host is a first preset signal, controlling the preset state machine to enter the second state from the first state; When the signal input by the preset host is a second preset signal, controlling the preset state machine to enter the third state from the second state; When the signal input by the preset host is a third preset signal, controlling the preset state machine to enter the fourth state from the third state; The device number input by the preset host is obtained to determine the external device corresponding to the device number as the target external device for interacting with the preset host.

8. A data transmission device based on an enhanced serial peripheral interface, characterized in that: Applied to a target functional component, the target functional component being a functional component for performing a data transmission task determined from a first functional component, a second functional component, a third functional component, and a fourth functional component according to a type of data to be transmitted, the device comprising: a data writing module, configured to, when a write request sent by a preset host is obtained, write first data carried in the write request into a local first preset cache, and generate a first interrupt signal to a target processor, so that the target processor writes the data in the first preset cache into a baseboard management controller; a data reading module, configured to receive the second data sent by the baseboard management controller by using a local second preset cache, and send a target message to the preset host, so as to respond to a read request sent by the preset host based on the target message, and send the second data in the second preset cache to the preset host; Among them, the first functional component is a functional component set based on the keyboard controller interface, the second functional component is a functional component set based on the IPMI block transfer interface, the third functional component is a functional component set based on the mailbox message, and the fourth functional component is a functional component set based on the input and output interface.

9. An electronic device, characterized in that: include: Memory, used to store computer programs; A processor, configured to execute the computer program to implement the steps of the data transmission method based on the enhanced serial peripheral interface as claimed in any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that: Used to store computer programs; wherein, when the computer program is executed by a processor, the steps of the data transmission method based on the enhanced serial peripheral interface as described in any one of claims 1 to 7 are implemented.

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