DMA transmission method and device

Abstract

The invention provides a DMA transmission method and device, and the method comprises the steps: obtaining a transmission command through obtaining a DMA command descriptor; wherein the DMA descriptor at least comprises a maximum parallel transmission unit size and a destination address; distributing the transmission command to a target number of DMA transmission units according to the maximum parallel transmission unit size to obtain a plurality of parallel burst transmission commands; wherein the parallel burst transmission command comprises target transmission commands of all DMA transmission units; and executing the parallel burst transmission command. According to the method, a field with the maximum parallel transmission unit size is added in a DMA descriptor, the requirement of a user for data setting or data migration of an address in a specified range is scattered to a plurality of PORT for parallel transmission, the maximum parallel transmission unit size meeting the requirement of a destination address terminal MEM is met, the performance can reach the maximum performance which can be provided by the terminal MEM as much as possible, and the performance of the terminal MEM is improved. And the data transmission efficiency is improved.

Description

Technical Field

[0001] The present invention relates to the technical field of data storage, and in particular to a DMA transmission method and device. Background Art

[0002] There are currently two main ways to access data between MEM (Memory), one is through the central processing unit (CPU), and the other is through direct memory access (DMA). When data is transferred through the CPU, the CPU needs to execute a series of read and write instructions to complete the data movement. Specifically, the CPU first reads data from the source address and then writes the data to the destination address. Although this method is simple, it will take up a lot of CPU resources, causing the CPU to be unable to perform other tasks efficiently, thereby affecting the overall performance of the system. DMA is a more efficient way of data transmission. The DMA controller can transfer data directly between the memory and the peripheral without passing through the CPU. In this way, the CPU only needs to intervene at the beginning and end of the transfer, which greatly reduces the burden on the CPU and improves the parallel processing capability of the system.

[0003] DMA can complete large-scale data transfers without occupying CPU resources, so it has significant efficiency advantages when processing large amounts of data. The DMA controller can operate independently of the CPU and can perform data transfers in the background, thereby improving the parallel processing capabilities of the entire system.

[0004] However, in certain scenarios, traditional DMA devices have insufficient performance. Examples of these scenarios are as follows: In a bus system, the DMA device is connected to PORT0 of the DDRC (Dynamic Random Access Memory Controller) through the bus to read and write data to PORT0. Limited by the bus and interface bandwidth, the data transmission performance of the DMA device and DDRC PORT0 has an upper limit. DDRC generally controls multiple DRAM (Dynamic Random Access Memory) particles and provides multiple PORTs, allowing multiple PORTs to access in parallel. In theory, multiple PORT access can increase bandwidth and improve overall transmission performance. However, if multiple DMA devices are simply used, DMA0 is connected to PORT0, DMA1 is connected to PORT1, and multiple DMAs are used to transmit data to DDRC in parallel, it is very likely that the performance will be worse than that of a single DMA. The reasons are as follows: Although DDRC provides multiple PORTs to increase bandwidth, its internal processing is limited by DRAM particles.

[0005] Specifically, the DDRC address configuration generally maps different address bits to access different CS (ChipSelect), BG (Bank Group), BA (Bank Address), COL (Column Address), and ROW (Row Address). If you need to access different rows, you need to precharge (Precharge) first and then activate (Active). Therefore, the ROW bit is generally placed in the high position of the address. This can avoid the problem of frequent Precharge and Active of DDRC when accessing a DRAM address, which reduces performance.

[0006] If the addresses of the two ports are on the same ROW, DDRC can quickly respond to the two ports. If the addresses of the two ports are not on the same ROW, DDRC cannot quickly respond to the two ports. It can be considered that the maximum address range of the unchanged ROW is the maximum parallel transmission range of the two ports.

[0007] When using a single DMA to transfer data from a single PORT, the address is continuous and serial, and the DDRC will not frequently switch ROWs, causing performance degradation. When using 2DMA from 2 PORTs, the user configures the address of the transfer, and it is difficult to ensure that the addresses of the two PORTs are on the same ROW. Operations that are not on the same ROW will cause frequent precharge and active inside the DDRC, seriously reducing the DMA transmission performance. In similar scenarios, it is difficult for traditional DMA devices to improve transmission performance by increasing the number of devices, and the transmission performance is limited. Summary of the invention

[0008] The present invention provides a DMA transmission method and device, which are used to solve the defect of limited transmission performance in the prior art and achieve improvement of transmission.

[0009] The present invention provides a DMA transmission method, comprising the following steps: Acquire a DMA command descriptor to obtain a transfer command; wherein the DMA descriptor at least includes a maximum parallel transfer unit size and a destination address; Allocating the transfer command to a target number of DMA transfer units according to the maximum parallel transfer unit size to obtain a plurality of parallel burst transfer commands; wherein the parallel burst transfer command includes the target transfer commands of all DMA transfer units; The parallel burst transfer command is executed.

[0010] According to a DMA transmission method provided by the present invention, the transmission command is distributed to a target number of DMA transmission units according to the maximum parallel transmission unit size according to a preset formula; Wherein, the preset formula includes: Where α refers to the number of DMA transfer units, β refers to the target number, δ refers to the δth parallel transfer, DMA_DEST_ADDR(α,β,δ) means that there are β DMA transfer units in total, the destination address of the δth parallel transfer of the αth DMA transfer unit, DEST_ADDR_ALIGNED refers to the base address of the simplified destination address, which satisfies the alignment restriction of the maximum parallel transfer unit size, and MULTI_SIZE refers to the maximum parallel transfer unit size.

[0011] According to a DMA transmission method provided by the present invention, the DMA transmission unit executes the target transmission commands in parallel.

[0012] According to a DMA transmission method provided by the present invention, a target number of DMA transmission units are connected to ports on a target number of buses.

[0013] According to a DMA transmission method provided by the present invention, the parallel burst transmission command is executed, and then the method further comprises: After all parallel burst transfer commands are completed, the completion status is written to the DMA completion status buffer.

[0014] According to a DMA transmission method provided by the present invention, after completing all parallel burst transmission commands, the completion status is written into a DMA completion status buffer area, and then further includes: User gets command completion status based on DMA completion status buffer.

[0015] The present invention also provides a DMA transmission device, comprising the following modules: A command module, used for acquiring a DMA command descriptor to obtain a transfer command; wherein the DMA descriptor at least includes a maximum parallel transfer unit size and a destination address; A control module, configured to distribute the transfer command to a target number of DMA transfer units according to the maximum parallel transfer unit size, to obtain a plurality of parallel burst transfer commands; wherein the parallel burst transfer command includes the target transfer commands of all DMA transfer units; An execution module is used to execute the parallel burst transfer command.

[0016] The present invention also provides an electronic device, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein when the processor executes the program, any one of the above-mentioned DMA transmission methods is implemented.

[0017] The present invention also provides a non-transitory computer-readable storage medium on which a computer program is stored. When the computer program is executed by a processor, the DMA transmission method described above is implemented.

[0018] The present invention also provides a computer program product, comprising a computer program, wherein when the computer program is executed by a processor, the computer program implements any one of the above-mentioned DMA transmission methods.

[0019] The DMA transmission method and device provided by the present invention obtain a transmission command by acquiring a DMA command descriptor; wherein the DMA descriptor includes at least a maximum parallel transmission unit size and a destination address; the transmission command is distributed to a target number of DMA transmission units according to the maximum parallel transmission unit size to obtain multiple parallel burst transmission commands; wherein the parallel burst transmission command includes the target transmission commands of all DMA transmission units; and the parallel burst transmission command is executed. The present invention adds a field of the maximum parallel transmission unit size to the DMA descriptor, and distributes the user's demand for data setting or data movement of a specified range of addresses to multiple PORTs for parallel transmission, and meets the maximum parallel transmission unit size required by the destination address terminal MEM, so that the performance can reach the maximum performance that the terminal MEM can provide as much as possible, thereby increasing data transmission efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] In order to more clearly illustrate the technical solutions in the present invention or the prior art, a brief introduction will be given below to the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0021] Figure 1 It is a flow chart of the DMA transmission method provided by the present invention.

[0022] Figure 2 It is a schematic diagram of an implementation scenario of the DMA transmission method provided by the present invention.

[0023] Figure 3 The diagram is a schematic diagram of executing parallel burst transfer commands according to an embodiment of the DMA transfer method provided by the present invention.

[0024] Figure 4 It is a structural schematic diagram of a DMA transmission device provided by the present invention.

[0025] Figure 5 It is a structural schematic diagram of the electronic device provided by the present invention. DETAILED DESCRIPTION

[0026] In order to make the purpose, technical solution and advantages of the present invention clearer, the technical solution of the present invention will be clearly and completely described below in conjunction with the drawings of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0027] Combine the following Figure 1-Figure 3 Describe the DMA transfer method of the present invention, Figure 1 It is a flow chart of the DMA transmission method provided by the present invention, such as Figure 1 As shown, the method includes the following steps.

[0028] Step 110: Acquire a DMA command descriptor to obtain a transfer command; wherein the DMA descriptor at least includes a maximum parallel transfer unit size and a destination address.

[0029] It should be noted that the DMA referred to in the present invention is Direct Memory Access, which is a technology that allows certain hardware subsystems to directly access system memory without going through a central processing unit (CPU).

[0030] The present invention does not limit the source of the DMA command descriptor obtained in step 110. In a specific embodiment, the central processing unit generates and sends the DMA command descriptor, and writes the DMA command descriptor through the control bus.

[0031] The DMA command descriptor includes at least the maximum parallel transfer unit size and the destination address. In some embodiments, the DMA command descriptor also includes an ID, a source address, a mode, a transfer length, a set data, a set data size, and the like.

[0032] In addition, the setting of the maximum parallel transmission unit size is related to the configuration of the dynamic random access memory controller (DDRC), specifically, the maximum value of the address range of two parallel PORT ports without the time-consuming operation of ROW switching in the DDRC. The present invention adds a maximum parallel transmission unit size in the DMA descriptor, provides more precise control for DMA transmission, and ensures that parallel transmission can achieve the best effect.

[0033] Among them, the dynamic random access memory controller is a hardware or software component used to manage dynamic random access memory (DRAM), responsible for coordinating data read and write operations to ensure efficient use of memory and performance optimization.

[0034] The transfer command refers to the transfer action corresponding to the DMA command descriptor, including the data setting function for the specified address range and the data movement from the source address to the destination address.

[0035] Step 120: Allocate the transfer command to a target number of DMA transfer units according to the maximum parallel transfer unit size to obtain a plurality of parallel burst transfer commands; wherein the parallel burst transfer command includes the target transfer commands of all DMA transfer units.

[0036] It can be understood that the traditional DMA can parse the configured DMA descriptor, and the DMA transmission module can realize the data setting function of the specified address range and the data moving function from the source address to the destination address. After completion, the result is written into the command completion status area, waiting to be read out to determine whether the command corresponding to the DMA descriptor is executed by the DMA device. The present invention does not directly execute the transmission action corresponding to the DMA command descriptor, but decomposes it and executes the decomposed transmission command.

[0037] Specifically, in step 120, after obtaining the DMA descriptor, the field will be parsed, that is, the amount of data for parallel transmission will be divided according to the minimum parallel transmission unit size field in the DMA command descriptor, and the DMA transmission command will be decomposed into parallel operations on multiple DMA transmission units, and the destination address and transmission size of the parallel operation are within the range of the maximum parallel transmission size.

[0038] In other words, in order to ensure that the operated PORT port can achieve the highest parallel performance, the present invention divides the transmission destination address configuration of the DMA transmission unit according to the maximum parallel transmission size, so that the DDRC does not need to perform the time-consuming operation of ROW switching, so that the performance can reach the maximum performance that the terminal MEM can provide as much as possible.

[0039] The aforementioned port (PORT) is used to describe a logical channel in a memory controller or bus interface that allows a hardware device or system component to interact with the memory for reading and writing.

[0040] In addition, the aforementioned "burst" refers to an efficient data transmission mode (Burst). In this mode, data is transmitted in the form of continuous blocks (ie, bursts) rather than individual bytes or words. Burst transmission can significantly improve the efficiency of data transmission because it reduces the number of setups and synchronizations that the bus or interface needs to perform between each transmission.

[0041] Step 130: Execute the parallel burst transfer command.

[0042] In step 130, after obtaining multiple parallel burst transfer commands, the DMA transfer unit performs parallel transfer according to the corresponding parallel burst transfer commands, and after the current parallel burst transfer is completed, the next parallel burst transfer is issued again until all the transfers required by the DMA command corresponding to the DMA command descriptor are completed. In this way, it can be ensured that the data of each parallel transfer is within the maximum parallel transfer unit size, ensuring that the operated PORT can achieve the highest parallel performance.

[0043] It should be emphasized that during the execution process, all parallel burst transfer commands can be allocated at one time and then executed one by one, or execution can be started after the current parallel burst transfer command is obtained, and after the execution is completed, execution is carried out according to the next allocated parallel burst transfer command. The present invention does not impose any restrictions on this.

[0044] The following further describes step 120. In some embodiments, the transfer command is allocated to a target number of DMA transfer units according to the maximum parallel transfer unit size according to a preset formula; Wherein, the preset formula includes: Wherein, α refers to the number of the DMA transfer unit, β refers to the target quantity, that is, the number of DMA transfer units, δ refers to the δth parallel transfer, DMA_DEST_ADDR(α,β,δ) means that there are β DMA transfer units in total, the destination address of the δth parallel transfer of the αth DMA transfer unit, DEST_ADDR_ALIGNED refers to the base address of the simplified destination address, which satisfies the alignment restriction of the maximum parallel transfer unit size, and MULTI_SIZE refers to the maximum parallel transfer unit size.

[0045] Specifically, the configuration division of the transmission destination address of the DMA transmission unit in step 120 can be simplified to a preset formula for calculating the DMA destination address.

[0046] Further, in some embodiments, the DMA transfer unit executes the target transfer commands in parallel.

[0047] Specifically, the implementation scenario of the present invention includes multiple DMA transfer units. During the decomposition process of the transfer command, the destination address configuration is divided for each DMA transfer unit according to the maximum parallel transfer unit size to form a target transfer command for each DMA transfer unit. After all DMA transfer units are allocated with the target transfer command, the current parallel burst transfer command is obtained, and the allocation of the next parallel burst transfer command is repeated in this way.

[0048] Further, based on the above embodiments, in some embodiments, the target number of DMA transfer units are connected to the target number of ports on the bus.

[0049] Specifically, Figure 2 As shown, in the implementation scenario of the present invention, a target number of DMA transmission modules are integrated and connected to a target number of PORTs on the bus, thereby realizing multi-interface parallel transmission of data.

[0050] Among them, bus refers to a group of wires or channels used to transmit data, addresses and control signals in computers and other electronic systems. It is the key infrastructure for communication and data exchange between various components within the system.

[0051] The present invention adds a field - maximum parallel transmission unit size - in the DMA descriptor, distributes the user's demand for data setting or data movement in a specified range of addresses to multiple PORTs for parallel transmission, and meets the maximum parallel transmission unit size required by the destination address terminal MEM, so that the performance can reach the maximum performance that the terminal MEM can provide as much as possible, thereby improving data transmission efficiency.

[0052] Further, executing the parallel burst transfer command, further comprising: After all parallel burst transfer commands are completed, the completion status is written to the DMA completion status buffer.

[0053] Specifically, when all decomposed commands are executed, the completion status is written into the DMA completion status buffer, waiting to be read out for the user to determine whether the command corresponding to the DMA descriptor is executed.

[0054] Further, based on the above embodiment, after all parallel burst transfer commands are completed, the completion status is written into the DMA completion status buffer area, and then the following is further included: User gets command completion status based on DMA completion status buffer.

[0055] Specifically, during the implementation process, the user (CPU, etc.) obtains the command completion status from the DMA completion status buffer through the control bus to complete the required DMA transfer.

[0056] Based on the above embodiments, a specific embodiment is given for a more detailed description. Figure 3As shown, under a certain configuration of the DDRC of this embodiment, the maximum parallel transmission unit size is 128KiB. If the two PORTs of the DDRC receive read and write data that are not in the same 128KiB aligned address range, the DDRC needs to continuously switch ROWs internally to give corresponding responses on the two PORTs respectively and continuously. At this time, the performance of multi-PORT access is not only not improved, but also lower than the performance of single-PORT access. If the address range of the two parallel PORTs can be guaranteed to be within the same 128KiB address range, the DDRC does not need to perform the time-consuming operation of ROW switching, and can quickly give corresponding responses on the two PORTs. At this time, the performance of multi-PORT access is higher than that of single PORT, thereby improving the transmission efficiency.

[0057] In the prior art, if there are two traditional DMAs that require a multi-core CPU to configure, it is difficult to ensure that the two DMAs can write in parallel in the same 128KiB range. If the length of a transmission is greater than 128KiB, there will be more problems and it will be difficult to achieve.

[0058] Based on the DMA transmission method provided by the present invention, if you want to realize the transmission from MEM_A to DDR_A, the source address is 0x40, the destination address is 0x10000040, and the transmission size is 256KiB, then you can directly configure the write in the descriptor to realize parallel writing; specifically, it is allocated to DMA_0, starting from 0x10000040 to 0x1000FFFF, and the transmission size is 65472Bytes, and it is allocated to DMA_1, starting from 0x10010000 to 0x1001FFFF, and the transmission size is 64KiB. These two transmissions can be carried out in parallel. After the current transmission is completed, it is allocated to DMA_0 again. Starting from 0x10020000 to 0x1002FFFF, the transfer size is 64KiB, which is assigned to DMA_1. Starting from 0x10030000 to 0x1003FFFF, the transfer size is 64KiB. After the parallel transfer is completed, it is assigned to DMA_0, starting from 0x10040000 to 0x1004003F, and the transfer size is 64Bytes. After all the transfers are completed, the results are written to the command completion status area to complete this transfer.

[0059] The DMA transmission method provided by the present invention obtains a transmission command by acquiring a DMA command descriptor; wherein the DMA descriptor at least includes a maximum parallel transmission unit size and a destination address; the transmission command is distributed to a target number of DMA transmission units according to the maximum parallel transmission unit size to obtain multiple parallel burst transmission commands; wherein the parallel burst transmission command includes the target transmission commands of all DMA transmission units; and the parallel burst transmission command is executed. The present invention adds a field of the maximum parallel transmission unit size to the DMA descriptor, and distributes the user's demand for data setting or data movement of a specified range of addresses to multiple PORTs for parallel transmission, and meets the maximum parallel transmission unit size required by the destination address terminal MEM, so that the performance can reach the maximum performance that the terminal MEM can provide as much as possible, thereby increasing data transmission efficiency.

[0060] The DMA transmission device provided by the present invention is described below. The DMA transmission device described below and the DMA transmission method described above can be referred to in correspondence with each other. Figure 4 As shown, the device includes the following modules: The command module 410 is used to obtain a DMA command descriptor to obtain a transfer command; wherein the DMA descriptor at least includes a maximum parallel transfer unit size and a destination address; The control module 420 is used to distribute the transmission command to the target number of DMA transmission units according to the maximum parallel transmission unit size to obtain multiple parallel burst transmission commands; wherein the parallel burst transmission command includes the target transmission commands of all DMA transmission units; The execution module 430 is configured to execute the parallel burst transfer command.

[0061] According to a DMA transmission device provided by the present invention, the transmission command is distributed to a target number of DMA transmission units according to the maximum parallel transmission unit size according to a preset formula; Wherein, the preset formula includes: Where α refers to the number of DMA transfer units, β refers to the target number, δ refers to the δth parallel transfer, DMA_DEST_ADDR(α,β,δ) means that there are β DMA transfer units in total, the destination address of the δth parallel transfer of the αth DMA transfer unit, DEST_ADDR_ALIGNED refers to the base address of the simplified destination address, which satisfies the alignment restriction of the maximum parallel transfer unit size, and MULTI_SIZE refers to the maximum parallel transfer unit size.

[0062] According to a DMA transmission device provided by the present invention, the DMA transmission unit executes the target transmission commands in parallel.

[0063] According to a DMA transmission device provided by the present invention, a target number of DMA transmission units are connected to ports on a target number of buses.

[0064] According to a DMA transmission device provided by the present invention, the parallel burst transmission command is executed, and then the following steps are further included: After all parallel burst transfer commands are completed, the completion status is written to the DMA completion status buffer.

[0065] According to a DMA transmission device provided by the present invention, after completing all parallel burst transmission commands, the completion status is written into a DMA completion status buffer area, and then further includes: User gets command completion status based on DMA completion status buffer.

[0066] The DMA transmission device provided by the present invention obtains a transmission command by acquiring a DMA command descriptor; wherein the DMA descriptor at least includes a maximum parallel transmission unit size and a destination address; the transmission command is distributed to a target number of DMA transmission units according to the maximum parallel transmission unit size to obtain multiple parallel burst transmission commands; wherein the parallel burst transmission command includes the target transmission commands of all DMA transmission units; and the parallel burst transmission command is executed. The present invention adds a field of the maximum parallel transmission unit size to the DMA descriptor, and distributes the user's demand for data setting or data movement of a specified range of addresses to multiple PORTs for parallel transmission, and meets the maximum parallel transmission unit size required by the destination address terminal MEM, so that the performance can reach the maximum performance that the terminal MEM can provide as much as possible, thereby increasing data transmission efficiency.

[0067] Figure 5 An example of a physical structure diagram of an electronic device is shown in FIG. Figure 5 As shown, the electronic device may include: a processor 510, a communication interface 520, a memory 530 and a communication bus 540, wherein the processor 510, the communication interface 520 and the memory 530 communicate with each other through the communication bus 540. The processor 510 may call the logic instructions in the memory 530 to execute the DMA transmission method, which includes: obtaining a DMA command descriptor to obtain a transmission command; wherein the DMA descriptor at least includes a maximum parallel transmission unit size and a destination address; allocating the transmission command to a target number of DMA transmission units according to the maximum parallel transmission unit size to obtain multiple parallel burst transmission commands; wherein the parallel burst transmission command includes the target transmission commands of all DMA transmission units; and executing the parallel burst transmission command.

[0068] In addition, the logic instructions in the above-mentioned memory 530 can be implemented in the form of a software functional unit and can be stored in a computer-readable storage medium when it is sold or used as an independent product. Based on such an understanding, the technical solution of the present invention, in essence, or the part that contributes to the prior art or the part of the technical solution, can be embodied in the form of a software product, and the computer software product is stored in a storage medium, including a number of instructions for a computer device (which can be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the method described in each embodiment of the present invention. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), disk or optical disk, etc. Various media that can store program codes.

[0069] On the other hand, the present invention also provides a computer program product, which includes a computer program. The computer program can be stored on a non-transitory computer-readable storage medium. When the computer program is executed by a processor, the computer can execute the DMA transmission method provided by the above-mentioned methods, and the method includes: obtaining a DMA command descriptor to obtain a transmission command; wherein the DMA descriptor at least includes a maximum parallel transmission unit size and a destination address; allocating the transmission command to a target number of DMA transmission units according to the maximum parallel transmission unit size to obtain multiple parallel burst transmission commands; wherein the parallel burst transmission command includes the target transmission commands of all DMA transmission units; and executing the parallel burst transmission command.

[0070] On the other hand, the present invention also provides a non-transitory computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, is implemented to execute the DMA transfer method provided by the above-mentioned methods, the method comprising: obtaining a DMA command descriptor to obtain a transfer command; wherein the DMA descriptor at least includes a maximum parallel transfer unit size and a destination address; allocating the transfer command to a target number of DMA transfer units according to the maximum parallel transfer unit size to obtain multiple parallel burst transfer commands; wherein the parallel burst transfer command includes the target transfer commands of all DMA transfer units; and executing the parallel burst transfer command.

[0071] The device embodiments described above are merely illustrative, wherein the units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they may be located in one place, or they may be distributed on multiple network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the scheme of this embodiment. Ordinary technicians in this field can understand and implement it without paying creative labor.

[0072] Through the description of the above implementation methods, those skilled in the art can clearly understand that each implementation method can be implemented by means of software plus a necessary general hardware platform, and of course, can also be implemented by hardware. Based on this understanding, the above technical solution is essentially or the part that contributes to the prior art can be embodied in the form of a software product, and the computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, a disk, an optical disk, etc., including a number of instructions for a computer device (which can be a personal computer, a server, or a network device, etc.) to execute the methods described in each embodiment or some parts of the embodiments.

[0073] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A DMA transmission method, characterized in that: include: Acquire a DMA command descriptor to obtain a transfer command; wherein the DMA descriptor at least includes a maximum parallel transfer unit size and a destination address; Allocating the transfer command to a target number of DMA transfer units according to the maximum parallel transfer unit size to obtain a plurality of parallel burst transfer commands; wherein the parallel burst transfer command includes the target transfer commands of all DMA transfer units; The parallel burst transfer command is executed.

2. The DMA transmission method according to claim 1, characterized in that: Allocating the transmission command to a target number of DMA transmission units according to the maximum parallel transmission unit size according to a preset formula; Wherein, the preset formula includes: Where α refers to the number of DMA transfer units, β refers to the target number, δ refers to the δth parallel transfer, DMA_DEST_ADDR(α,β,δ) means that there are β DMA transfer units in total, the destination address of the δth parallel transfer of the αth DMA transfer unit, DEST_ADDR_ALIGNED refers to the base address of the simplified destination address, which satisfies the alignment restriction of the maximum parallel transfer unit size, and MULTI_SIZE refers to the maximum parallel transfer unit size.

3. The DMA transmission method according to claim 1, characterized in that: The DMA transfer unit executes the target transfer commands in parallel.

4. The DMA transmission method according to claim 1, characterized in that: A target number of the DMA transfer units are connected to the ports on the target number of buses.

5. The DMA transmission method according to claim 1, characterized in that: Executing the parallel burst transfer command, and then further comprising: After all parallel burst transfer commands are completed, the completion status is written to the DMA completion status buffer.

6. The DMA transmission method according to claim 5, characterized in that: After all parallel burst transfer commands are completed, the completion status is written to the DMA completion status buffer, followed by: User gets command completion status based on DMA completion status buffer.

7. A DMA transmission device, characterized in that: include: A command module, used for acquiring a DMA command descriptor to obtain a transfer command; wherein the DMA descriptor at least includes a maximum parallel transfer unit size and a destination address; A control module, configured to distribute the transfer command to a target number of DMA transfer units according to the maximum parallel transfer unit size, to obtain a plurality of parallel burst transfer commands; wherein the parallel burst transfer command includes the target transfer commands of all DMA transfer units; An execution module is used to execute the parallel burst transfer command.

8. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein: When the processor executes the computer program, the DMA transmission method according to any one of claims 1 to 6 is implemented.

9. A non-transitory computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the DMA transmission method according to any one of claims 1 to 6 is implemented.

10. A computer program product, comprising a computer program, characterized in that When the computer program is executed by a processor, the DMA transmission method according to any one of claims 1 to 6 is implemented.

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