Hot plug control circuit

Abstract

The invention discloses a hot plug control circuit, the circuit comprises a processor, an SATA controller, a power supply module, a power supply controller and a PCIE slot, the processor is connected with the PCIE slot, one end of the power supply controller is connected with the processor, the other end of the power supply controller is connected with the power supply module, the power supply module is connected with the PCIE slot and the SATA controller, and the power supply controller is connected with the power supply module. The power supply controller is used for controlling the power supply module to supply power to the PCIE slot and the SATA controller, the processor is integrated with a plurality of PCIE interfaces, the SATA controller is used for converting the PCIE interfaces into the SATA interfaces, the hot plug reliability of hardware equipment can be improved, and updating or capacity expansion can be carried out under the startup condition without influencing system operation.

Description

Technical Field

[0001] The present invention relates to the field of computer technology, and in particular to a hot-swap control circuit. Background Art

[0002] Hot-plugging or Hot Swap means plugging and unplugging while powered on. The hot-plugging function allows users to remove and replace damaged hard disks, power supplies, or boards without shutting down the system or cutting off the power supply, thereby improving the system's ability to recover from disasters in a timely manner, scalability, and flexibility. For example, some disk mirroring systems for high-end applications can provide hot-plugging functions for disks. On the one hand, in the military, telecommunications, and financial fields, after the equipment is put into operation, it must operate day and night. When disassembling, repairing, maintaining, and expanding the components of these equipment, the system cannot be shut down, as shutting down means significant economic losses. This requires that the equipment components can be connected or removed while the system is powered on.

[0003] The existing hot-swap technology mainly relies on capacitors and inductors to achieve instantaneous suppression of impact, but this approach may cause a huge impact on the power supply, and then the system may be reset and restarted. Therefore, how to improve the reliability of hot-swap hardware devices has become a technical problem that needs to be solved urgently. Summary of the invention

[0004] In view of the above technical problems, the present invention provides a hot-swap control circuit, which helps to improve the reliability of hot-swap of hardware devices and can also be updated or expanded while the system is powered on without affecting system operation.

[0005] The present invention provides a hot-swap control circuit. The circuit comprises a processor, a SATA controller, a power module, a power controller and a PCIE slot. The processor is connected to the PCIE slot. One end of the power controller is connected to the processor and the other end is connected to the power module. The power module is respectively connected to the PCIE slot and the SATA controller. The power controller is used to control the power module to supply power to the PCIE slot and the SATA controller. The processor is integrated with a plurality of PCIE interfaces. The SATA controller is connected to the PCIE interface and is used to convert the PCIE interface into a SATA interface.

[0006] Optionally, the SATA controller is integrated into the processor, and the processor may be one of 88SE9235, 88SE9230 or 88SE3220.

[0007] Optionally, the SATA controller includes a first SATA controller and a second SATA controller.

[0008] Optionally, the power controller adopts a TPS3808 chip.

[0009] Optionally, the circuit further includes a first analog switch and a second analog switch, and the first pin of the TPS3808 chip is respectively connected to the sixth pin of the first analog switch and the sixth pin of the second analog switch.

[0010] Optionally, the circuit further includes a hardware device, the hardware device is connected to the PCIE slot, and the hardware device is pluggably connected to the PCIE slot.

[0011] Optionally, the hardware device includes a network card, a RAID card, a solid state drive SSD, a graphics processor GPU card, a graphics card or an acceleration card.

[0012] Optionally, the PCIE interface includes a PCIE16X interface, a PCIE8X interface, a PCIE4X interface and a PCIE1X interface.

[0013] Optionally, the power module includes a power supply and a DC-DC module, and the DC-DC module is connected to the power supply to step down the power supply into a first power supply, a second power supply and a third power supply.

[0014] Optionally, the power module also includes a first group of capacitors and a second group of capacitors, the first group of capacitors and the second group of capacitors respectively include multiple capacitors in parallel, the first group of capacitors is connected to the second pin of the DC-DC chip, and the second group of capacitors is connected to the third pin of the DC-DC chip.

[0015] In the technical solution provided by the embodiment of the present invention, one end of the power controller is connected to the processor, and the other end is connected to the power module, the power module is respectively connected to the PCIE slot and the SATA controller, the power controller is used to control the power module to supply power to the PCIE slot and the SATA controller, the processor is integrated with multiple PCIE interfaces, and the SATA controller is connected to the PCIE interface to convert the PCIE interface into a SATA interface. Compared with the prior art, the present invention helps to improve the reliability of hot plugging of hardware devices, and can also be updated or expanded when the system is turned on without affecting the system operation. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 The figure is a schematic diagram of a hot-swap control circuit of the present invention.

[0017] Figure 2 The present invention is a circuit diagram of a power controller of a hot-swap control circuit. DETAILED DESCRIPTION

[0018] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present invention.

[0019] It should be noted that when an element is described as being "connected" or "connected to" another element, it may be directly connected to the other element, or one or more intermediate elements may exist therebetween. The serial numbers assigned to the components herein, such as "first", "second", etc., are only used to distinguish the objects described and do not have any order or technical meaning.

[0020] This application provides a hot swap control circuit, please refer to Figure 1 As shown, the circuit includes a processor, a SATA controller, a power module, a power controller and a PCIE slot, the processor is connected to the PCIE slot, one end of the power controller is connected to the processor, and the other end is connected to the power module, the power module is respectively connected to the PCIE slot and the SATA controller, the power controller is used to control the power module to supply power to the PCIE slot and the SATA controller, the processor is integrated with multiple PCIE interfaces, and the SATA controller is connected to the PCIE interface to convert the PCIE interface into a SATA interface.

[0021] In one embodiment of the present invention, the SATA controller is integrated into the processor, and the processor may be one of 88SE9235, 88SE9230 or 88SE3220. 88SE9235, 88SE9230 or 88SE3220 is a four-port 3Gbps or 6Gbps SATA RAID I / O processor that provides a dual-channel PCIE 2.0 interface and SATA controller function, and adds HyperDuo embedded processor technology for use in environments where solid-state drives and mechanical hard disks are mixed. It can automatically identify the most frequently accessed data and files and optimize performance. This technology has two working modes: Safe Mode, which mirrors the data of the solid-state drive to the mechanical disk to optimize data protection; Capacity Mode: Combines the capacity of the solid-state drive and the mechanical hard disk into one. Both modes can automatically identify the LBA range of the solid-state drive and the mechanical hard disk to ensure the same user experience.

[0022] In one embodiment of the present invention, the PCIE interface includes a PCIE16X interface, a PCIE8X interface, a PCIE4X interface and a PCIE1X interface. PCIE (peripheral component interconnect express) is a high-speed serial computer expansion bus standard designed to replace the old PCI, PCI-X and AGP bus standards. PCIE also has a variety of specifications, from PCIE1x to PCIE32x, which can meet the needs of low-speed devices and high-speed devices that will appear in the future. The PCIE interface can not only exist as a bus to undertake the transmission channel, but also exist directly in the form of an interface. For example, the PCIE slot on the motherboard can be directly inserted into a solid-state hard drive, using the PCIE bus NVMe protocol.

[0023] According to the PCIE2.0 basic specification, the PCIE interface uses a layered architecture. The main layers are the physical layer, MAC layer, data link layer, and transaction layer. In addition, the core adapter layer handles the forwarding of PCIE transaction layer packets (TLPs) to the internal bus.

[0024] The PCIE interface supports hot-plugging, and users can insert or remove PCIe devices, such as solid-state drives and network cards, without turning off the power. The hot-plugging function of the PCIE interface is implemented through SMBUS (System Management Bus), which is a bus used for low-speed communication and is often used to monitor and control hardware devices, such as detecting device presence (PRSNT#) and link activation signals (WAKE#).

[0025] In one embodiment of the present invention, the SATA controller includes a first SATA controller and a second SATA controller. The SATA controller is used to provide a single-line PCIE 2.0 interface and a SATA controller function, and its main function is to convert the PCIE interface into a SATA interface. It can be connected to a storage chip. Specifically, the storage chip is selected to use an SSD solid-state hard disk with a SATA bus. Compared with a traditional mechanical hard disk, it has the characteristics of small area, low power consumption, high stability and high speed. The design chooses to use a single-chip 128GB uSSD from Silicon Motion. The chip model is SM619GED. It integrates a SATA controller and NANDFlash in a chip with a size of 20mm x 16mm. Its main function is to provide a hardware installation environment for the operating system of the core card.

[0026] SATA controllers can extend SATA interfaces through PCIE interfaces, allowing motherboards or other devices to connect to more hard drives. For example, some expansion cards use PCIE interfaces to connect to motherboards and provide additional SATA 6Gbps interfaces.

[0027] The SATA controller consists of 4 SATA interfaces, which are accessed by the host through the PCIE function. The SATA controller supports PCI-IDE mode and AHCI mode.

[0028] The AHCL interface uses PCIe BAR5, which is a memory BAR. The host driver programs the registers in PCIe BAR5 to control the 4 SATA ports. All ACHL mode interface registers are located in the SATA controller. The basic operation sequence of AHCL mode is as follows:

[0029] 1. The host driver programs all registers pointing to command and data structures. The host driver also prepares commands and data for the four SATA ports.

[0030] 2. The host program CMD_ISSUE (R138h / R1B8h / R238h / R2Bh[31:0]) issues a command. When receiving the command, the SATA controller reads the data and memory data.

[0031] 3. The SATA controller sends the command to the device and automatically performs data transmission.

[0032] 4. The SATA controller sends an interrupt to the host driver, which checks the status. After the status check is complete, the command is executed.

[0033] The AHCI data storage structure consists of three parts: SATA Received FIS, SATA Command List and SATA CommandTable.

[0034] In one embodiment of the present invention, the circuit further comprises a hardware device, the hardware device is connected to the PCIE slot, and the hardware device is pluggable and connected to the PCIE slot. In the present application, the PCIE device may be a network card, a redundant array of independent disks (RAID) card, a PCI solid state disk (SSD), a graphics processing unit (GPU) card, a graphics card or an acceleration card, etc.

[0035] In one embodiment of the present invention, the circuit further includes a flash memory (FLASH) chip, and the FLASH chip stores all the IP core configuration information, pin configuration information, etc. of the processor.

[0036] In one embodiment of the present invention, the power controller uses a TPS3808 chip. Figure 2As shown, the circuit also includes a first analog switch and a second analog switch, and the first pin of the TPS3808 chip is respectively connected to the sixth pin of the first analog switch and the sixth pin of the second analog switch. Specifically, the first analog switch and the second analog switch can be SN74LVC1G3157DCKR chips. The sixth pin of the TPS3808 chip is respectively connected to a 3.3V power supply and one end of a capacitor C961, and the other end of the capacitor C961 is grounded. The fifth pin of the TPS3808 chip is connected to a processor, and the fourth pin of the TPS3808 chip is grounded through a capacitor C962. The first pins of the first analog switch and the second analog switch are respectively connected to RAID, and the fifth pins of the first analog switch and the second analog switch are respectively connected to a 3.3V power supply and one end of a capacitor C963, and the other end of the capacitor C963 is grounded.

[0037] The TPS3808 chip monitors the system voltage of the circuit from 0.4V to 5V and issues an open-drain RESET signal when the SENSE voltage falls below the preset threshold or when the manual reset (MR) pin drops to logic low. After the SENSE voltage and the manual reset (MR) pin recover above their respective thresholds, the RESET output remains low for a user-adjustable delay time.

[0038] In one embodiment of the present invention, the power module includes a power supply and a DC-DC module, and the DC-DC module is connected to a 12V power supply and is used to step down the 12V power supply into a first power supply, a second power supply and a third power supply. Specifically, the first power supply is 1.0V, the second power supply is 1.8V, and the third power supply is 3.3V. The power pin (VDD pin) of the present invention is directly connected to the VDD plane of the power layer, with short and wide routing to minimize the digital power routing inductance. Use a via close to the VDD pin to connect to the plane, avoiding the use of the top layer routing.

[0039] The power module also includes a first group of capacitors and a second group of capacitors, wherein the first group of capacitors and the second group of capacitors respectively include a plurality of capacitors connected in parallel, the first group of capacitors is connected to the second pin of the DC-DC module, and the second group of capacitors is connected to the third pin of the DC-DC module. The plurality of capacitors in the first capacitor group and the second capacitor group of the present invention are all ceramic decoupling capacitors, which are used to filter low-frequency power supply noise. In order to reduce system noise, a high-frequency surface-mounted monolithic ceramic bypass capacitor should be as close to the channel VDD pin as possible.

[0040] The hot-swap control circuit of the present invention can be updated or expanded when the system is powered on without affecting the system operation, and achieves the purpose of hot-swap current control.

[0041] The above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit the same. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that the technical solutions described in the aforementioned embodiments may still be modified, or some of the technical features may be replaced by equivalents. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A hot-swap control circuit, characterized in that: The circuit includes a processor, a SATA controller, a power module, a power controller and a PCIE slot. The processor is connected to the PCIE slot. One end of the power controller is connected to the processor and the other end is connected to the power module. The power module is respectively connected to the PCIE slot and the SATA controller. The power controller is used to control the power module to supply power to the PCIE slot and the SATA controller. The processor is integrated with multiple PCIE interfaces. The SATA controller is connected to the PCIE interface to convert the PCIE interface into a SATA interface.

2. The hot-swap control circuit according to claim 1, characterized in that: The SATA controller is integrated in the processor, and the processor may be one of 88SE9235, 88SE9230 or 88SE3220.

3. The hot-swap control circuit according to claim 1, characterized in that: The SATA controller includes a first SATA controller and a second SATA controller.

4. The hot-swap control circuit according to claim 1, characterized in that: The power supply controller adopts TPS3808 chip.

5. The hot-swap control circuit according to claim 4, characterized in that: The circuit also includes a first analog switch and a second analog switch, and the first pin of the TPS3808 chip is connected to the sixth pin of the first analog switch and the sixth pin of the second analog switch respectively.

6. The hot-swap control circuit according to claim 1, characterized in that: The circuit also includes a hardware device, which is connected to the PCIE slot and is pluggable to the PCIE slot.

7. The hot-swap control circuit according to claim 6, characterized in that: The hardware devices include network cards, RAID cards, solid-state drives (SSDs), image processor (GPU) cards, graphics cards or acceleration cards.

8. The hot-swap control circuit according to claim 1, characterized in that: The PCIE interface includes a PCIE16X interface, a PCIE8X interface, a PCIE4X interface and a PCIE1X interface.

9. The hot-swap control circuit according to claim 1, characterized in that: The power supply module comprises a power supply and a DC-DC module. The DC-DC module is connected to the power supply to reduce the voltage of the power supply into a first power supply, a second power supply and a third power supply.

10. The hot-swap control circuit according to claim 9, characterized in that: The power module also includes a first group of capacitors and a second group of capacitors, wherein the first group of capacitors and the second group of capacitors respectively include a plurality of capacitors connected in parallel, the first group of capacitors is connected to the second pin of the DC-DC chip, and the second group of capacitors is connected to the third pin of the DC-DC chip.

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