IIC Master IP core module based on APB bus
By designing an IIC Master IP core module based on APB bus, the problem of lack of efficient IIC Master IP core running on APB bus in the prior art is solved, and the system integration level is improved and multiple device support is achieved, reducing the complexity and cost of system debugging.
Patent Information
- Application Number
- CN202510199444.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-02-24
- Publication Date
- 2025-05-13
AI Technical Summary
The prior art lacks an efficient and flexible IIC Master IP core module that can run on the APB bus, which is difficult to meet the needs of efficient data transmission and support of the IIC bus protocol in embedded systems.
A IIC Master IP core module based on APB bus is designed, including APB interface module, FIFO memory module and IIC interface module. These modules realize the basic timing and functional characteristics of the IIC bus protocol, and support 7-bit address mode, bidirectional communication, 16-bit data transmission and APB bus interface.
It has achieved improved system integration, supported the connection and bidirectional data transmission of multiple peripheral devices, enhanced the practicality of IP cores and chip integration, and reduced the complexity and cost of system debugging.
Smart Images
Figure CN119988286A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the embedded field, and more specifically to an IIC Master IP core module based on an APB bus. Background Art
[0002] The application of AMBA bus architecture is very extensive, covering multiple fields from low-power embedded systems to high-performance computing systems. In low-power embedded systems, such as smart homes, automotive electronics and medical equipment, AMBA bus can provide a more efficient and reliable information exchange channel; while in high-performance computing systems, AMBA bus can achieve high-speed data transmission between multiple processors and other components through distributed systems.
[0003] The IIC bus is an interconnection technology that is different from the AMBA bus architecture. IIC uses two-wire serial data transmission and is suitable for occasions that require low-speed, short-distance data transmission, such as consumer electronics, industrial electronics, etc. By connecting various chips through the IIC bus, these chips can exchange data simply and quickly to achieve coordinated operation of the system.
[0004] In embedded system design, IIC Master modules are widely used in various types of application fields. They can actively control all slave devices on the bus, realize efficient communication between the processor and various peripheral devices, and other external hardware / software modules work together to achieve a high level of chip integration.
[0005] With the development of SOC integrated circuit technology, APB bus has also been widely used. Therefore, it is very meaningful to design an IIC Master IP that can run on the APB bus. Summary of the invention
[0006] The purpose of the present invention is to overcome the shortcomings of the prior art and provide an IIC Master IP core module based on the APB bus, which has small hardware resource occupancy, clear structure, easy integration, high performance, strong flexibility and easy verification and debugging.
[0007] The object of the present invention is achieved through the following solutions:
[0008] An IIC Master IP core module based on an APB bus, comprising: an APB interface module, a FIFO storage module and an IIC interface module;
[0009] The APB interface module is used to complete the chip selection function, address decoding and conversion from the APB interface to the internal protocol of the IIC interface, so that the IIC Master IIC interface module can be correctly mounted on the APB bus;
[0010] The FIFO storage module is used to cache data. At the same time, a counter logic module is also provided in the FIFO storage module to count the number of available slots. For a non-reset state, if the read enable is high, the write enable is low and the FIFO is not empty, the counter is decreased; otherwise, if the write enable is high, the read enable is low and the FIFO is not full, the counter is increased.
[0011] The IIC interface module is used to implement the functional design of clock generation, state machine control, state machine implementation, timeout counter and register group according to the IIC communication protocol.
[0012] Furthermore, the input interface of the APB interface module supports the AMBA3 bus protocol, and the module is the interface for the IICMaster IP core to communicate with the central processing unit.
[0013] Furthermore, the APB interface module includes: inside the APB interface module, before the transmission process is performed, the configuration data and delay of the IIC bus are first stored in the corresponding register, and then the transmission process can be performed.
[0014] Furthermore, the FIFO module includes a TX FIFO module and an RX FIFO module; the TX FIFO module is a register array with a width of 32 and a depth of 4, and its function is to store the data to be transmitted by the APB interface module until the IIC interface module reads the data; the RX FIFO module is a register array with a width of 32 and a depth of 4, and its function is to store the data received from the IIC interface module until the system takes it away.
[0015] Furthermore, the IIC interface module includes a clock generation module, which is used to generate an SCL signal using a counter in a programmed manner, and to compare the send / receive counter with the frequency division stored in the data configuration register. When the counter is greater than or equal to one-quarter frequency division and less than three-quarter frequency division, SCL is set to a high level, thereby controlling the clock frequency.
[0016] Furthermore, the IIC interface module includes a state machine controller module for controlling data transmitted on the IIC communication bus through a state machine, decomposing bytes into bits, defining parameters of the state machine bit by bit, and defining state control signals.
[0017] Furthermore, the IIC interface module includes a state machine implementation module for controlling data transmission and generating corresponding level signals to complete the control of SDA and SCL, so as to specifically implement each transmission state in the state machine.
[0018] Furthermore, the IIC interface module includes a timeout counter module, which is used to update the value of the timeout counter according to the judgment result by judging the state of the PRESETn signal and the value of the current timeout counter count_timeout when triggered by the rising edge PCLK.
[0019] Furthermore, the IIC interface module includes a register group module for counting and determining the direction of data flow in the I1C bus state machine and for performing data transmission with the corresponding module. Different registers are involved in the transmission according to different reading and writing processes.
[0020] Furthermore, different counter signals are used to generate the SCL signal according to different bus data transmission directions.
[0021] The beneficial effects of the present invention include:
[0022] (1) Improve system integration: Based on the module of the present invention, it can be connected to multiple peripheral devices (such as sensors, converters ADC / DAC, real-time clock RTC, EEPROM modules and memories, power management, LED drivers, etc.) through a bus. Multiple devices can be mounted on the same bus and support bidirectional data transmission, thereby improving system integration.
[0023] (2) Support for a variety of different devices: Based on the module of the present invention, since the IIC bus protocol is widely used in various types of devices (such as memory, fingerprint recognition, capacitive screen, etc.), the IIC Master IP based on the APB bus should also support a variety of different types of IIC devices, which in turn enhances the practicality of the IP core; and based on the module of the present invention, it supports efficient and reliable data communication and control in embedded systems, and can more efficiently exchange data streams between the IIC bus protocol and other processor peripheral devices, while supporting data sharing and interaction between a variety of different types of devices, which greatly improves the degree of chip integration, thereby reducing overall costs and simplifying system debugging.
[0024] (3) Realize low power consumption design: Based on the module of the present invention, when data transmission is not required, the slave device can pull down the SCL line to put the master device into a waiting state, thereby reducing the power consumption of the entire system. In addition, the static power consumption of the devices on the bus mainly depends on their operating voltage and the leakage current of the I / O port. Since the bus uses open-drain output, no current will flow through the bus when no data transmission is performed.
[0025] (4) Simplified implementation of address mapping: Based on the module of the present invention, a bus can be shared among multiple devices. In this way, only one device is connected to the bus at the same time, thereby reducing the possibility of address conflicts. The IIC controller logic and other peripheral modules can be integrated into the SOC chip through address mapping, which can avoid the need for a large number of complex interface logic construction required by traditional independent hardware controllers, thereby reducing the impact on system-level layout and design and simplifying the entire SoC development process. BRIEF DESCRIPTION OF THE DRAWINGS
[0026] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative labor.
[0027] Figure 1 It is a structural block diagram of the present invention;
[0028] Figure 2 This is the IIC bus state machine of the present invention. DETAILED DESCRIPTION
[0029] All features disclosed in all embodiments in this specification, or steps in all methods or processes implicitly disclosed, except for mutually exclusive features and / or steps, can be combined and / or expanded or replaced in any manner.
[0030] In view of the current situation in the background, the inventor of the present invention believes that: Traditionally, the IIC Master controller is implemented by an independent hardware module, and additional interface logic is required to communicate with other parts of the system. In modern SOC chips, the integrated IIC Master controller can avoid these complex interface logics, thereby reducing system cost and complexity. On the other hand, the APB bus is a low-speed transmission bus in the AMBA series bus, which is used to connect various peripheral low-speed devices, such as UART, SPI, IIC, etc. Since the APB bus is often used to integrate processor peripherals such as CPU and memory, the inventor of the present invention believes that the IIC Master IP design based on the APB bus can make the data flow between the IIC bus protocol and other processor peripherals more efficiently exchanged, while supporting data sharing and interaction between multiple different types of devices. This greatly improves the degree of chip integration, thereby bringing many benefits to embedded system development.
[0031] In the concept of the present invention, a new technical solution is provided, which specifically divides and designs three functional modules inside the IIC Master IP core, namely the APB interface module, the FIFO storage module and the IIC interface module, which are used to complete the basic timing of the IIC transmission protocol. In a more specific implementation, the AMBA3 bus protocol is used as a reference, and the design is carried out with the goal of realizing the basic transmission timing and functional characteristics of the IIC bus protocol. The main functions are as follows: support for 7-bit address mode, bidirectional communication between the host and the slave, the transmission mode complies with the IIC bus protocol, support for 16-bit data transmission and support for the APB bus interface.
[0032] like Figure 1 As shown in the figure, the detailed design description of each module is as follows:
[0033] 1. APB interface module
[0034] In the conception of the present invention, the input interface of the APB interface module supports the AMBA3 bus protocol. The module is the key interface for the IICMaster IP core to communicate with the central processing unit. Its main functions are to complete the chip selection function inside the module, address decoding, and conversion from the APB interface to the internal protocol of the IIC interface, so that the IIC Master IIC interface module can be correctly mounted on the APB bus.
[0035] Inside the APB interface module, before the transmission process is carried out, the present invention requires the configuration data and delay of the IIC bus to be stored in the corresponding registers before the transmission process can be carried out. The main functions of this design are to convert the input signal into the read and write control signal of the FIFO memory, store the signal in the FIFO, assign the logic of the required signal of the APB bus state machine, complete the relevant instructions of its write process and read process, and write the relevant statements of the transmission error.
[0036] 2. FIFO module
[0037] The main function of the FIFO module is to cache data. Since the transmission rate of the IIC bus is lower than that of the APB bus, a buffer module is designed in the concept of the present invention, which specifically includes a TX FIFO module and an RX FIFO module. The TX FIFO is a register array with a width of 32 and a depth of 4. Its function is to store the data to be transmitted by the APB interface module until the IIC interface module reads the data. The RX FIFO is also a register array with a width of 32 and a depth of 4. Its function is to store the data received from the IIC interface module until the system takes it away. A counter logic is written inside the FIFO to count the number of available slots. For the non-reset state, if the read enable is high, the write enable is low and the FIFO is not empty, the counter is reduced; otherwise, if the write enable is high, the read enable is low and the FIFO is not full, the counter is increased.
[0038] 3. IIC interface module
[0039] The IIC interface module is the core module, and the module is specifically designed according to the IIC communication protocol, including a clock generation module, a state machine controller module, a state machine implementation module, a timeout counter module and a register group module. In the concept of the present invention, PCLK and PRESETN are used as signals of the APB bus module, and are introduced into the IIC bus module as system clock and reset signals.
[0040] Clock generation module: The IIC interface module needs to generate an SCL signal, and its system clock is PCLK (APB interface module clock). It can be seen from the IIC bus transmission timing that the IIC drive clock frequency (PCLK here) should be more than twice the SCL. If twice the frequency is selected, SDA can only be changed on the falling edge or on the rising edge of the CLK acquired by the current data, which is prone to glitches. Therefore, a 12-fold frequency is selected in the concept of the present invention. In the concept of the present invention, SCL is not generated by directly dividing the PCLK frequency, but a programming method is used to generate SCL using a counter. By comparing the sending\receiving counter with the frequency division stored in the data configuration register, when the counter is greater than or equal to one-quarter of the frequency division and less than three-quarters of the frequency division, SCL is made high, thereby controlling the clock frequency; the SCL clock generated by this module is more stable than the ordinary frequency division signal. Furthermore, in the concept of the present invention, different counter signals are used to generate SCL according to the different directions of bus data transmission.
[0041] State machine controller module: This module controls the data transmitted on the IIC communication bus through a state machine, decomposes bytes into bits, and defines the parameters of the state machine bit by bit. Its initial state (IDLE) and start bit (START) need to be defined. Due to the APB bus transmission protocol restrictions, the data bit is 32 bits. According to the IIC bus communication protocol, every 8 bits require a response bit (RESPONSE), and 32 bits of data need to be responded to 4 times. Finally, the delay bit (DELAY_BYTES), no valid response bit (NACK) and STOP are defined, totaling 40 state machine parameters, and two state machine registers with a bit width of 6 are defined as state control signals. The state machine is as follows: Figure 2 .
[0042] State machine implementation module: This module controls the data transmission and generates specific level signals to complete the control of SDA and SCL to specifically implement each transmission state in the state machine. The transmission direction needs to be specified before the signal is transmitted.
[0043] Timeout counter: When the rising edge PCLK triggers this module, it updates the value of the timeout counter according to the judgment result by judging the state of the PRESETn signal and the value of the current timeout counter count_timeout.
[0044] Register group: The register module is used to count and determine the direction of data flow in the I1C bus state machine, and is used to transmit data with other modules. Depending on the read and write process, the registers involved in the transmission are also different.
[0045] Table 1 is the definition of each port signal of the IIC Master IP core.
[0046] Table 1 IIC Master IP core port signals
[0047]
[0048]
[0049] It should be noted that within the scope of protection defined in the claims of the present invention, the following embodiments can be combined and / or expanded or replaced in any logical way from the above specific implementation methods, such as disclosed technical principles, disclosed technical features or implicitly disclosed technical features.
[0050] Example 1
[0051] An IIC Master IP core module based on an APB bus, comprising: an APB interface module, a FIFO storage module and an IIC interface module;
[0052] The APB interface module is used to complete the chip selection function, address decoding and conversion from the APB interface to the internal protocol of the IIC interface, so that the IIC Master IIC interface module can be correctly mounted on the APB bus;
[0053] The FIFO storage module is used to cache data. At the same time, a counter logic module is also provided in the FIFO storage module to count the number of available slots. For a non-reset state, if the read enable is high, the write enable is low and the FIFO is not empty, the counter is decreased; otherwise, if the write enable is high, the read enable is low and the FIFO is not full, the counter is increased.
[0054] The IIC interface module is used to implement the functional design of clock generation, state machine control, state machine implementation, timeout counter and register group according to the IIC communication protocol.
[0055] Example 2
[0056] On the basis of Example 1, the input interface of the APB interface module supports the AMBA3 bus protocol, and the module is the interface for the IIC Master IP core to communicate with the central processing unit.
[0057] Example 3
[0058] On the basis of Embodiment 1, the APB interface module includes: inside the APB interface module, before the transmission process is performed, the configuration data and delay of the IIC bus are first stored in the corresponding register, and then the transmission process can be performed.
[0059] Example 4
[0060] On the basis of Example 1, the FIFO module includes a TX FIFO module and an RX FIFO module; the TXFIFO module is a register array with a width of 32 and a depth of 4, and its function is to store the data to be transmitted by the APB interface module until the IIC interface module reads the data; the RX FIFO module is a register array with a width of 32 and a depth of 4, and its function is to store the data received from the IIC interface module until the system takes it away.
[0061] Example 5
[0062] On the basis of Example 1, the IIC interface module includes a clock generation module, which is used to generate an SCL signal using a counter in a programmed manner, and compare the send / receive counter with the division stored in the data configuration register. When the counter is greater than or equal to one-quarter division and less than three-quarter division, SCL is set to a high level, thereby controlling the clock frequency.
[0063] Example 6
[0064] Based on Example 1, the IIC interface module includes a state machine controller module, which is used to control data transmitted on the IIC communication bus through a state machine, decompose bytes into bits, define parameters of the state machine bit by bit, and define state control signals.
[0065] Example 7
[0066] On the basis of Example 1, the IIC interface module includes a state machine implementation module for controlling data transmission and generating corresponding level signals to complete the control of SDA and SCL, so as to specifically implement each transmission state in the state machine.
[0067] Example 8
[0068] Based on Example 1, the IIC interface module includes a timeout counter module, which is used to update the value of the timeout counter according to the judgment result by judging the state of the PRESETn signal and the value of the current timeout counter count_timeout when triggered by the rising edge PCLK.
[0069] Example 9
[0070] Based on Example 1, the IIC interface module includes a register group module for counting and determining the data flow direction in the I1C bus state machine and for performing data transmission with the corresponding module. Depending on the reading and writing process, the registers involved in the transmission are different.
[0071] Example 10
[0072] On the basis of Embodiment 5, different counter signals are used to generate the SCL signal according to different bus data transmission directions.
[0073] The units involved in the embodiments of the present invention may be implemented by software or hardware, and the units described may also be arranged in a processor. The names of these units do not, in some cases, limit the units themselves.
[0074] According to one aspect of an embodiment of the present invention, a computer program product or a computer program is provided, the computer program product or the computer program includes a computer instruction, and the computer instruction is stored in a computer-readable storage medium. A processor of a computer device reads the computer instruction from the computer-readable storage medium, and the processor executes the computer instruction, so that the computer device executes the method provided in the above various optional implementations.
[0075] As another aspect, an embodiment of the present invention further provides a computer-readable medium, which may be included in the electronic device described in the above embodiment; or may exist independently without being assembled into the electronic device. The above computer-readable medium carries one or more programs, and when the above one or more programs are executed by an electronic device, the electronic device implements the method described in the above embodiment.
Claims
1. An IIC Master IP core module based on APB bus, characterized in that: include: APB interface module, FIFO storage module and IIC interface module; The APB interface module is used to complete the chip selection function, address decoding and conversion from the APB interface to the internal protocol of the IIC interface, so that the IIC Master IIC interface module can be correctly mounted on the APB bus; The FIFO storage module is used to cache data. At the same time, a counter logic module is also provided in the FIFO storage module to count the number of available slots. For a non-reset state, if the read enable is high, the write enable is low and the FIFO is not empty, the counter is decreased; otherwise, if the write enable is high, the read enable is low and the FIFO is not full, the counter is increased. The IIC interface module is used to implement the functional design of clock generation, state machine control, state machine implementation, timeout counter and register group according to the IIC communication protocol.
2. The IIC Master IP core module based on the APB bus according to claim 1, characterized in that: The input interface of the APB interface module supports the AMBA3 bus protocol, and the module is the interface for the IIC Master IP core to communicate with the central processing unit.
3. The IIC Master IP core module based on APB bus according to claim 1, characterized in that: The APB interface module includes: inside the APB interface module, before the transmission process is carried out, the configuration data and delay of the IIC bus are first stored in the corresponding register, and then the transmission process can be carried out.
4. The IIC Master IP core module based on the APB bus according to claim 1, characterized in that: The FIFO module includes a TX FIFO module and an RX FIFO module; the TX FIFO module is a register array with a width of 32 and a depth of 4, and its function is to store the data to be transmitted by the APB interface module until the IIC interface module reads the data; the RXFIFO module is a register array with a width of 32 and a depth of 4, and its function is to store the data received from the IIC interface module until the system takes it away.
5. The IIC Master IP core module based on APB bus according to claim 1, characterized in that: The IIC interface module includes a clock generation module, which is used to generate an SCL signal using a counter in a programmed manner, and compare the send / receive counter with the frequency division stored in the data configuration register. When the counter is greater than or equal to one-quarter frequency division and less than three-quarter frequency division, SCL is set to a high level, thereby controlling the clock frequency.
6. The IIC Master IP core module based on APB bus according to claim 1, characterized in that: The IIC interface module includes a state machine controller module, which is used to control data transmitted on the IIC communication bus through a state machine, decompose bytes into bits, define parameters of the state machine bit by bit, and define state control signals.
7. The IIC Master IP core module based on APB bus according to claim 1, characterized in that: The IIC interface module includes a state machine implementation module, which is used to control the transmission of data and generate corresponding level signals to complete the control of SDA and SCL, so as to specifically implement each transmission state in the state machine.
8. The IIC Master IP core module based on APB bus according to claim 1, characterized in that: The IIC interface module includes a timeout counter module, which is used to update the value of the timeout counter according to the judgment result by judging the state of the PRESETn signal and the value of the current timeout counter count_timeout when triggered by the rising edge PCLK.
9. The IIC Master IP core module based on APB bus according to claim 1, characterized in that: The IIC interface module includes a register group module, which is used to count and determine the data flow direction in the I1C bus state machine and to perform data transmission with the corresponding module. Depending on the different reading and writing processes, the registers involved in the transmission are different.
10. The IIC Master IP core module based on APB bus according to claim 5, characterized in that: Depending on the direction of bus data transmission, different counter signals are used to generate the SCL signal.