Minimum-delay fine-grained parallel Givens rotation method for ultra-large-scale matrix QR decomposition

Abstract

The present invention discloses a method for minimal-delay fine-grained parallel Givens rotation of ultra-large-scale matrix QR decomposition, relating to the technical field of signal and information processing. The method comprises: an outer loop and an inner loop, wherein the outer loop is responsible for calculating a row vector of a Q matrix and an R matrix, and the inner loop is responsible for the Givens rotation of the two row vectors; the outer loop is decomposed into multiple loop blocks and a multi-level PE unit array is used to realize parallel operation of the outer loop slices, while the parallel calculation of the inner loop slices is realized by a step-by-step decreasing element update module inside the PE unit; the collaborative design of the inner and outer loop slices significantly reduces the idle time of hardware resources and optimizes the generation and transmission of key data, so that the system starts calculation with minimal delay; the method improves the utilization efficiency of hardware accelerators and is suitable for ultra-large-scale matrix decomposition tasks in the fields of signal processing, image processing, and scientific computing.

Description

Technical Field

[0001] The present invention relates to the technical field of signal and information processing, and in particular to a super-large-scale matrix QR decomposition minimum delay fine-grained parallel Givens rotation method. Background Art

[0002] The rapid advancement of modern technology has led to an explosive growth in data volumes, and performance standards for intensive computing are constantly rising. Matrix operations play a central role in intensive computing, and their performance largely determines the overall performance of the system. Large-scale matrix QR decomposition has a wide range of applications in signal processing, image processing, computational fluid dynamics, and computational structural mechanics.

[0003] The implementation of QR decomposition varies for matrices of different sizes. For small-scale QR decomposition, a two-dimensional Systolic array is typically used. While this two-dimensional array structure offers high parallelism, it consumes significant hardware resources, with the number of processing units in the array typically reaching O(n²). As the matrix size increases, chip area and power consumption limits the implementation of QR decomposition using a two-dimensional array structure. For larger matrices, folding and mapping methods are often used to fold the two-dimensional array into a one-dimensional structure. This method achieves a linear array with O(n) processing units. However, as the matrix size increases, this approach remains challenging to implement. Currently, fine-grained parallel structures are often used for QR decomposition of very large matrices. Within this fine-grained parallel structure, the PE unit offers a simple structure and strong scalability, but it also has certain limitations: existing designs primarily focus on optimizing the pipeline operations of the outer loop blocks, while parallel computing within the inner loop blocks is underdeveloped. This design means that the startup of the subsequent PE unit must rely on the results of two iterative calculations by the previous PE unit. This means that the startup must first wait for the previous PE unit to complete one set of Givens rotations, and then wait for the next set of Givens rotations to generate the required valid data. This dependency results in a long startup wait time for the subsequent PE unit. This wait time increases significantly with increasing matrix size and the number of PE units, significantly limiting the computational efficiency of the QR decomposition hardware accelerator. Summary of the Invention

[0004] The purpose of the present invention is to provide a minimum-latency fine-grained parallel Givens Rotation method, which realizes efficient calculation of ultra-large-scale matrix QR decomposition through the collaborative parallel design of inner and outer loop slices, significantly reduces hardware latency and optimizes resource utilization.

[0005] The technical solution of the present invention is to provide a minimal-delay fine-grained parallel Givens rotation method for ultra-large-scale matrix QR decomposition, which uses an operation architecture with an outer loop and an inner loop to perform matrix decomposition. The method includes: the outer loop is responsible for calculating a row vector of the Q matrix and the R matrix, and the inner loop is responsible for Givens rotation of the two row vectors;

[0006] When performing QR decomposition on a very large matrix, the outer loop of the matrix is ​​decomposed into several outer loop blocks, each of which contains multiple outer loop slices. Each outer loop slice is calculated by a PE unit and is responsible for updating a row vector of the matrix.

[0007] Each PE unit is connected sequentially in a cascade manner and processes the computational tasks of the outer loop slice in parallel within the outer loop block. The first-level PE unit reads the initial matrix row vector from the external memory and updates it. Each subsequent PE unit starts the computation immediately after receiving the partial intermediate results generated by the previous-level PE unit, updates the row vector it is responsible for, and passes the intermediate results to the next-level PE unit in real time until all computational tasks of the outer loop block are completed.

[0008] Each PE unit further divides the outer loop slice into multiple inner loop slices. Each PE unit contains an update factor calculation module and several element update modules. Each inner loop slice is responsible for performing the Givens rotation operation on two row vectors in the matrix. After the update factor calculation module calculates the Givens rotation factor, it directly passes the data to the element update module. The element update module processes part of the update task of the current row vector step by step and passes the intermediate data to the next level PE unit in real time. The next level element update module receives the data generated by the previous level element update module step by step and starts the operation in real time to complete all the calculation tasks of the inner loop slice.

[0009] After all PE units complete the above calculations, the updated results generated by the last-level PE unit are written into the off-chip memory for storage.

[0010] In any of the above technical solutions, further, the number of element update modules in each PE unit decreases step by step, specifically:

[0011] The first-level PE unit contains n element update modules; the second-level PE unit contains n-1 element update modules; the p-th level PE unit contains (n-p+1) element update modules; and the last-level PE unit contains only 1 element update module.

[0012] In any of the above technical solutions, further, the first-level PE unit reads the initial matrix data from the off-chip memory, and the remaining PE units immediately receive and start calculations after the previous-level PE unit generates intermediate calculation data, and the last-level PE unit writes the calculation results back to the off-chip memory to provide input data for subsequent outer loop blocks.

[0013] In any of the above technical solutions, further, the outer loop block is executed in a serial manner, and after all outer loop slices of an outer loop block are calculated, the calculation of the next outer loop block is started;

[0014] Inside the outer loop block, PE units execute the computational tasks of the outer loop slice in parallel through cascading.

[0015] In any of the above technical solutions, further, the n PE element update modules in the PE units responsible for the i-th outer loop slice implement parallel calculation of an inner loop block by:

[0016] In the first inner loop block, the first-level element update module performs Givens rotation on the i-th vector and the (i+1)-th vector received by the current PE unit; the updated i-th vector is passed to the second-level element update module of the PE unit, and the (i+1)-th vector is passed to the PE unit responsible for updating the (i+1)-th vector;

[0017] In the s-th inner loop block, the first-level element update module performs Givens rotation on the (i+n×(s-1)+1)-th vector received by the current PE unit and the i-th vector stored in the on-chip memory in the (s-1)-th inner loop block;

[0018] The k-th level element update module (k≠1) performs Givens rotation on the (i+k)-th vector received by the current PE unit and the i-th vector updated by the (k-1)-th level element update module of the current PE unit;

[0019] The k-th PE unit passes the updated i-th vector to the (k+1)-th element update module of the current PE unit, and passes the (i+k)-th vector to the PE unit responsible for the (i+1)-th outer loop slice;

[0020] The n-th level element update module saves the i-th vector generated by the update in the on-chip memory for the calculation of the next inner loop block;

[0021] Each inner loop block is executed serially. After the calculation of the previous inner loop block is completed, the calculation of the next inner loop block is started until the calculation of all inner loop blocks is completed.

[0022] In any of the above technical solutions, further, the intermediate vectors calculated by the non-last-stage PE units are transmitted to the next-stage PE units through the data path; the intermediate vectors calculated by the last-stage PE units are stored in an off-chip memory to provide input for calculations of subsequent outer loop blocks;

[0023] The vector updated by the givens rotation performed by the non-last-level element update module in the inner loop is passed to the next-level element update module, and the i-th vector updated by the last-level element update module is stored in the on-chip memory.

[0024] The beneficial effects of the present invention are:

[0025] This paper optimizes the key steps in the QR decomposition of very large matrices and proposes a minimum-delay fine-grained parallel Givens Rotation method. This method solves the problems of low hardware resource utilization and high computational latency in the QR decomposition of very large matrices through innovative architecture design and parallel computing design.

[0026] The present invention combines the pipeline design of the outer loop slice with the pipeline design of the inner loop slice for the first time, achieving efficient coordinated allocation of computing tasks in time and hardware resources.

[0027] The present invention fully utilizes the characteristics of data correlation in Givens rotation calculation through the step-by-step element update module design and the PE unit cascade pipeline architecture, breaking through the limitations of traditional fine-grained parallel methods. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] The advantages of the above and additional aspects of the present invention will become apparent and readily understood from the following description of the embodiments with reference to the accompanying drawings, in which:

[0029] Figure 1 is a spatiotemporal diagram of a minimal-delay fine-grained parallel Givens rotation method for ultra-large-scale matrix QR decomposition according to one embodiment of the present invention;

[0030] Figure 2 1. A schematic diagram of data dependencies between an outer loop and an inner loop of a minimally delayed fine-grained parallel Givens rotation method for ultra-large-scale matrix QR decomposition according to an embodiment of the present invention;

[0031] Figure 3 is a schematic flow chart of a method for performing minimum-delay fine-grained parallel Givens rotation for ultra-large-scale matrix QR decomposition according to an embodiment of the present invention;

[0032] Figure 4 1 is a space-time diagram of the prior art of the minimum delay fine-grained parallel Givens rotation method for ultra-large-scale matrix QR decomposition according to one embodiment of the present invention. DETAILED DESCRIPTION

[0033] In order to more clearly understand the above-mentioned objects, features and advantages of the present invention, the present invention is further described in detail below with reference to the accompanying drawings and specific embodiments. It should be noted that the embodiments of the present invention and the features therein can be combined with each other without conflict.

[0034] In the following description, many specific details are set forth to facilitate a full understanding of the present invention. However, the present invention may also be implemented in other ways different from those described herein. Therefore, the scope of protection of the present invention is not limited to the specific embodiments disclosed below.

[0035] like Figures 1 to 3 As shown, this embodiment provides a minimum delay fine-grained parallel Givens rotation method for ultra-large-scale matrix QR decomposition, which includes: an outer loop and an inner loop, the outer loop is responsible for calculating a row vector of the Q matrix and the R matrix, and the inner loop is responsible for the Givens rotation of the two row vectors.

[0036] The system architecture comprises a multi-level array of processing units (PEs), each of which houses an update factor calculation module and multiple element update modules. Through a collaborative pipeline design of outer and inner loops, this method significantly improves the efficiency of matrix QR decomposition, reduces hardware resource idleness and waiting time, and achieves efficient parallelization of operations.

[0037] In the outer loop, the outer loop block is first divided, and the outer loop of the matrix is ​​decomposed into several outer loop blocks. Each outer loop block contains multiple outer loop slices; each outer loop slice is calculated by a processing unit (PE unit).

[0038] During the QR decomposition process, the outer loop is responsible for updating each row vector of the Q and R matrices. To achieve parallel processing, the outer loop is decomposed into several outer loop blocks, each of which contains multiple outer loop slices. The computation of each outer loop slice is completed by a PE unit.

[0039] The execution order of the outer loop blocks is serial. After the first outer loop block completes the calculation, its result is used as the input of the second outer loop block, and the execution is serialized in sequence until the calculation of all outer loop blocks is completed.

[0040] Multiple outer loop slices within each outer loop block are cascaded to achieve pipelined parallel operation. The first-level PE unit receives initial matrix data from external memory and, after completing a partial update, immediately passes the intermediate results to the second-level PE unit, which then continues the calculation. This continues in this order, with each PE unit passing the intermediate data to the next level after completing its task, until the last PE unit completes its update and writes the results back to memory. This pipeline design significantly reduces waiting time between PE units, improving the system's overall computational efficiency.

[0041] The structure of the PE unit is designed. Each PE unit consists of an update factor calculation module (FAC_CAL) and an element update module (GR_UPD). The update factor calculation module (FAC_CAL) is responsible for calculating the update factor required for Givens rotation; the element update module (GR_UPD) is responsible for updating each element of the row vector.

[0042] The number of element update modules in each level of PE unit decreases gradually. Specifically, the first level PE unit contains n element update modules; the second level PE unit contains n-1 modules; the p-th level PE unit contains (n-p+1) modules; and the last level PE unit contains only 1 module.

[0043] This step-by-step design can not only save hardware resources, but also match the task volume of PE units at different levels to avoid resource waste.

[0044] Each PE unit is connected to adjacent units in a cascaded fashion. The first-level PE unit reads the matrix data to be processed from external memory and, after completing the update, passes the intermediate results to the next-level unit. Subsequent PE units immediately initiate calculations upon receiving the intermediate data from the previous unit, continuing until all row vectors within the outer loop block are updated.

[0045] Then in the inner loop, each PE unit further divides the outer loop slice it is responsible for into multiple inner loop slices, each of which contains the Givens rotation calculation task for two row vectors.

[0046] Each PE unit contains multiple element update modules, which are cascaded to realize pipeline parallel calculation of the inner loop slice. The specific operations are as follows: after the first-level element update module receives data from the update factor calculation module, it immediately starts the Givens rotation operation and updates some elements of the two row vectors; the subsequent element update modules receive the output data of the previous module step by step and continue the update operation until the update of all row vectors is completed; the last-level element update module stores the updated row vectors in the on-chip memory (BRAM) to provide input for subsequent calculations.

[0047] The element update module in the PE unit adopts a multi-pipeline parallel computing method. The n PE element update modules in the PE unit responsible for the i-th outer loop slice realize the multi-pipeline parallelism of an inner loop block in the following way:

[0048] In the first inner loop block, the first-level element update module performs Givens rotation on the i-th vector and the (i+1)-th vector received by the current PE unit; in the s-th inner loop block, the first-level element update module performs Givens rotation on the (i+n×(s-1)+1)-th vector received by the current PE unit and the i-th vector stored in the on-chip memory in the (s-1)-th inner loop block; the k-th level element update module (k≠1) performs Givens rotation on the (i+k)-th vector received by the current PE unit and the (k-1)-th level element update module of the current PE unit. The i-th vector updated by the module performs a Givens rotation; the k-th level PE unit passes the updated i-th vector to the (k+1)-th level element update module of the current PE unit, and passes the (i+k)-th vector to the PE unit responsible for the (i+1)-th outer loop slice; the n-th level element update module saves the updated i-th vector in the on-chip memory for the calculation of the next inner loop block; each inner loop block is executed serially, and after the calculation of the previous inner loop block is completed, the calculation of the next inner loop block is started until the calculation of all inner loop blocks is completed.

[0049] The results of the inner loop slices are stored in on-chip memory, reducing the frequency of access to off-chip memory and optimizing data transfer efficiency. In addition, the serial execution of the inner loop slices ensures that the next loop slice can be started immediately after the current loop slice completes its calculation.

[0050] Before the outer loop and the inner loop work together, the system first performs data initialization operations: the ultra-large-scale matrix is ​​divided into blocks for processing, and the data of each block is stored in the external memory. The first-level PE unit reads the initial data from the external memory and starts the calculation.

[0051] In the collaborative work of the outer loop and the inner loop, the pipeline parallel design of the outer loop slice ensures the continuous data flow between PE units, and the pipeline parallel processing of the inner loop slice improves the computing efficiency within a single PE unit. The final result is written back to the external memory by the last-level PE unit for subsequent use.

[0052] like Figure 1The figure shows a time-space diagram of the minimum-delay fine-grained parallel Givens Rotation method in the present invention. This diagram takes an existing fine-grained parallel model containing three PE units as an example. Since the method in the present invention uses a parallel computing mode when processing inner loop slices, the startup conditions of the PE unit responsible for computing the (i+1)th outer loop slice are:

[0053] The PE unit responsible for the i-th outer loop slice calculates A(i+1,i+1) when performing Givens rotation on the i-th and (i+1)-th row vectors.

[0054] The PE unit responsible for the i-th outer loop slice calculates A(i+2,i+1) when performing Givens rotation on the (i+2)-th row vector and the i-th vector updated by the current-level PE unit.

[0055] Figure 4 For the update factors and element update time of the existing conventional cycle, the latter PE unit needs to wait for the previous level operation to complete before it can start the operation. Figure 1 and Figure 4 As can be seen, after the pipelined parallel operation of the inner loop slice, the critical data required for PE unit startup can be generated in advance, significantly shortening the waiting time for subsequent PE units to start and reducing the idle rate of PE units. As the matrix size increases, the number of PE array cycles also increases, and the role of this model in reducing latency and improving QR decomposition efficiency will become more significant.

[0056] In summary, the present invention proposes a minimum delay fine-grained parallel Givens rotation method for ultra-large-scale matrix QR decomposition, including: the method includes: an outer loop and an inner loop, the outer loop is responsible for the calculation of a row vector of the Q matrix and the R matrix, and the inner loop is responsible for the Givens rotation of the two row vectors.

[0057] The outer loop of the matrix is ​​decomposed into several outer loop blocks, each of which contains multiple outer loop slices; each outer loop slice is calculated by a PE unit.

[0058] Each PE unit is connected in a cascade manner and processes the computational tasks of the outer loop slice in parallel through a pipeline within the outer loop block; each PE unit contains an update factor calculation module and several element update modules, which are responsible for the computational tasks of the inner loop slice; the element update module completes the Givens rotation calculation of the inner loop slice through a pipeline parallel manner.

[0059] The steps in the present invention can be adjusted in sequence, combined, or deleted according to actual needs.

[0060] The units in the device of the present invention can be combined, divided and deleted according to actual needs.

[0061] Although the present invention has been disclosed in detail with reference to the accompanying drawings, it should be understood that these descriptions are merely illustrative and are not intended to limit the application of the present invention. The scope of the present invention is defined by the appended claims and includes various modifications, variations, and equivalents made to the invention without departing from the scope and spirit of the present invention.

Claims

1. Minimum delay fine-grained parallel Givens rotation method for ultra-large-scale matrix QR decomposition, characterized by: The method utilizes an operation architecture having an outer loop and an inner loop to perform matrix decomposition, wherein the outer loop is responsible for calculating a row vector of a Q matrix and an R matrix, and the inner loop is responsible for performing a Givens rotation on the two row vectors; When performing QR decomposition on a very large matrix, the outer loop of the matrix is ​​decomposed into several outer loop blocks, each of which contains multiple outer loop slices. Each outer loop slice is calculated by a PE unit and is responsible for updating a row vector of the matrix. Each PE unit is connected sequentially in a cascade manner and processes the computational tasks of the outer loop slice in parallel within the outer loop block. The first-level PE unit reads the initial matrix row vector from the external memory and updates it. Each subsequent PE unit starts the computation immediately after receiving the partial intermediate results generated by the previous-level PE unit, updates the row vector it is responsible for, and passes the intermediate results to the next-level PE unit in real time until all computational tasks of the outer loop block are completed. Each PE unit further divides the outer loop slice into multiple inner loop slices. Each PE unit contains an update factor calculation module and several element update modules. Each inner loop slice is responsible for performing the Givens rotation operation on two row vectors in the matrix. After the update factor calculation module calculates the Givens rotation factor, it directly passes the data to the element update module. The element update module processes part of the update task of the current row vector step by step and passes the intermediate data to the next level PE unit in real time. The next level element update module receives the data generated by the previous level element update module step by step and starts the operation in real time to complete all the calculation tasks of the inner loop slice. After all PE units complete the above calculations, the updated results generated by the last-level PE unit are written into the off-chip memory for storage.

2. The ultra-large-scale matrix QR decomposition minimum delay fine-grained parallel Givens rotation method according to claim 1, characterized in that: The number of element update modules in each PE unit decreases step by step, specifically: The first-level PE unit contains n element update modules; the second-level PE unit contains n-1 element update modules; the p-th level PE unit contains (n-p+1) element update modules; and the last-level PE unit contains only 1 element update module.

3. The ultra-large-scale matrix QR decomposition minimum delay fine-grained parallel Givens rotation method according to claim 2, characterized in that: The first-level PE unit reads the initial matrix data from the off-chip memory. The remaining PE units receive and start calculations immediately after the intermediate calculation data is generated by the previous-level PE unit. The last-level PE unit writes the calculation results back to the off-chip memory to provide input data for the subsequent outer loop blocks.

4. The ultra-large-scale matrix QR decomposition minimum delay fine-grained parallel Givens rotation method according to claim 1, characterized in that: The outer loop block is executed in a serial manner. After all the outer loop slices of an outer loop block are calculated, the calculation of the next outer loop block is started. Inside the outer loop block, PE units execute the computational tasks of the outer loop slice in parallel through cascading.

5. The ultra-large-scale matrix QR decomposition minimum delay fine-grained parallel Givens rotation method according to claim 1, characterized in that: The n PE element update modules in the PE unit responsible for the i-th outer loop slice implement parallel computation of an inner loop block in the following way: In the first inner loop block, the first-level element update module performs Givens rotation on the i-th vector and the (i+1)-th vector received by the current PE unit; the updated i-th vector is passed to the second-level element update module of the PE unit, and the (i+1)-th vector is passed to the PE unit responsible for updating the (i+1)-th vector; In the s-th inner loop block, the first-level element update module performs Givens rotation on the (i+n×(s-1)+1)-th vector received by the current PE unit and the i-th vector stored in the on-chip memory in the (s-1)-th inner loop block; The k-th level element update module (k≠1) performs Givens rotation on the (i+k)-th vector received by the current PE unit and the i-th vector updated by the (k-1)-th level element update module of the current PE unit; The k-th PE unit passes the updated i-th vector to the (k+1)-th element update module of the current PE unit, and passes the (i+k)-th vector to the PE unit responsible for the (i+1)-th outer loop slice; The n-th level element update module saves the i-th vector generated by the update in the on-chip memory for the calculation of the next inner loop block; Each inner loop block is executed serially. After the calculation of the previous inner loop block is completed, the calculation of the next inner loop block is started until the calculation of all inner loop blocks is completed.

6. The ultra-large-scale matrix QR decomposition minimum delay fine-grained parallel Givens rotation method according to claim 5, characterized in that: The intermediate vectors calculated by the non-last-level PE units are passed to the next-level PE units through the data path; the intermediate vectors calculated by the last-level PE units are stored in the off-chip memory to provide input for the calculation of the subsequent outer loop blocks; The vector updated by the givens rotation performed by the non-last-level element update module in the inner loop is passed to the next-level element update module, and the i-th vector updated by the last-level element update module is stored in the on-chip memory.

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