A RISC-V architecture-based encryption and decryption circuit system and method

Abstract

The application discloses a kind of based on RISC-V architecture's encryption and decryption circuit system and method, to accelerate encryption and decryption process while improving resource utilization, and enhance the real-time and versatility of encryption and decryption operation in embedded system, in combination with the extensible characteristics of control and state register (CSR) in RISC-V instruction set privilege architecture, the process of input and output data is accelerated by privilege instruction and extension privilege register configuration mode and, the working configuration of encryption and decryption circuit is completed by privilege register configuration module, the start of encryption and decryption calculation is controlled by encryption and decryption global control module and encryption and decryption calculation control module, and according to different algorithm, the state machine of three kinds of algorithms is started to control the flow of calculation, and in combination with the general computing resource deployed in computing path, various complex operations in calculation process are realized, so as to increase the utilization rate of logic resource, meet the encryption and decryption demand of different application scenarios.

Description

Technical Field

[0001] The present invention belongs to the field of information security technology, and specifically relates to an encryption and decryption circuit system and method based on the RISC-V architecture. Background Art

[0002] With the rapid development of IoT technology, the demand for data storage, processing, and transmission between devices continues to increase. Advances in information technology have led to more frequent digital information exchange, but this has also posed more serious security risks. Ensuring the security of digital information has become a critical issue, and data encryption is a key means of ensuring this. While software encryption plays a vital role in data protection, hardware-level security solutions are equally crucial, ensuring more reliable and secure communications for IoT devices.

[0003] Against this backdrop, RISC-V, an open-source instruction set architecture, has garnered widespread attention and adoption worldwide thanks to its simple design, flexible scalability, and lack of patent licensing. RISC-V's open-source nature allows developers to freely customize the architecture based on specific needs, lowering the barrier to entry and cost of chip design and providing high scalability for diverse application scenarios. Furthermore, RISC-V greatly facilitates the expansion of cryptographic algorithms and other complex functions by defining CSR instructions and CSR registers (control status registers). This design makes it possible to expand cryptographic algorithm-specific registers and instructions on the RISC-V architecture, enabling hardware-level acceleration of cryptographic algorithms and meeting the dual requirements of high performance and low power consumption.

[0004] In modern digital system design, resource sharing and reuse strategies are of profound significance. Sharing hardware resources across multiple modules or functions not only significantly reduces system hardware complexity and production costs, but also significantly improves resource utilization, allowing the same hardware resources to serve different functions at different times, thereby enhancing overall system efficiency. This approach also effectively reduces power consumption, avoids resource waste, simplifies system scheduling and management, and enhances design flexibility to meet the dynamic demands of complex computing scenarios.

[0005] The AES algorithm is generally the best choice for data encryption. However, as the core element of the encryption process, the security of the key is also crucial. The ECC algorithm ensures key security during communication, particularly during the key exchange phase, effectively preventing malicious attackers from tampering with data. Furthermore, the SHA algorithm further ensures data integrity and security. In blockchain technology, SHA is widely used to ensure the immutability and transparency of transaction data. Its collision resistance and efficient computation have made blockchain a core technology in multiple industries, including finance, supply chain, and smart contracts, driving innovation and development in these fields.

[0006] By combining the Internet of Things, RISC-V, cryptographic algorithms, and shared resources and reuse strategies, not only can the overall performance and security of the system be improved, but a solid foundation can also be laid for future technological innovation and applications. Summary of the Invention

[0007] To address the shortcomings of the existing technology, achieve the purpose of accelerating the encryption process while reducing energy consumption during encryption and decryption, improving resource utilization, and enhancing the real-time and versatility of encryption and decryption operations in embedded systems, the present invention adopts the following technical solutions:

[0008] A RISC-V architecture-based encryption and decryption circuit system includes a privileged register configuration module, a temporary variable storage module, an encryption and decryption global control module, an encryption and decryption calculation control module, a digest algorithm control module, a symmetric algorithm calculation module, an asymmetric algorithm control module, and a computing resource data path module. The system is characterized in that the privileged register configuration module is connected to the encryption and decryption calculation control module via the encryption and decryption global control module and is also connected to the computing resource data path module for encryption and decryption data exchange and status return. The encryption and decryption calculation control module is connected to the global calculation path module after passing through the digest algorithm control module, the symmetric algorithm control module, and the asymmetric algorithm control module, respectively, to enable inference calculations of different algorithms and working modes.

[0009] Privileged register configuration module, used to obtain privileged CSR instructions, configure encryption and decryption working modes, and input and output encryption and decryption data;

[0010] Temporary variable storage module, used to temporarily store the calculation results of round operations during the calculation process;

[0011] The global encryption and decryption control module is used to shield software write operations during encryption and decryption operations to ensure the normal operation of the encryption and decryption circuits;

[0012] The encryption and decryption calculation control module is used to start inference calculations of different algorithms and different working modes according to register status information;

[0013] The digest algorithm control module is used to control the digest hash algorithm calculation process and record work information, and call the computing resources required by the digest hash algorithm;

[0014] Symmetric algorithm control module, used to control the symmetric algorithm calculation process and record work information, and call the computing resources required by the symmetric algorithm;

[0015] Asymmetric algorithm control module, used to control the asymmetric calculation process and record work information, and call the computing resources required by the asymmetric algorithm;

[0016] The global computing path module is used to deploy a large number of general computing resources and multiplexers to complete complex computing resource combinations based on state information.

[0017] Furthermore, the privileged register configuration module includes a parsing module, a general register read and write interface, and an extended register group. The privileged instruction obtained is a CSR (Control and Status Registers) instruction, which is used to read the data of the general register and write it to the CSR register of the interface in the original format / set / clear form. The data in the CSR register is written to the general register of the write-back register index. Through the read and write operations on the general register, the read and write interface of the general register is extended, and read and write signals, read register index, and write register index are provided to integrate this encryption and decryption circuit into any processor; after the CSR instruction is translated by the parsing module, a read signal and a write signal are generated as well as the index of the privileged register that needs to be operated in this cycle to configure and read the extended register group.

[0018] Furthermore, the extended register includes a control register, a status register, an input register, an output register, a key register, an elliptic curve A parameter register, an elliptic curve B parameter register, a modulus register, a generation point register, and a random number register. The control register is used to configure the working mode of the encryption and decryption circuit, the status register is used to reflect the operating status of the encryption and decryption circuit, the input register is used to input the data to be encrypted or decrypted into the encryption and decryption circuit, the output register is used to read the encrypted data or decrypted data after completing the encryption or decryption work, the key register is used to obtain the key required for use in the encryption process, the elliptic curve A parameter register is used to implement the configuration of parameter A in the elliptic curve, the elliptic curve B parameter register is used to implement the configuration of parameter B in the elliptic curve, the modulus register is used to determine the modulus used when performing elliptic curve operations, the generation point register is used to determine the generation point of the elliptic curve, and the random number register is used to use random numbers for encryption during the encryption process.

[0019] Furthermore, the encryption and decryption circuit supports encryption and decryption of SHA256, AES128, and ECC256. By decomposing the special calculations in the calculation process of the three algorithms, the integrated general computing resources are time-division multiplexed, and combined with the MUX unit attached to each logic resource, multiple computing resources are connected by a state machine control to constitute special operations in the encryption or decryption process, so that resources can be shared in multiple security algorithms and multiple working modes, and the data flow and data path are controlled only by control signals, thereby greatly reducing the integration of logic resources.

[0020] Furthermore, the encryption and decryption circuit system based on the RISC-V architecture is characterized in that the encryption and decryption circuit can implement the encryption mode of the SHA256 algorithm, the encryption mode and decryption mode of the AES128 algorithm, and the encryption mode and decryption mode of the ECC256 algorithm.

[0021] Furthermore, the single-round encryption module of the SHA256 algorithm includes: Ch function, ∑0 function, Maj function, ∑1 function, σ0 function, σ1 function, 32-bit addition operation, circular right shift operation, and logical right shift operation. The single-round operation is executed in only one clock cycle.

[0022] The Ch function consists of 32-bit negation, AND operation, and XOR operation of three variables. The encryption and decryption circuit calls the 32-bit negation operation unit, 32-bit AND operation unit, and 32-bit XOR operation unit logic unit. The input of the 32-bit XOR operation resource is controlled by the state machine as the output of two 32-bit AND operation units. The input of one 32-bit AND operation unit is the first and second independent variables of the Ch function, and the input of the other 32-bit AND operation unit is the result of the negation of the first independent variable and the third independent variable. Its logic function is:

[0023]

[0024] The Maj function designs a 32-bit AND operation and XOR operation on three variables. This function is implemented by calling a 32-bit AND operation unit and a 32-bit XOR operation unit. The state machine controls the first 32-bit AND operation unit to input the first and second independent variables, the second 32-bit AND operation unit to input the first and third independent variables, and the third 32-bit AND operation unit to input the second and third independent variables. Its logic function is:

[0025]

[0026] The ∑0 function involves three different times of circular right shift operations on a variable and the sequential exclusive OR of the results. This function is implemented by calling three circular right shift units and two 32-bit exclusive OR units. The circular right shift module in the data path can select different circular right shift units, which are configured as circular right shifts of 1 bit, 13 bits, and 22 bits according to the state machine configuration. Its logic function is:

[0027]

[0028] The ∑1 function involves three different times of circular right shift operations on a variable and the sequential exclusive OR of the results. This function is implemented by calling three circular right shift units and two 32-bit exclusive OR units. The circular right shift module in the data path can select different circular right shift units, which are configured as 6-bit, 11-bit, and 25-bit circular right shifts according to the state machine. Its logic function is:

[0029]

[0030] The σ0 function involves two different times of circular right shift operations and one logical right shift operation on a variable, as well as the sequential exclusive OR of the results. This function is implemented by calling two circular right shift units, one logical right shift, and two 32-bit exclusive OR units. The circular right shift module in the data path can select different circular right shift units, which are respectively configured as 7-bit circular right shift, 18-bit circular right shift, and 3-bit logical right shift according to the state machine configuration. Its logic function is:

[0031]

[0032] The σ1 function involves two different times of circular right shift operations and one logical right shift operation on a variable, as well as the sequential exclusive OR of the results. This function is implemented by calling two circular right shift units, one logical right shift, and two 32-bit exclusive OR units. The circular right shift module in the data path can select different circular right shift units, which are respectively configured as 17-bit circular right shift, 19-bit circular right shift, and 10-bit logical right shift according to the state machine configuration. Its logic function is:

[0033]

[0034] The encryption process divides 256-bit data into 32-bit blocks and performs multiple encryption operations. This encryption process is achieved by calling multiple adders. The circular right shift operation is a circular right shift of the result after a single round of encryption and then stored in a temporary variable register file. The encryption and decryption calculation control module of the encryption and decryption circuit directly and intermittently stores the data returned by the data path module, thereby replacing the circular right shift operation.

[0035] The message expansion process will perform message expansion according to the round information recorded in the digest algorithm module. The original message is stored in the register stack of the privileged register. After the extended message is calculated, it is stored in the temporary variable register. The calculation process is to add two original messages, the result of one message after the σ0 function operation, and the result of one message after the σ1 function operation in sequence. It needs to call three 32-bit addition units. The message expansion function is:

[0036] W j =σ1(W j-2 )+W j-7 +σ0(W j-15 )+W j-16 ,forj=16→63

[0037] Furthermore, the single-round encryption module of the AES128 algorithm includes a byte substitution module, a row shift module, a column obfuscation module, and a round key addition module. The AES128 last-round single-round encryption module includes a byte substitution module, a row shift module, and a round key addition module. The encryption and decryption calculation control module calculates the encryption rounds and generates different data paths in the last round to avoid column mixing.

[0038] The single-round decryption module of the AES128 algorithm includes: an inverse byte substitution module, a reverse row displacement module, an inverse column obfuscation module, and a round key addition module. The last-round single-round decryption module includes an inverse byte substitution module, a reverse row displacement module, and a round key addition module. The encryption and decryption calculation control module calculates the encryption rounds and generates different data paths in the last round to avoid inverse column mixing.

[0039] The key expansion module of the AES128 algorithm first inputs the initial key into a 4×4 state matrix. The 4 bytes in each column of this 4×4 matrix form a word. The 4 words in the 4 columns of the matrix are named W[0], W[1], W[2] and W[3] in sequence. They form an array W in word units. The key expansion module expands the W array by 40 new columns to form an extended key array. If i is not a multiple of 4, then the i-th column is determined by the following equation:

[0040]

[0041] If i is a multiple of 4, then the i-th column is determined by the following equation:

[0042]

[0043] The T function transformation is a process of word rotation, byte substitution, and round constant XOR. The word rotation is a byte shift left, the byte substitution is the same as the byte substitution in the round operation, and the round constant is a process of XORing according to different round numbers and different constants.

[0044] The byte substitution and reverse byte substitution modules use GF(2 8 ) on the subfield algorithm, the computational process is essentially based on GF(2 8 ) based on the inversion operation of irreducible polynomials and the linear operation of matrices on the extended field, in the encryption and decryption circuit, GF(2 8 ) is transformed into the inverse algorithm on the extended field of GF(2 4 ) inverse process on the extended domain of GF(2 4 ) is directly implemented using a logic function on the extended domain. The conversion process involves single-bit AND and single-bit XOR operations. The essence of the calculation process of these transformations on the extended domain is AND or XOR operations between specific bits. Each bit of the 32-bit XOR calculation unit deployed in the data calculation path is an independent calculation process, which converts the complex operation in the byte substitution into a universal operation for each bit, thereby realizing the complex operation. The difference between the inverse byte substitution process and the byte substitution is that the specific bits of the linear transformation are different. The data calculation path receives the control signal of the symmetric encryption control module and constructs different data paths to achieve different linear transformations, thereby realizing the inverse byte substitution.

[0045] The row shift and reverse row shift modules, taking into account that the data input to the data path module is executed on a column basis, while the row shift and reverse row shift are executed on a row basis, will first perform column conversion before performing row shift, then reuse the circular shift logic resources of the data calculation path to implement row shift, and then perform the reverse row-column conversion process after the row shift to obtain the row shift result;

[0046] The column mixing module, the essence of which is to perform multiple XOR operations on bytes, considers that a 32-bit XOR device resource is four 8-bit XOR devices, and column mixing and inverse column mixing are repeated processes. The XOR resources integrated in the calculation path module realize column mixing through data flow control, and save logic resources by reusing the results of forward column mixing;

[0047] The round key adding module operates on the principle of XOR operation, and the encryption and decryption circuit directly reuses XOR resources to implement round key addition;

[0048] The key expansion module, all XOR operations are implemented by multiplexing 32-bit XOR calculation units in the calculation path, the row shift process in the T function is multiplexed with the cyclic shift module in the calculation path, the byte substitution module is multiplexed with the byte substitution module in the round calculation process, the essence of the round constant is an algorithm of sequentially multiplying X in each round in the extension field, the encryption and decryption circuit directly implements the transformation process of each bit after each round of multiplication X operation, and the performance is the XOR operation process of different bits, which directly multiplexes the XOR calculation unit of the calculation path;

[0049] Further, the encryption process of the ECC256 algorithm uses a random number as a coefficient, performs point multiplication operation on a point represented by a public key on an elliptic curve, and performs point addition operation on the obtained point and a point represented by plaintext to obtain ciphertext 1, wherein the random number is used to perform point multiplication operation on a generator point to obtain ciphertext 2;

[0050] The decryption process of the ECC256 algorithm uses the private key to perform point multiplication operation on the result 1 of the key 2, and then uses the ciphertext 1 to perform point addition operation on the result 1 to obtain plaintext;

[0051] The ECC256 algorithm module includes: an elliptic curve point addition operation module, an elliptic curve multiple point operation, an elliptic curve point multiplication operation, and 256-bit modulo addition, modulo subtraction, modulo multiplication, and modulo inverse operation;

[0052] The modulo addition operation module is a 256-bit addition operation, and a prime number P is subjected to a modulo operation. The encryption and decryption circuit implements the function of 256 addition by multiplexing the 32-bit adder through the increase of the carry output, the carry input and the mode selection of addition and subtraction of the 32-bit adder through the state machine, and the modulo operation is a subtraction operation of the result after addition and the modulus from high 32 bits to low 32 bits in turn. When the carry output is found, it is judged whether the number is greater than the modulus. If it is greater than the modulus, the subtraction operation is initiated and the cycle is restarted. If there is no carry output, it means that the number is less than the modulus, and then the modulo operation is completed;

[0053] The modulo subtraction operation module needs to judge the size relationship of the two numbers to be subtracted first. First, the subtraction operation is performed in turn. If the carry output is found in the subtraction process, it means that the minuend is smaller than the subtrahend, and the order of the two numbers is exchanged to perform the subtraction operation again. Then the modulo operation is performed. If there is no carry output in the subtraction operation process, the modulo operation is directly performed;

[0054] The modular multiplication module uses the Montgomery modular reduction algorithm to calculate the modular multiplication operation. First, the actual calculation process of the 256-bit multiplier is analyzed based on the 32-bit multiplier, and the operation process of each 32 bits of the actual result is calculated, thereby realizing the 256-bit multiplication operation. In the process of modular multiplication, it is necessary to first implement the 32-bit modular reduction algorithm, and then each 32-bit word of the 256 bits is sequentially and finally spliced ​​together to obtain the 256-bit modular multiplication result.

[0055] The modular inverse calculation module uses an extended Euclidean algorithm to calculate the modular inverse, which makes better use of hardware implementation from the perspective of hardware implementation;

[0056] The essence of the point addition operation module is to obtain the horizontal and vertical coordinates of the coordinate point symmetrical about the x-axis of the intersection of the line connecting the two points and the elliptic curve, realize the modular addition, modular subtraction, modular multiplication, and modular inverse operations of the selectively calling data path module, and implement the point addition algorithm in combination with ECC, where (x1, y1) and (x2, y2) represent the two base points P1 and P2 of the point addition operation, and (x3, y3) represent the result coordinates;

[0057] x3=λ 2 -x1-x2

[0058] y3=λ(x1-x3)-y1

[0059]

[0060] The essence of the point doubling operation module is to obtain the horizontal and vertical coordinates of the coordinate point symmetrical about the x-axis of the intersection of a tangent line and an elliptic curve, realize the modular addition, modular subtraction, modular multiplication, and modular inverse operations of the selectively called data path module, and implement the point doubling algorithm in combination with ECC, where (x1, y1) represents the base points P1 and P2 of the point doubling operation, and (x3, y3) represents the result coordinates;

[0061] x3=λ 2 -2x1

[0062] y3=λ(x1-x3)-y1

[0063]

[0064] The essence of the point multiplication operation module is to obtain the doubling point, connect the coordinates of the intersection of the starting point and the doubling point with the elliptic curve about x as a new point, connect the starting point and the new point and the coordinate point symmetrical about the x-axis with the intersection of the elliptic curve as a new point, and so on to realize point multiplication, and use the binary coding algorithm to reduce the complexity of the operation, convert the coefficients of the point multiplication into binary form, and judge whether each bit is "1" in turn starting from the highest bit. If it is "1", a point addition operation is performed, and a doubling operation is performed after each judgment, and then it is used as the base point for the next point addition.

[0065] Furthermore, the encryption and decryption circuit system based on the RISC-V architecture performs encryption and decryption, including the following steps:

[0066] Step 1: Configure the privileged register, continuously send privileged instructions to the encryption and decryption circuit to implement the configuration of the state. The privileged instructions are executed in a pipeline during the execution process. The configuration work includes inputting the key, inputting the plaintext or ciphertext, configuring the encryption or decryption mode, configuring the encryption or decryption algorithm to be used, configuring the generator register, configuring the random number register, and finally enabling the encryption and decryption circuit to start calculation;

[0067] Step 2: After encryption or decryption is completed, the encryption and decryption circuit will perform encryption and decryption operations. Depending on the algorithm and working mode, the calculation completion information is obtained by checking the interrupt signal or the flag bit on the status register;

[0068] Step 3: After detecting that the interrupt signal is set or the calculation completion flag in the status register is set, read the data in the output register; when the data reading operation is completed, the calculation enable signal is automatically cleared.

[0069] The advantages and beneficial effects of the present invention are:

[0070] The hardware implementation of the encryption algorithm in the present invention has significant advantages over software implementation. First, in terms of performance, the hardware accelerator can execute multiple computing tasks in parallel, greatly improving the speed of encryption and decryption, especially when processing big data. Second, the hardware implementation reduces the intermediate steps of the calculation and the delay of data transmission through dedicated circuits, significantly reducing the energy consumption of the system. Therefore, it is more efficient than the existing encryption and decryption calculations based on software implementation.

[0071] The present invention adopts RISC-V privileged instructions to simplify the algorithm configuration process, reduce the operations that need to be executed multiple times through general instructions, and reduce the number of memory accesses, thereby significantly reducing energy consumption, so that the system can maintain low power consumption characteristics while processing data efficiently, and is particularly suitable for embedded systems and Internet of Things devices; the logic resource sharing technology adopted by the present invention avoids the hardware from being specially designed for a specific task; therefore, compared with the existing hardware deployment based on a single encryption and decryption algorithm, the present invention has lower power consumption and higher resource utilization. BRIEF DESCRIPTION OF THE DRAWINGS

[0072] Figure 1 2 is a diagram of the system hardware architecture of an embodiment of the present invention.

[0073] Figure 2 Flowchart of a method according to an embodiment of the present invention.

[0074] Figure 3 Schematic diagram of register function coding and indexing in an embodiment of the present invention.

[0075] Figure 4 Schematic diagram of the state machine jump of the digest algorithm in an embodiment of the present invention.

[0076] Figure 5 Schematic diagram of summary algorithm control and data interaction in an embodiment of the present invention.

[0077] Figure 6 This is a schematic diagram of the state machine jump of the symmetric encryption algorithm in an embodiment of the present invention.

[0078] Figure 7 Schematic diagram of symmetric algorithm control and data interaction in an embodiment of the present invention.

[0079] Figure 8 Schematic diagram of the state machine jump of the asymmetric encryption algorithm in an embodiment of the present invention.

[0080] Figure 9 Schematic diagram of asymmetric algorithm control and data interaction in an embodiment of the present invention. DETAILED DESCRIPTION

[0081] The following describes the specific embodiments of the present invention in detail with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are only used to illustrate and explain the present invention and are not intended to limit the present invention.

[0082] like Figure 1 As shown, an encryption and decryption circuit system based on the RISC-V architecture includes a privileged register configuration module, a temporary variable storage module, an encryption and decryption global control module, an encryption and decryption calculation control module, a digest algorithm control module, a symmetric encryption algorithm calculation module, an asymmetric algorithm control module, and a global calculation path module;

[0083] Privileged register configuration module, for user input privileged CSR instruction, configuration encryption and decryption mode and input and output encryption and decryption data;

[0084] Temporary variable storage module, for temporary storage of the calculation results of the round operation during the calculation process;

[0085] Encryption and decryption global control module, for shielding software write operation during encryption and decryption operation process, ensuring normal operation of encryption and decryption circuit.

[0086] Encryption and decryption calculation control module, for starting inference calculation of different algorithms and different working modes according to register state information;

[0087] Abstract algorithm control module, for controlling hash algorithm calculation process and recording working information, calling required calculation resources of hash algorithm;

[0088] Symmetric algorithm control module, for controlling symmetric algorithm calculation process and recording working information, calling required calculation resources of symmetric algorithm;

[0089] Asymmetric algorithm control module, for controlling asymmetric calculation process and recording working information, calling required calculation resources of asymmetric algorithm;

[0090] Global calculation channel module, for deploying a large number of general-purpose calculation resources and multi-channel selectors, and completing complex calculation resource combination according to state information.

[0091] As shown in Figure 2 , the software transmits encryption and decryption circuit working mode configuration information, including encryption and decryption algorithm configuration, encryption and decryption working mode configuration, encryption and decryption circuit interrupt enable configuration, error interrupt enable configuration, by sending CSR instruction to the privileged register module of the encryption and decryption circuit, and transmits encryption and decryption data information, including encryption and decryption data, encryption and decryption key, and elliptic curve A parameter, elliptic curve B parameter, modulus, generator point, random number required in asymmetric algorithm;

[0092] The configurations required to be completed depend on the privileged CSR instruction characteristics of RISC-V architecture. The specific behavior of CSR instruction is to read the data in general register, write the data in general register to CSR register in the form of original format / set / clear, and then write the data in the CSR register to the general register with write-back register index;

[0093] This module expands the read-write interface of general register for general register read-write operation, and provides read-write signal, read register index and write register index to integrate the encryption and decryption circuit into any processor;

[0094] For the configuration of extended registers, this module sets up an internal extended register group. After translating the CSR instruction, this module will generate read and write signals and the index of the privileged register that needs to be operated in this cycle, so as to configure and read the extended register group.

[0095] After completing the configuration of the parameter information, the software needs to be configured to start the software. After starting, the privileged register configuration module will instruct the encryption and decryption global control module to enter the start calculation state. When the encryption and decryption global control module enters the start calculation state, it will send a shielding signal to the privileged register configuration module, indicating that all write register behaviors in the privileged register configuration module are shielded. This is done to prevent the software from rewriting data when the hardware is performing calculations, which may cause errors in the final encryption and decryption calculation results.

[0096] After the encryption and decryption global control module enters the start-up calculation state, the module will also instruct the encryption and decryption calculation control module to start a specific calculation mode, including digest algorithm encryption mode, symmetric algorithm encryption mode, symmetric algorithm decryption mode, asymmetric algorithm encryption mode, and asymmetric algorithm decryption mode; when entering the digest algorithm calculation mode, the encryption and decryption calculation control module will send an enable signal to the digest algorithm control module, and the digest algorithm control module will obtain control of the calculation data path, and then rebuild the calculation data path during the calculation process to complete the privileged calculation in the calculation process; when entering the symmetric algorithm calculation mode, the encryption and decryption calculation control module will send an enable signal to the symmetric algorithm control module, and the symmetric algorithm control module will obtain control of the calculation data path, and then rebuild the calculation data path during the calculation process to complete the special calculation in the calculation process; when entering the asymmetric algorithm calculation mode, the encryption and decryption calculation control module will send an enable signal to the asymmetric algorithm control module, and the asymmetric algorithm control module will start multiple internal state machines and complete the asymmetric algorithm calculation through some algorithm combinations. During this process, the asymmetric algorithm control module will also call computing resources in some calculation data paths;

[0097] After configuring the encryption and decryption circuit and starting calculations, the software can obtain the calculated data in two ways. The first is to continuously read the calculation completion status bit in the status register. When the calculation completion status bit is found to be "1", the software can start reading the value in the output register. The output register value to be read varies depending on the configured algorithm. The other way is to obtain the interrupt response of the encryption and decryption circuit. When the software receives the interrupt response notification from the encryption and decryption circuit, it can start reading the value in the output register to obtain the result data.

[0098] like Figure 3As shown, the extended register configuration module extends 10 privileged registers in machine mode, namely the control register, status register, input register, output register, key register, elliptic curve A parameter register, elliptic curve B parameter register, modulus register, generator point register, and random number register. Its function is that the control register is used to configure the working mode of the encryption and decryption circuit, the status register is used to reflect the operating status of the encryption and decryption circuit, the input register is used to input the data to be encrypted or decrypted into the encryption and decryption circuit, the output register is used to read the encrypted data or decrypted data after the encryption or decryption is completed, the key register is used to obtain the key required for use in the encryption process, the elliptic curve A parameter register is used to configure the parameter A in the elliptic curve, the elliptic curve B parameter register is used to configure the parameter B in the elliptic curve, the modulus register is used to determine the modulus used in the elliptic curve operation, the generator point register is used to determine the generator point of the elliptic curve, and the random number register is used to use random numbers for encryption during the encryption process; at the same time, the index of the privileged register is customized, and the user uses the CSR instruction and the index of each register to locate the privileged register.

[0099] like Figure 4 As shown in the figure, when the user configures the working mode to SHA256 encryption working state, the encryption and decryption calculation control module will control the digest algorithm control module to enter the calculation state. The state machine of the digest algorithm calculation control module starts in IDLE and then jumps to SHA256_ENCRYPT to start the SHA256 algorithm encryption operation. The SHA256 algorithm requires 64 rounds of encryption operations.

[0100] After completing 64 rounds of SHA256 encryption calculation, the state of the digest algorithm control module will jump to SHA256_UPDATE, perform the superposition operation of the calculation result and the initial key, update the ciphertext output register group, and set the calculation completion flag. Then it will jump to the FINISH state and wait for the software to read the encrypted data. After the reading is completed, the software clears the enable end, the digest algorithm control module jumps back to the IDLE state, and the encryption and decryption global control module and the encryption and decryption calculation control module return to the default state.

[0101] like Figure 5 As shown, the global calculation control module will control the digest algorithm state machine that starts the digest algorithm calculation control module. After the startup is completed, the digest algorithm calculation state machine will send a path construction signal and a round signal to the calculation data path. The calculation data path will construct different data paths according to the different signals.

[0102] In the encryption process, a key is used in each round, the key is natural number '0' starting to increase, the binary representation of the decimal point of the cube root of each prime number is 32 bits, a total of 64 primes; after the compression of the first block message is completed, it needs to be superimposed with an initial message, the initial message is natural number '0' starting to increase, the binary representation of the decimal point of the square root of each prime number is 32 bits, a total of 8 primes, considering that the cube root and square root are not as good as directly storing data on hardware, and the performance and area of the round selection method, so in the circuit implementation, these data are directly stored in the calculation data path.

[0103] At the beginning of the first round of encryption, the digest algorithm control module controls the encryption data and message source of the calculation data path to be the register group of the privilege register configuration module, and in the subsequent rounds, the source of the encryption data and the message is the temporary variable storage module, after a round of encryption operation, the encrypted data is temporarily stored in the temporary variable storage module;

[0104] For message expansion, no message expansion is performed from the first round of calculation to the 16th round of calculation, the digest algorithm control module controls the message output signal of the calculation path to be the message input signal, and then stored in the temporary variable register, and when the message expansion is performed, the digest algorithm calculation control module sends a control signal to the calculation path, so that the output key signal is derived from the message expansion result

[0105] The general computing resources used in the SHA256 encryption operation process and the SHA256 message expansion process are the same resources, and the encryption operation needs to be completed after the message expansion, so the encryption and decryption circuit reduces the deployment of logic resources by state machine multiplexing, increases the utilization rate of logic resources, and considering that the area priority is higher than the speed in the embedded field, the security is more reasonable. After each round operation is completed, the results of the round operation are stored alternately to reduce the use of logic right shift resources.

[0106] In the embodiment of the application, the single round encryption module of the SHA256 algorithm comprises: Ch function, ∑0 function, M aj function, ∑1 function, σ0 function, σ1 function, 32-bit addition operation, cyclic right shift operation, logic right shift operation, all computing resources are derived from the calculation data path; the single round operation only executes one clock cycle.

[0107] The Ch function consists of 32-bit negation, AND operation, and XOR operation of three variables. The encryption and decryption circuit calls the 32-bit negation operation unit, 32-bit AND operation unit, and 32-bit XOR operation unit logic unit. The input of the 32-bit XOR operation resource is controlled by the state machine as the output of two 32-bit AND operation units. The input of one 32-bit AND operation unit is the first variable and the second independent variable of the Ch function, and the input of the other 32-bit AND operation unit is the result of the negation of the first independent variable and the third independent variable. Its logic function is:

[0108]

[0109] M aj The function is designed to perform 32-bit AND and XOR operations on three variables. This function is implemented by calling 32-bit AND and XOR units. The state machine controls the first 32-bit AND unit to take the first and second independent variables as input, the second 32-bit AND unit to take the first and third independent variables as input, and the third 32-bit AND unit to take the second and third independent variables as input. The logic function is:

[0110]

[0111] The ∑0 function involves three different times of circular right shift operations on a variable and the sequential exclusive OR of the results. This function is implemented by calling three circular right shift units and two 32-bit exclusive OR units. The circular right shift module in the data path can select different circular right shift units, which are configured as circular right shifts of 1 bit, 13 bits, and 22 bits according to the state machine configuration. Its logic function is:

[0112]

[0113] The ∑1 function involves three different times of circular right shift operations on a variable and the sequential exclusive OR of the results. This function is implemented by calling three circular right shift units and two 32-bit exclusive OR units. The circular right shift module in the data path can select different circular right shift units, which are configured as 6-bit, 11-bit, and 25-bit circular right shifts according to the state machine. Its logic function is:

[0114]

[0115] The σ0 function involves two different times of circular right shift operations and one logical right shift operation on a variable, as well as the sequential exclusive OR of the results. This function is implemented by calling two circular right shift units, one logical right shift, and two 32-bit exclusive OR units. The circular right shift module in the data path can select different circular right shift units, which are respectively configured as 7-bit circular right shift, 18-bit circular right shift, and 3-bit logical right shift according to the state machine configuration. Its logic function is:

[0116]

[0117] The σ1 function involves two different times of circular right shift operations and one logical right shift operation on a variable, as well as the sequential exclusive OR of the results. This function is implemented by calling two circular right shift units, one logical right shift, and two 32-bit exclusive OR units. The circular right shift module in the data path can select different circular right shift units, which are respectively configured as 17-bit circular right shift, 19-bit circular right shift, and 10-bit logical right shift according to the state machine configuration. Its logic function is:

[0118]

[0119] The encryption process divides 256-bit data into 32-bit blocks and performs multiple encryption operations. This encryption process is achieved by calling multiple adders. The circular right shift operation is a circular right shift of the result after a single round of encryption and then stored in a temporary variable register file. The encryption and decryption calculation control module of the encryption and decryption circuit directly and intermittently stores the data returned by the data path module, thereby replacing the circular right shift operation.

[0120] The message expansion process will perform message expansion according to the round information recorded in the digest algorithm module. The calculation process is to add two original keys, the result of one key after the σ0 function operation, and the result of one key after the σ1 function operation in sequence. It needs to call three 32-bit addition units. The message expansion function is:

[0121] W j =σ1(W j-2 )+W j-7 +σ0(W j-15 )+W j-16 , for j=16→63

[0122] like Figure 6As shown, when the user configures the working mode to be AES128 symmetric encryption working state, the encryption and decryption calculation control module will control the symmetric algorithm control module to enter the encryption calculation state. The state machine of the symmetric algorithm calculation control module starts in IDLE, and then jumps to AES_INITIAL after the calculation is started. In this state, the round key addition calculation and the first row shift operation are performed on the plaintext, and key expansion is performed at the same time. In this state, the byte substitution module, shift operation resources and XOR operation resources are reused, and then it will jump to AES_COL3, AES_COL2, AES_COL1, and AES_COL0 states at once. In this state, the encryption and decryption calculation control module will perform a round of AES128 algorithm operations on 128 bits in 32-bit units, including byte substitution, column mixing, row shifting, and round key addition. At the same time, in the AES_COL3, AES_COL2, AES_COL1, and AES_COL0 states, 32-bit key expansion is performed at the same time to improve calculation efficiency.

[0123] The encryption and decryption control module keeps track of the encryption rounds. During the final round, it skips the column mixing calculation by chaining the output of the byte substitution and the input of the row shift. After completing 10 operations, the encryption and decryption calculation control module transitions to the FINISH state, notifying the global control module to begin reading the ciphertext. After the global control module clears the global calculation enable, the encryption and decryption calculation module returns to the IDLE state.

[0124] When the user configures the working mode to AES128 decryption working state, the starting state is IDLE. At this time, the key input to the encryption and decryption circuit is the original key. Before the decryption operation, the key must be expanded 10 rounds. The states are KEY_COL0, KEY_COL1, KEY_COL2, and KEY_COL3 respectively. 10 rounds of key expansion operations are performed in 32-bit units in the four states.

[0125] After completing the key expansion, it will jump to AES_INITIAL to perform round key addition calculations and the first reverse shift operation on the key, and then jump to AES_EXPAND state for key reverse expansion. In this state, the byte substitution module, shift operation resources and XOR operation resources are reused, and then it will jump to AES_COL0, AES_COL1, AES_COL2, and AES_COL3 states at once. In this state, the encryption and decryption calculation control module will perform a round of AES128 algorithm operations on 128 bits in 32-bit units, including reverse byte substitution, reverse column mixing, reverse shift, and round key addition. At the same time, in the AES_COL0, AES_COL1, AES_COL21, and AES_COL3 states, the 32-bit key reverse expansion work is performed at the same time to improve computing efficiency.

[0126] The encryption and decryption control module records the number of encryption rounds. During the final round, it skips the inverse column mixing calculation by linking the output of the inverse byte substitution and the input of the reverse row shift. After completing 10 operations, the encryption and decryption calculation control module transitions to the FINISH state to notify the global control module to begin reading plaintext. After the global control module clears the global calculation enable, the encryption and decryption calculation module returns to the IDLE state.

[0127] like Figure 7 As shown, the global calculation control module will control the startup of the AES algorithm state machine of the symmetric algorithm calculation control module. After startup, the AES algorithm calculation state machine sends a path construction signal and a round signal to the calculation data path. The calculation data path will build different data paths based on these signals. At the same time, the AES algorithm control state machine sends a column data selection signal to the temporary register group module to control the selection of word data and word key for round operations in the calculation data path.

[0128] At the beginning of the first round of encryption, the digest algorithm control module controls the data and key sources of the calculation data path to be the register group of the privileged register configuration module. In subsequent rounds, the data source is the single-column encryption and decryption data temporary register, and the key source is the single-column key temporary register. After a round of encryption operation, the intermediate data and intermediate extended key will be temporarily stored in the temporary register group.

[0129] In an embodiment of the present invention, a single-round encryption module of the AES128 algorithm includes a byte substitution module, a row shift module, a column obfuscation module, and a round key addition module. The AES128 last-round single-round encryption module includes a byte substitution module, a row shift module, and a round key addition module. The encryption and decryption calculation control module calculates the encryption rounds and generates different data paths in the last round to avoid column mixing.

[0130] The single-round decryption module of the AES128 algorithm includes: an inverse byte substitution module, a reverse shift module, an inverse column obfuscation module, and a round key addition module. The last round of the single-round decryption module includes the inverse byte substitution module, the reverse shift module, and the round key addition module. The encryption and decryption calculation control module calculates the encryption rounds and generates different data paths in the last round to avoid reverse column mixing.

[0131] The key expansion module of the AES128 algorithm first inputs the initial key into a 4x4 state matrix, 4 bytes of each column of the 4x4 matrix form a word, the 4 words of the 4 columns of the matrix are named as W[0], W[1], W[2] and W[3] in turn, which form a word array W, the key expansion module expands 40 new columns for the W array to form an expanded key array, if i is not a multiple of 4, the ith column is determined by the following equation:

[0132]

[0133] If i is a multiple of 4, the ith column is determined by the following equation:

[0134]

[0135] The T function transformation is a process of word cycle, byte substitution and round constant XOR, wherein the word cycle is a left shift of one byte, the byte substitution is the same as that in the byte substitution in the round operation, and the round constant is a process of XOR according to different round numbers and different constants;

[0136] The byte substitution and inverse byte substitution module adopts the subfield algorithm on GF(2 8 ), and the calculation process is essentially an inverse operation based on an irreducible polynomial on the extension field of GF(2 8 ) and a linear operation of a matrix. In the encryption and decryption circuit, the inverse algorithm on the extension field of GF(2 8 ) is first converted into an inverse process on the extension field of GF(2 4 ), and the inverse operation on the extension field of GF(2 4 ) is directly realized by using a logic function. The conversion process involves single-bit AND operation and single-bit XOR operation. The essence of the calculation process of these transformations on the extension field is AND or XOR operation between specific bits. The 32-bit XOR calculation unit in the data calculation path is independently operated at each bit, which converts the complex operation in the byte substitution into general operation at each bit, thereby realizing complex operation. The difference between the inverse byte substitution process and the byte substitution lies in the specific bits of the linear transformation. The data calculation path receives the control signal of the symmetric encryption control module to construct different data paths, thereby realizing different linear transformations and then realizing the inverse byte substitution.

[0137] The row shift and inverse row shift module considers that the data input into the data path module is executed by column, while the row shift and inverse row shift are executed by row. Therefore, before the row shift, the column conversion is performed first, and then the row shift is realized by reusing the cyclic shift logic resource of the data calculation path. After the row shift, the inverse row conversion process is performed to obtain the result of the row shift.

[0138] The essence of the column mixing module is to perform multiple XOR operations on bytes. Considering that a 32-bit XOR device resource is four 8-bit XOR devices, and the column mixing and inverse column mixing processes are repeated, the XOR resources integrated in the calculation path module realize column mixing through data flow control and save logic resources by reusing the results of the forward column mixing.

[0139] The round key addition module operates on the principle of exclusive-OR operation. The encryption and decryption circuit directly reuses the exclusive-OR resource to implement round key addition.

[0140] In the key expansion module, all XOR operations are implemented by reusing the 32-bit XOR calculation unit in the calculation path. The row shift process in the T function reuses the circular shift module in the calculation path, and the byte substitution module reuses the byte substitution module in the round calculation process. The essence of the round constant is the algorithm of multiplying by X in each round on the expansion domain. The encryption and decryption circuit directly implements the transformation process of each bit after the multiplication by X in each round, which is manifested as the XOR operation process of different bits, directly reusing the XOR calculation unit in the calculation path;

[0141] like Figure 8 As shown in the figure, when the user configures the working mode to be ECC256 encryption working state, the starting state is IDLE, and then jumps to DOT_PRODUCT0. In this state, the random number in the random number register and the public key in the key register will be multiplied by a point multiplication operation. In this state, the waiting state is maintained, and an enable signal for the point multiplication operation is generated at the same time. The point multiplication operation is started, and the key register is written after the calculation is completed and the state jumps to DOT_PRODUCT1. In this state, the random number and the generator point in the generator point register are multiplied by a point multiplication operation. The point multiplication operation is started again, and the calculation is completed and the generator point register is written and the state jumps to POINT_ADD0. After the point multiplication operation of the plaintext and the key register is completed, the point addition operation of the updated key is completed, and the point addition operation is started, and the output register is written after the calculation is completed.

[0142] When the user configures the working mode to be ECC256 decryption working state, the starting state DOT_PRODUCT2 is used. In this state, the first block of 256-bit data in the input register and the private key in the key register are multiplied. In this state, the waiting state is maintained, the point multiplication operation is started, and after the calculation is completed, the output register is written and the state is jumped to POINT_ADD1. The second block of 256-bit data in the input register and the updated result after the point multiplication operation in the output register are added. After the calculation is completed, the result is written to the output register again.

[0143] like Figure 9As shown, the global calculation module global calculation control module will control the algorithm state machine of the asymmetric algorithm calculation control module to start. After the startup is completed, different state jumps are performed according to the encryption or decryption working mode configuration. The module includes a point multiplication controller for controlling the startup of the point addition controller and the point doubling controller; the point addition controller is used to start the modular addition controller, modular subtraction controller, modular multiplication controller, and modular inversion controller according to the formula of the point addition operation; the point doubling controller is used to start the modular addition controller, modular subtraction controller, modular multiplication controller, and modular inversion controller according to the formula of the point doubling operation; the modular addition controller, modular subtraction controller, modular multiplication controller, and modular inversion controller control the startup of the 32-bit multiplier and the 32-bit carry adder in the calculation data path according to the specific hardware implementation method to complete the modular operation;

[0144] In this process, the operands of the adder and multiplier come from the temporary register bank or from the privileged register bank when the data is first used, and are written to the temporary register bank after the calculation is completed or written to the privileged register when the final result is completed.

[0145] The modular addition module is a 256-bit addition operation and performs a modular operation on a prime number P. The encryption and decryption circuit implements the 256-bit addition function by adding a carry output, a carry input, and an addition and subtraction mode selection to the 32-bit adder, and multiplexing the 32-bit adder through a state machine. The modular operation is a cyclic subtraction operation of the result after addition and the modulus, performed from the high 32 bits to the low 32 bits. When a carry output is found, it is determined whether the number is greater than the modulus. If it is greater than the modulus, a subtraction operation is initiated and the cycle is restarted. If there is no carry output, it means that the number is less than the modulus, and the modular operation is completed.

[0146] The modular subtraction module needs to first determine the size relationship between the two numbers to be subtracted, and first perform subtraction operations in sequence. If it is found that a carry is output during the subtraction process, it means that the minuend is smaller than the subtrahend. Then the order of the two numbers is swapped and the subtraction operation is performed again, and then the modular operation is performed; if there is no carry output during the subtraction operation, the modular operation is directly performed;

[0147] The modular multiplication module uses the Montgomery modular reduction algorithm to calculate the modular multiplication operation. First, the actual calculation process of the 256-bit multiplier is analyzed based on the 32-bit multiplier, and the operation process of each 32 bits of the actual result is calculated, thereby realizing the 256-bit multiplication operation. In the process of modular multiplication, it is necessary to first implement the 32-bit modular reduction algorithm, and then each 32-bit word of the 256 bits is sequentially and finally spliced ​​together to obtain the 256-bit modular multiplication result.

[0148] The modular inverse calculation module uses an extended Euclidean algorithm to calculate the modular inverse, which makes better use of hardware implementation from the perspective of hardware implementation;

[0149] The essence of the point addition operation module is to obtain the horizontal and vertical coordinates of the coordinate point symmetrical about the x-axis of the intersection of the line connecting the two points and the elliptic curve, realize the modular addition, modular subtraction, modular multiplication, and modular inverse operations of the selectively calling data path module, and implement the point addition algorithm in combination with ECC, where (x1, y1) and (x2, y2) represent the two base points P1 and P2 of the point addition operation, and (x3, y3) represent the result coordinates;

[0150] x3=λ 2 -x1-x2

[0151] y3=λ(x1-x3)-y1

[0152]

[0153] The essence of the point doubling operation module is to obtain the horizontal and vertical coordinates of the coordinate point symmetrical about the x-axis of the intersection of a tangent line and an elliptic curve, realize the modular addition, modular subtraction, modular multiplication, and modular inverse operations of the selectively called data path module, and implement the point doubling algorithm in combination with ECC, where (x1, y1) represents the base points P1 and P2 of the point doubling operation, and (x3, y3) represents the result coordinates;

[0154] x3=λ 2 -2x1

[0155] y3=λ(x1-x3)-y1

[0156]

[0157] The essence of the point multiplication operation module is to obtain the doubling point, connect the coordinates of the intersection of the starting point and the doubling point with the elliptic curve about x as a new point, connect the starting point and the new point and the coordinate point symmetrical about the x-axis with the intersection of the elliptic curve as a new point, and so on to realize point multiplication, and use the binary coding algorithm to reduce the complexity of the operation, convert the coefficients of the point multiplication into binary form, and judge whether each bit is "1" in turn starting from the highest bit. If it is "1", a point addition operation is performed, and a doubling operation is performed after each judgment, and then it is used as the base point for the next point addition.

[0158] The above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit the same. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some or all of the technical features therein. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. An encryption and decryption circuit system based on the RISC-V architecture, comprising a privileged register configuration module, a temporary variable storage module, an encryption and decryption global control module, an encryption and decryption calculation control module, a digest algorithm control module, a symmetric algorithm calculation module, an asymmetric algorithm control module, and a computing resource data path module, characterized in that: The privileged register configuration module is connected to the encryption and decryption calculation control module through the encryption and decryption global control module, and is also connected to the computing resource data path module for encryption and decryption data exchange and status return. The encryption and decryption calculation control module is connected to the global calculation path module after passing through the digest algorithm control module, the symmetric algorithm control module, and the asymmetric algorithm control module respectively to start reasoning calculations of different algorithms and working modes; The privileged register configuration module is used to obtain privileged instructions, configure encryption and decryption working modes, and input and output encryption and decryption data; Temporary variable storage module, used to temporarily store the calculation results of round operations during the calculation process; The global encryption and decryption control module is used to shield software write operations during encryption and decryption operations; The encryption and decryption calculation control module is used to start inference calculations of different algorithms and different working modes according to register status information; The digest algorithm control module is used to control the digest algorithm calculation process, record work information, and call the computing resources required by the digest algorithm; Symmetric algorithm control module, used to control the symmetric algorithm calculation process and record work information, and call the computing resources required by the symmetric algorithm; Asymmetric algorithm control module, used to control the asymmetric calculation process and record work information, and call the computing resources required by the asymmetric algorithm; The global computing path module is used to deploy computing resources and multiplexers, and complete complex computing resource combinations based on status information.

2. The encryption and decryption circuit system based on the RISC-V architecture according to claim 1, characterized in that: The privileged register configuration module includes a parsing module, a general register read and write interface, and an extended register group. The privileged instruction obtained is a CSR instruction, which is used to read the data of the general register and write it into the CSR register of the interface in the original format, set, and cleared. The data in the CSR register is written into the general register of the write-back register index; after the CSR instruction is translated by the parsing module, a read signal and a write signal are generated as well as the index of the privileged register that needs to be operated in this cycle to configure and read the extended register group.

3. The encryption and decryption circuit system based on the RISC-V architecture according to claim 1, characterized in that: The extended registers include a control register, a status register, an input register, an output register, a key register, an elliptic curve A parameter register, an elliptic curve B parameter register, a modulus register, a generation point register, and a random number register. The control register is used to configure the working mode of the encryption and decryption circuit. The status register is used to reflect the operating status of the encryption and decryption circuit. The input register is used to input the data to be encrypted or decrypted into the encryption and decryption circuit. The output register is used to read the encrypted data or decrypted data after completing the encryption or decryption work. The key register is used to obtain the key required for use in the encryption process. The elliptic curve A parameter register is used to configure the parameter A in the elliptic curve. The elliptic curve B parameter register is used to configure the parameter B in the elliptic curve. The modulus register is used to determine the modulus used when performing elliptic curve operations. The generation point register is used to determine the generation point of the elliptic curve. The random number register is used to use random numbers for encryption during the encryption process.

4. The encryption and decryption circuit system based on the RISC-V architecture according to claim 1, characterized in that: The encryption and decryption circuit supports SHA256, AES128, and ECC256 encryption and decryption. By decomposing the special calculations in the calculation process of the three algorithms, integrating general computing resources for time division multiplexing, and combining the MUX unit attached to each logical resource, a state machine controls the connection of multiple computing resources to form special operations in the encryption or decryption process, so that multiple security algorithms and multiple working modes can share resources, and the data flow and data path are controlled only by control signals.

5. The encryption and decryption circuit system based on the RISC-V architecture according to claim 4, characterized in that: The encryption and decryption circuit can implement the encryption mode of the SHA256 algorithm, the encryption mode of the AES128 algorithm, the encryption mode and decryption mode of the ECC256 algorithm.

6. The encryption and decryption circuit system based on the RISC-V architecture according to claim 5, characterized in that: The single-round encryption module of the SHA256 algorithm includes: Ch function, ∑0 function, M aj function,∑1 function, function, Function, 32-bit addition, circular right shift, logical right shift, a single round of operation is executed in only one clock cycle; The Ch function consists of 32-bit negation, AND operation, and XOR operation of three variables. The encryption and decryption circuit calls the 32-bit negation operation unit, 32-bit AND operation unit, and 32-bit XOR operation unit logic unit. The input of the 32-bit XOR operation resource is controlled by the state machine as the output of two 32-bit AND operation units. The input of one 32-bit AND operation unit is the first and second independent variables of the Ch function, and the input of the other 32-bit AND operation unit is the result of the negation of the first independent variable and the third independent variable. Its logic function is: M aj The function is designed to perform 32-bit AND and XOR operations on three variables. This function is implemented by calling 32-bit AND and XOR units. The state machine controls the first 32-bit AND unit to take the first and second independent variables as input, the second 32-bit AND unit to take the first and third independent variables as input, and the third 32-bit AND unit to take the second and third independent variables as input. The logic function is: The ∑0 function involves three different times of circular right shift operations on a variable and the sequential exclusive OR of the results. This function is implemented by calling three circular right shift units and two 32-bit exclusive OR units. The circular right shift module in the data path can select different circular right shift units, which are configured as circular right shifts of 1 bit, 13 bits, and 22 bits according to the state machine configuration. Its logic function is: The ∑1 function involves three different times of circular right shift operations on a variable and the sequential exclusive OR of the results. This function is implemented by calling three circular right shift units and two 32-bit exclusive OR units. The circular right shift module in the data path can select different circular right shift units, which are configured as 6-bit, 11-bit, and 25-bit circular right shifts according to the state machine. Its logic function is: The function involves two different times of circular right shift operations and one logical right shift operation on a variable, as well as the sequential exclusive OR of the results. This function is implemented by calling two circular right shift units, one logical right shift, and two 32-bit exclusive OR units. The circular right shift module in the data path can select different circular right shift units, which are respectively configured as 7-bit circular right shift, 18-bit circular right shift, and 3-bit logical right shift according to the state machine configuration. Its logic function is: The function involves two different times of circular right shift operations and one logical right shift operation on a variable, as well as the sequential exclusive OR of the results. This function is implemented by calling two circular right shift units, one logical right shift, and two 32-bit exclusive OR units. The circular right shift module in the data path can select different circular right shift units, which are respectively configured as 17-bit circular right shift, 19-bit circular right shift, and 10-bit logical right shift according to the state machine configuration. Its logic function is: The encryption process divides 256-bit data into 32-bit blocks and performs multiple encryption operations. This encryption process is achieved by calling multiple adders. The circular right shift operation is a circular right shift of the result after a single round of encryption and then stored in a temporary variable register file. The encryption and decryption calculation control module of the encryption and decryption circuit directly and intermittently stores the data returned by the data path module, thereby replacing the circular right shift operation. The message expansion process will perform message expansion according to the round information recorded in the digest algorithm module. The original message is stored in the register stack of the privileged register. After the extended message is calculated, the extended message is stored in the temporary variable register. The calculation process is 2 original messages, 1 message after The result of the function operation, 1 message passed The results of the function operations are added in sequence, which requires calling three 32-bit addition units. The message extension function is: 。 7. The encryption and decryption circuit system based on the RISC-V architecture according to claim 5, characterized in that: The single-round encryption module of the AES128 algorithm includes a byte substitution module, a row shift module, a column obfuscation module, and a round key addition module. The last round of the AES128 single-round encryption module includes a byte substitution module, a row shift module, and a round key addition module. The encryption and decryption calculation control module calculates the encryption rounds and generates different data paths in the last round to avoid column mixing. The single-round decryption module of the AES128 algorithm includes: an inverse byte substitution module, a reverse row displacement module, an inverse column obfuscation module, and a round key addition module. The last-round single-round decryption module includes an inverse byte substitution module, a reverse row displacement module, and a round key addition module. The encryption and decryption calculation control module calculates the encryption rounds and generates different data paths in the last round to avoid inverse column mixing. The key expansion module of the AES128 algorithm first inputs the initial key into a 4×4 state matrix. The 4 bytes in each column of this 4×4 matrix form a word. The 4 words in the 4 columns of the matrix are named W[0], W[1], W[2] and W[3] in sequence. They form an array W in word units. The key expansion module expands the W array by 40 new columns to form an extended key array. If i is not a multiple of 4, then the i-th column is determined by the following equation: If i is a multiple of 4, then the i-th column is determined by the following equation: The T function transformation is a process of word rotation, byte substitution, and round constant XOR. The word rotation is a byte shift left, the byte substitution is the same as the byte substitution in the round operation, and the round constant is a process of XORing according to different round numbers and different constants. The byte substitution and reverse byte substitution modules use GF(2 8 ) on the subfield algorithm, the computational process is essentially based on GF(2 8 ) based on the inversion operation of irreducible polynomials and the linear operation of matrices on the extended field, in the encryption and decryption circuit, GF(2 8 ) is transformed into the inverse algorithm on the extended field of GF(2 4 ) inverse process on the extended domain of GF(2 4 ) is directly implemented using a logic function on the extended domain. The conversion process involves single-bit AND and single-bit XOR operations. The essence of the calculation process of these transformations on the extended domain is AND or XOR operations between specific bits. Each bit of the 32-bit XOR calculation unit deployed in the data calculation path is an independent calculation process, which converts the complex operation in the byte substitution into a universal operation for each bit, thereby realizing the complex operation. The difference between the inverse byte substitution process and the byte substitution is that the specific bits of the linear transformation are different. The data calculation path receives the control signal of the symmetric encryption control module and constructs different data paths to achieve different linear transformations, thereby realizing the inverse byte substitution. The row shift and reverse row shift modules take into account that the data input to the data path module is executed by column, while the row shift and reverse row shift are executed by row. Therefore, before the row shift is performed, a column conversion is performed first, and then the circular shift logic resources of the data calculation path are reused to realize the row shift. After the row shift, the reverse row-column conversion process is performed to obtain the row shift result; The essence of the column mixing module is to perform multiple XOR operations on bytes. Considering that a 32-bit XOR device resource is composed of four 8-bit XOR devices, and the column mixing and inverse column mixing are repeated processes, the XOR resources integrated in the calculation path module realize column mixing through data flow control and save logic resources by reusing the results of the forward column mixing. The round key adding module operates on the principle of XOR operation, and the encryption and decryption circuit directly reuses XOR resources to implement round key addition; In the key expansion module, all exclusive OR operations are implemented by reusing the 32-bit exclusive OR calculation unit in the calculation path. The row shift process in the T function reuses the circular shift module in the calculation path. The byte substitution module reuses the byte substitution module in the round calculation process. The essence of the round constant is the algorithm of performing multiplication by X in each round on the expansion domain. The encryption and decryption circuit directly implements the transformation process of each bit after the multiplication by X in each round, which is manifested as the exclusive OR operation process of different bits, directly reusing the exclusive OR calculation unit of the calculation path.

8. The encryption and decryption circuit system based on the RISC-V architecture according to claim 5, characterized in that: The ECC256 encryption process uses a random number as a coefficient, performs a point multiplication operation on the point represented by the public key on the elliptic curve, and performs a point addition operation on the obtained point and the point represented by the plaintext to obtain ciphertext 1. Here, the random number is used to perform a point multiplication operation on the generator point to obtain ciphertext 2; The decryption process of the ECC256 algorithm uses the private key to perform a dot multiplication operation on the key 2, and then uses the ciphertext 1 to perform a dot addition operation on the result 1 to obtain the plaintext; The modules of the ECC256 algorithm include: elliptic curve point addition operation module, elliptic curve point doubling operation module, elliptic curve point multiplication operation module, and 256-bit modular addition, modular subtraction, modular multiplication, and modular inverse operations; The modular addition module is a 256-bit addition operation and performs a modular operation on a prime number P. The encryption and decryption circuit implements the 256-bit addition function by adding a carry output, a carry input, and an addition and subtraction mode selection to the 32-bit adder, and multiplexing the 32-bit adder through a state machine. The modular operation is a cyclic subtraction operation of the result after addition and the modulus, performed from the high 32 bits to the low 32 bits. When a carry output is found, it is determined whether the number is greater than the modulus. If it is greater than the modulus, a subtraction operation is initiated and the cycle is restarted. If there is no carry output, it means that the number is less than the modulus, and the modular operation is completed. The modular subtraction module needs to first determine the size relationship between the two numbers to be subtracted, and first perform subtraction operations in sequence. If it is found that a carry is output during the subtraction process, it means that the minuend is smaller than the subtrahend. Then the order of the two numbers is swapped and the subtraction operation is performed again, and then the modular operation is performed; if there is no carry output during the subtraction operation, the modular operation is directly performed; The modular multiplication module uses the Montgomery modular reduction algorithm to calculate the modular multiplication operation. First, the actual calculation process of the 256-bit multiplier is analyzed based on the 32-bit multiplier, and the operation process of each 32 bits of the actual result is calculated, thereby realizing the 256-bit multiplication operation. During the modular multiplication operation, it is necessary to first implement the 32-bit modular reduction algorithm, and then each 32-bit word of the 256 bits is sequentially and finally spliced ​​together to obtain the 256-bit modular multiplication result; The modular inverse calculation module uses an extended Euclidean algorithm to calculate the modular inverse, which makes better use of hardware implementation from the perspective of hardware implementation; The essence of the point addition operation module is to obtain the horizontal and vertical coordinates of the coordinate point symmetrical about the x-axis of the intersection of the line connecting the two points and the elliptic curve, realize the modular addition, modular subtraction, modular multiplication, and modular inverse operations of the selectively called data path module, and implement the point addition algorithm in combination with ECC, where (x1, y1) and (x2, y2) represent the two base points P1 and P2 of the point addition operation, and (x3, y3) represent the result coordinates; The essence of the point doubling operation module is to obtain the horizontal and vertical coordinates of the coordinate point symmetrical about the x-axis of the intersection of a tangent line and an elliptic curve, realize the modular addition, modular subtraction, modular multiplication, and modular inverse operations of the selectively called data path module, and implement the point doubling algorithm in combination with ECC, where (x1, y1) represents the base points P1 and P2 of the point doubling operation, and (x3, y3) represents the result coordinates; The essence of the point multiplication operation module is to obtain the doubling point, connect the coordinates of the intersection of the starting point and the doubling point with the elliptic curve about x as a new point, connect the starting point and the new point and the coordinate point symmetrical about the x-axis with the intersection of the elliptic curve as a new point, and so on to realize point multiplication, and use the binary coding algorithm to reduce the complexity of the operation, convert the coefficients of the point multiplication into binary form, and judge whether each bit is 1 in turn starting from the highest bit. If it is 1, perform a point addition operation, and perform a doubling operation after each judgment, and then use it as the base point for the next point addition.

9. An encryption and decryption circuit method based on RISC-V architecture, characterized by: The encryption and decryption circuit system based on the RISC-V architecture according to any one of claims 1 to 8 comprises the following steps: Step 1: Configure the privileged register, continuously send privileged instructions to the encryption and decryption circuit to implement the configuration of the state. The privileged instructions are executed in a pipeline during the execution process. The configuration work includes inputting the key, inputting the plaintext or ciphertext, configuring the encryption or decryption mode, configuring the encryption or decryption algorithm to be used, configuring the generator register, configuring the random number register, and finally enabling the encryption and decryption circuit to start calculation; Step 2: After encryption or decryption is completed, the encryption and decryption circuit will perform encryption and decryption operations. Depending on the algorithm and working mode, the calculation completion information is obtained by checking the interrupt signal or the flag bit on the status register; Step 3: After detecting that the interrupt signal is set or the calculation completion flag in the status register is set, read the data in the output register; When the data reading operation is completed, the calculation enable signal is automatically cleared.

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