Integrated circuit software and hardware collaborative design optimization method based on graph neural network analysis

Abstract

The invention relates to the field of integrated circuits, and discloses an integrated circuit software and hardware collaborative design optimization method based on graph neural network analysis, which comprises the following steps: mapping a graph neural network on a target analog integrated circuit to obtain a graph neural network mapping circuit, and performing power consumption parameter prediction and classification on the graph neural network mapping circuit to obtain a power consumption parameter prediction result; and finally, carrying out fault point tracing and software and hardware design optimization on the classified graph neural network mapping circuit. According to the method, the position where software and hardware design optimization needs to be carried out in the integrated circuit can be determined in a graph neural network mapping mode, software and hardware design optimization is achieved according to different positions and different parameters, power consumption generated in the operation process of the circuit is reduced, and the purposes of energy conservation, emission reduction and gain are achieved.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuits, and in particular to an integrated circuit software and hardware collaborative design optimization method based on graph neural network analysis. Background Art

[0002] Graph neural network is a neural network model specially designed for processing graph structure data. Graph structure data is a complex relational network composed of nodes and directed edges, where nodes represent entities and edges represent the relationship between entities. This data structure is widely present in the real world, such as social networks, knowledge graphs, molecular structures, etc. As the core of modern electronic devices, the design complexity of integrated circuits and every subtle production link directly affect the performance of the final product. Software-hardware co-design is an effective method that aims to improve the overall performance of the system by combining the advantages of software and hardware. As a powerful artificial intelligence technology, graph neural network can process and analyze complex graph structure data, providing new ideas for the software-hardware co-design of integrated circuits. By mapping graph neural network on integrated circuits, the purpose of predicting the fault location of integrated circuits can be achieved by graph neural network, which significantly improves the performance and efficiency of integrated circuits. Therefore, an integrated circuit software-hardware co-design optimization method based on graph neural network analysis is proposed. Summary of the invention

[0003] The present invention overcomes the deficiencies of the prior art and provides an integrated circuit software and hardware collaborative design optimization method based on graph neural network analysis.

[0004] In order to achieve the above object, the technical solution adopted by the present invention is:

[0005] The first aspect of the present invention provides an integrated circuit hardware and software collaborative design optimization method based on graph neural network analysis, comprising the following steps:

[0006] Constructing a graph neural network and a target analog integrated circuit, and mapping the graph neural network on the target analog integrated circuit to obtain a graph neural network mapping circuit;

[0007] Running the graph neural network mapping circuit, generating prediction data of the running power consumption parameters, performing a qualified analysis on the predicted data of the running power consumption parameters, and finally classifying the target analog integrated circuit based on the qualified analysis results;

[0008] The fault point of the classified graph neural network mapping circuit is traced, and the software and hardware design of the classified graph neural network mapping circuit is optimized based on the fault point tracing results.

[0009] Furthermore, in a preferred embodiment of the present invention, the graph neural network and the target analog integrated circuit are constructed, and the graph neural network is mapped on the target analog integrated circuit to obtain a graph neural network mapping circuit, specifically:

[0010] Acquire an integrated circuit that needs to be analyzed for software and hardware, mark it as a target integrated circuit, and determine a circuit structure of the target integrated circuit in the target integrated circuit;

[0011] Wherein, the circuit structure of the target integrated circuit includes circuit element parameters, circuit element arrangement positions and wire wiring scheme of the target integrated circuit;

[0012] Introducing circuit simulation software, importing the circuit structure of the target integrated circuit into the circuit simulation software, and constructing a simulation circuit of the target integrated circuit in the circuit simulation software, expressed as a target simulated integrated circuit;

[0013] Introducing a graph neural network benchmark model, wherein the graph neural network benchmark model includes an input layer, a hidden layer, and an output layer, and simultaneously introducing a big data network, in which the structural connection mode of the graph neural network benchmark model used for predicting indicator data of integrated circuits is retrieved and calibrated as the target structural connection mode;

[0014] In the graph neural network benchmark model, the connection mode between the input layer, the hidden layer, and the output layer is set to the target structure connection mode to obtain the graph neural network model to be set;

[0015] Running the target analog integrated circuit, and during the operation of the target analog integrated circuit, real-time monitoring of the operating power consumption parameters of the target analog integrated circuit is carried out, and the parameters are calibrated as the real-time operating power consumption parameters, and at the same time, real-time monitoring of the component operating parameters of different components in the target analog integrated circuit is carried out, and the parameters are calibrated as the real-time operating parameters of the circuit components;

[0016] Perform feature analysis on the real-time power consumption parameters and the real-time operating parameters of circuit elements of different components to generate connection relationships of different components. Generate an adjacency matrix of the target analog integrated circuit based on the connection relationships of the different components. Import the adjacency matrix of the target analog integrated circuit, the real-time power consumption parameters and the real-time operating parameters of circuit elements of different components into the graph neural network model to be set for forward propagation to obtain a graph neural network mapping circuit.

[0017] Furthermore, in a preferred embodiment of the present invention, the operation graph neural network mapping circuit generates prediction data of operation power consumption parameters, performs qualification analysis on the prediction data of operation power consumption parameters, and finally classifies the target analog integrated circuit based on the qualification analysis results, specifically:

[0018] A preset circuit operation time, during which a graph neural network mapping circuit is operated, wherein when the graph neural network mapping circuit is operated, operating power consumption parameters of the graph neural network mapping circuit and component operation parameters of different components after the circuit operation time can be predicted;

[0019] After obtaining the circuit operation time, the graph neural network maps the operation power consumption parameters of the circuit and the component operation parameters of different components, and calibrates them into predicted operation power consumption parameters and predicted component operation parameters of different components;

[0020] Preset standard data of predicted operating power consumption parameters, calibrate them as standard operating power consumption parameters, and simultaneously preset standard data of predicted component operating parameters of different components to obtain standard component operating parameters of different components;

[0021] The predicted operating power consumption parameters and the predicted component operating parameters of different components are analyzed. If the predicted operating power consumption parameters are greater than the standard operating power consumption parameters, and there are components whose predicted component operating parameters are less than the corresponding standard component operating parameters, the graph neural network mapping circuit is calibrated as a type of predicted operating power consumption abnormal simulation circuit, and the corresponding component is calibrated as a predicted operating parameter abnormal component;

[0022] If the predicted operating power consumption parameter is greater than the operating power consumption standard parameter, but there is no component whose predicted component operating parameter is less than the corresponding standard component operating parameter, the graph neural network mapping circuit is calibrated as a second-class predicted operating power consumption abnormal simulation circuit;

[0023] If the predicted operating power consumption parameter is not greater than the operating power consumption standard parameter, the graph neural network mapping circuit is calibrated as a qualified analog circuit.

[0024] Furthermore, in a preferred embodiment of the present invention, the fault point tracing of the classified graph neural network mapping circuit is performed, and the software and hardware design optimization of the classified graph neural network mapping circuit is performed based on the fault point tracing result, specifically:

[0025] For a type of predicted operation power consumption abnormality simulation circuit, in the type of predicted operation power consumption abnormality simulation circuit, determining whether a component with abnormal predicted operation parameters is a replaceable component;

[0026] Wherein, the replaceable component is a component that can be replaced with the same type in a type of predicted operation power consumption abnormality simulation circuit. If the predicted operation parameter abnormality component is a replaceable component, then in the type of predicted operation power consumption abnormality simulation circuit, the predicted operation parameter abnormality component that is a replaceable component is simulated replaced;

[0027] If the component with abnormal predicted operating parameters is not a replaceable component, a correction scheme for the component with abnormal predicted operating parameters is retrieved in the big data network and outputted so that the predicted component operating parameters of all components in a type of predicted operating power consumption abnormality simulation circuit are not less than the corresponding standard component operating parameters;

[0028] When the predicted component operating parameters of all components in a type of predicted abnormal operating power consumption simulation circuit are not less than the corresponding standard component operating parameters, and the predicted operating power consumption parameters of a type of predicted abnormal operating power consumption simulation circuit are not greater than the operating power consumption standard parameters, the type of predicted abnormal operating power consumption simulation circuit is classified as a qualified simulation circuit;

[0029] When the predicted component operating parameters of all components in a type of predicted operating power consumption abnormality simulation circuit are not less than the corresponding standard component operating parameters, the predicted operating power consumption parameters of the type of predicted operating power consumption abnormality simulation circuit are still greater than the operating power consumption standard parameters, then the type of predicted operating power consumption abnormality simulation circuit is divided into a type of predicted operating power consumption abnormality simulation circuit;

[0030] The circuit fault point traceback is performed on the second type of predicted operating power consumption abnormality simulation circuit, and the software and hardware design of the second type of predicted operating power consumption abnormality simulation circuit is optimized based on the fault point tracing results.

[0031] Further, in a preferred embodiment of the present invention, the circuit fault point tracing is performed on the two types of predicted operation power consumption abnormal simulation circuits, and the software and hardware design optimization of the two types of predicted operation power consumption abnormal simulation circuits is performed based on the fault point tracing results, specifically:

[0032] In the second type of prediction operation power consumption abnormality simulation circuit, all network nodes are obtained, wherein the network nodes are elements in the second type of prediction operation power consumption abnormality simulation circuit;

[0033] The connection mode between different components is obtained in the second type of simulation circuit for predicting abnormal operation power consumption, and the directed edges between all network nodes are defined based on the connection mode between different components;

[0034] Run the second type of prediction operation power consumption abnormality simulation circuit, calculate the gradient value of the directed edge between all network nodes in real time, and calibrate it as the directed edge gradient value;

[0035] Preset a standard variation range of the directed edge gradient value, preset a gradient value analysis time, and determine whether the directed edge gradient value is maintained within the standard variation range of the directed edge gradient value during the gradient value analysis time;

[0036] If not, it is determined that there is an abnormality in the connection mode of the components in the second type of predicted operation power consumption abnormality simulation circuit, and in the second type of predicted operation power consumption abnormality simulation circuit, the components corresponding to the directed edge gradient values ​​that are not maintained within the directed edge gradient value standard variation range are determined and marked as connection abnormal components;

[0037] In the second type of predicted operation power consumption abnormality simulation circuit, the component architecture is adjusted for all abnormally connected components, and it is determined whether the abnormally connected components still exist after the component architecture is adjusted;

[0038] If so, all suitable connection modes for the abnormal connection components are retrieved based on the big data network, marked as the connection modes of the components to be selected, all the connection modes of the components to be selected are output, and the connection modes of the components to be selected that do not have abnormal connection components after output are marked as the target connection modes;

[0039] When there are no abnormally connected components in the second type of predicted operating power consumption abnormality simulation circuit, but the predicted operating power consumption parameters of the second type of predicted operating power consumption abnormality simulation circuit are still greater than the operating power consumption standard parameters, the circuit software optimization design of the second type of predicted operating power consumption abnormality simulation circuit is performed to obtain a simulation circuit whose predicted operating power consumption parameters are not greater than the operating power consumption standard parameters.

[0040] Furthermore, in a preferred embodiment of the present invention, the circuit software optimization design of the second type of predicted operation power consumption abnormal simulation circuit is performed to obtain a simulation circuit whose predicted operation power consumption parameter is not greater than the operation power consumption standard parameter, specifically:

[0041] The second type of predicted abnormal operating power consumption simulation circuits after component architecture adjustment and target connection mode output are calibrated as simulation circuits to be optimized by the software;

[0042] Configuring an FPGA accelerator in the software to be optimized simulation circuit, wherein the FPGA accelerator is an accelerator for adjusting parameters of the graph neural network in the software to be optimized simulation circuit;

[0043] Run the software to be optimized analog circuit, calculate the predicted operating power consumption parameters of the software to be optimized analog circuit, introduce a Markov chain algorithm to analyze the predicted operating power consumption parameters of the software to be optimized analog circuit, determine the position that affects the predicted operating power consumption parameters of the software to be optimized analog circuit in the graph neural network of the software to be optimized analog circuit, and mark it as the power consumption parameter influencing position;

[0044] Obtain the graph neural network operating parameters at the position where the power consumption parameters affect the position, and adjust the graph neural network operating parameters at the position where the power consumption parameters affect the position in the FPGA accelerator until the predicted operating power consumption parameters of the simulation circuit to be optimized by the software are no greater than the operating power consumption standard parameters, thereby obtaining a qualified simulation circuit.

[0045] The second aspect of the present invention further provides an integrated circuit software and hardware collaborative design optimization system based on graph neural network analysis, the integrated circuit software and hardware collaborative design optimization system includes a memory and a processor, the memory stores an integrated circuit software and hardware collaborative design optimization method, and when the integrated circuit software and hardware collaborative design optimization method is executed by the processor, the following steps are implemented:

[0046] Constructing a graph neural network and a target analog integrated circuit, and mapping the graph neural network on the target analog integrated circuit to obtain a graph neural network mapping circuit;

[0047] Running the graph neural network mapping circuit, generating prediction data of the running power consumption parameters, performing a qualified analysis on the predicted data of the running power consumption parameters, and finally classifying the target analog integrated circuit based on the qualified analysis results;

[0048] The fault point of the classified graph neural network mapping circuit is traced, and the software and hardware design of the classified graph neural network mapping circuit is optimized based on the fault point tracing results.

[0049] The present invention solves the technical defects existing in the background technology, and the present invention has the following beneficial effects: mapping the graph neural network on the target analog integrated circuit to obtain a graph neural network mapping circuit, and predicting and classifying the power consumption parameters of the graph neural network mapping circuit, and finally tracing the fault point and optimizing the software and hardware design of the classified graph neural network mapping circuit. The present invention can determine the locations in the integrated circuit that require software and hardware design optimization by means of graph neural network mapping, and realize software and hardware design optimization according to different locations and parameters, thereby reducing the power consumption generated by the circuit during operation, achieving energy conservation and emission reduction, and achieving the purpose of this gain. BRIEF DESCRIPTION OF THE DRAWINGS

[0050] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, drawings of other embodiments can be obtained based on these drawings without paying creative work.

[0051] Figure 1 A flow chart of an integrated circuit hardware and software collaborative design optimization method based on graph neural network analysis is shown;

[0052] Figure 2 A flow chart of a method for optimizing the software and hardware design of a classified graph neural network mapping circuit is shown;

[0053] Figure 3The program view of the integrated circuit hardware and software collaborative design optimization system based on graph neural network analysis is shown. DETAILED DESCRIPTION

[0054] In order to more clearly understand the above-mentioned purpose, features and advantages of the present invention, the present invention is further described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be noted that the embodiments of the present application and the features in the embodiments can be combined with each other without conflict.

[0055] In the following description, many specific details are set forth to facilitate a full understanding of the present invention. However, the present invention may also be implemented in other ways different from those described herein. Therefore, the protection scope of the present invention is not limited to the specific embodiments disclosed below.

[0056] Figure 1 A flowchart of an integrated circuit hardware and software collaborative design optimization method based on graph neural network analysis is shown, comprising the following steps:

[0057] S102: construct a graph neural network and a target analog integrated circuit, and map the graph neural network on the target analog integrated circuit to obtain a graph neural network mapping circuit;

[0058] S104: running the graph neural network mapping circuit to generate prediction data of the running power consumption parameters, and performing a qualified analysis on the prediction data of the running power consumption parameters, and finally classifying the target analog integrated circuit based on the qualified analysis results;

[0059] S106: Trace the fault points of the classified graph neural network mapping circuit, and optimize the software and hardware design of the classified graph neural network mapping circuit based on the fault point tracing results.

[0060] Furthermore, in a preferred embodiment of the present invention, the graph neural network and the target analog integrated circuit are constructed, and the graph neural network is mapped on the target analog integrated circuit to obtain a graph neural network mapping circuit, specifically:

[0061] Acquire an integrated circuit that needs to be analyzed for software and hardware, mark it as a target integrated circuit, and determine a circuit structure of the target integrated circuit in the target integrated circuit;

[0062] Wherein, the circuit structure of the target integrated circuit includes circuit element parameters, circuit element arrangement positions and wire wiring scheme of the target integrated circuit;

[0063] Introducing circuit simulation software, importing the circuit structure of the target integrated circuit into the circuit simulation software, and constructing a simulation circuit of the target integrated circuit in the circuit simulation software, expressed as a target simulated integrated circuit;

[0064] Introducing a graph neural network benchmark model, wherein the graph neural network benchmark model includes an input layer, a hidden layer, and an output layer, and simultaneously introducing a big data network, in which the structural connection mode of the graph neural network benchmark model used for predicting indicator data of integrated circuits is retrieved and calibrated as the target structural connection mode;

[0065] In the graph neural network benchmark model, the connection mode between the input layer, the hidden layer, and the output layer is set to the target structure connection mode to obtain the graph neural network model to be set;

[0066] Running the target analog integrated circuit, and during the operation of the target analog integrated circuit, real-time monitoring of the operating power consumption parameters of the target analog integrated circuit is carried out, and the parameters are calibrated as the real-time operating power consumption parameters, and at the same time, real-time monitoring of the component operating parameters of different components in the target analog integrated circuit is carried out, and the parameters are calibrated as the real-time operating parameters of the circuit components;

[0067] Perform feature analysis on the real-time power consumption parameters and the real-time operating parameters of circuit elements of different components to generate connection relationships of different components. Generate an adjacency matrix of the target analog integrated circuit based on the connection relationships of the different components. Import the adjacency matrix of the target analog integrated circuit, the real-time power consumption parameters and the real-time operating parameters of circuit elements of different components into the graph neural network model to be set for forward propagation to obtain a graph neural network mapping circuit.

[0068] It should be noted that an integrated circuit is a circuit that integrates multiple functions. There are different circuit elements in the integrated circuit, and different circuit elements are connected together through connecting wires. Constructing a simulation circuit of an integrated circuit can realize the mapping of a graph neural network on the integrated circuit, and realize the purpose of predicting circuit fault points on the integrated circuit through the graph neural network. The efficiency value of operating on the simulation software is higher. After constructing the target analog integrated circuit in the circuit simulation software, it is necessary to map the graph neural network on the target analog integrated circuit so that the target analog integrated circuit can monitor the fault points and power consumption data in real time through the graph neural network during operation, providing conditions for the optimization of the software and hardware design of the circuit. First, the graph neural network benchmark model is introduced, and the appropriate connection method between the input layer, hidden layer and output layer of the graph neural network benchmark model is determined to realize the preliminary construction of the graph neural network model. The graph neural network model after preliminary construction is suitable for analyzing the parameters of the integrated circuit during operation. After the real-time operation power consumption parameters and the real-time operation parameters of the circuit elements of different components are imported into the graph neural network to be set model, the graph neural network mapping circuit can be obtained by combining the adjacency matrix. Among them, the purpose of constructing the adjacency matrix is ​​to enable the cloud core parameters to be forward propagated in the model to achieve the purpose of mapping the graph neural network on the circuit.

[0069] Furthermore, in a preferred embodiment of the present invention, the operation graph neural network mapping circuit generates prediction data of operation power consumption parameters, performs qualification analysis on the prediction data of operation power consumption parameters, and finally classifies the target analog integrated circuit based on the qualification analysis results, specifically:

[0070] A preset circuit operation time, during which a graph neural network mapping circuit is operated, wherein when the graph neural network mapping circuit is operated, operating power consumption parameters of the graph neural network mapping circuit and component operation parameters of different components after the circuit operation time can be predicted;

[0071] After obtaining the circuit operation time, the graph neural network maps the operation power consumption parameters of the circuit and the component operation parameters of different components, and calibrates them into predicted operation power consumption parameters and predicted component operation parameters of different components;

[0072] Preset standard data of predicted operating power consumption parameters, calibrate them as standard operating power consumption parameters, and simultaneously preset standard data of predicted component operating parameters of different components to obtain standard component operating parameters of different components;

[0073] The predicted operating power consumption parameters and the predicted component operating parameters of different components are analyzed. If the predicted operating power consumption parameters are greater than the standard operating power consumption parameters, and there are components whose predicted component operating parameters are less than the corresponding standard component operating parameters, the graph neural network mapping circuit is calibrated as a type of predicted operating power consumption abnormal simulation circuit, and the corresponding component is calibrated as a predicted operating parameter abnormal component;

[0074] If the predicted operating power consumption parameter is greater than the operating power consumption standard parameter, but there is no component whose predicted component operating parameter is less than the corresponding standard component operating parameter, the graph neural network mapping circuit is calibrated as a second-class predicted operating power consumption abnormal simulation circuit;

[0075] If the predicted operating power consumption parameter is not greater than the operating power consumption standard parameter, the graph neural network mapping circuit is calibrated as a qualified analog circuit.

[0076] It should be noted that after the graph neural network is mapped on the target analog integrated circuit, the graph neural network is used to predict the operating power consumption parameters of the graph neural network mapped circuit and the component operating parameters of different components after the circuit operation time, that is, the predicted operating power consumption parameters and the predicted component operating parameters of different components are used to determine whether the circuit can maintain the operating power consumption at a low level after the circuit operation time. The standard parameters are preset, and the predicted operating power consumption parameters and the predicted component operating parameters of different components are compared with the corresponding standard parameters respectively, and the graph neural network mapping circuit is classified based on the comparison results. The classification method is that if the predicted component operating parameters of the component are less than the corresponding standard component operating parameters, the predicted operating power consumption of the circuit must be greater than the standard value. At this time, the circuit is marked as a type I predicted operating power consumption abnormal simulation circuit, and the corresponding component is marked as a predicted operating parameter abnormal component; on the contrary, if the predicted component operating parameters of the component are not less than the corresponding standard component operating parameters, but the predicted operating power consumption of the circuit is still greater than the standard value, it proves that the circuit may have abnormalities in the component connection method, connection architecture, etc., and the circuit is marked as a type II predicted operating power consumption abnormal simulation circuit.

[0077] Figure 2 A flowchart of a method for optimizing the software and hardware design of a classified graph neural network mapping circuit is shown, including the following steps:

[0078] S202: Perform component analysis on a type of predicted abnormal operation power consumption simulation circuit, and simulate replacement of replaceable components based on the case analysis results;

[0079] S204: tracing the circuit fault point of the second type of predicted operation power consumption abnormality simulation circuit, and optimizing the hardware design of the second type of predicted operation power consumption abnormality simulation circuit based on the fault point tracing result;

[0080] S206: Performing circuit software optimization design on the second type of predicted abnormal operation power consumption simulation circuit to obtain a simulation circuit whose predicted operation power consumption parameters are not greater than the operation power consumption standard parameters.

[0081] Furthermore, in a preferred embodiment of the present invention, the component analysis is performed on a type of predicted abnormal operation power consumption simulation circuit, and the simulated replacement of replaceable components is performed based on the case analysis results, specifically:

[0082] For a type of predicted operation power consumption abnormality simulation circuit, in the type of predicted operation power consumption abnormality simulation circuit, determining whether a component with abnormal predicted operation parameters is a replaceable component;

[0083] Wherein, the replaceable component is a component that can be replaced with the same type in a type of predicted operation power consumption abnormality simulation circuit. If the predicted operation parameter abnormality component is a replaceable component, then in the type of predicted operation power consumption abnormality simulation circuit, the predicted operation parameter abnormality component that is a replaceable component is simulated replaced;

[0084] If the component with abnormal predicted operating parameters is not a replaceable component, a correction scheme for the component with abnormal predicted operating parameters is retrieved in the big data network and outputted so that the predicted component operating parameters of all components in a type of predicted operating power consumption abnormality simulation circuit are not less than the corresponding standard component operating parameters;

[0085] When the predicted component operating parameters of all components in a type of predicted abnormal operating power consumption simulation circuit are not less than the corresponding standard component operating parameters, and the predicted operating power consumption parameters of a type of predicted abnormal operating power consumption simulation circuit are not greater than the operating power consumption standard parameters, the type of predicted abnormal operating power consumption simulation circuit is classified as a qualified simulation circuit;

[0086] When the predicted component operating parameters of all components in a type of predicted operating power consumption abnormality simulation circuit are not less than the corresponding standard component operating parameters, the predicted operating power consumption parameters of the type of predicted operating power consumption abnormality simulation circuit are still greater than the operating power consumption standard parameters, then the type of predicted operating power consumption abnormality simulation circuit is divided into a type of predicted operating power consumption abnormality simulation circuit.

[0087] It should be noted that in a type of predicted operation power consumption abnormal simulation circuit, since there are components that are predicted operation parameter abnormal components, it is necessary to perform abnormal processing on the predicted operation parameter abnormal components so that there are no predicted operation parameter abnormal components in the circuit. First, determine whether the predicted operation parameter abnormal component is a replaceable component. If so, the predicted operation parameter abnormal component can be directly replaced with a component of the same type but with no abnormal operation parameters, so that the predicted component operation parameters of all components in the type of predicted operation power consumption abnormal simulation circuit are not less than the corresponding standard component operation parameters. After replacing the components, the predicted operation parameter abnormal components that are not replaceable components are corrected so that there are no predicted operation parameter abnormal components in the type of predicted operation power consumption abnormal simulation circuit. At this time, if the circuit is qualified, it is calibrated as a qualified simulation circuit. If it is unqualified, it is divided into two types of predicted operation power consumption abnormal simulation circuits and continues to be analyzed. At this time, it is determined that although the individual parameters of the components in the circuit are correct, the position may be incorrect, resulting in abnormal power consumption.

[0088] Further, in a preferred embodiment of the present invention, the circuit fault point tracing is performed on the two types of predicted operation power consumption abnormal simulation circuits, and the hardware design optimization of the two types of predicted operation power consumption abnormal simulation circuits is performed based on the fault point tracing results, specifically:

[0089] In the second type of prediction operation power consumption abnormality simulation circuit, all network nodes are obtained, wherein the network nodes are elements in the second type of prediction operation power consumption abnormality simulation circuit;

[0090] The connection mode between different components is obtained in the second type of simulation circuit for predicting abnormal operation power consumption, and the directed edges between all network nodes are defined based on the connection mode between different components;

[0091] Run the second type of prediction operation power consumption abnormality simulation circuit, calculate the gradient value of the directed edge between all network nodes in real time, and calibrate it as the directed edge gradient value;

[0092] Preset a standard variation range of the directed edge gradient value, preset a gradient value analysis time, and determine whether the directed edge gradient value is maintained within the standard variation range of the directed edge gradient value during the gradient value analysis time;

[0093] If not, it is determined that there is an abnormality in the connection mode of the components in the second type of predicted operation power consumption abnormality simulation circuit, and in the second type of predicted operation power consumption abnormality simulation circuit, the components corresponding to the directed edge gradient values ​​that are not maintained within the directed edge gradient value standard variation range are determined and marked as connection abnormal components;

[0094] In the second type of predicted operation power consumption abnormality simulation circuit, the component architecture is adjusted for all abnormally connected components, and it is determined whether the abnormally connected components still exist after the component architecture is adjusted;

[0095] If so, all suitable connection modes for the abnormal connection components are retrieved based on the big data network, marked as the connection modes of the components to be selected, all the connection modes of the components to be selected are output, and the connection modes of the components to be selected that do not have abnormal connection components after output are marked as the target connection modes;

[0096] When there are no abnormally connected components in the second type of predicted operating power consumption abnormality simulation circuit, but the predicted operating power consumption parameters of the second type of predicted operating power consumption abnormality simulation circuit are still greater than the operating power consumption standard parameters, the circuit software optimization design of the second type of predicted operating power consumption abnormality simulation circuit is performed to obtain a simulation circuit whose predicted operating power consumption parameters are not greater than the operating power consumption standard parameters.

[0097] It should be noted that in the second type of simulation circuit for predicting abnormal operation power consumption, there may be errors in the connection relationship of the components, such as incorrect component position during the connection process, or the connection method is not a normal connection method, which will increase the operation power consumption of the circuit. Since the circuit is a circuit mapped by the graph neural network, when the circuit is running, the components are equal to the nodes in the graph neural network, and the nodes are connected by directed edges. The gradient value of the directed edge reflects the connection performance between the two nodes. If the connection performance between the two nodes does not match the expected performance, the gradient value of the directed edge will be abnormal, and the gradient value of the directed edge will not be maintained within the standard variation range of the directed edge gradient value during the gradient value analysis time. At this time, it is necessary to determine all components corresponding to the abnormal directed edge gradient value, mark them as abnormal connection components, and adjust the component architecture of the abnormal connection components to achieve hardware design optimization. Among them, the component architecture adjustment includes but is not limited to adjusting the connection position of the component, the shape of the component, etc. If there are still abnormal connection components after the component architecture is adjusted, it is necessary to use other connection methods to adjust the abnormal connection components, and judge that there is a problem with the connection method of the current abnormal connection component, and it is necessary to use other connection methods to connect.

[0098] Furthermore, in a preferred embodiment of the present invention, the circuit software optimization design of the second type of predicted operation power consumption abnormal simulation circuit is performed to obtain a simulation circuit whose predicted operation power consumption parameter is not greater than the operation power consumption standard parameter, specifically:

[0099] The second type of predicted abnormal operating power consumption simulation circuits after component architecture adjustment and target connection mode output are calibrated as simulation circuits to be optimized by the software;

[0100] Configuring an FPGA accelerator in the software to be optimized simulation circuit, wherein the FPGA accelerator is an accelerator for adjusting parameters of the graph neural network in the software to be optimized simulation circuit;

[0101] Run the software to be optimized analog circuit, calculate the predicted operating power consumption parameters of the software to be optimized analog circuit, introduce a Markov chain algorithm to analyze the predicted operating power consumption parameters of the software to be optimized analog circuit, determine the position that affects the predicted operating power consumption parameters of the software to be optimized analog circuit in the graph neural network of the software to be optimized analog circuit, and mark it as the power consumption parameter influencing position;

[0102] Obtain the graph neural network operating parameters at the position where the power consumption parameters affect the position, and adjust the graph neural network operating parameters at the position where the power consumption parameters affect the position in the FPGA accelerator until the predicted operating power consumption parameters of the simulation circuit to be optimized by the software are no greater than the operating power consumption standard parameters, thereby obtaining a qualified simulation circuit.

[0103] It should be noted that when the connection mode changes, that is, there is no abnormal connection element in the second type of predicted operation power consumption abnormal simulation circuit, but the predicted operation power consumption parameter of the second type of predicted operation power consumption abnormal simulation circuit is still greater than the standard operation power consumption parameter, the second type of predicted operation power consumption abnormal simulation circuit is marked as a software to be optimized simulation circuit, and the software to be optimized simulation circuit is optimized by software design, so as to achieve the purpose of reducing the operation power consumption of the circuit through software design. Configure the FPGA accelerator, and the FPGA accelerator adjusts the parameters and structure of the neural network model to adapt to the hardware characteristics of the FPGA. At the same time, the model compression and quantization technologies are used to reduce the storage requirements and calculation amount of the model, so as to achieve the purpose of reducing power consumption. The Markov chain algorithm analyzes the predicted operation power consumption parameters of the software to be optimized simulation circuit, and can determine the node position on the graph neural network that affects the circuit power consumption abnormality, that is, the power consumption parameter influence position, and adjust the graph neural network operation parameters of the power consumption parameter influence position through the FPGA accelerator until the circuit is adjusted to a qualified simulation circuit and then stop adjusting, so as to achieve that the predicted operation power consumption parameters of the software to be optimized simulation circuit are not greater than the standard operation power consumption parameters.

[0104] In addition, the integrated circuit hardware and software collaborative design optimization method based on graph neural network analysis also includes the following steps:

[0105] Adjusting the component architecture of all abnormally connected components is classified as hardware design optimization, and adjusting the operating parameters of the graph neural network that affects power consumption parameters in real time through the FPGA accelerator is classified as software design optimization.

[0106] Calculate the execution time of hardware design optimization and software design optimization respectively in real time, and preset the maximum execution time of hardware design optimization and software design optimization;

[0107] Perform hardware design optimization and software design optimization at the same time, and determine whether there is a time point within the maximum execution time of the hardware design optimization and software design optimization for the second type of predicted abnormal operation power consumption simulation circuit to be a qualified simulation circuit;

[0108] If so, the corresponding time point is marked as a qualified time point, and the real-time status of the hardware design optimization and the software design optimization at the qualified time point is output, wherein the real-time status of the hardware design optimization and the software design optimization are respectively the real-time component architecture of the abnormally connected component and the real-time parameters of the graph neural network operating parameters of the power consumption parameter-affecting position;

[0109] If not, determining whether the second type of predicted operation power consumption abnormal simulation circuit is a qualified simulation circuit after the maximum execution time of hardware design optimization and software design optimization;

[0110] If not, the second type of predicted operating power consumption abnormal simulation circuit is marked as an unqualified simulation circuit.

[0111] It should be noted that the advantages of software and hardware are combined for collaborative optimization. At the software level, optimization can be performed for specific hardware architectures to improve the execution efficiency of the software. At the hardware level, a flexible hardware architecture can be designed to adapt to different neural network models and application scenarios. Simultaneous hardware design optimization and software design optimization can improve the efficiency of power consumption processing, and the efficiency of simultaneous optimization is higher than that of separate optimization, because there may be a time point when hardware design optimization and software design optimization reach a balance, resulting in qualified circuit power consumption parameters. If there is a qualified analog circuit after the maximum execution time, it can be optimized by separate design. If there is still no qualified analog circuit after the maximum execution time, it proves that the circuit is scrapped.

[0112] like Figure 3 As shown, the second aspect of the present invention further provides an integrated circuit software and hardware collaborative design optimization system based on graph neural network analysis, the integrated circuit software and hardware collaborative design optimization system includes a memory 31 and a processor 32, the memory 31 stores an integrated circuit software and hardware collaborative design optimization method, and when the integrated circuit software and hardware collaborative design optimization method is executed by the processor 32, the following steps are implemented:

[0113] Constructing a graph neural network and a target analog integrated circuit, and mapping the graph neural network on the target analog integrated circuit to obtain a graph neural network mapping circuit;

[0114] Running the graph neural network mapping circuit, generating prediction data of the running power consumption parameters, performing a qualified analysis on the predicted data of the running power consumption parameters, and finally classifying the target analog integrated circuit based on the qualified analysis results;

[0115] The fault point of the classified graph neural network mapping circuit is traced, and the software and hardware design of the classified graph neural network mapping circuit is optimized based on the fault point tracing results.

[0116] The above are only specific embodiments of the present invention, but the protection scope of the present invention is not limited thereto. Any person skilled in the art who is familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed by the present invention, which should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention should be based on the protection scope of the claims.

Claims

1. An integrated circuit hardware and software collaborative design optimization method based on graph neural network analysis, characterized in that: The following steps are involved: Constructing a graph neural network and a target analog integrated circuit, and mapping the graph neural network on the target analog integrated circuit to obtain a graph neural network mapping circuit; Running the graph neural network mapping circuit, generating prediction data of the running power consumption parameters, performing a qualified analysis on the predicted data of the running power consumption parameters, and finally classifying the target analog integrated circuit based on the qualified analysis results; The fault point of the classified graph neural network mapping circuit is traced, and the software and hardware design of the classified graph neural network mapping circuit is optimized based on the fault point tracing results.

2. The integrated circuit hardware and software collaborative design optimization method based on graph neural network analysis according to claim 1, characterized in that: The graph neural network and the target analog integrated circuit are constructed, and the graph neural network is mapped on the target analog integrated circuit to obtain a graph neural network mapping circuit, specifically: Acquire an integrated circuit that needs to be analyzed for software and hardware, mark it as a target integrated circuit, and determine a circuit structure of the target integrated circuit in the target integrated circuit; Wherein, the circuit structure of the target integrated circuit includes circuit element parameters, circuit element arrangement positions and wire wiring scheme of the target integrated circuit; Introducing circuit simulation software, importing the circuit structure of the target integrated circuit into the circuit simulation software, and constructing a simulation circuit of the target integrated circuit in the circuit simulation software, expressed as a target simulated integrated circuit; Introducing a graph neural network benchmark model, wherein the graph neural network benchmark model includes an input layer, a hidden layer, and an output layer, and simultaneously introducing a big data network, in which the structural connection mode of the graph neural network benchmark model used for predicting indicator data of integrated circuits is retrieved and calibrated as the target structural connection mode; In the graph neural network benchmark model, the connection mode between the input layer, the hidden layer, and the output layer is set to the target structure connection mode to obtain the graph neural network model to be set; Running the target analog integrated circuit, and during the operation of the target analog integrated circuit, real-time monitoring of the operating power consumption parameters of the target analog integrated circuit is carried out, and the parameters are calibrated as the real-time operating power consumption parameters, and at the same time, real-time monitoring of the component operating parameters of different components in the target analog integrated circuit is carried out, and the parameters are calibrated as the real-time operating parameters of the circuit components; Perform feature analysis on the real-time power consumption parameters and the real-time operating parameters of circuit elements of different components to generate connection relationships of different components. Generate an adjacency matrix of the target analog integrated circuit based on the connection relationships of the different components. Import the adjacency matrix of the target analog integrated circuit, the real-time power consumption parameters and the real-time operating parameters of circuit elements of different components into the graph neural network model to be set for forward propagation to obtain a graph neural network mapping circuit.

3. The integrated circuit hardware and software collaborative design optimization method based on graph neural network analysis according to claim 1, characterized in that: The operation graph neural network mapping circuit generates prediction data of the operation power consumption parameters, performs a qualified analysis on the prediction data of the operation power consumption parameters, and finally classifies the target analog integrated circuit based on the qualified analysis results, specifically: A preset circuit operation time, during which a graph neural network mapping circuit is operated, wherein when the graph neural network mapping circuit is operated, operating power consumption parameters of the graph neural network mapping circuit and component operation parameters of different components after the circuit operation time can be predicted; After obtaining the circuit operation time, the graph neural network maps the operation power consumption parameters of the circuit and the component operation parameters of different components, and calibrates them into predicted operation power consumption parameters and predicted component operation parameters of different components; Preset standard data of predicted operating power consumption parameters, calibrate them as standard operating power consumption parameters, and simultaneously preset standard data of predicted component operating parameters of different components to obtain standard component operating parameters of different components; The predicted operating power consumption parameters and the predicted component operating parameters of different components are analyzed. If the predicted operating power consumption parameters are greater than the standard operating power consumption parameters, and there are components whose predicted component operating parameters are less than the corresponding standard component operating parameters, the graph neural network mapping circuit is calibrated as a type of predicted operating power consumption abnormal simulation circuit, and the corresponding component is calibrated as a predicted operating parameter abnormal component; If the predicted operating power consumption parameter is greater than the operating power consumption standard parameter, but there is no component whose predicted component operating parameter is less than the corresponding standard component operating parameter, the graph neural network mapping circuit is calibrated as a second-class predicted operating power consumption abnormal simulation circuit; If the predicted operating power consumption parameter is not greater than the operating power consumption standard parameter, the graph neural network mapping circuit is calibrated as a qualified analog circuit.

4. The integrated circuit hardware and software collaborative design optimization method based on graph neural network analysis according to claim 1, characterized in that: The fault point tracing of the classified graph neural network mapping circuit and the software and hardware design optimization of the classified graph neural network mapping circuit based on the fault point tracing result are specifically as follows: For a type of predicted operation power consumption abnormality simulation circuit, in the type of predicted operation power consumption abnormality simulation circuit, determining whether a component with abnormal predicted operation parameters is a replaceable component; Wherein, the replaceable component is a component that can be replaced with the same type in a type of predicted operation power consumption abnormality simulation circuit. If the predicted operation parameter abnormality component is a replaceable component, then in the type of predicted operation power consumption abnormality simulation circuit, the predicted operation parameter abnormality component that is a replaceable component is simulated replaced; If the component with abnormal predicted operating parameters is not a replaceable component, a correction scheme for the component with abnormal predicted operating parameters is retrieved in the big data network and outputted so that the predicted component operating parameters of all components in a type of predicted operating power consumption abnormality simulation circuit are not less than the corresponding standard component operating parameters; When the predicted component operating parameters of all components in a type of predicted abnormal operating power consumption simulation circuit are not less than the corresponding standard component operating parameters, and the predicted operating power consumption parameters of a type of predicted abnormal operating power consumption simulation circuit are not greater than the operating power consumption standard parameters, the type of predicted abnormal operating power consumption simulation circuit is classified as a qualified simulation circuit; When the predicted component operating parameters of all components in a type of predicted operating power consumption abnormality simulation circuit are not less than the corresponding standard component operating parameters, the predicted operating power consumption parameters of the type of predicted operating power consumption abnormality simulation circuit are still greater than the operating power consumption standard parameters, then the type of predicted operating power consumption abnormality simulation circuit is divided into a type of predicted operating power consumption abnormality simulation circuit; The circuit fault point traceback is performed on the second type of predicted operating power consumption abnormality simulation circuit, and the software and hardware design of the second type of predicted operating power consumption abnormality simulation circuit is optimized based on the fault point tracing results.

5. The integrated circuit hardware and software collaborative design optimization method based on graph neural network analysis according to claim 4, characterized in that: The circuit fault point tracing is performed on the two types of predicted operation power consumption abnormal simulation circuits, and the software and hardware design optimization is performed on the two types of predicted operation power consumption abnormal simulation circuits based on the fault point tracing results, specifically: In the second type of prediction operation power consumption abnormality simulation circuit, all network nodes are obtained, wherein the network nodes are elements in the second type of prediction operation power consumption abnormality simulation circuit; The connection mode between different components is obtained in the second type of simulation circuit for predicting abnormal operation power consumption, and the directed edges between all network nodes are defined based on the connection mode between different components; Run the second type of prediction operation power consumption abnormality simulation circuit, calculate the gradient value of the directed edge between all network nodes in real time, and calibrate it as the directed edge gradient value; Preset a standard variation range of the directed edge gradient value, preset a gradient value analysis time, and determine whether the directed edge gradient value is maintained within the standard variation range of the directed edge gradient value during the gradient value analysis time; If not, it is determined that there is an abnormality in the connection mode of the components in the second type of predicted operation power consumption abnormality simulation circuit, and in the second type of predicted operation power consumption abnormality simulation circuit, the components corresponding to the directed edge gradient values ​​that are not maintained within the directed edge gradient value standard variation range are determined and marked as connection abnormal components; In the second type of predicted operation power consumption abnormality simulation circuit, the component architecture is adjusted for all abnormally connected components, and it is determined whether the abnormally connected components still exist after the component architecture is adjusted; If so, all suitable connection modes for the abnormal connection components are retrieved based on the big data network, marked as the connection modes of the components to be selected, all the connection modes of the components to be selected are output, and the connection modes of the components to be selected that do not have abnormal connection components after output are marked as the target connection modes; When there are no abnormally connected components in the second type of predicted operating power consumption abnormality simulation circuit, but the predicted operating power consumption parameters of the second type of predicted operating power consumption abnormality simulation circuit are still greater than the operating power consumption standard parameters, the circuit software optimization design of the second type of predicted operating power consumption abnormality simulation circuit is performed to obtain a simulation circuit whose predicted operating power consumption parameters are not greater than the operating power consumption standard parameters.

6. The integrated circuit hardware and software collaborative design optimization method based on graph neural network analysis according to claim 5, characterized in that: The circuit software optimization design of the second type of predicted operation power consumption abnormal simulation circuit is performed to obtain a simulation circuit whose predicted operation power consumption parameter is not greater than the operation power consumption standard parameter, specifically: The second type of predicted abnormal operating power consumption simulation circuits after component architecture adjustment and target connection mode output are calibrated as simulation circuits to be optimized by the software; Configuring an FPGA accelerator in the software to be optimized simulation circuit, wherein the FPGA accelerator is an accelerator for adjusting parameters of the graph neural network in the software to be optimized simulation circuit; Run the software to be optimized analog circuit, calculate the predicted operating power consumption parameters of the software to be optimized analog circuit, introduce a Markov chain algorithm to analyze the predicted operating power consumption parameters of the software to be optimized analog circuit, determine the position that affects the predicted operating power consumption parameters of the software to be optimized analog circuit in the graph neural network of the software to be optimized analog circuit, and mark it as the power consumption parameter influencing position; Obtain the graph neural network operating parameters at the position where the power consumption parameters affect the position, and adjust the graph neural network operating parameters at the position where the power consumption parameters affect the position in the FPGA accelerator until the predicted operating power consumption parameters of the simulation circuit to be optimized by the software are no greater than the operating power consumption standard parameters, thereby obtaining a qualified simulation circuit.

7. An integrated circuit hardware and software collaborative design optimization system based on graph neural network analysis, characterized in that: The integrated circuit software and hardware collaborative design optimization system includes a memory and a processor, wherein the integrated circuit software and hardware collaborative design optimization method program is stored in the memory, and when the integrated circuit software and hardware collaborative design optimization method program is executed by the processor, the steps of the integrated circuit software and hardware collaborative design optimization method based on graph neural network analysis as described in any one of claims 1 to 6 are implemented: Constructing a graph neural network and a target analog integrated circuit, and mapping the graph neural network on the target analog integrated circuit to obtain a graph neural network mapping circuit; Running the graph neural network mapping circuit, generating prediction data of the running power consumption parameters, performing a qualified analysis on the predicted data of the running power consumption parameters, and finally classifying the target analog integrated circuit based on the qualified analysis results; The fault point of the classified graph neural network mapping circuit is traced, and the software and hardware design of the classified graph neural network mapping circuit is optimized based on the fault point tracing results.

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