Integrated Circuit Hardware and Software Co-design Optimization Method Based on Graph Neural Network Analysis

Abstract

The present invention relates to the field of integrated circuits and discloses a method for collaborative design and optimization of integrated circuit software and hardware based on graph neural network analysis, comprising the following steps: mapping a graph neural network onto a target analog integrated circuit to obtain a graph neural network mapping circuit, predicting and classifying power consumption parameters of the graph neural network mapping circuit, and finally tracing the fault points and optimizing the software and hardware design of the classified graph neural network mapping circuit. The present invention can determine the locations in the integrated circuit that require software and hardware design optimization through graph neural network mapping, and implement software and hardware design optimization based on different locations and parameters, thereby reducing the power consumption generated by the circuit during operation, achieving energy conservation and emission reduction, and achieving the purpose of this invention.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuits, and in particular to an integrated circuit software and hardware collaborative design optimization method based on graph neural network analysis. Background Art

[0002] Graph neural networks are a type of neural network model specifically designed to process graph-structured data. Graph-structured data is a complex relational network consisting of nodes and directed edges, where nodes represent entities and edges represent relationships between entities. This data structure is widely present in the real world, such as social networks, knowledge graphs, and molecular structures. Integrated circuits are the core of modern electronic devices. Their design complexity and every subtle manufacturing step directly impact the performance of the final product. Software-hardware co-design is an effective approach that aims to improve overall system performance by combining the strengths of software and hardware. Graph neural networks, as a powerful artificial intelligence technology, can process and analyze complex graph-structured data, providing new insights into software-hardware co-design for integrated circuits. By mapping graph neural networks onto integrated circuits, graph neural networks can predict the location of IC faults, significantly improving IC performance and efficiency. Therefore, we propose an optimization method for integrated circuit software-hardware co-design based on graph neural network analysis. Summary of the Invention

[0003] The present invention overcomes the shortcomings of the prior art and provides an integrated circuit software and hardware collaborative design optimization method based on graph neural network analysis.

[0004] In order to achieve the above object, the technical solution adopted by the present invention is:

[0005] A first aspect of the present invention provides an integrated circuit hardware and software collaborative design optimization method based on graph neural network analysis, comprising the following steps:

[0006] Constructing a graph neural network and a target analog integrated circuit, and mapping the graph neural network onto the target analog integrated circuit to obtain a graph neural network mapping circuit;

[0007] Running a graph neural network mapping circuit to generate prediction data of operating power consumption parameters, performing a qualification analysis on the prediction data of the operating power consumption parameters, and finally classifying the target analog integrated circuit based on the qualification analysis results;

[0008] The fault point of the classified graph neural network mapping circuit is traced, and the software and hardware design of the classified graph neural network mapping circuit is optimized based on the fault point tracing results.

[0009] Furthermore, in a preferred embodiment of the present invention, the graph neural network and the target analog integrated circuit are constructed, and the graph neural network is mapped on the target analog integrated circuit to obtain a graph neural network mapping circuit, specifically:

[0010] Obtaining an integrated circuit that requires software and hardware analysis, marking it as a target integrated circuit, and determining a circuit structure of the target integrated circuit in the target integrated circuit;

[0011] The circuit structure of the target integrated circuit includes circuit element parameters, circuit element arrangement positions, and wire routing scheme of the target integrated circuit;

[0012] Introducing circuit simulation software, importing the circuit structure of the target integrated circuit into the circuit simulation software, and constructing a simulation circuit of the target integrated circuit in the circuit simulation software, expressed as a target simulated integrated circuit;

[0013] Introducing a graph neural network benchmark model, wherein the graph neural network benchmark model includes an input layer, a hidden layer, and an output layer. Simultaneously, introducing a big data network, retrieving the structural connection mode of the graph neural network benchmark model used for predicting indicator data of integrated circuits in the big data network, and calibrating it as the target structural connection mode;

[0014] In the graph neural network benchmark model, the connection mode between the input layer, hidden layer, and output layer is set to the target structure connection mode to obtain the graph neural network model to be set;

[0015] Running the target analog integrated circuit, and monitoring the operating power consumption parameters of the target analog integrated circuit in real time during the operation of the target analog integrated circuit, and calibrating the parameters into real-time operating power consumption parameters, while also monitoring the component operating parameters of different components in the target analog integrated circuit in real time, and calibrating the parameters into real-time operating parameters of circuit components;

[0016] Perform feature analysis on the real-time power consumption parameters and the real-time operating parameters of circuit elements of different components to generate the connection relationship of different components. Based on the connection relationship of the different components, generate the adjacency matrix of the target analog integrated circuit. Import the adjacency matrix of the target analog integrated circuit, the real-time power consumption parameters and the real-time operating parameters of circuit elements of different components into the graph neural network model to be set for forward propagation to obtain the graph neural network mapping circuit.

[0017] Furthermore, in a preferred embodiment of the present invention, the operation graph neural network mapping circuit generates prediction data of the operation power consumption parameters, performs a qualification analysis on the prediction data of the operation power consumption parameters, and finally classifies the target analog integrated circuit based on the qualification analysis results, specifically:

[0018] Preset circuit operation time, and operate the graph neural network mapping circuit during the circuit operation time, wherein, when the graph neural network mapping circuit is operated, operating power consumption parameters of the graph neural network mapping circuit and component operation parameters of different components after the circuit operation time are predicted;

[0019] After obtaining the circuit operation time, the graph neural network maps the circuit operation power consumption parameters and the component operation parameters of different components, and calibrates them into predicted operation power consumption parameters and predicted component operation parameters of different components;

[0020] Presetting standard data for predicting operating power consumption parameters and calibrating them as standard operating power consumption parameters; and simultaneously presetting standard data for predicting component operating parameters of different components to obtain standard component operating parameters of different components;

[0021] The predicted operating power consumption parameters and the predicted component operating parameters of different components are analyzed. If the predicted operating power consumption parameters are greater than the standard operating power consumption parameters, and there are components whose predicted component operating parameters are less than the corresponding standard component operating parameters, the graph neural network mapping circuit is calibrated as a type of predicted operating power consumption abnormal simulation circuit, and the corresponding component is calibrated as a predicted operating parameter abnormal component;

[0022] If the predicted operating power consumption parameter is greater than the standard operating power consumption parameter, but there is no component whose predicted component operating parameter is less than the corresponding standard component operating parameter, then the graph neural network mapping circuit is calibrated as a second-class predicted operating power consumption abnormal simulation circuit;

[0023] If the predicted operating power consumption parameter is not greater than the operating power consumption standard parameter, the graph neural network mapping circuit is calibrated as a qualified analog circuit.

[0024] Furthermore, in a preferred embodiment of the present invention, the fault point tracing of the classified graph neural network mapping circuit is performed, and the software and hardware design of the classified graph neural network mapping circuit is optimized based on the fault point tracing result, specifically:

[0025] For a type of predicted operation power consumption abnormality simulation circuit, within the type of predicted operation power consumption abnormality simulation circuit, determining whether a component with abnormal predicted operation parameters is a replaceable component;

[0026] Wherein, the replaceable component is a component that can be replaced with a similar component in a type of predicted operation power consumption abnormality simulation circuit. If the component with abnormal predicted operation parameters is a replaceable component, then in the type of predicted operation power consumption abnormality simulation circuit, the component with abnormal predicted operation parameters that is a replaceable component is simulated replaced;

[0027] If the component with the predicted abnormal operating parameters is not a replaceable component, a correction solution for the component with the predicted abnormal operating parameters is retrieved from the big data network and outputted, so that the predicted component operating parameters of all components in a type of predicted abnormal operating power consumption simulation circuit are not less than the corresponding standard component operating parameters;

[0028] When the predicted component operating parameters of all components in a type of predicted operating power consumption abnormality simulation circuit are not less than the corresponding standard component operating parameters, and the predicted operating power consumption parameters of the type of predicted operating power consumption abnormality simulation circuit are not greater than the operating power consumption standard parameters, the type of predicted operating power consumption abnormality simulation circuit is classified as a qualified simulation circuit;

[0029] When the predicted component operating parameters of all components in a type of predicted operating power consumption abnormality simulation circuit are not less than the corresponding standard component operating parameters, the predicted operating power consumption parameters of the type of predicted operating power consumption abnormality simulation circuit are still greater than the operating power consumption standard parameters, then the type of predicted operating power consumption abnormality simulation circuit is divided into a type two predicted operating power consumption abnormality simulation circuit;

[0030] The circuit fault point tracing is performed on the second type of predicted operating power consumption abnormality simulation circuit, and the software and hardware design of the second type of predicted operating power consumption abnormality simulation circuit is optimized based on the fault point tracing results.

[0031] Furthermore, in a preferred embodiment of the present invention, the circuit fault point tracing is performed on the second type of predicted operating power consumption abnormality simulation circuit, and the software and hardware design optimization of the second type of predicted operating power consumption abnormality simulation circuit is performed based on the fault point tracing result, specifically:

[0032] In the second type of predicted operation power consumption abnormality simulation circuit, all network nodes are obtained, wherein the network nodes are elements in the second type of predicted operation power consumption abnormality simulation circuit;

[0033] Obtain the connection mode between different components in the second type of predicted operating power consumption anomaly simulation circuit, and define the directed edges between all network nodes based on the connection mode between different components;

[0034] Running the second type of predicted power consumption anomaly simulation circuit, calculating the gradient values ​​of directed edges between all network nodes in real time, and calibrating them as directed edge gradient values;

[0035] Preset a standard variation range of the directed edge gradient value and a gradient value analysis time, and determine whether the directed edge gradient value is maintained within the standard variation range of the directed edge gradient value within the gradient value analysis time;

[0036] If not, it is determined that there is an abnormality in the connection mode of the components in the second type of predicted operating power consumption abnormality simulation circuit, and in the second type of predicted operating power consumption abnormality simulation circuit, the components corresponding to the directed edge gradient values ​​that do not remain within the standard variation range of the directed edge gradient values ​​are determined and marked as connection abnormal components;

[0037] In the second type of predicted operation power consumption abnormality simulation circuit, adjusting the component architecture of all abnormally connected components, and determining whether the abnormally connected components still exist after the component architecture adjustment;

[0038] If so, all suitable connection modes for connecting abnormal components are retrieved based on the big data network, and are marked as connection modes of components to be selected. All connection modes of components to be selected are output, and the connection modes of components to be selected that do not contain abnormal connection components after output are marked as target connection modes.

[0039] When there are no abnormal connection components in the second-category predicted operating power consumption abnormality simulation circuit, but the predicted operating power consumption parameters of the second-category predicted operating power consumption abnormality simulation circuit are still greater than the operating power consumption standard parameters, the circuit software optimization design of the second-category predicted operating power consumption abnormality simulation circuit is performed to obtain a simulation circuit whose predicted operating power consumption parameters are not greater than the operating power consumption standard parameters.

[0040] Furthermore, in a preferred embodiment of the present invention, the circuit software optimization design of the second type of predicted abnormal operating power consumption simulation circuit is performed to obtain a simulation circuit whose predicted operating power consumption parameter is not greater than the operating power consumption standard parameter, specifically:

[0041] The second type of predicted abnormal operating power consumption simulation circuits after component architecture adjustment and target connection mode output are calibrated as simulation circuits to be optimized by the software;

[0042] Configuring an FPGA accelerator in the software simulation circuit to be optimized, wherein the FPGA accelerator is an accelerator for adjusting parameters of the graph neural network in the software simulation circuit to be optimized;

[0043] Running the software to be optimized analog circuit, calculating the predicted operating power consumption parameters of the software to be optimized analog circuit, and introducing a Markov chain algorithm to analyze the predicted operating power consumption parameters of the software to be optimized analog circuit, determining the position that affects the predicted operating power consumption parameters of the software to be optimized analog circuit in the graph neural network of the software to be optimized analog circuit, and marking it as the power consumption parameter influencing position;

[0044] Obtain the graph neural network operating parameters at the position where the power consumption parameters affect the graph neural network, and adjust the parameters of the graph neural network operating parameters at the position where the power consumption parameters affect the graph neural network in the FPGA accelerator until the predicted operating power consumption parameters of the simulation circuit to be optimized by the software are no greater than the standard operating power consumption parameters, thereby obtaining a qualified simulation circuit.

[0045] A second aspect of the present invention further provides an integrated circuit software and hardware collaborative design optimization system based on graph neural network analysis. The integrated circuit software and hardware collaborative design optimization system includes a memory and a processor. The memory stores an integrated circuit software and hardware collaborative design optimization method. When the integrated circuit software and hardware collaborative design optimization method is executed by the processor, the following steps are implemented:

[0046] Constructing a graph neural network and a target analog integrated circuit, and mapping the graph neural network onto the target analog integrated circuit to obtain a graph neural network mapping circuit;

[0047] Running a graph neural network mapping circuit to generate prediction data of operating power consumption parameters, performing a qualification analysis on the prediction data of the operating power consumption parameters, and finally classifying the target analog integrated circuit based on the qualification analysis results;

[0048] The fault point of the classified graph neural network mapping circuit is traced, and the software and hardware design of the classified graph neural network mapping circuit is optimized based on the fault point tracing results.

[0049] The present invention solves the technical defects existing in the background technology, and has the following beneficial effects: mapping the graph neural network on the target analog integrated circuit to obtain a graph neural network mapping circuit, and predicting and classifying the power consumption parameters of the graph neural network mapping circuit, and finally tracing the fault point and optimizing the software and hardware design of the classified graph neural network mapping circuit. The present invention can determine the locations in the integrated circuit that require software and hardware design optimization by means of graph neural network mapping, and realize software and hardware design optimization according to different locations and parameters, thereby reducing the power consumption generated by the circuit during operation, achieving energy conservation and emission reduction, and achieving the purpose of this gain. BRIEF DESCRIPTION OF THE DRAWINGS

[0050] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, without paying any creative work, they can also obtain drawings of other embodiments based on these drawings.

[0051] Figure 1 A flowchart of an integrated circuit hardware and software collaborative design optimization method based on graph neural network analysis is shown;

[0052] Figure 2 A flow chart of a method for optimizing the software and hardware design of a classified graph neural network mapping circuit is shown;

[0053] Figure 3The program view of the integrated circuit hardware and software collaborative design optimization system based on graph neural network analysis is shown. DETAILED DESCRIPTION

[0054] In order to more clearly understand the above-mentioned objects, features and advantages of the present invention, the present invention is further described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be noted that, in the absence of conflict, the embodiments of the present application and the features therein can be combined with each other.

[0055] In the following description, many specific details are set forth to facilitate a full understanding of the present invention. However, the present invention may also be implemented in other ways different from those described herein. Therefore, the scope of protection of the present invention is not limited to the specific embodiments disclosed below.

[0056] Figure 1 A flowchart of an integrated circuit hardware and software collaborative design optimization method based on graph neural network analysis is shown, comprising the following steps:

[0057] S102: Construct a graph neural network and a target analog integrated circuit, and map the graph neural network onto the target analog integrated circuit to obtain a graph neural network mapping circuit;

[0058] S104: running the graph neural network mapping circuit to generate prediction data of the operation power consumption parameters, performing a qualification analysis on the prediction data of the operation power consumption parameters, and finally classifying the target analog integrated circuit based on the qualification analysis results;

[0059] S106: Trace the fault point of the classified graph neural network mapping circuit, and optimize the software and hardware design of the classified graph neural network mapping circuit based on the fault point tracing results.

[0060] Furthermore, in a preferred embodiment of the present invention, the graph neural network and the target analog integrated circuit are constructed, and the graph neural network is mapped on the target analog integrated circuit to obtain a graph neural network mapping circuit, specifically:

[0061] Obtaining an integrated circuit that requires software and hardware analysis, marking it as a target integrated circuit, and determining a circuit structure of the target integrated circuit in the target integrated circuit;

[0062] The circuit structure of the target integrated circuit includes circuit element parameters, circuit element arrangement positions, and wire routing scheme of the target integrated circuit;

[0063] Introducing circuit simulation software, importing the circuit structure of the target integrated circuit into the circuit simulation software, and constructing a simulation circuit of the target integrated circuit in the circuit simulation software, expressed as a target simulated integrated circuit;

[0064] Introducing a graph neural network benchmark model, wherein the graph neural network benchmark model includes an input layer, a hidden layer, and an output layer. Simultaneously, introducing a big data network, retrieving the structural connection mode of the graph neural network benchmark model used for predicting indicator data of integrated circuits in the big data network, and calibrating it as the target structural connection mode;

[0065] In the graph neural network benchmark model, the connection mode between the input layer, hidden layer, and output layer is set to the target structure connection mode to obtain the graph neural network model to be set;

[0066] Running the target analog integrated circuit, and monitoring the operating power consumption parameters of the target analog integrated circuit in real time during the operation of the target analog integrated circuit, and calibrating the parameters into real-time operating power consumption parameters, while also monitoring the component operating parameters of different components in the target analog integrated circuit in real time, and calibrating the parameters into real-time operating parameters of circuit components;

[0067] Perform feature analysis on the real-time power consumption parameters and the real-time operating parameters of circuit elements of different components to generate the connection relationship of different components. Based on the connection relationship of the different components, generate the adjacency matrix of the target analog integrated circuit. Import the adjacency matrix of the target analog integrated circuit, the real-time power consumption parameters and the real-time operating parameters of circuit elements of different components into the graph neural network model to be set for forward propagation to obtain the graph neural network mapping circuit.

[0068] It should be noted that an integrated circuit (IC) is a circuit that integrates multiple functions. It contains various circuit elements, connected by connecting wires. Constructing an IC simulation circuit allows for mapping a graph neural network onto the IC, enabling circuit fault point prediction on the IC through the graph neural network. This is more efficient when performed within simulation software. After constructing the target analog IC within circuit simulation software, the graph neural network needs to be mapped onto the target IC. This allows the target IC to monitor fault points and power consumption data in real time during operation, facilitating software and hardware design optimization. First, a graph neural network benchmark model is introduced, and the appropriate connections between its input, hidden, and output layers are determined to achieve a preliminary construction of the graph neural network model. This preliminary construction of the graph neural network model is suitable for analyzing IC runtime parameters. After importing the real-time power consumption parameters and the real-time operating parameters of different circuit components into the Graph Neural Network model to be configured, combined with the adjacency matrix, the Graph Neural Network mapping circuit can be obtained. The purpose of constructing the adjacency matrix is ​​to enable forward propagation of cloud core parameters within the model, achieving the goal of mapping the graph neural network onto the circuit.

[0069] Furthermore, in a preferred embodiment of the present invention, the operation graph neural network mapping circuit generates prediction data of the operation power consumption parameters, performs a qualification analysis on the prediction data of the operation power consumption parameters, and finally classifies the target analog integrated circuit based on the qualification analysis results, specifically:

[0070] Preset circuit operation time, and operate the graph neural network mapping circuit during the circuit operation time, wherein, when the graph neural network mapping circuit is operated, operating power consumption parameters of the graph neural network mapping circuit and component operation parameters of different components after the circuit operation time are predicted;

[0071] After obtaining the circuit operation time, the graph neural network maps the circuit operation power consumption parameters and the component operation parameters of different components, and calibrates them into predicted operation power consumption parameters and predicted component operation parameters of different components;

[0072] Presetting standard data for predicting operating power consumption parameters and calibrating them as standard operating power consumption parameters; and simultaneously presetting standard data for predicting component operating parameters of different components to obtain standard component operating parameters of different components;

[0073] The predicted operating power consumption parameters and the predicted component operating parameters of different components are analyzed. If the predicted operating power consumption parameters are greater than the standard operating power consumption parameters, and there are components whose predicted component operating parameters are less than the corresponding standard component operating parameters, the graph neural network mapping circuit is calibrated as a type of predicted operating power consumption abnormal simulation circuit, and the corresponding component is calibrated as a predicted operating parameter abnormal component;

[0074] If the predicted operating power consumption parameter is greater than the standard operating power consumption parameter, but there is no component whose predicted component operating parameter is less than the corresponding standard component operating parameter, then the graph neural network mapping circuit is calibrated as a second-class predicted operating power consumption abnormal simulation circuit;

[0075] If the predicted operating power consumption parameter is not greater than the operating power consumption standard parameter, the graph neural network mapping circuit is calibrated as a qualified analog circuit.

[0076] It should be noted that after mapping the graph neural network onto the target analog integrated circuit, the graph neural network is used to predict the circuit's operating time and the operating power consumption parameters of the circuit and the component operating parameters of different components. The purpose is to determine whether the circuit can maintain a low operating power consumption level after the circuit's operating time. Standard parameters are preset, and the predicted operating power consumption parameters and the predicted component operating parameters of different components are compared with the corresponding standard parameters. Based on the comparison results, the graph neural network-mapped circuit is classified. The classification method is as follows: if the predicted component operating parameter of a component is less than the corresponding standard component operating parameter, the circuit's predicted operating power consumption must be greater than the standard value. In this case, the circuit is labeled as a Class I analog circuit with abnormal predicted operating power consumption, and the corresponding component is labeled as a component with abnormal predicted operating parameter. Conversely, if the predicted component operating parameter of a component is not less than the corresponding standard component operating parameter, but the circuit's predicted operating power consumption is still greater than the standard value, it indicates that the circuit may have an anomaly in the component connection method or connection architecture, and the circuit is labeled as a Class II analog circuit with abnormal predicted operating power consumption.

[0077] Figure 2 A flowchart of a method for optimizing the software and hardware design of a classified graph neural network mapping circuit is shown, including the following steps:

[0078] S202: Performing component analysis on a type of simulated circuit with predicted abnormal operating power consumption, and performing simulated replacement of replaceable components based on the case analysis results;

[0079] S204: tracing the circuit fault point of the second type of predicted abnormal operation power consumption simulation circuit, and optimizing the hardware design of the second type of predicted abnormal operation power consumption simulation circuit based on the fault point tracing result;

[0080] S206: performing circuit software optimization design on the second type of predicted abnormal operating power consumption simulation circuit to obtain a simulation circuit whose predicted operating power consumption parameters are not greater than standard operating power consumption parameters.

[0081] Furthermore, in a preferred embodiment of the present invention, the component analysis of a type of predicted abnormal operating power consumption simulation circuit is performed, and the simulated replacement of replaceable components is performed based on the case analysis results, specifically:

[0082] For a type of predicted operation power consumption abnormality simulation circuit, within the type of predicted operation power consumption abnormality simulation circuit, determining whether a component with abnormal predicted operation parameters is a replaceable component;

[0083] Wherein, the replaceable component is a component that can be replaced with a similar component in a type of predicted operation power consumption abnormality simulation circuit. If the component with abnormal predicted operation parameters is a replaceable component, then in the type of predicted operation power consumption abnormality simulation circuit, the component with abnormal predicted operation parameters that is a replaceable component is simulated replaced;

[0084] If the component with the predicted abnormal operating parameters is not a replaceable component, a correction solution for the component with the predicted abnormal operating parameters is retrieved from the big data network and outputted, so that the predicted component operating parameters of all components in a type of predicted abnormal operating power consumption simulation circuit are not less than the corresponding standard component operating parameters;

[0085] When the predicted component operating parameters of all components in a type of predicted operating power consumption abnormality simulation circuit are not less than the corresponding standard component operating parameters, and the predicted operating power consumption parameters of the type of predicted operating power consumption abnormality simulation circuit are not greater than the operating power consumption standard parameters, the type of predicted operating power consumption abnormality simulation circuit is classified as a qualified simulation circuit;

[0086] When the predicted component operating parameters of all components in a type of predicted operating power consumption abnormality simulation circuit are not less than the corresponding standard component operating parameters, the predicted operating power consumption parameters of the type of predicted operating power consumption abnormality simulation circuit are still greater than the operating power consumption standard parameters, then the type of predicted operating power consumption abnormality simulation circuit is divided into a type of predicted operating power consumption abnormality simulation circuit.

[0087] It should be noted that in a type of predicted operating power consumption abnormality simulation circuit, since there are components with abnormal predicted operating parameters, it is necessary to perform abnormal processing on the components with abnormal predicted operating parameters so that there are no abnormal predicted operating parameters components in the circuit. First, determine whether the components with abnormal predicted operating parameters are replaceable components. If so, the components with abnormal predicted operating parameters can be directly replaced with components of the same type but with normal operating parameters, so that the predicted component operating parameters of all components in the type of predicted operating power consumption abnormality simulation circuit are not less than the corresponding standard component operating parameters. After the components are replaced, the components with abnormal predicted operating parameters that are not replaceable components are corrected so that there are no abnormal predicted operating parameters components in the type of predicted operating power consumption abnormality simulation circuit. At this time, if the circuit is qualified, it is calibrated as a qualified simulation circuit. If it is unqualified, it is divided into the second type of predicted operating power consumption abnormality simulation circuit and continues to be analyzed. At this time, it is determined that although the individual parameters of the components in the circuit are correct, the positions may be incorrect, resulting in abnormal power consumption.

[0088] Furthermore, in a preferred embodiment of the present invention, the circuit fault point tracing is performed on the two types of predicted operating power consumption abnormality simulation circuits, and the hardware design optimization of the two types of predicted operating power consumption abnormality simulation circuits is performed based on the fault point tracing results, specifically:

[0089] In the second type of predicted operation power consumption abnormality simulation circuit, all network nodes are obtained, wherein the network nodes are elements in the second type of predicted operation power consumption abnormality simulation circuit;

[0090] Obtain the connection mode between different components in the second type of predicted operating power consumption anomaly simulation circuit, and define the directed edges between all network nodes based on the connection mode between different components;

[0091] Running the second type of predicted power consumption anomaly simulation circuit, calculating the gradient values ​​of directed edges between all network nodes in real time, and calibrating them as directed edge gradient values;

[0092] Preset a standard variation range of the directed edge gradient value and a gradient value analysis time, and determine whether the directed edge gradient value is maintained within the standard variation range of the directed edge gradient value within the gradient value analysis time;

[0093] If not, it is determined that there is an abnormality in the connection mode of the components in the second type of predicted operating power consumption abnormality simulation circuit, and in the second type of predicted operating power consumption abnormality simulation circuit, the components corresponding to the directed edge gradient values ​​that do not remain within the standard variation range of the directed edge gradient values ​​are determined and marked as connection abnormal components;

[0094] In the second type of predicted operation power consumption abnormality simulation circuit, adjusting the component architecture of all abnormally connected components, and determining whether the abnormally connected components still exist after the component architecture adjustment;

[0095] If so, all suitable connection modes for connecting abnormal components are retrieved based on the big data network, and are marked as connection modes of components to be selected. All connection modes of components to be selected are output, and the connection modes of components to be selected that do not contain abnormal connection components after output are marked as target connection modes.

[0096] When there are no abnormal connection components in the second-category predicted operating power consumption abnormality simulation circuit, but the predicted operating power consumption parameters of the second-category predicted operating power consumption abnormality simulation circuit are still greater than the operating power consumption standard parameters, the circuit software optimization design of the second-category predicted operating power consumption abnormality simulation circuit is performed to obtain a simulation circuit whose predicted operating power consumption parameters are not greater than the operating power consumption standard parameters.

[0097] It should be noted that in the second-category simulation circuit for predicting abnormal operating power consumption, component connections may contain errors. For example, incorrect component placement or abnormal connection methods during connection can increase the circuit's operating power consumption. Since the circuit is mapped using a graph neural network, during circuit operation, the components are equivalent to nodes in the graph neural network. Nodes are connected by directed edges, and the gradient of a directed edge reflects the performance of the connection between the two nodes. If the connection performance between the two nodes does not meet expectations, the gradient of the directed edge will be abnormal. During the gradient analysis time, the gradient of the directed edge will not remain within the standard variation range of the directed edge gradient value. In this case, it is necessary to identify all components with abnormal directed edge gradient values, label them as abnormal connection components, and adjust the component architecture of these abnormal connection components to achieve hardware design optimization. Component architecture adjustments include, but are not limited to, adjusting component connection positions and shapes. If abnormal connection components still exist after the component architecture adjustments, it is necessary to adjust the abnormal connection components using alternative connection methods. This indicates that there is a problem with the current connection method of the abnormal connection component and that a different connection method is needed.

[0098] Furthermore, in a preferred embodiment of the present invention, the circuit software optimization design of the second type of predicted abnormal operating power consumption simulation circuit is performed to obtain a simulation circuit whose predicted operating power consumption parameter is not greater than the operating power consumption standard parameter, specifically:

[0099] The second type of predicted abnormal operating power consumption simulation circuits after component architecture adjustment and target connection mode output are calibrated as simulation circuits to be optimized by the software;

[0100] Configuring an FPGA accelerator in the software simulation circuit to be optimized, wherein the FPGA accelerator is an accelerator for adjusting parameters of the graph neural network in the software simulation circuit to be optimized;

[0101] Running the software to be optimized analog circuit, calculating the predicted operating power consumption parameters of the software to be optimized analog circuit, and introducing a Markov chain algorithm to analyze the predicted operating power consumption parameters of the software to be optimized analog circuit, determining the position that affects the predicted operating power consumption parameters of the software to be optimized analog circuit in the graph neural network of the software to be optimized analog circuit, and marking it as the power consumption parameter influencing position;

[0102] Obtain the graph neural network operating parameters at the position where the power consumption parameters affect the graph neural network, and adjust the parameters of the graph neural network operating parameters at the position where the power consumption parameters affect the graph neural network in the FPGA accelerator until the predicted operating power consumption parameters of the simulation circuit to be optimized by the software are no greater than the standard operating power consumption parameters, thereby obtaining a qualified simulation circuit.

[0103] It should be noted that if the connection structure changes, meaning there are no connection anomalies in the second-category predicted power consumption anomaly simulation circuit, but the predicted power consumption parameters of the second-category predicted power consumption anomaly simulation circuit are still greater than the standard operating power consumption parameters, the second-category predicted power consumption anomaly simulation circuit is designated as a software-optimized simulation circuit and software design optimization is performed on the software-optimized simulation circuit to achieve the goal of reducing the circuit's operating power consumption through software design. An FPGA accelerator is configured to adjust the parameters and structure of the neural network model to adapt to the hardware characteristics of the FPGA. Simultaneously, model compression and quantization techniques are utilized to reduce the model's storage requirements and computational complexity, thereby reducing power consumption. A Markov chain algorithm analyzes the predicted power consumption parameters of the software-optimized simulation circuit to determine the node locations on the graph neural network that affect the circuit's power consumption anomaly, i.e., the locations influencing the power consumption parameters. The FPGA accelerator then adjusts the graph neural network operating parameters at the locations influencing the power consumption parameters until the circuit is qualified as a simulation circuit, at which point the adjustment ceases, ensuring that the predicted power consumption parameters of the software-optimized simulation circuit do not exceed the standard operating power consumption parameters.

[0104] In addition, the integrated circuit hardware and software collaborative design optimization method based on graph neural network analysis also includes the following steps:

[0105] Adjusting the component architecture of all abnormally connected components is classified as hardware design optimization, and adjusting the graph neural network operating parameters that affect power consumption parameters in real time through FPGA accelerators is classified as software design optimization.

[0106] Calculate the execution time of hardware design optimization and software design optimization in real time, and preset the maximum execution time of hardware design optimization and software design optimization;

[0107] Perform hardware design optimization and software design optimization simultaneously, and determine whether there is a time point within the maximum execution time of the hardware design optimization and software design optimization at which the second type of predicted abnormal power consumption simulation circuit becomes a qualified simulation circuit;

[0108] If so, the corresponding time point is marked as a qualified time point, and the real-time status of the hardware design optimization and the software design optimization at the qualified time point is output, wherein the real-time status of the hardware design optimization and the software design optimization are respectively the real-time component architecture of the abnormal component connected and the real-time parameters of the graph neural network operating parameters at the position where the power consumption parameters affect;

[0109] If not, determining whether the second type of predicted abnormal operating power consumption simulation circuit is a qualified simulation circuit after the maximum execution time of the hardware design optimization and the software design optimization;

[0110] If not, the second type of analog circuit with abnormal predicted operating power consumption is marked as an unqualified analog circuit.

[0111] It should be noted that the advantages of software and hardware are combined for collaborative optimization. At the software level, optimization can be performed for specific hardware architectures to improve the execution efficiency of the software. At the hardware level, a flexible hardware architecture can be designed to adapt to different neural network models and application scenarios. Simultaneous hardware design optimization and software design optimization can improve the efficiency of power consumption processing. The efficiency of simultaneous optimization is higher than that of separate optimizations because there may be a time point when hardware design optimization and software design optimization reach a balance, resulting in qualified circuit power consumption parameters. If a qualified analog circuit exists after the maximum execution time, it can be optimized by separate design. If a qualified analog circuit still does not exist after the maximum execution time, it proves that the circuit is scrapped.

[0112] like Figure 3 As shown, the second aspect of the present invention further provides an integrated circuit software and hardware collaborative design optimization system based on graph neural network analysis, the integrated circuit software and hardware collaborative design optimization system includes a memory 31 and a processor 32, the memory 31 stores an integrated circuit software and hardware collaborative design optimization method, and when the integrated circuit software and hardware collaborative design optimization method is executed by the processor 32, the following steps are implemented:

[0113] Constructing a graph neural network and a target analog integrated circuit, and mapping the graph neural network onto the target analog integrated circuit to obtain a graph neural network mapping circuit;

[0114] Running a graph neural network mapping circuit to generate prediction data of operating power consumption parameters, performing a qualification analysis on the prediction data of the operating power consumption parameters, and finally classifying the target analog integrated circuit based on the qualification analysis results;

[0115] The fault point of the classified graph neural network mapping circuit is traced, and the software and hardware design of the classified graph neural network mapping circuit is optimized based on the fault point tracing results.

[0116] The above are merely specific embodiments of the present invention, but the scope of protection of the present invention is not limited thereto. Any modifications or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be based on the scope of protection of the claims.

Claims

1. An integrated circuit hardware and software collaborative design optimization method based on graph neural network analysis, characterized in that: The following steps are involved: Constructing a graph neural network and a target analog integrated circuit, and mapping the graph neural network onto the target analog integrated circuit to obtain a graph neural network mapping circuit; Running a graph neural network mapping circuit to generate prediction data of operating power consumption parameters, performing a qualification analysis on the prediction data of the operating power consumption parameters, and finally classifying the target analog integrated circuit based on the qualification analysis results; Conduct fault tracing on the classified graph neural network mapping circuit, and optimize the software and hardware design of the classified graph neural network mapping circuit based on the fault tracing results; The construction of the graph neural network and the target analog integrated circuit, and mapping the graph neural network on the target analog integrated circuit to obtain a graph neural network mapping circuit, is specifically as follows: Obtaining an integrated circuit that requires software and hardware analysis, marking it as a target integrated circuit, and determining a circuit structure of the target integrated circuit in the target integrated circuit; The circuit structure of the target integrated circuit includes circuit element parameters, circuit element arrangement positions, and wire routing scheme of the target integrated circuit; Introducing circuit simulation software, importing the circuit structure of the target integrated circuit into the circuit simulation software, and constructing a simulation circuit of the target integrated circuit in the circuit simulation software, expressed as a target simulated integrated circuit; Introducing a graph neural network benchmark model, wherein the graph neural network benchmark model includes an input layer, a hidden layer, and an output layer. Simultaneously, introducing a big data network, retrieving the structural connection mode of the graph neural network benchmark model used for predicting indicator data of integrated circuits in the big data network, and calibrating it as the target structural connection mode; In the graph neural network benchmark model, the connection mode between the input layer, hidden layer, and output layer is set to the target structure connection mode to obtain the graph neural network model to be set; Running the target analog integrated circuit, and monitoring the operating power consumption parameters of the target analog integrated circuit in real time during the operation of the target analog integrated circuit, and calibrating the parameters into real-time operating power consumption parameters, while also monitoring the component operating parameters of different components in the target analog integrated circuit in real time, and calibrating the parameters into real-time operating parameters of circuit components; Perform feature analysis on the real-time power consumption parameters and the real-time operating parameters of circuit elements of different components to generate the connection relationship of different components. Based on the connection relationship of the different components, generate the adjacency matrix of the target analog integrated circuit. Import the adjacency matrix of the target analog integrated circuit, the real-time power consumption parameters and the real-time operating parameters of circuit elements of different components into the graph neural network model to be set for forward propagation to obtain the graph neural network mapping circuit.

2. The integrated circuit hardware and software collaborative design optimization method based on graph neural network analysis according to claim 1 is characterized in that: The operation graph neural network mapping circuit generates prediction data of the operation power consumption parameters, performs a qualification analysis on the prediction data of the operation power consumption parameters, and finally classifies the target analog integrated circuit based on the qualification analysis results, specifically: Preset circuit operation time, and operate the graph neural network mapping circuit during the circuit operation time, wherein, when the graph neural network mapping circuit is operated, operating power consumption parameters of the graph neural network mapping circuit and component operation parameters of different components after the circuit operation time are predicted; After obtaining the circuit operation time, the graph neural network maps the circuit operation power consumption parameters and the component operation parameters of different components, and calibrates them into predicted operation power consumption parameters and predicted component operation parameters of different components; Presetting standard data for predicting operating power consumption parameters and calibrating them as standard operating power consumption parameters; and simultaneously presetting standard data for predicting component operating parameters of different components to obtain standard component operating parameters of different components; The predicted operating power consumption parameters and the predicted component operating parameters of different components are analyzed. If the predicted operating power consumption parameters are greater than the standard operating power consumption parameters, and there are components whose predicted component operating parameters are less than the corresponding standard component operating parameters, the graph neural network mapping circuit is calibrated as a type of predicted operating power consumption abnormal simulation circuit, and the corresponding component is calibrated as a predicted operating parameter abnormal component; If the predicted operating power consumption parameter is greater than the standard operating power consumption parameter, but there is no component whose predicted component operating parameter is less than the corresponding standard component operating parameter, then the graph neural network mapping circuit is calibrated as a second-class predicted operating power consumption abnormal simulation circuit; If the predicted operating power consumption parameter is not greater than the operating power consumption standard parameter, the graph neural network mapping circuit is calibrated as a qualified analog circuit.

3. The integrated circuit hardware and software collaborative design optimization method based on graph neural network analysis according to claim 1 is characterized in that: The fault point tracing of the classified graph neural network mapping circuit and the software and hardware design optimization of the classified graph neural network mapping circuit based on the fault point tracing result are specifically as follows: For a type of predicted operation power consumption abnormality simulation circuit, within the type of predicted operation power consumption abnormality simulation circuit, determining whether a component with abnormal predicted operation parameters is a replaceable component; Wherein, the replaceable component is a component that can be replaced with a similar component in a type of predicted operation power consumption abnormality simulation circuit. If the component with abnormal predicted operation parameters is a replaceable component, then in the type of predicted operation power consumption abnormality simulation circuit, the component with abnormal predicted operation parameters that is a replaceable component is simulated replaced; If the component with the predicted abnormal operating parameters is not a replaceable component, a correction solution for the component with the predicted abnormal operating parameters is retrieved from the big data network and outputted, so that the predicted component operating parameters of all components in a type of predicted abnormal operating power consumption simulation circuit are not less than the corresponding standard component operating parameters; When the predicted component operating parameters of all components in a type of predicted operating power consumption abnormality simulation circuit are not less than the corresponding standard component operating parameters, and the predicted operating power consumption parameters of the type of predicted operating power consumption abnormality simulation circuit are not greater than the operating power consumption standard parameters, the type of predicted operating power consumption abnormality simulation circuit is classified as a qualified simulation circuit; When the predicted component operating parameters of all components in a type of predicted operating power consumption abnormality simulation circuit are not less than the corresponding standard component operating parameters, the predicted operating power consumption parameters of the type of predicted operating power consumption abnormality simulation circuit are still greater than the operating power consumption standard parameters, then the type of predicted operating power consumption abnormality simulation circuit is divided into a type two predicted operating power consumption abnormality simulation circuit; The circuit fault point tracing is performed on the second type of predicted operating power consumption abnormality simulation circuit, and the software and hardware design of the second type of predicted operating power consumption abnormality simulation circuit is optimized based on the fault point tracing results.

4. The method for optimizing integrated circuit hardware and software collaborative design based on graph neural network analysis according to claim 3, characterized in that: The circuit fault point tracing is performed on the second type of predicted operation power consumption abnormal simulation circuit, and the software and hardware design optimization of the second type of predicted operation power consumption abnormal simulation circuit is performed based on the fault point tracing result, specifically: In the second type of predicted operation power consumption abnormality simulation circuit, all network nodes are obtained, wherein the network nodes are elements in the second type of predicted operation power consumption abnormality simulation circuit; In the second type of simulation circuit for predicting abnormal operating power consumption, the connection mode between different components is obtained, and based on the connection mode between different components, the directed edges between all network nodes are defined; Run the second type of predicted operating power consumption anomaly simulation circuit, calculate the gradient values ​​of the directed edges between all network nodes in real time, and calibrate them as directed edge gradient values; Preset a standard variation range of the directed edge gradient value and a gradient value analysis time, and determine whether the directed edge gradient value is maintained within the standard variation range of the directed edge gradient value within the gradient value analysis time; If not, it is determined that there is an abnormality in the connection mode of the components in the second type of predicted operating power consumption abnormality simulation circuit, and in the second type of predicted operating power consumption abnormality simulation circuit, the components corresponding to the directed edge gradient values ​​that do not remain within the standard variation range of the directed edge gradient values ​​are determined and marked as connection abnormal components; In the second type of predicted operation power consumption abnormality simulation circuit, adjusting the component architecture of all abnormally connected components, and determining whether the abnormally connected components still exist after the component architecture adjustment; If so, all suitable connection modes for connecting abnormal components are retrieved based on the big data network, and are marked as connection modes of components to be selected. All connection modes of components to be selected are output, and the connection modes of components to be selected that do not contain abnormal connection components after output are marked as target connection modes. When there are no abnormal connection components in the second-category predicted operating power consumption abnormality simulation circuit, but the predicted operating power consumption parameters of the second-category predicted operating power consumption abnormality simulation circuit are still greater than the operating power consumption standard parameters, the circuit software optimization design of the second-category predicted operating power consumption abnormality simulation circuit is performed to obtain a simulation circuit whose predicted operating power consumption parameters are not greater than the operating power consumption standard parameters.

5. The integrated circuit hardware and software collaborative design optimization method based on graph neural network analysis according to claim 4 is characterized in that: The circuit software optimization design of the second type of predicted abnormal operating power consumption simulation circuit is performed to obtain a simulation circuit whose predicted operating power consumption parameter is not greater than the operating power consumption standard parameter, specifically: The second type of predicted abnormal operating power consumption simulation circuits after component architecture adjustment and target connection mode output are calibrated as simulation circuits to be optimized by the software; Configuring an FPGA accelerator in the software simulation circuit to be optimized, wherein the FPGA accelerator is an accelerator for adjusting parameters of the graph neural network in the software simulation circuit to be optimized; Running the software to be optimized analog circuit, calculating the predicted operating power consumption parameters of the software to be optimized analog circuit, and introducing a Markov chain algorithm to analyze the predicted operating power consumption parameters of the software to be optimized analog circuit, determining the position that affects the predicted operating power consumption parameters of the software to be optimized analog circuit in the graph neural network of the software to be optimized analog circuit, and marking it as the power consumption parameter influencing position; Obtain the graph neural network operating parameters at the position where the power consumption parameters affect the graph neural network, and adjust the parameters of the graph neural network operating parameters at the position where the power consumption parameters affect the graph neural network in the FPGA accelerator until the predicted operating power consumption parameters of the simulation circuit to be optimized by the software are no greater than the standard operating power consumption parameters, thereby obtaining a qualified simulation circuit.

6. An integrated circuit hardware and software collaborative design optimization system based on graph neural network analysis, characterized by: The integrated circuit software and hardware collaborative design optimization system includes a memory and a processor, and the memory stores an integrated circuit software and hardware collaborative design optimization method program. When the integrated circuit software and hardware collaborative design optimization method program is executed by the processor, the integrated circuit software and hardware collaborative design optimization method steps based on graph neural network analysis as described in any one of claims 1 to 5 are implemented.

Images