A power supply network design method and related equipment

Abstract

The present application relates to the field of chip technology and discloses a power network design method and related equipment, including: obtaining design rules and constraint rules for power network design in an integrated circuit; identifying multiple voltage domains in the integrated circuit, and multiple power distribution networks corresponding to each voltage domain, each voltage domain corresponding to a different voltage value; generating the metal shape of the top metal and the metal shape of the corresponding bottom metal corresponding to each of the power distribution networks according to the design rules; establishing a power connection between the top metal and the corresponding bottom metal corresponding to each of the power distribution networks according to the metal shape of the top metal and the metal shape of the corresponding bottom metal, the design rules and the constraint rules, so as to design a power network corresponding to each of the voltage domains. The technical solution of the embodiment of the present application can effectively improve the power network wiring quality and chip performance and stability.

Description

Technical Field

[0001] The present application relates to the field of chip technology, and more specifically, to a power supply network design method and related equipment. Background Art

[0002] In the Fin-Field-Effect-Transistor (FinFET) process, the constraints faced by power network design are showing a significant increase compared to traditional processes. Traditionally, power network design can be achieved based on a single rule, such as minimum metal line area. However, the FinFET process, with its introduction of advanced technologies such as multiple masks and FinTrack, has made the factors required for power network design extremely complex.

[0003] If such complex constraints were to be evaluated one by one, the algorithm would inevitably be burdened with heavy computational effort, causing the amount of calculation to increase exponentially. This would not only consume a significant amount of computational time but also consume a vast amount of computing resources, significantly limiting the practical application effectiveness and efficiency of power network routing algorithms. Summary of the Invention

[0004] The Summary of the Invention introduces a series of simplified concepts that will be further described in the Detailed Description of the Invention. The Summary of the Invention of this application is not intended to limit the key features and essential technical features of the claimed technical solution, nor is it intended to determine the scope of protection of the claimed technical solution.

[0005] In a first aspect, the present application proposes a power network design method, comprising:

[0006] Obtain design rules and constraints for power network design in integrated circuits;

[0007] Identifying multiple voltage domains in the integrated circuit and multiple power distribution networks corresponding to each of the voltage domains, each of the voltage domains corresponding to a different voltage value;

[0008] Generating a metal shape of a top metal layer and a metal shape of a bottom metal layer corresponding to each power distribution network according to the design rules;

[0009] According to the metal shape of the top metal and the corresponding bottom metal corresponding to each of the power distribution networks, the design rules and the constraint rules, a power connection is established between the top metal and the corresponding bottom metal corresponding to each of the power distribution networks to design a power network corresponding to each of the voltage domains.

[0010] In a feasible embodiment, according to the design rules, the metal shape of the top metal and the metal shape of the corresponding bottom metal corresponding to each of the power distribution networks are generated, including: determining the size and position of the metal shape of the top metal and the corresponding bottom metal corresponding to each of the power distribution networks according to the power network design parameters in the design rules; determining the direction of the metal shape of the top metal corresponding to each of the power distribution networks according to the wiring direction of the layer where the top metal corresponding to each of the power distribution networks is located; determining the direction of the metal shape of the bottom metal corresponding to each of the power distribution networks according to the wiring direction of the layer where the bottom metal corresponding to each of the power distribution networks is located; generating the metal shape of the top metal corresponding to each of the power distribution networks according to the determined size, position and direction of the metal shape of the top metal corresponding to each of the power distribution networks; generating the metal shape of the bottom metal corresponding to each of the power distribution networks according to the determined size, position and direction of the metal shape of the bottom metal corresponding to each of the power distribution networks.

[0011] In a feasible embodiment, the method further includes: when the power network design parameters do not include a length parameter, if the wiring direction is a horizontal direction, determining that the lengths of the metal shapes of the top metal and the corresponding bottom metal corresponding to each of the power distribution networks are both the longest lengths in the horizontal direction; if the wiring direction is a vertical direction, determining that the lengths of the metal shapes of the top metal and the corresponding bottom metal corresponding to each of the power distribution networks are both the longest lengths in the vertical direction.

[0012] In a feasible embodiment, the method further includes: if the process of the integrated circuit is the first process, after establishing a power connection between the top metal corresponding to each power distribution network and the corresponding bottom metal, continuing to establish a power connection between the bottom metal and the metal layer where the circuit functional unit is located; if the process of the integrated circuit is the second process, after establishing a power connection between the top metal corresponding to each power distribution network and the corresponding bottom metal, continuing to establish a power connection between the bottom metal and the bottom metal, so as to realize the power connection through the bottom metal and the metal layer where the circuit functional unit is located.

[0013] In a feasible embodiment, according to the metal shape of the top metal and the metal shape of the corresponding bottom metal corresponding to each power distribution network, the design rules and the constraint rules, a power connection is established between the top metal and the corresponding bottom metal corresponding to each power distribution network, including: if the top metal and the corresponding bottom metal corresponding to each power distribution network are adjacent metal layers, then according to the metal shape of the top metal and the metal shape of the bottom metal, and the through-hole design parameters in the design rules, a plurality of first through-holes are generated to establish a power connection between the top metal and the bottom metal through the plurality of first through-holes; if the top metal and the corresponding bottom metal corresponding to each power distribution network are non-adjacent metal layers, then according to the metal shape of the top metal and the metal shape of the bottom metal, and the minimum area constraint in the constraint rules, the metal shape of the intermediate layer metal is generated layer by layer between the top metal and the bottom metal; according to the through-hole design parameters, a plurality of second through-holes are generated between the adjacent layers of the top metal, the intermediate layer metal and the bottom metal to establish a power connection between the top metal and the bottom metal through the metal shape of the intermediate layer metal and the plurality of second through-holes between the adjacent layers.

[0014] In a feasible implementation, based on the metal shape of the top metal and the metal shape of the bottom metal, and the minimum area constraint in the constraint rule, the metal shape of the intermediate layer metal is generated layer by layer between the top metal and the bottom metal, including: determining the area of ​​the metal shape of the intermediate layer metal based on the projection of the metal shape of the top metal and the metal shape of the bottom metal on the intermediate layer metal; if the determined area of ​​the metal shape of the intermediate layer metal is smaller than the minimum area constraint, filling the metal shape of the intermediate layer metal to generate a new metal shape of the intermediate layer metal.

[0015] In a feasible embodiment, the method further includes: performing violation prediction on the peripheral area of ​​the new metal shape of the intermediate layer metal to obtain a prediction result, and the prediction result is used to indicate the probability of a violation; if the prediction result exceeds a preset threshold, the preliminary wiring evaluation index of the logic point corresponding to the peripheral area is updated to obtain a new wiring evaluation index, and the new wiring evaluation index is used to guide the adjustment of the violation.

[0016] In a feasible embodiment, according to the through-hole design parameters, a plurality of second through-holes are generated between the adjacent layers of the top metal, the middle metal and the bottom metal, including: determining the border of the through-hole array between the adjacent layers according to the area requirements of the upper metal in the adjacent layers of the top metal, the middle metal and the bottom metal and the through-hole design parameters; deleting the outermost part of the border of the through-hole array that exceeds the encirclement range of the lower metal according to the size of the lower metal in the adjacent layers to obtain a new border of the through-hole array; determining the unit spacing of the through-hole array in the longitudinal and transverse directions according to the through-hole design parameters, and generating the through-hole array according to the new border of the through-hole array and the unit spacing of the through-hole array, wherein the through-hole array includes the plurality of second through-holes.

[0017] In a feasible embodiment, the method also includes: if the target design parameters in the design rules do not match the target requirement parameters of the process of the integrated circuit, determining the greatest common factor or greatest common multiple of the target design parameters and the target requirement parameters; adjusting the target design parameters according to the greatest common factor or the greatest common multiple to obtain new design parameters.

[0018] In a feasible embodiment, the method further includes: calculating the voltage drop of each power distribution network based on the resistance value of each power distribution network corresponding to the target voltage domain and the current value of each power distribution network under the maximum load state; if the voltage drop of the target power distribution network in each power distribution network is less than the voltage value of the target voltage domain, determining that the area corresponding to the target power distribution network is an insufficiently powered area; if the voltage drop of the target power distribution network is greater than the voltage value of the target voltage domain, determining the target path in the target power distribution network, inserting a power filter element in the target path to reduce the voltage drop of the target path, and the voltage drop of the target path is greater than a preset voltage threshold.

[0019] In a feasible implementation, the method further includes: parsing the unified power format file in the constraint rules to obtain a parsed file; determining the position where the power control element needs to be inserted and the position where the power isolation element needs to be inserted based on the positioning information in the parsed file; inserting the power control element at the position where the power control element needs to be inserted, and inserting the power isolation element at the position where the power isolation element needs to be inserted, according to the insertion information in the parsed file, the power control element is used to control the on and off of the power supply, and the power isolation element is used to isolate the power supply networks corresponding to each of the voltage domains.

[0020] In a second aspect, the present application proposes a power network design device, comprising:

[0021] an acquisition unit configured to acquire design rules and constraint rules for a power network design in an integrated circuit;

[0022] an identification unit configured to identify a plurality of voltage domains in the integrated circuit and a plurality of power distribution networks corresponding to each of the voltage domains, each of the voltage domains corresponding to a different voltage value;

[0023] a generating unit configured to generate a metal shape of a top metal layer and a metal shape of a bottom metal layer corresponding to each of the power distribution networks according to the design rules;

[0024] The connection unit is configured to establish a power connection between the top metal and the corresponding bottom metal corresponding to each power distribution network according to the metal shape of the top metal and the corresponding bottom metal corresponding to each power distribution network, the design rules and the constraint rules, so as to design a power network corresponding to each voltage domain.

[0025] In a third aspect, an electronic device comprises: a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor is configured to implement the steps of the power supply network design method according to any one of the first aspects described above when executing the computer program stored in the memory.

[0026] In a fourth aspect, the present application further proposes a computer-readable storage medium having a computer program stored thereon, and when the computer program is executed by a processor, the power supply network design method of any one of the first aspects is implemented.

[0027] In a fifth aspect, the present application further proposes a chip, which at least includes a power supply network designed by any power supply network design method of the first aspect.

[0028] In summary, the power network design method proposed in this application, by acquiring design rules and constraint rules, constructs a systematic design process from identifying voltage domains and power distribution networks, to generating top and bottom metal shapes, and finally establishing power connections, which can adapt to complex voltage domain situations. The design rules and constraint rules are fully considered throughout the design process, avoiding the limitations of traditional single rule design methods and effectively solving the problem of increased constraints. By accurately designing according to the rules at each key step, a large number of invalid calculation attempts caused by blind design are avoided, the quality of power network wiring is effectively improved, and chip performance and stability are enhanced. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Various other advantages and benefits will become apparent to those skilled in the art upon reading the detailed description of the preferred embodiment below. The accompanying drawings are for illustration purposes only and are not to be considered as limiting the present description. The same reference symbols are used throughout the drawings to represent the same components. In the drawings:

[0030] Figure 1 This is a structural diagram of a traditional power supply network.

[0031] Figure 2 A flowchart of a power supply network design method provided in an embodiment of the present application.

[0032] Figure 3 A flowchart of a power supply network design method provided in an embodiment of the present application.

[0033] Figure 4 A flowchart of a power supply network design method provided in an embodiment of the present application.

[0034] Figure 5 A flowchart of a power supply network design method provided in an embodiment of the present application.

[0035] Figure 6 A schematic diagram of the structure of a power network design device provided in an embodiment of the present application.

[0036] Figure 7 A schematic diagram of the structure of an electronic device with a power supply network design provided in an embodiment of the present application. DETAILED DESCRIPTION

[0037] The terms "first", "second", "third", "fourth", etc. (if any) in the specification and claims of this application and the above-mentioned drawings are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that the numbers used in this way can be interchanged where appropriate so that the embodiments described herein can be implemented in an order other than that illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices. The technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the embodiments described are only some embodiments of the present application, not all embodiments.

[0038] Before further describing the embodiments of the present application in detail, the nouns and terms involved in the embodiments of the present application are explained. The nouns and terms involved in the embodiments of the present application are subject to the following interpretations.

[0039] 1. FinFET

[0040] FinFET is an advanced semiconductor process technology. It uses a fin-shaped three-dimensional transistor structure that allows current to flow in three directions. Compared with traditional planar transistors, this increases the transistor surface area and improves the gate's control over the channel. It can effectively improve the performance of integrated circuits, reduce power consumption, and reduce size. It is widely used in high-performance chip manufacturing.

[0041] 2. Plane technology

[0042] Planar technology is a traditional integrated circuit manufacturing process in which transistors and other components are constructed on a two-dimensional surface, resulting in a relatively simple structure. Compared to FinFET technology, planar technology uses fewer metal layers and has a lower transistor integration density, but it still has applications in cost-sensitive applications or where performance requirements are less demanding.

[0043] 3. Power network

[0044] The power network is a network system that introduces power from the outside into an integrated circuit and distributes it to various functional modules and components. It consists of power pins, buses, rails, decoupling capacitors, and voltage regulators. Its main function is to provide stable and reliable power supply and reduce power supply noise. Factors such as current carrying capacity, noise suppression, and electromagnetic compatibility must be comprehensively considered during design.

[0045] 4. Source / Destination Network

[0046] In integrated circuits, the source network connects the positive terminal of the power supply (usually represented by VDD) to the components and modules that require power. The ground network connects the negative terminal of the power supply (usually represented by VSS) to the components and modules that require power. The source / ground network is a crucial component of the power distribution network. They provide operating voltage to transistors, logic gates, and other components within the chip, forming a current loop and ensuring proper chip operation. Furthermore, the design of the source / ground network is crucial for reducing power supply noise and improving chip stability and reliability.

[0047] 5. Metal layer

[0048] Metal layers are a crucial component of integrated circuit manufacturing and are typically made of metal materials (such as aluminum and copper). Metal layers connect the various components and functional modules within a chip, forming electrical interconnections. During chip manufacturing, multiple metal layers are stacked together, connected through structures such as vias. Different metal layers perform different functions within the chip, such as power and signal transmission. The design and layout of these metal layers must consider factors such as wiring density, signal integrity, and electromagnetic interference to ensure high chip performance and reliability.

[0049] 6. Through hole

[0050] In integrated circuit manufacturing, a via is a conductive channel that vertically penetrates multiple metal or insulating layers. It is typically created by forming a hole in an insulating layer through processes such as photolithography and etching, and then filling it with a conductive material such as metal (such as copper). The primary function of a via is to achieve electrical connections between different metal layers, enabling signal or power transmission within the multilayer structure. This effectively connects the various components and functional modules within the chip in three dimensions, making it a key structure in building complex integrated circuit interconnection networks.

[0051] 7. DRC

[0052] DRC, or Design Rule Check, is a crucial step in the integrated circuit design process. Using specialized software tools, it comprehensively checks the IC layout according to the design rules specified by the semiconductor manufacturing process. These rules cover aspects such as geometric dimensions, spacing, and layer-to-layer relationships, such as minimum line width, minimum spacing, and metal layer coverage requirements. DRC ensures that the designed layout can be correctly manufactured under given process conditions, avoiding chip manufacturing failures or performance degradation caused by design failures. It is a crucial means of ensuring the manufacturability and reliability of integrated circuit designs.

[0053] Based on the above description, please refer to Figure 1 , Figure 1 This is a structural diagram of a traditional power supply network. Figure 1 The power network shown includes: top-layer metal power line ①, top-layer metal ground line ②, middle-layer metal power line ③, middle-layer metal ground line ④, bottom-layer metal ground line ⑤, bottom-layer metal power line ⑥, and inter-metal vias ⑦. Power lines and ground lines are typically routed alternately.

[0054] The top metal power line ① receives power from an external power source and transmits it to the entire power network, providing power support for various circuit modules within the chip. Like the "backbone" of the power network, it carries a large amount of current. The top metal ground line ② provides a zero-potential reference point for the circuit, forming a current loop. This not only stabilizes the circuit potential and reduces signal interference, but also acts as an electrostatic discharge path, protecting the chip from damage.

[0055] The middle-layer metal power lines ③ and ground lines ④ complement the top-layer wiring. The middle-layer metal power lines ③ distribute power more precisely to specific circuit modules, making them particularly suitable for locally high-power modules in complex chip layouts, providing a more direct power supply. The middle-layer metal ground lines ④ complement the top-layer ground lines, providing a more stable potential reference for local circuits, further reducing ground impedance and minimizing voltage fluctuations on the ground lines. The top-layer and middle-layer wiring, as well as the middle-layer and bottom-layer wiring, are arranged in a cross-pattern. This greatly enhances wiring flexibility, providing connection points for circuit modules from different directions to accommodate complex circuit layouts. Furthermore, the cross-patterning ensures a more uniform distance between the power and ground lines, helping to reduce electromagnetic interference, optimize power distribution, and ensure a stable power supply for circuit modules at all levels.

[0056] The bottom metal ground line ⑤ serves as the foundational ground layer for the entire power network, providing a large ground plane and effectively reducing ground resistance. It also shields and isolates external electromagnetic interference, reducing the impact of external interference on the chip's internal circuits. The bottom metal power line ⑥ assists the middle and top power lines, further optimizing power distribution and providing power to circuit modules on the bottom layer or in specific locations.

[0057] Intermetallic vias (7) are key pathways connecting power and ground lines across different metal layers. They enable smooth transmission of electrical energy between the top, middle, and bottom layers, ensuring reliable electrical connections between circuit modules on each layer and the power supply network. During current transmission, vias also balance current distribution, guiding it evenly across layers and preventing problems such as overheating caused by excessive current in certain areas. Furthermore, a suitable via layout helps improve electromagnetic compatibility and reduce the intensity of electromagnetic interference.

[0058] It should be noted that Figure 1 Only three layers of power supply network are shown in FIG. Figure 1 The illustration does not limit the number of power network layers.

[0059] Figure 2 FIG. 1 is a flow chart showing a method for designing a power supply network according to an embodiment of the present application. Figure 2 As shown, the power network design method includes:

[0060] Step S210: obtaining design rules and constraint rules for power network design in an integrated circuit;

[0061] Step S220: identifying multiple voltage domains in the integrated circuit and multiple power distribution networks corresponding to each voltage domain, each voltage domain corresponding to a different voltage value;

[0062] Step S230: Generate a metal shape of the top metal layer and a metal shape of the bottom metal layer corresponding to each power distribution network according to the design rules;

[0063] Step S240: Based on the metal shape of the top metal and the corresponding bottom metal of each power distribution network, design rules and constraint rules, establish a power connection between the top metal and the corresponding bottom metal of each power distribution network to design a power network corresponding to each voltage domain.

[0064] These steps are described in detail below.

[0065] In step S210 , design rules and constraint rules for power network design in an integrated circuit are obtained.

[0066] In integrated circuit design, the design rules and constraints for power networks are the core foundation for ensuring the reliability and functionality of power supply systems. These rules guide the physical implementation and electrical performance optimization of power networks through multi-dimensional definitions and constraints.

[0067] Design rules are primarily defined directly by the user through parameter settings and cover the basic physical properties of the power network. These include geometric parameters such as width, pitch, and offset for the power network. They also include voltage domain names, voltage values, voltage switches, source / ground network names, and metal layer connection rules for standard cell pins. These rules can be entered during the layout planning phase through the user interface or configuration files.

[0068] Constraint rules are mainly obtained from the Technology Database (TechDatabase) and the Unified Power Format (UPF) files. These rules together reflect the limitations of manufacturing processes and electrical performance. TechDatabase contains process parameters for Design Rule Check (DRC), such as Via Generation Rules and Metal Enclosure Rules. These rules ensure the manufacturing feasibility of metal lines and vias. For example, the minimum area of ​​metal lines in the FinFET process must meet both planar and 3D constraints (such as edge length and continuous edge length), while the top metal enclosure (Top Metal Enclosure) and bottom metal enclosure (Bottom Metal Enclosure) dimensions of the via must meet cross-layer DRC requirements to prevent short circuits or open circuits during the manufacturing process. In addition, TechDatabase also contains resistance and capacitance data for metal layers and via layers. These parameters are critical for electrical performance simulation. Low-power voltage constraint rules can be obtained from UPF files.

[0069] In step S220 , multiple voltage domains in the integrated circuit and multiple power distribution networks corresponding to each voltage domain are identified, where each voltage domain corresponds to a different voltage value.

[0070] In integrated circuit design, a voltage domain refers to independent areas within a chip that share the same supply voltage. Because different functional modules within a chip (such as digital circuits, analog circuits, and input / output interfaces) have varying voltage requirements (for example, core logic typically uses low voltage to reduce power consumption, while I / O interfaces require higher voltage to ensure signal integrity), multiple voltage domains are required. Each domain corresponds to a different voltage value, and each domain has its own independent power supply network. The core goal is to provide stable voltage for circuits in specific areas and meet the current transmission requirements of different modules through differentiated design.

[0071] Identifying multiple voltage domains within an integrated circuit can be accomplished by parsing design rules and constraint rules. As previously mentioned, design rules explicitly include key information such as voltage domain names, voltage values, and voltage switches. The UPF file within the constraint rules further defines the boundaries and interactions of each voltage domain through low-power constraints. For example, when a design includes dynamic voltage and frequency scaling, the voltage domains corresponding to different operating modes are clearly labeled.

[0072] Each voltage domain contains multiple power distribution networks, also known as source / ground networks, which work together to form a complete current transmission path. During the design and manufacturing process, IC design rules, such as design rule checking (DRC) requirements for metal line width, spacing, and via layout, must be strictly adhered to to avoid problems such as short circuits and open circuits. Furthermore, the source / ground networks of different voltage domains must be designed based on the characteristics of each voltage domain. For example, high-voltage domains may use thicker metal layers due to their high current requirements, while low-voltage domains may use a denser via layout to reduce resistance.

[0073] In step S230 , a metal shape of a top metal layer and a metal shape of a bottom metal layer corresponding to each power distribution network are generated according to design rules.

[0074] In integrated circuit design, to build a stable and efficient power network, the top and bottom metal shapes corresponding to the source / ground network can be accurately generated. The chip is divided into multiple voltage domains, each with its own unique power supply requirements and operating characteristics.

[0075] Within each voltage domain, numerous source / ground networks exist. The source network provides positive voltage to circuit modules, while the ground network serves as a return path for reference potential. Together, they form the power distribution network. To ensure these networks can properly and efficiently transmit current, corresponding metal shapes must be generated for them.

[0076] For the top metal, it plays an important role in carrying large currents in current transmission. The metal shape of the top metal can be determined according to the design rules. For example, if a source network needs to transmit a large current, then in order to reduce resistance, the top metal line will be designed to be relatively wide. At the same time, in order to achieve uniform distribution of current, the top metal can be designed into a grid or a structure similar to a tree trunk and branches. The main line is responsible for transmitting the main current, and the branch line accurately guides the current to each power module to ensure that the circuit modules in the entire voltage domain can obtain stable power supply.

[0077] The bottom metal layer is equally critical. It typically focuses on powering low-current areas and serves as a crucial path for signal return. The bottom metal layer can adopt a checkerboard pattern or parallel lines. This structure not only maximizes space utilization but also, by being orthogonal to the top metal layer, effectively reduces electromagnetic interference and ensures stable signal transmission.

[0078] In step S240, based on the metal shape of the top metal corresponding to each power distribution network and the metal shape of the corresponding bottom metal, design rules and constraint rules, a power connection is established between the top metal corresponding to each power distribution network and the corresponding bottom metal to design a power network corresponding to each voltage domain.

[0079] Establishing power connections between the top and bottom metal layers is a critical step in power network design. This process requires compliance with design rules and constraints. Design rules play a crucial guiding role in this process. They are primarily defined by the user through parameter settings based on actual requirements. Constraints are primarily obtained from the TechDatabase and UPF files.

[0080] After generating the metal shapes of the top and bottom metal layers corresponding to each source / ground network, power connections can be established between the top and bottom metal layers corresponding to each power distribution network based on the metal shapes, design rules, and constraint rules. This means establishing a power connection between the top and bottom metal layers corresponding to each source network, and between the top and bottom metal layers corresponding to each ground network. When establishing connections, the location and method of the connections must be determined strictly in accordance with the design rules, while also meeting the constraints' requirements for manufacturing process and electrical performance. For example, based on the via generation rules, vias that meet the size requirements are placed in appropriate locations to achieve reliable connections between the top and bottom metal layers. In this way, the various power distribution networks are organically combined, ultimately successfully designing a power network that meets the electrical performance requirements of each voltage domain, ensuring stable and efficient chip operation under different operating conditions.

[0081] The power network design method proposed in this application, by acquiring design rules and constraint rules, constructs a systematic design process from identifying voltage domains and power distribution networks, to generating top and bottom metal shapes, and finally establishing power connections. It can adapt to complex voltage domain situations. Fully considering design rules and constraint rules throughout the design process avoids the limitations of traditional single-rule design methods and effectively solves the problem of increasing constraints. By accurately designing according to rules at each key step, a large number of invalid calculation attempts caused by blind design are avoided, effectively improving the quality of power network wiring and enhancing chip performance and stability.

[0082] In some embodiments of the present application, generating the metal shape of the top metal and the metal shape of the corresponding bottom metal corresponding to each power distribution network according to the design rules can specifically include the following steps: first, determining the size and position of the metal shape of the top metal and the corresponding bottom metal corresponding to each power distribution network according to the power network design parameters in the design rules; then, determining the direction of the metal shape of the top metal corresponding to each power distribution network according to the wiring direction of the layer where the top metal corresponding to each power distribution network is located; determining the direction of the metal shape of the bottom metal corresponding to each power distribution network according to the wiring direction of the layer where the bottom metal corresponding to each power distribution network is located; finally, generating the metal shape of the top metal corresponding to each power distribution network according to the determined size, position and direction of the metal shape of the top metal corresponding to each power distribution network; generating the metal shape of the bottom metal corresponding to each power distribution network according to the determined size, position and direction of the metal shape of the bottom metal corresponding to each power distribution network.

[0083] Specifically, in the process of generating the metal shapes of the top metal and the bottom metal, the size and position of the metal shape of the top metal corresponding to each power distribution network, as well as the size and position of the metal shape of the bottom metal corresponding to each power distribution network, can be first determined based on the power network design parameters in the design rules.

[0084] It's important to explain that the top metal layer typically consists of multiple metal lines. Each metal line primarily serves as a conductive pathway, carrying electrical signals. The number of metal lines depends on circuit complexity and design requirements. The size of the top metal's metal features refers to geometric characteristics such as the width, length, and spacing between metal lines. These characteristics directly impact circuit performance, power consumption, and reliability. The width of a metal line determines the current it can carry. Wider metal lines can handle higher currents, but they also occupy more chip area. Therefore, selecting the appropriate width is a trade-off between ensuring sufficient current capacity and minimizing the space occupied by other components. The length of a metal line affects the distance a signal can travel. Excessively long metal lines increase signal latency, thereby reducing circuit speed. Therefore, metal lines are typically kept as short as possible to shorten signal paths and reduce latency. The spacing between metal lines prevents short circuits or crosstalk between different metal lines. Appropriate spacing also improves signal integrity and prevents problems such as electromagnetic interference. The location of the top metal's metal features refers to the layout and arrangement of the metal lines on the chip.

[0085] The base metal layer is typically composed of multiple metal lines. The metal shape size of the base metal refers to geometric characteristics such as the width, length, and spacing between the metal lines. These characteristics also directly affect circuit performance, power consumption, and reliability. The width of the metal lines determines the current the base metal can carry. Wider metal lines can carry higher currents, but they may also increase the chip's parasitic capacitance and parasitic resistance, which in turn affects signal integrity. Therefore, selecting the appropriate width requires a balance between current capacity and signal integrity. The length of the metal lines affects the distance the signal can propagate. Longer base metal lines may increase signal delay, thereby reducing circuit speed. Furthermore, longer metal lines may increase power consumption and noise. Therefore, it is generally desirable to keep the base metal lines as short as possible to shorten signal paths and reduce latency. The spacing between metal lines ensures that short circuits and crosstalk between different metal lines are prevented. Appropriate spacing also improves signal integrity and prevents electromagnetic interference and other issues. Particularly in power supply networks, the base metal spacing must also meet current density requirements to ensure uniform current distribution and avoid local overheating. The base metal shape position refers to the layout and arrangement of the metal lines on the chip.

[0086] The power network design parameters can be geometric parameters such as the length, width, spacing, and displacement of the power network. These parameters provide the core basis for determining the size and position of the metal shape. Taking the example of determining the size and position of the metal shape of the top metal based on the power network design parameters, the length, width, and spacing of the metal lines of the top metal and the spacing between adjacent metal lines can be determined based on the length, width, and spacing of the power network. At the same time, the position of the metal lines of the top metal on the chip can be determined based on the displacement parameters of the power network. The method for determining the size and position of the metal shape of the bottom metal is similar and will not be repeated here.

[0087] Next, the wiring direction is also an important factor in determining the direction of the metal shape. For the top metal, the wiring direction of the layer it is located in has a specific plan. In chip design, the top metal may be designed with a specific wiring direction, such as horizontal or vertical, based on the overall layout requirements. This wiring direction directly determines the direction of the top metal shape. For example, if the wiring direction of the layer where the top metal is located is planned to be horizontal, then the corresponding top metal shape will also be mainly horizontal. Similarly, the wiring direction of the layer where the bottom metal is located determines the direction of the bottom metal shape. The bottom metal usually focuses on high-density wiring, and its wiring direction setting cooperates with the top metal to reduce electromagnetic interference. If the wiring direction of the layer where the bottom metal is located is vertical, then the bottom metal shape will be mainly vertical, forming an orthogonal arrangement with the horizontal direction of the top metal, effectively reducing signal interference between different source / ground networks and ensuring the stable operation of the power supply network.

[0088] Finally, based on the size, position, and direction of the top metal shape corresponding to each power distribution network previously determined, the metal shape of the top metal can be generated. Similarly, for the bottom metal, based on the determined size, position, and direction, a metal shape of the bottom metal that meets the requirements can be generated. This process ensures that the generation of the metal shape of the top metal and the metal shape of the bottom metal in the power network not only meets the various parameter requirements in the design rules, but also adapts to the overall electrical performance and layout requirements of the chip, laying a solid foundation for the subsequent establishment of a stable and efficient power connection between the top metal and the bottom metal, thereby ensuring that the entire power network can provide stable and reliable power support for each component within the integrated circuit.

[0089] As previously mentioned, when the power network design parameters include length parameters, the length of the top metal trace and the length of the bottom metal trace corresponding to each power distribution network can be determined directly based on the length parameters. However, the power network design parameters do not necessarily include length parameters. When the power network design parameters do not include length parameters, the length of the metal trace can be determined based on the routing direction.

[0090] In some embodiments of the present application, when the length parameter is not included in the power network design parameters, if the wiring direction is horizontal, the length of the metal shape of the top metal and the corresponding bottom metal corresponding to each power distribution network is determined to be the longest length in the horizontal direction; if the wiring direction is vertical, the length of the metal shape of the top metal and the corresponding bottom metal corresponding to each power distribution network is determined to be the longest length in the vertical direction.

[0091] In this embodiment, when the wiring direction is horizontal, the length of the metal shapes of the top and bottom metal layers corresponding to each power distribution network can be set to the longest length in the horizontal direction. This means that in the horizontal direction, the metal lines need to extend as far as possible to cover the entire current path. This is done to ensure that current can flow smoothly from the power supply end to the load end, avoiding current bottlenecks or increased voltage drops caused by too short metal lines.

[0092] When routing in a vertical direction, the length of the metal shapes for the top and bottom metal layers of each power distribution network can be set to the maximum length in the vertical direction. This means that the metal lines need to extend as far as possible in the vertical direction to cover the entire current path. This ensures that current can flow smoothly from the power source to the load, avoiding current bottlenecks or increased voltage drops caused by metal lines that are too short.

[0093] In some embodiments of the present application, the power connection method varies depending on the process of the integrated circuit. Specifically, if the process of the integrated circuit is the first process, after establishing a power connection between the top metal layer corresponding to each power distribution network and the corresponding bottom metal layer, a power connection is established between the bottom metal layer and the metal layer where the circuit functional unit is located. If the process of the integrated circuit is the second process, after establishing a power connection between the top metal layer corresponding to each power distribution network and the corresponding bottom metal layer, a power connection is established between the bottom metal layer and the bottom-most metal layer, thereby achieving a power connection through the bottom metal layer and the metal layer where the circuit functional unit is located.

[0094] The first process can be a FinFET process, the second process can be a planar process, and the circuit functional modules can be standard cells and macro cells. In an integrated circuit using the FinFET process, after establishing a power connection between the top metal and bottom metal corresponding to each power distribution network, due to the characteristics of the FinFET process, in order to ensure that the circuit functional units can obtain a stable and accurate power supply, it is necessary to further establish a power connection between the bottom metal and the metal layer where the circuit functional units are located. The FinFET process has a three-dimensional structure and high device integration, and has extremely strict requirements for the accuracy and efficiency of power distribution. By directly connecting the bottom metal to the metal layer where the standard cells and macro cells are located, the loss and interference during the power transmission process can be minimized, meeting the process's stringent requirements for high performance and low power consumption, thereby ensuring the stable operation and high performance of the entire integrated circuit.

[0095] For integrated circuits using planar technology, after establishing power connections between the top metal and bottom metal of each power distribution network, a further power connection can be established between the bottom metal and the bottom metal. The bottom metal here is the smallest wiring layer in the planar technology. It has good conductivity and low resistance, and can serve as the global power distribution layer.

[0096] The reason for this is that the planar process is a two-dimensional structure with relatively few metal layers. Unlike the FinFET process, there are no more metal layers to achieve direct connection between the bottom metal and the metal layer where the circuit functional units are located. By connecting the bottom metal to the minimum wiring layer, the power supply can be distributed across the entire chip with the help of the minimum wiring layer, thereby providing power to circuit functional units such as standard cells and macro cells. This method conforms to the characteristics of the planar process and effectively reduces process complexity and cost while meeting the basic functions of the circuit.

[0097] In some embodiments of the present application, Figure 3As shown, establishing a power connection between the top metal layer and the bottom metal layer can be achieved through a through hole. Specifically, step S240 can specifically include steps S310 to S330, which are described in detail as follows:

[0098] Step S310: If the top metal and the corresponding bottom metal corresponding to each power distribution network are adjacent metal layers, multiple first through holes are generated according to the metal shape of the top metal and the metal shape of the bottom metal, as well as the through hole design parameters in the design rules, so as to establish a power connection between the top metal and the bottom metal through the multiple first through holes.

[0099] When establishing a power connection between the top metal and the bottom metal, on the one hand, if the top metal and the corresponding bottom metal corresponding to each power distribution network are adjacent metal layers, multiple first through-holes can be generated according to the metal shape of the top metal and the metal shape of the bottom metal, as well as the through-hole design parameters in the design rules, so as to establish a power connection between the top metal and the bottom metal through the multiple first through-holes.

[0100] In integrated circuit design, adjacent metal layers mean two layers of metal are physically adjacent, separated only by an insulating layer. The top and bottom metal layers each have specific metal shapes that determine the path and range of current transmission. The via design parameters in the design rules specify requirements for via size, spacing, and location.

[0101] Based on this information, multiple first vias can be generated at appropriate locations. These vias act like bridges, traversing the insulating layer between them and connecting the top and bottom metal layers, thereby enabling power transmission between the two layers. For example, design rules may dictate a minimum via diameter of 0.1 micron and a minimum spacing of 0.2 micron between adjacent vias. Based on the metal geometry of the top and bottom metal layers, multiple vias can be placed where these parameters are met to ensure a stable and reliable power connection.

[0102] Step S320: If the top metal and the corresponding bottom metal corresponding to each power distribution network are non-adjacent metal layers, the metal shape of the intermediate layer metal is generated layer by layer between the top metal and the bottom metal according to the metal shape of the top metal and the metal shape of the bottom metal, and the minimum area constraint in the constraint rule.

[0103] On the other hand, if the top metal and the corresponding bottom metal corresponding to each power distribution network are non-adjacent metal layers, the metal shape of the intermediate layer metal can be generated layer by layer between the top metal and the bottom metal according to the metal shape of the top metal and the metal shape of the bottom metal, as well as the minimum area constraint in the constraint rule.

[0104] When the top metal and bottom metal are not adjacent metal layers, they cannot be directly connected through vias and require the use of an intermediate metal layer to achieve power transmission. The minimum area constraint in the constraint rule means that the metal shape of the intermediate metal layer must meet certain area requirements. This is to ensure that the intermediate metal layer can carry sufficient current and avoid overheating and other problems caused by excessive current density due to a small area.

[0105] When generating the metal shapes for the intermediate metal layers, you can start with the top metal layer and, following specific algorithms and rules, generate the metal shapes for the intermediate metal layers layer by layer. These shapes must match the shapes of the top and bottom metal layers and meet minimum area constraints. For example, when generating the shapes for the intermediate metal layers, you need to consider how to effectively guide the current from the top metal layer to the intermediate layer, and then transfer it to the bottom metal layer through the intermediate layer. At the same time, ensure that the area of ​​the intermediate metal layer is large enough to meet the current transmission requirements.

[0106] Step S330: Generate multiple second vias between the top metal, the middle metal, and the adjacent layers of the bottom metal according to the via design parameters, so as to establish a power connection between the top metal and the bottom metal through the metal shape of the middle metal and the multiple second vias between the adjacent layers.

[0107] After generating the metal shape of the middle layer metal of the top layer metal and the bottom layer metal, multiple second through holes can be generated between the top layer metal, the middle layer metal and the adjacent layers of the bottom layer metal according to the through hole design parameters to establish a power connection between the top layer metal and the bottom layer metal through the metal shape of the middle layer metal and the multiple second through holes between the adjacent layers.

[0108] After the metal shape of the intermediate layer metal is generated, connections can be established between adjacent layers. Similarly, based on the through-hole design parameters in the design rules, multiple second through-holes are generated between the top metal and the adjacent intermediate layer metal, between each intermediate layer metal, and between the last intermediate layer metal and the bottom metal. These second through-holes connect the metals of adjacent layers to form a complete power transmission path. Through the metal shape of the intermediate layer metal and the multiple second through-holes between these adjacent layers, power can be transmitted from the top metal through the intermediate layer metal in sequence and finally to the bottom metal, thereby realizing power connection between non-adjacent metal layers. For example, multiple through-holes are generated between the top metal and the first intermediate layer metal to introduce the current of the top metal into the first intermediate layer metal; then multiple through-holes are generated between the first intermediate layer metal and the second intermediate layer metal to continue transmitting the current until it reaches the bottom metal.

[0109] This method of establishing power connections improves the flexibility and reliability of connections by adopting different strategies for adjacent and non-adjacent metal layers, and can better adapt to complex chip layout and routing; at the same time, it strictly follows design rules and constraints to ensure electrical performance and meet the stability requirements of the chip under different operating conditions; in addition, it can also optimize the performance of the power distribution network, make power distribution more balanced, reduce electromagnetic interference, and improve the overall operating stability and electromagnetic compatibility of the chip.

[0110] In some embodiments of the present application, Figure 4 As shown, step S320 may specifically include steps S410 to S420, which are described in detail as follows:

[0111] In step S410 , the area of ​​the metal shape of the middle metal layer is determined according to the metal shape of the top metal layer and the projection of the metal shape of the bottom metal layer on the middle metal layer.

[0112] In integrated circuit design, the top and bottom metal layers are spatially located at different levels, with the middle metal layer located between them. By projecting the shapes of the top and bottom metal layers onto the plane of the middle metal layer, we can determine the projected areas of the two metal layers on the middle layer. These projected areas reflect the spatial correspondence between the top and bottom metal layers and the middle metal layer.

[0113] For example, the top metal layer might be rectangular, and the bottom metal layer circular. Projecting these onto the plane of the middle metal layer yields corresponding rectangular and circular projections. By calculating the total area covered by these projections, the initial area of ​​the middle metal layer can be determined. This area calculation provides the foundational data for determining whether the minimum area constraint is met.

[0114] In step S420 , if the determined area of ​​the metal shape of the intermediate metal layer is smaller than the minimum area constraint, the metal shape of the intermediate metal layer is filled to generate a new metal shape of the intermediate metal layer.

[0115] The minimum area constraint in the constraint rules is to ensure that the intermediate metal layer has sufficient conductive area to carry current, to avoid excessive current density due to a small area, which in turn causes problems such as heat and electromigration, affecting the performance and reliability of the chip.

[0116] When the calculated area of ​​the intermediate metal shape is less than the minimum area constraint, it can be filled. This filling can be done by expanding the existing shape or adding metal areas within it. For example, if the intermediate metal shape is a small rectangle that does not meet the minimum area requirement, you can evenly add metal strips of a certain width around the rectangle, or add some metal blocks inside the rectangle to increase its area so that it meets the minimum area constraint and generates a new metal shape that meets the requirements.

[0117] In some embodiments of the present application, after generating a new metal shape of the intermediate layer metal, a violation prediction can be performed on the surrounding area of ​​the new metal shape of the intermediate layer metal to obtain a prediction result, which is used to indicate the probability of a violation occurring; if the prediction result exceeds a preset threshold, the preliminary wiring evaluation index of the logic point corresponding to the surrounding area is updated to obtain a new wiring evaluation index, which is used to guide the adjustment of the violation.

[0118] Specifically, after generating a new metal shape for the intermediate metal layer, the area surrounding the new metal shape can be predicted for violations. Violations refer to violations of wiring rules, which are a series of strict standards set during the integrated circuit manufacturing process to ensure chip performance and manufacturability. These standards include metal line width, spacing, overlap, and many other requirements. The final inspection result is a specific numerical value or probability value that intuitively reflects the probability of violations in the surrounding area. The preset threshold is a standard set in advance. When the prediction result exceeds this preset threshold, it means that there is a high probability of violations in the surrounding area of ​​the new shape of the intermediate metal layer.

[0119] In integrated circuit design, a 3D routing database stores routing information for all levels of the chip, including the location, routing, and connectivity of metal lines. This information is recorded as logical coordinate points, forming a three-dimensional routing map. The preliminary routing assessment metric, also known as the EVA value, is a numerical value used to assess the importance, risk, or other relevant indicators of a logical coordinate point in the design. It comprehensively considers factors such as routing density, routing length, and the number of vias, and can reflect the quality of the current routing design. When the prediction results indicate a high risk of violation, it indicates a high risk of DRC violations in the surrounding area. In this case, the EVA values ​​of the corresponding logical coordinate points in the surrounding area need to be updated to reflect this change. For example, if the EVA value of a logical coordinate point originally indicated a low risk, but the DRC prediction indicates a high risk of violation, the EVA value needs to be updated to a value indicating a high risk. This allows designers to use the updated EVA value to make targeted adjustments to these high-risk areas during subsequent design optimization to reduce the likelihood of DRC violations and improve the quality and manufacturability of the integrated circuit design.

[0120] In some embodiments of the present application, Figure 5 As shown, according to the via design parameters, generating a plurality of second vias between adjacent layers of the top metal layer, the middle metal layer, and the bottom metal layer may specifically include steps S510 to S530. These steps are described below:

[0121] Step S510 : Determine the borders of the through hole arrays between adjacent layers according to the area requirements of the top metal layer, the middle metal layer, and the upper metal layer in the adjacent layers of the bottom metal layer and the through hole design parameters.

[0122] In integrated circuit design, different metal layers require electrical connections through vias. To generate multiple second vias in adjacent layers of the top metal layer, the middle metal layer, and the bottom metal layer, in this embodiment, the borders of the via arrays between adjacent layers can be determined based on the area requirements of the upper metal layers in the adjacent layers of the top metal layer, the middle metal layer, and the bottom metal layer, as well as the via design parameters. The area of ​​the upper metal layer determines the range within which the vias can be arranged. Furthermore, the via design parameters, which include information such as the size and number of the vias, must also be considered.

[0123] By comprehensively considering the area requirements of the upper metal layer and the via design parameters, the area that the via array between adjacent layers should occupy, that is, the via array border, can be determined. For example, if the upper metal layer area is small, then the via array border will also be correspondingly small. The shape and size of this border must be reasonably planned based on the via design parameters to ensure that the subsequently generated vias meet the electrical performance and manufacturing process requirements.

[0124] Step S520 : According to the size of the lower metal layer in the adjacent layer, delete the outermost portion of the frame of the through hole array that exceeds the surrounding range of the lower metal layer to obtain a new frame of the through hole array.

[0125] After determining the initial boundaries of the via array, the size of the underlying metal in the adjacent layer must also be considered. The size of the underlying metal limits the actual range of the via array, as the vias must be surrounded by the underlying metal to ensure effective current transmission.

[0126] Specifically, the outermost portion of the via array's border can be examined. If any portion extends beyond the underlying metal, it is removed. This process results in a new border for the via array that conforms to the underlying metal's dimensional requirements. This new border ensures that the via array matches the underlying metal's layout, avoiding electrical connectivity issues caused by vias extending beyond the underlying metal.

[0127] Step S530: Determine the unit spacing of the through hole array in the longitudinal and transverse directions according to the through hole design parameters, and generate a through hole array according to the new border of the through hole array and the unit spacing of the through hole array, wherein the through hole array includes a plurality of second through holes.

[0128] After obtaining the new frame of the via array, the next step is to determine the unit pitch of the via array in the vertical and horizontal directions based on the via design parameters. Setting the unit pitch is very important. It ensures sufficient space between vias to avoid electrical shorts or interference caused by too small a pitch. It also ensures that the layout of the entire via array meets the design requirements and manufacturing process standards.

[0129] Then, combining the new border of the via array with the determined unit pitch, a specific via array can be generated. This via array includes multiple second vias that will establish effective electrical connections between adjacent layers of the top metal, middle metal, and bottom metal, allowing current to be smoothly transmitted between different metal layers, thereby realizing the various functions of the integrated circuit.

[0130] In some embodiments of the present application, the second through hole can be a large-sized through hole by default. In an integrated circuit, current needs to be transmitted between different metal layers through the second through hole. The large-sized second through hole has a larger cross-sectional area, which can reduce resistance and reduce energy loss during current transmission, thereby improving the current passing capacity. Therefore, in the absence of special requirements, a large-sized second through hole is selected by default to construct a through hole array to ensure that current can flow stably and efficiently between the upper and lower metal layers to meet the electrical performance requirements of the circuit.

[0131] As mentioned earlier, design rules are primarily set by the user. However, due to the particularity of the FinFET process, these user-set parameters may not match the FinTrack requirements of the FinFET process. FinTrack requirements are a series of strict specifications for fin-related design and manufacturing in the FinFET process. They cover fin dimensions (such as width, height, length, etc., which must be precise at the nanometer level), fin pitch (which must be precisely controlled to achieve high-density integration and avoid interference), patterning accuracy (complex processes are used to ensure that the fin shape, size, and position meet the design, and processes such as lithography and etching require extremely high precision), material selection and quality (the properties of the substrate and related deposited materials must meet specific conditions), and process control (all parameters in multiple complex steps must be precisely controlled) to ensure the realization of high-performance and high-reliability FinFET devices.

[0132] In some embodiments of the present application, if the target design parameters in the design rules do not match the target requirement parameters of the integrated circuit process, the greatest common factor or greatest common multiple of the target design parameters and the target requirement parameters can be determined, and the target design parameters can be adjusted according to the greatest common factor or the greatest common multiple to obtain new design parameters.

[0133] For example, if a user-defined design rule specifies a metal line width of 10 microns, while a specific process requires a 12 micron width, this creates a mismatch. To resolve this mismatch, the greatest common factor (GCF) or greatest common multiple (LCM) of these two mismatched parameters is found. For the example above, the GCF of 10 and 12 is 2, and the LCM is 60. The goal of calculating the GCF or LCM is to find a value that balances the two parameters. The target design parameters are adjusted based on the calculated GCF or LCM. If adjustments are made based on the GCF, design parameters can be adjusted by multiples of the GCF. For example, the metal line width can be adjusted to multiples of 2, such as 8 microns or 12 microns, to more closely match the process requirements. If the lowest common multiple is used as the basis, multiple design parameters can be adjusted uniformly so that they can meet the process requirements while also conforming to the overall framework of the design rules as much as possible, so as to achieve a balance between the design rules and process requirements, and obtain new design parameters, so that the integrated circuit design can not only meet the feasibility of process manufacturing, but also achieve the performance and functions expected by the design rules as much as possible.

[0134] In some embodiments of the present application, in order to promptly discover problems in the designed power supply network and avoid rework caused by discovering problems after chip manufacturing is completed, thereby saving design time and cost and reducing project risks. In this embodiment, the voltage drop of the power supply network under maximum load can be calculated to ensure the stability and reliability of the integrated circuit power supply network. Specifically, the voltage drop of each power distribution network can be calculated based on the resistance value of each power distribution network corresponding to the target voltage domain and the current value of each power distribution network under maximum load; if the voltage drop of the target power distribution network in each power distribution network is less than the voltage value of the target voltage domain, the area corresponding to the target power distribution network is determined to be an insufficiently powered area; if the voltage drop of the target power distribution network is greater than the voltage value of the target voltage domain, the target path in the target power distribution network is determined, and a power filter element is inserted in the target path to reduce the voltage drop of the target path, and the voltage drop of the target path is greater than a preset voltage threshold.

[0135] In this embodiment, the target voltage domain refers to a specific voltage range that corresponds to a portion of a power network, including multiple power distribution networks. Each power distribution network has its own resistance value and a corresponding current value under maximum load. According to Ohm's law (voltage drop = current × resistance), the voltage drop of each power distribution network can be calculated using the resistance value of each power distribution network and its current value under maximum load.

[0136] After calculating the voltage drop of each power distribution network, the voltage drop of each power distribution network (i.e., the target power distribution network) can be compared with the voltage value of the target voltage domain. If the voltage drop of a target power distribution network is less than the voltage value of the target voltage domain, this means that when the power distribution network transmits power, the voltage has dropped to a level insufficient for normal operation by the time it reaches its corresponding area. Therefore, the area corresponding to this target power distribution network can be determined to be underpowered. For example, if the target voltage domain requires a voltage of 1.2V, but the voltage drop of a power distribution network causes the voltage reaching the corresponding area to be only 1.0V, then this area may not function properly and is considered underpowered.

[0137] If the voltage drop in a target power distribution network exceeds the voltage value of the target voltage domain, this indicates a problem with the power distribution network, possibly due to excessive resistance or current. In this case, it is necessary to further identify the target paths within the target power distribution network. Target paths are those paths where the voltage drop exceeds a preset voltage threshold. The preset voltage threshold is a pre-defined standard used to determine whether the voltage drop is excessive. If the voltage drop in a target path exceeds this threshold, measures must be taken to reduce the voltage drop. Inserting power filter components (such as decoupling capacitors) in the target path is a common solution. Power filter components provide local charge storage and release capabilities. When current changes, they can quickly replenish or absorb charge, thereby reducing voltage fluctuations and voltage drop, ensuring power stability and enabling the target path to meet normal power supply requirements.

[0138] In some embodiments of the present application, in order to meet the low power design goal of UPF in the constraint rules, in this embodiment, the UPF file can be read and processed. Specifically, first, the unified power format file in the constraint rules can be parsed to obtain the parsed file; then, according to the positioning information in the parsed file, the position where the power control element needs to be inserted and the position where the power isolation element needs to be inserted are determined; finally, according to the insertion information in the parsed file, the power control element is inserted at the position where the power control element needs to be inserted, and the power isolation element is inserted at the position where the power isolation element needs to be inserted. The power control element is used to control the on and off of the power supply, and the power isolation element is used to isolate the power supply networks corresponding to each voltage domain.

[0139] As previously mentioned, the constraints obtained in this application contain a Unified Power Format (UPF) file. This UPF file records various information and constraints related to power management. First, this UPF file can be parsed. Using specific parsing tools or algorithms, the content in the UPF file is converted into a clearer and easier-to-process format, resulting in a parsed file.

[0140] In some embodiments, a lexical analyzer can be used to analyze the read UPF commands. Its working principle is similar to breaking a sentence into individual words and determining the part of speech and meaning of each word. Here, the lexical analyzer breaks down the UPF command into <operation, parameter> tuples.

[0141] For example, a UPF command might include "Set the power switch on time to 10 microseconds." The lexical analyzer will identify "set" as an operation and "Power switch on time to 10 microseconds" as a parameter, combining them into a tuple. This is done to convert complex UPF commands into a more concise and easy-to-process form, making it easier for subsequent algorithms to further process and apply this constraint information.

[0142] After obtaining the parsed file, the corresponding power distribution network can be found within the entire power network based on the location information within the parsed file. For example, a constraint may specify a specific power network or ground network. This location information can be used to determine the specific locations where power control components and power isolation components need to be inserted. The location information details where these components need to be inserted within the entire power network. The power control component controls the on / off power supply. For example, when certain circuit modules are not required, the power control component can be used to cut off their power supply, thereby saving energy. The power isolation component, on the other hand, isolates the power networks corresponding to different voltage domains, preventing electrical interference and current leakage between different voltage domains and ensuring stable operation of each voltage domain.

[0143] Finally, based on the insertion information in the parsed file, the corresponding components are inserted at the previously determined locations. This allows for effective management of the power network, ensuring stable power supply to each circuit module as designed, while avoiding interference between different voltage domains and ensuring the normal operation of the entire integrated circuit system.

[0144] In some embodiments of the present application, connectivity checking is an important step in ensuring the correct implementation of circuit functions, and its main purpose is to ensure that the connections between all standard cells, macro modules and the power supply network are accurate. During or after the power supply network design process, a connectivity check can be performed to prevent isolated nodes that are not connected to any standard cells or macro modules from appearing in the power supply network. If there are dangling nodes, the power lines or ground lines connected to these nodes will not be able to provide power to the components in the circuit, which will not only cause the related components to fail to work, but may also cause electrical performance problems, such as increased power supply noise, decreased circuit stability, etc. Through connectivity checking, these connection errors can be discovered and corrected in a timely manner, ensuring the normal power supply of the chip and improving the reliability and performance of the chip.

[0145] In the second aspect, the present application also proposes a power network design device, such as Figure 6 As shown, the power network design device includes: an acquisition unit 601 , an identification unit 602 , a generation unit 603 and a connection unit 604 .

[0146] Among them, the acquisition unit 601 is configured to acquire design rules and constraint rules for the design of the power network in the integrated circuit; the identification unit 602 is configured to identify multiple voltage domains in the integrated circuit, and multiple power distribution networks corresponding to each of the voltage domains, each of the voltage domains corresponding to a different voltage value; the generation unit 603 is configured to generate the metal shape of the top metal and the metal shape of the corresponding bottom metal corresponding to each of the power distribution networks according to the design rules; the connection unit 604 is configured to establish a power connection between the top metal and the corresponding bottom metal corresponding to each of the power distribution networks according to the metal shape of the top metal and the metal shape of the corresponding bottom metal corresponding to each of the power distribution networks, the design rules and the constraint rules, so as to design the power network corresponding to each of the voltage domains.

[0147] In some embodiments of the present application, the generation unit 603 is further configured to determine the size and position of the metal shape of the top metal and the corresponding bottom metal corresponding to each of the power distribution networks according to the power network design parameters in the design rules; determine the direction of the metal shape of the top metal corresponding to each of the power distribution networks according to the wiring direction of the layer where the top metal corresponding to each of the power distribution networks is located; determine the direction of the metal shape of the bottom metal corresponding to each of the power distribution networks according to the wiring direction of the layer where the bottom metal corresponding to each of the power distribution networks is located; generate the metal shape of the top metal corresponding to each of the power distribution networks according to the determined size, position and direction of the metal shape of the top metal corresponding to each of the power distribution networks; generate the metal shape of the bottom metal corresponding to each of the power distribution networks according to the determined size, position and direction of the metal shape of the bottom metal corresponding to each of the power distribution networks.

[0148] In some embodiments of the present application, the device also includes a determination unit, which is configured to, when the power network design parameters do not include a length parameter, if the wiring direction is a horizontal direction, determine that the length of the metal shape of the top metal and the corresponding bottom metal corresponding to each power distribution network is the longest length in the horizontal direction; if the wiring direction is a vertical direction, determine that the length of the metal shape of the top metal and the corresponding bottom metal corresponding to each power distribution network is the longest length in the vertical direction.

[0149] In some embodiments of the present application, the connection unit 604 is further configured to, if the process of the integrated circuit is the first process, then after establishing a power connection between the top metal corresponding to each power distribution network and the corresponding bottom metal, continue to establish a power connection between the bottom metal and the metal layer where the circuit functional unit is located; if the process of the integrated circuit is the second process, then after establishing a power connection between the top metal corresponding to each power distribution network and the corresponding bottom metal, continue to establish a power connection between the bottom metal and the bottom metal, so as to realize the power connection through the bottom metal and the metal layer where the circuit functional unit is located.

[0150] In some embodiments of the present application, the connection unit 604 is further configured to generate a plurality of first through-holes according to the metal shape of the top metal and the metal shape of the bottom metal, and the through-hole design parameters in the design rules if the top metal and the corresponding bottom metal corresponding to each power distribution network are adjacent metal layers, so as to establish a power connection between the top metal and the bottom metal through the plurality of first through-holes; if the top metal and the corresponding bottom metal corresponding to each power distribution network are non-adjacent metal layers, then generate the metal shape of the intermediate layer metal layer by layer between the top metal and the bottom metal according to the metal shape of the top metal and the metal shape of the bottom metal, and the minimum area constraint in the constraint rule; and generate a plurality of second through-holes between the adjacent layers of the top metal, the intermediate layer metal and the bottom metal according to the through-hole design parameters, so as to establish a power connection between the top metal and the bottom metal through the metal shape of the intermediate layer metal and the plurality of second through-holes between the adjacent layers.

[0151] In some embodiments of the present application, the generation unit 603 is further configured to determine the area of ​​the metal shape of the intermediate layer metal based on the metal shape of the top layer metal and the projection of the metal shape of the bottom layer metal on the intermediate layer metal; if the determined area of ​​the metal shape of the intermediate layer metal is smaller than the minimum area constraint, the metal shape of the intermediate layer metal is filled to generate a new metal shape of the intermediate layer metal.

[0152] In some embodiments of the present application, the device also includes a prediction unit, which is configured to perform violation prediction on the peripheral area of ​​the new metal shape of the intermediate layer metal to obtain a prediction result, and the prediction result is used to indicate the probability of a violation; if the prediction result exceeds a preset threshold, the preliminary wiring evaluation index of the logic point corresponding to the peripheral area is updated to obtain a new wiring evaluation index, and the new wiring evaluation index is used to guide the adjustment of the violation.

[0153] In some embodiments of the present application, the generation unit 603 is further configured to determine the border of the through-hole array between the adjacent layers based on the area requirements of the top metal, the middle metal, and the upper metal in the adjacent layers of the bottom metal and the through-hole design parameters; delete the outermost part of the border of the through-hole array that exceeds the enclosing range of the lower metal according to the size of the lower metal in the adjacent layers to obtain a new border of the through-hole array; determine the unit spacing of the through-hole array in the longitudinal and transverse directions according to the through-hole design parameters, and generate the through-hole array according to the new border of the through-hole array and the unit spacing of the through-hole array, wherein the through-hole array includes the multiple second through-holes.

[0154] In some embodiments of the present application, the determination unit is further configured to determine the greatest common factor or greatest common multiple of the target design parameters and the target requirement parameters if the target design parameters in the design rules do not match the target requirement parameters of the process of the integrated circuit; and adjust the target design parameters according to the greatest common factor or the greatest common multiple to obtain new design parameters.

[0155] In some embodiments of the present application, the device also includes a calculation unit, which is configured to calculate the voltage drop of each power distribution network based on the resistance value of each power distribution network corresponding to the target voltage domain and the current value of each power distribution network under the maximum load state; if the voltage drop of the target power distribution network in each power distribution network is less than the voltage value of the target voltage domain, the area corresponding to the target power distribution network is determined to be an insufficiently powered area; if the voltage drop of the target power distribution network is greater than the voltage value of the target voltage domain, the target path in the target power distribution network is determined, and a power filter element is inserted into the target path to reduce the voltage drop of the target path, and the voltage drop of the target path is greater than a preset voltage threshold.

[0156] In some embodiments of the present application, the device also includes a parsing unit, which is configured to parse the unified power format file in the constraint rules to obtain a parsed file; determine the position where the power control element needs to be inserted and the position where the power isolation element needs to be inserted based on the positioning information in the parsed file; insert the power control element at the position where the power control element needs to be inserted, and insert the power isolation element at the position where the power isolation element needs to be inserted, according to the insertion information in the parsed file, the power control element is used to control the on and off of the power supply, and the power isolation element is used to isolate the power supply networks corresponding to each of the voltage domains.

[0157] Based on the same concept, a power network designed using the power network design method described in any of the above embodiments should also be within the scope of protection of this application. Similarly, a chip that includes at least one power network designed using the power network design method described in any of the above embodiments should also be within the scope of protection of this application.

[0158] like Figure 7 As shown, an embodiment of the present application also provides an electronic device 700, including a memory 710, a processor 720, and a computer program 711 stored in the memory 710 and executable on the processor. When the processor 720 executes the computer program 711, the steps of any of the above-mentioned power supply network design methods are implemented.

[0159] Since the electronic device introduced in this embodiment is a device used to implement a power network design device in the embodiment of the present application, based on the method introduced in the embodiment of the present application, technical personnel in this field can understand the specific implementation of the electronic device of this embodiment and its various variations. Therefore, how the electronic device implements the method in the embodiment of the present application is no longer introduced in detail here. As long as the equipment used by technical personnel in this field to implement the method in the embodiment of the present application falls within the scope of protection to be protected by this application.

[0160] During specific implementation, the computer program 711 can implement any implementation in the corresponding embodiment when executed by the processor 720.

[0161] It should be noted that, in the above embodiments, the description of each embodiment has its own focus. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant description of other embodiments.

[0162] Those skilled in the art will appreciate that the embodiments of the present application may be provided as methods, systems, or computer program products. Therefore, the present application may take the form of an entirely hardware embodiment, an entirely software embodiment, or an embodiment combining software and hardware. Furthermore, the present application may take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to memory, disk, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0163] The present application is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program products according to the embodiments of the present application. It should be understood that each process and / or box in the flowchart and / or block diagram, as well as the combination of processes and / or boxes in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded computer, or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 a process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0164] These computer program instructions may also be stored in a computer readable memory that can direct a computer or other programmable data processing device to work in a specific manner, so that the instructions stored in the computer readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 a process or multiple processes and / or boxes Figure 1 The function specified in one or more boxes.

[0165] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operational steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing the instructions executed on the computer or other programmable device for implementing the process. Figure 1 a process or multiple processes and / or boxes Figure 1 A step that specifies a function in one or more boxes.

[0166] An embodiment of the present application further provides a computer program product, which includes computer software instructions. When the computer software instructions are executed on a processing device, the processing device executes the processing flow of the power network design in the corresponding embodiment.

[0167] A computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, they fully or partially produce the processes or functions according to the embodiments of the present application. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, computer instructions can be transmitted from one website, computer, server, or data center to another website, computer, server, or data center via wired (e.g., coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) means. The computer-readable storage medium can be any available medium that can be stored by a computer, or a data storage device such as a server or data center that integrates one or more available media. Available media can include magnetic media (e.g., floppy disks, hard disks, magnetic tapes), optical media (e.g., DVDs), or semiconductor media (e.g., solid-state drives (SSDs)).

[0168] Those skilled in the art will clearly understand that, for the convenience and brevity of description, the specific working processes of the systems, devices and units described above can refer to the corresponding processes in the aforementioned method embodiments and will not be repeated here.

[0169] In the several embodiments provided in this application, it should be understood that the disclosed systems, devices and methods can be implemented in other ways. For example, the device embodiments described above are merely schematic. For example, the division of units is only a logical function division. In actual implementation, there may be other division methods, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be an indirect coupling or communication connection through some interface, device or unit, which can be electrical, mechanical or other forms.

[0170] Units described as separate components may or may not be physically separate, and components shown as units may or may not be physical units, that is, they may be located in one place or distributed across multiple network units. Some or all of these units may be selected to achieve the purpose of this embodiment according to actual needs.

[0171] In addition, the functional units in the various embodiments of the present application may be integrated into a single processing unit, or each unit may exist physically separately, or two or more units may be integrated into a single unit. The aforementioned integrated units may be implemented in the form of hardware or software functional units.

[0172] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application, or the part that contributes to the prior art, or all or part of the technical solution can be embodied in the form of a software product. The computer software product is stored in a storage medium and includes a number of instructions for enabling a computer device (which can be a personal computer, server, or network device, etc.) to execute all or part of the steps of the various embodiments of the present application. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM), random access memory (RAM), disk or optical disk, and other media that can store program code.

[0173] The above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present application.

Claims

1. A power network design method, characterized in that: include: Obtain design rules and constraints for power network design in integrated circuits; Identifying multiple voltage domains in the integrated circuit and multiple power distribution networks corresponding to each of the voltage domains, each of the voltage domains corresponding to a different voltage value; Generating a metal shape of a top metal layer and a metal shape of a bottom metal layer corresponding to each power distribution network according to the design rules; If the top metal and the corresponding bottom metal corresponding to each of the power distribution networks are non-adjacent metal layers, then determining the area of ​​the metal shape of the intermediate metal layer according to the metal shape of the top metal layer and the projection of the metal shape of the bottom metal layer on the intermediate metal layer, wherein the intermediate metal layer is the metal between the top metal layer and the bottom metal layer for realizing power transmission; if the determined area of ​​the metal shape of the intermediate metal layer is less than the minimum area constraint in the constraint rule, then filling the metal shape of the intermediate metal layer to generate a new metal shape of the intermediate metal layer; According to the through-hole design parameters in the design rules, multiple second through-holes are generated between the top metal layer, the middle metal layer, and the adjacent layers of the bottom metal layer, so as to establish a power connection between the top metal layer and the bottom metal layer through the metal shape of the middle metal layer and the multiple second through-holes between the adjacent layers, thereby designing a power supply network corresponding to each of the voltage domains.

2. The method according to claim 1, characterized in that Generating a metal shape of a top metal layer and a metal shape of a bottom metal layer corresponding to each power distribution network according to the design rules, including: Determining the size and position of the metal shapes of the top metal layer and the bottom metal layer corresponding to each of the power distribution networks according to the power network design parameters in the design rules; Determining the direction of the metal shape of the top metal layer corresponding to each power distribution network according to the wiring direction of the layer where the top metal layer corresponding to each power distribution network is located; Determining the direction of the metal shape of the bottom metal corresponding to each power distribution network according to the wiring direction of the layer where the bottom metal corresponding to each power distribution network is located; generating a metal shape of the top metal corresponding to each power distribution network according to the determined size, position and direction of the metal shape of the top metal corresponding to each power distribution network; The metal shape of the underlying metal corresponding to each power distribution network is generated according to the determined size, position and direction of the metal shape of the underlying metal corresponding to each power distribution network.

3. The method according to claim 2, characterized in that The method further comprises: When the power network design parameters do not include a length parameter, if the wiring direction is horizontal, then the lengths of the metal shapes of the top metal and the corresponding bottom metal corresponding to each power distribution network are determined to be the longest length in the horizontal direction; if the wiring direction is vertical, then the lengths of the metal shapes of the top metal and the corresponding bottom metal corresponding to each power distribution network are determined to be the longest length in the vertical direction.

4. The method according to claim 1, wherein The method further comprises: If the process of the integrated circuit is the first process, after establishing a power connection between the top metal layer corresponding to each power distribution network and the corresponding bottom metal layer, further establishing a power connection between the bottom metal layer and the metal layer where the circuit functional unit is located; If the process of the integrated circuit is the second process, after establishing a power connection between the top metal and the corresponding bottom metal corresponding to each of the power distribution networks, continue to establish a power connection between the bottom metal and the bottom metal to realize the power connection through the bottom metal and the metal layer where the circuit functional unit is located.

5. The method according to claim 1, wherein The method further comprises: If the top metal and the corresponding bottom metal corresponding to each of the power distribution networks are adjacent metal layers, a plurality of first through-holes are generated according to the metal shape of the top metal and the metal shape of the bottom metal, and the through-hole design parameters in the design rules, so as to establish a power connection between the top metal and the bottom metal through the plurality of first through-holes.

6. The method according to claim 1, wherein The method further comprises: Performing violation prediction on a peripheral area of ​​the new metal shape of the intermediate metal layer to obtain a prediction result, wherein the prediction result is used to indicate a probability of a violation occurring; If the prediction result exceeds a preset threshold, the preliminary wiring evaluation index of the logic points corresponding to the surrounding area is updated to obtain a new wiring evaluation index, and the new wiring evaluation index is used to guide the adjustment of the violation.

7. The method according to claim 1, characterized in that Generating a plurality of second through holes between adjacent layers of the top metal layer, the middle metal layer, and the bottom metal layer according to the through hole design parameters, comprising: Determining the border of the through hole array between the adjacent layers according to the area requirements of the top metal layer, the middle metal layer, and the upper metal layer in the adjacent layers of the bottom metal layer and the through hole design parameters; According to the size of the lower metal layer in the adjacent layer, deleting the outermost portion of the frame of the through hole array that exceeds the encirclement range of the lower metal layer to obtain a new frame of the through hole array; According to the through hole design parameters, the unit spacing of the through hole array in the longitudinal and transverse directions is determined, and according to the new border of the through hole array and the unit spacing of the through hole array, the through hole array is generated, and the through hole array includes the plurality of second through holes.

8. The method according to claim 1, characterized in that The method further comprises: If the target design parameters in the design rules do not match the target requirement parameters of the process of the integrated circuit, determining the greatest common factor or greatest common multiple of the target design parameters and the target requirement parameters; The target design parameters are adjusted according to the greatest common factor or the greatest common multiple to obtain new design parameters.

9. The method according to claim 1, characterized in that The method further comprises: Calculating the voltage drop of each power distribution network according to the resistance value of each power distribution network corresponding to the target voltage domain and the current value of each power distribution network under the maximum load state; If the voltage drop of the target power distribution network among the power distribution networks is less than the voltage value of the target voltage domain, determining that the area corresponding to the target power distribution network is an insufficiently powered area; If the voltage drop of the target power distribution network is greater than the voltage value of the target voltage domain, a target path in the target power distribution network is determined, and a power filter element is inserted into the target path to reduce the voltage drop of the target path, and the voltage drop of the target path is greater than a preset voltage threshold.

10. The method according to claim 1, characterized in that The method further comprises: Parsing the unified power format file in the constraint rules to obtain a parsed file; Determining, based on the positioning information in the parsed file, a position where a power control component needs to be inserted and a position where a power isolation component needs to be inserted; According to the insertion information in the parsed file, the power control element is inserted at the location where the power control element needs to be inserted, and the power isolation element is inserted at the location where the power isolation element needs to be inserted. The power control element is used to control the on and off of the power supply, and the power isolation element is used to isolate the power supply networks corresponding to each of the voltage domains.

11. A power network design device, characterized in that: include: an acquisition unit configured to acquire design rules and constraint rules for a power network design in an integrated circuit; an identification unit configured to identify a plurality of voltage domains in the integrated circuit and a plurality of power distribution networks corresponding to each of the voltage domains, each of the voltage domains corresponding to a different voltage value; a generating unit configured to generate a metal shape of a top metal layer and a metal shape of a bottom metal layer corresponding to each of the power distribution networks according to the design rules; The connection unit is configured to determine the area of ​​the metal shape of the intermediate layer metal according to the metal shape of the top layer metal and the projection of the metal shape of the bottom layer metal on the intermediate layer metal if the top layer metal and the corresponding bottom layer metal of each power distribution network are non-adjacent metal layers. The intermediate layer metal is the metal used to realize power transmission between the top layer metal and the bottom layer metal. If the determined area of ​​the metal shape of the intermediate layer metal is less than the minimum area constraint in the constraint rule, the metal shape of the intermediate layer metal is filled to generate a new metal shape of the intermediate layer metal; according to the through-hole design parameters in the design rule, a plurality of second through-holes are generated between the adjacent layers of the top layer metal, the intermediate layer metal and the bottom layer metal to establish a power connection between the top layer metal and the bottom layer metal through the metal shape of the intermediate layer metal and the plurality of second through-holes between the adjacent layers, thereby designing a power network corresponding to each of the voltage domains.

12. An electronic device comprising: A memory and a processor, wherein the processor is configured to implement the steps of the power supply network design method according to any one of claims 1 to 10 when executing a computer program stored in the memory.

13. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the power network design method according to any one of claims 1 to 10 are implemented.

14. A chip, characterized in that: The chip at least includes a power supply network designed by the power supply network design method according to any one of claims 1 to 10.

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