Graphics processor back blanking circuit and method based on assembly line
By using a pipeline-based back blanking circuit in the graphics processor, the front and back sides of the triangle are judged and split, which solves the problem that the graphics processor is difficult to effectively deal with invisible polygons, and improves the graphics processing efficiency and performance.
Patent Information
- Application Number
- CN202411748910.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-02
- Publication Date
- 2025-05-13
AI Technical Summary
In three-dimensional space, it is difficult for the graphics processor to effectively process invisible polygons and obscured polygons, resulting in reduced graphics processing efficiency.
The back blanking circuit of the graphics processor based on pipeline is adopted, and the circuit structure consisting of the graphic element command reception and triangle vertex coordinate extraction unit, triangle front and back judgment unit, designated surface removal unit, triangle element splitting and command assembly unit are used to determine and split the front and back of triangles, eliminate invisible triangle elements, and improve processing performance.
Through the pipeline structure, efficiently judge and process the front and back sides of the triangle, the processing performance of back blanking is maximized and the overall performance of the graphics processor is improved.
Smart Images
Figure CN119991407A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of computer hardware, and in particular to a pipeline-based backside blanking circuit and method for a graphics processor. Background Art
[0002] In three-dimensional space, although a polygon has two faces, the polygons marked as "back" cannot be seen, and some polygons are front-facing but are blocked by other polygons and cannot be seen. If invisible polygons are treated the same as visible polygons, the efficiency of graphics processing will be reduced. At this time, unnecessary faces can be culled to improve graphics processing efficiency. We can determine the front and back sides of the primitives based on the rotation direction of the triangle primitive vertices and the calculated A value, and then cull the hidden primitives or the back primitives according to the culling command to reduce the processing volume of the subsequent tasks; so as to fundamentally improve the processing performance of the graphics processor. On the other hand, a high-performance processing circuit is sought to increase the processing rate of back-face culling and thus improve the performance of the graphics processor. The invention discloses a pipeline-based back-face culling circuit for a graphics processor, wherein a four-level functional pipeline is adopted, and a full-pipeline structure is adopted in each level of the functional pipeline. In particular, after invisible triangle primitives are removed from a triangle, a buffer cache area is used to split the triangle into corresponding point primitives, line primitives, or triangle primitives in a pipeline recursive manner according to a polygon mode polygonmode configured by an Opengl command, and the triangles are sent to a lower-level pipeline, thereby maximally improving the processing performance of back-face culling. Summary of the invention
[0003] In order to solve the above-mentioned technical problems existing in the background technology, the present invention provides a pipeline-based graphics processor back-face culling circuit and method, which can efficiently judge the front and back faces of the received triangles, and then split the unculled triangles into corresponding point primitives, line primitives, or triangle primitives in a pipeline recursive manner using a buffer cache area according to the triangle primitive point drawing, line drawing, or fill mode configured by the GP parameter configuration unit, and send them to the lower-level pipeline, thereby maximizing the processing performance of back-face culling.
[0004] The technical solution of the present invention is: a pipeline-based graphics processor back-face blanking circuit, which is special in that: the pipeline-based graphics processor back-face blanking circuit includes a primitive command receiving and triangle vertex coordinate extraction unit, a triangle front and back face judgment unit, a specified face culling unit and a triangle primitive splitting and command assembly unit connected in sequence, and a GP parameter configuration unit is respectively connected to the triangle front and back face judgment unit, the specified face culling unit and the triangle primitive splitting and command assembly unit.
[0005] Furthermore, the primitive command receiving and triangle vertex coordinate extraction unit decodes and analyzes according to the received vertex commands of the previous-level primitives. There are three types of primitives sent to this level by the previous-level pipeline, namely point primitives, line primitives and triangle primitives. After decoding and analysis, the received point primitives and line primitives are directly transmitted to the triangle primitive splitting and command assembly unit according to the number of pipeline beats consumed by the triangle front and back face judgment unit and the specified face culling unit. If it is a triangle primitive after decoding and analysis, the three vertex coordinates (X1, Y1) (X2, Y2) (X3, Y3) of the triangle are extracted and sent to the lower-level triangle front and back face judgment unit. At the same time, the vertex boundary points and edge marks of the triangle primitives are transmitted downward to the triangle primitive splitting and command assembly unit according to the pipeline beats.
[0006] Furthermore, the triangle front and back side judgment unit calculates the A value according to the current triangle vertex rotation direction configured by the OpenGl command, and the triangle vertex coordinates (X1, Y1)(X2, Y2)(X3, Y3) output by the primitive command reception and triangle vertex coordinate extraction unit according to A=X1(Y2-Y3)+X2(Y3-Y1)+X3(Y1-Y2); when the triangle vertex rotation direction is counterclockwise and the A value is greater than 0, the triangle is judged to be the front side, otherwise it is the back side; when the triangle vertex rotation direction is clockwise and the A value is less than 0, the triangle is judged to be the front side, otherwise it is the back side.
[0007] Furthermore, the GP parameter configuration unit is used to configure the rotation direction of the currently received triangle vertex by OpenGl instructions, to remove the front, back or front-back triangles, whether to turn on the hidden function and the front-back drawing mode parameters of the triangle.
[0008] Furthermore, the face culling unit is specified to turn on the hidden face function and cull the front face, back face, or front and back face parameters according to the front and back face flags of the triangle calculated by the triangle front and back face judgment unit and the GP parameter configuration unit; when the hidden face function is turned off, all triangles are sent to the lower-level unit regardless of whether the received triangle is a front-face triangle or a back-face triangle, and whether the front-face triangle, back-face triangle, or the front and back-face triangles are culled; when the hidden face function is turned on, the received triangle is the front face, and the front-face triangle is culled, then no triangle is sent to the lower-level unit; the back-face triangle is processed in the same way as the front face; when the hidden face function is turned on, the received triangle has both the front face and the back face, and both the front and back-face triangles are culled, then no triangle is sent to the lower-level unit.
[0009] Furthermore, the triangle primitive splitting and command assembly unit reassembles the triangle primitive command according to the uncooked triangles sent by the specified face triangle culling unit, the current triangle front and back side drawing mode configured by the GP parameter configuration unit, and whether the triangle vertices transmitted by the primitive command reception and triangle vertex coordinate extraction unit are boundary points and boundary edges.
[0010] Furthermore, after the front and back face judgment of the previous triangle and the culling of the specified triangle face, the triangle transmitted to the triangle primitive splitting and command assembly unit is the front face and the triangle front face drawing mode configured by the OpenGl instruction is point drawing or line drawing, and according to the boundary points and boundary edge flags transmitted by the primitive command reception and triangle vertex coordinate extraction unit, it is split into corresponding point primitives and line primitive commands and sent to the lower-level pipeline unit; when the front triangle drawing mode configured by the OpenGl instruction is the fill mode, the boundary points and boundary edge flags received by the primitive command reception and triangle vertex coordinate extraction unit are no longer concerned, and the original triangle primitive command is directly sent to the lower-level pipeline unit in the received format; when the calculated triangle is the back face, the processing method is the same as the front face.
[0011] A method for implementing the above pipeline-based backside blanking circuit of a graphics processor is special in that the method comprises the following steps:
[0012] 1) The primitive command receiving and triangle vertex coordinate extraction unit decodes and analyzes the received primitive vertex commands of the previous stage. There are three types of primitives sent to this stage by the previous stage pipeline, namely point primitives, line primitives and triangle primitives. After decoding and analysis, the received point primitives and line primitives are directly transmitted to the triangle primitive splitting and command assembly unit according to the number of pipeline beats consumed by the triangle front and back face judgment unit and the specified face removal unit. If the decoding and analysis shows that it is a triangle primitive, the three vertex coordinates (X1, Y1) (X2, Y2) (X3, Y3) of the triangle are extracted and sent to the lower-level triangle front and back face judgment unit. At the same time, the vertex boundary points and edge marks of the triangle primitives are transmitted downward to the triangle primitive splitting and command assembly unit according to the pipeline beats;
[0013] 2) The triangle front and back face judgment unit calculates the A value according to the current triangle vertex rotation direction configured by the OpenGl command, and the triangle vertex coordinates (X1, Y1) (X2, Y2) (X3, Y3) received by the primitive command and output by the triangle vertex coordinate extraction unit according to A = X1 (Y2-Y3) + X2 (Y3-Y1) + X3 (Y1-Y2); when the triangle vertex rotation direction is counterclockwise and the A value is greater than 0, the triangle is judged to be the front face, otherwise it is the back face; when the triangle vertex rotation direction is clockwise and the A value is less than 0, the triangle is judged to be the front face, otherwise it is the back face;
[0014] 3) The designated face culling unit determines whether to enable the hidden function and cull the front face, back face, or front and back face parameters according to the front and back face flags of the triangles calculated by the triangle front and back face judgment unit and the GP parameter configuration unit; when the hidden function is turned off, all triangles are sent to the lower-level unit regardless of whether the received triangles are front face triangles or back face triangles, and whether the front face triangles, back face triangles, or front and back face triangles are culled; when the hidden function is turned on, the received triangle is the front face, and the front face triangles are culled, then no triangle is sent to the lower-level unit; the back face triangles are processed in the same way as the front face; when the hidden function is turned on, the received triangles have both the front face and the back face, and both the front and back face triangles are culled, then no triangle is sent to the lower-level unit;
[0015] 4) The triangle primitive splitting and command assembly unit reassembles the triangle primitive command according to the un-eliminated triangles sent by the designated face triangle elimination unit, the current triangle front and back drawing mode configured by the GP parameter configuration unit, and whether the triangle vertices transmitted by the primitive command reception and triangle vertex coordinate extraction unit are boundary points and boundary edges;
[0016] 5) After the front and back faces of the previous triangle are judged and the specified triangle faces are culled, the triangle transmitted to the triangle primitive splitting and command assembly unit is the front face and the triangle front drawing mode configured by the OpenGl instruction is point drawing or line drawing, and according to the boundary points and boundary edge flags transmitted by the primitive command reception and triangle vertex coordinate extraction unit, it is split into corresponding point primitives and line primitive commands and sent to the lower-level pipeline unit; when the front triangle drawing mode configured by the OpenGl instruction is the fill mode, the boundary points and boundary edge flags received by the primitive command reception and triangle vertex coordinate extraction unit are no longer concerned, and the original triangle primitive command is directly sent to the lower-level pipeline unit according to the received format; when the calculated triangle is the back face, the processing method is the same as the front face.
[0017] Furthermore, the GP parameter configuration unit is used to configure the rotation direction of the currently received triangle vertex by OpenGl instructions, to remove the front, back or front-back triangles, whether to turn on the hidden function and the front-back drawing mode parameters of the triangle.
[0018] The present invention has the following advantages:
[0019] 1) The present invention provides a pipeline-based back-face culling circuit and method for a graphics processor, the circuit structure of which consists of a primitive command receiving and triangle vertex coordinate extraction unit, a triangle front and back face judgment unit, a specified face culling unit, a triangle primitive splitting and command assembly unit, and a GP parameter configuration unit. The entire circuit structure adopts a full pipeline to efficiently perform front and back face judgment on the received triangles, and then according to the triangle primitive point drawing, line drawing, or fill mode configured by the GP parameter configuration unit, the unculled triangles are split into corresponding point primitives, line primitives, or triangle primitives in a pipeline recursive manner using a buffer cache area and sent to the lower-level pipeline, thereby maximizing the processing performance of back-face culling.
[0020] 2) The present invention provides a pipeline-based graphics processor back-face culling circuit and method, which can, after judging the front and back faces of received triangles, split the unculled triangles into corresponding point primitives, line primitives, or triangle primitives in a pipeline recursive manner using a buffer cache area according to the triangle primitive point drawing, line drawing, or fill mode configured by the GP parameter configuration unit, and send them to the lower-level pipeline. The entire primitive command reception and triangle vertex coordinate extraction, triangle front and back face judgment, specified triangle face culling, triangle primitive splitting and command assembly are implemented in a full pipeline, thereby maximizing the processing performance of back-face culling. BRIEF DESCRIPTION OF THE DRAWINGS
[0021] Figure 1 It is a circuit structure diagram of the present invention;
[0022] Figure 2 It is the primitive vertex command format of the present invention;
[0023] Figure 3 It is the vertex attribute data format in the present invention;
[0024] Figure 4 It is the vertex command format in the simple mode of the present invention;
[0025] Figure 5 The location and validity of vertex attribute data in the complex mode of the present invention;
[0026] Figure 6 It is a cache array defined in the present invention with a depth of 12 and a bit width of 1, 17, and 768 bits respectively;
[0027] Figure 7 It is the cache array command assembly status when a simple mode triangle is received in the present invention, the GP parameter configuration mode is the point-and-stroke mode, and the edgeflags are all valid;
[0028] Figure 8It is the cache array command assembly status when a simple mode triangle is received in the present invention, the GP parameter configuration mode is the line drawing mode, and the edgeflags are all valid;
[0029] Fig. 9 It is the cache array command assembly status when a complex mode command triangle is received in the present invention, the GP parameter configuration mode is the stipple mode, and the edgeflags are all valid;
[0030] Fig.10 It is the cache array command assembly status when a complex mode command triangle is received in the present invention, the GP parameter configuration mode is the line drawing mode, and the edgeflag is valid;
[0031] Fig.11 It is the cache array command assembly status when two command triangles of complex mode are received in the present invention, and the GP parameter configuration mode is the stipple mode, and the edgeflags are all valid;
[0032] Fig.12 It is the cache array command assembly status when two command triangles of complex mode are received in the present invention, and the GP parameter configuration mode is line drawing mode and edgeflags are all valid. DETAILED DESCRIPTION
[0033] The present invention is further described in detail below in conjunction with the accompanying drawings and specific embodiments.
[0034] See also Figure 1 The structure of a specific embodiment of a pipeline-based graphics processor back surface blanking circuit provided by the present invention includes a primitive command receiving and triangle vertex coordinate extraction unit, a triangle front and back surface judgment unit, a specified surface culling unit, a triangle primitive splitting and command assembling unit and a GP parameter configuration unit. The primitive command receiving and triangle vertex coordinate extraction unit, the triangle front and back surface judgment unit, the specified surface culling unit and the triangle primitive splitting and command assembling unit are connected in sequence, and the GP parameter configuration unit is respectively connected to the triangle front and back surface judgment unit, the specified surface culling unit and the triangle primitive splitting and command assembling unit.
[0035] The primitive command receiving and triangle vertex coordinate extraction unit receives the primitive command from the upper pipeline unit for decoding and parsing, wherein the primitive command format is as follows: Figure 2 As shown in Table 1, it contains a 17-bit command header and six 128-bit attribute data bits. The command header structure is shown in Table 1. By parsing and decoding bits 7-9 of the command header, it is determined whether the currently received primitive command is a point primitive, a line primitive, or a triangle primitive. The attributes that each vertex can carry (coordinates, front main color, front auxiliary color, back main color, back auxiliary color, 0-5 total 6 textures, fog coordinates, and boundary flags) are as follows: Figure 3 As shown in the figure, according to the number of attributes carried by each vertex, the vertex command format is divided into simple mode (containing only the coordinates of 3 vertices and the main color of the front face) as follows Figure 4 As shown in the figure, there is one command in complex mode (containing only vertex coordinates, front and back colors and zero texture) and two commands in complex mode (containing coordinates, colors, textures and fog coordinates). Figure 5 As shown. If the currently received primitive is a point primitive or a line primitive, no processing is performed on it, and the command is directly transmitted downward to the triangle primitive splitting and command assembly unit according to the received format according to the pipeline beat; if the currently received primitive is a triangle primitive, the coordinates of the three vertices of the triangle primitive (X1, Y1), (X2, Y2), (X3, Y3) and the boundary flags Edgeflag1, Edgeflag2, and Edgeflag3 are extracted, where Edgeflag1, Edgeflag2, and Edgeflag3 are 1 to indicate that the point is a boundary point or the edge is a boundary edge, and 0 indicates that it is an internal point and an internal edge; the coordinates of the three vertices of the triangle are output to the triangle front and back judgment unit, and at the same time, the vertex flags Edgeflag1, Edgeflag2, and Edgeflag3 of the triangle primitive and the attributes of the vertices are sent to the triangle primitive splitting and command assembly unit according to the pipeline length beat.
[0036] Table 1 The format of the 17-bit command header in the primitive vertex command is shown in the table
[0037]
[0038]
[0039] The triangle front and back judgment unit receives the coordinate values of the three vertices of the triangle from the primitive command receiving and triangle vertex coordinate extraction unit, multiplies the X coordinate of vertex 1 and the difference between the Y coordinates of vertex 2 and vertex 3, multiplies the X coordinate of vertex 2 and the difference between the Y coordinates of vertex 3 and vertex 1, and multiplies the X coordinate of vertex 3 and the difference between the Y coordinates of vertex 1 and vertex 2. Finally, the three products are added to obtain the A value (area) of the triangle. Then, according to the vertex rotation direction of the current triangle configured by the GP parameter configuration unit OpenGl instruction, when the vertex rotation direction of the triangle is counterclockwise and the A value is greater than 0, the triangle is judged to be the front side, otherwise it is the back side; when the vertex rotation direction of the triangle is clockwise and the A value is less than 0, the triangle is judged to be the front side, otherwise it is the back side.
[0040] The GP parameter configuration unit configures the rotation direction of the currently received triangle vertices according to the OpenGl command, removes the front, back or front-back triangles, whether to turn on the hidden function and the front-back drawing mode parameters of the triangle.
[0041] The designated face culling unit receives the triangle front and back face judgment unit outputs the triangle front and back face flag, and receives whether to open the hidden function and cull the front face, back face, or front and back face parameters configured by the GP parameter configuration unit; when the hidden function is turned off, no matter whether the received triangle is the front face triangle or the back face triangle, and whether the front face triangle, back face triangle, or the front and back face triangle are culled, all triangles are sent to the lower unit; when the hidden function is turned on, the received triangle is the front face, and the front face triangle is culled, no triangle is sent to the lower unit; when the hidden function is turned on, the received triangle is the back face, and the back face triangle is culled, no triangle is sent to the lower unit; when the hidden function is turned on, the received triangle is the front face, and the back face triangle is culled, the front face triangle is sent to the lower unit normally; when the hidden function is turned on, the received triangle is the back face, and the front face triangle is culled, the back face triangle is sent to the lower unit normally; when the hidden function is turned on, the received triangle is the back face, and the front face triangle is culled, the back face triangle is sent to the lower unit normally; when the hidden function is turned on, the received triangle has both the front face and the back face, and both the front and back face triangles are culled, no triangle is sent to the lower unit.
[0042] The triangle primitive decomposition and command assembly unit reassembles and sends the primitive command according to the triangle primitive command transmitted by the specified face culling unit, the front and back drawing mode configured by the GP parameter configuration unit, and whether the triangle vertices received by the primitive command and transmitted by the triangle vertex coordinate extraction unit are boundary points and boundary edges. When the currently received triangle is in simple mode, it is determined to be a front triangle by the triangle front and back judgment unit and the front drawing mode configured by the OpenGl instruction of the GP parameter configuration unit is the point drawing mode, as well as the boundary point flags Edgeflag[2], Edgeflag[1], and Edgeflag[0] sent by the primitive command reception and triangle vertex coordinate extraction unit, a defined array buffer with a depth of 12 and a bit width of 1 bit, 17 bit, and 768 bit is used as shown in the figure. Figure 6 As shown, after each clock cycle, the data of one array is recursively transferred to the previous array, for example, buffer2 data is transferred to buffer1, buffer3 data is transferred to buffer2, buffer4 data is transferred to buffer3... buffer12 data is transferred to buffer11. It is split into corresponding point primitive commands and sent to the lower-level pipeline units such as Figure 7 shown. Figure 7The figure shows the case where all three vertices of the triangle are boundary points, that is, Edgeflag[2], Edgeflag[1], and Edgeflag[0] are all 1, and the buffer_wr of each point primitive after the corresponding split is 1. When one of the vertices is an internal point, that is, one of the bits [2:0] of Edgeflag is 0, the corresponding buffer_wr is 0, and the corresponding triangle vertex is discarded after being split into point primitives and is no longer sent to the lower level pipeline. If the Edgeflag[2], Edgeflag[1], and Edgeflag[0] flags of the three vertices of the current triangle are two valid and one invalid, then they are separated. Figure 7 The command is split into three point primitive commands and two valid point primitive buffer_wr are set to 1 and sent to the lower pipeline unit, and one invalid point primitive buffer_wr is set to 0 and discarded; if the Edgeflag[2], Edgeflag[1], and Edgeflag[0] flags of the three vertices of the current triangle are valid and invalid, they are sent as Figure 7 The command is split into three point primitive commands and one valid point primitive buffer_wr is set to 1 and sent to the lower pipeline unit, and two invalid point primitive buffer_wr are set to 0 and discarded.
[0043] When the currently received triangle is in simple mode, it is determined to be a front triangle by the triangle front and back judgment unit, and the front drawing mode configured by the GP parameter configuration unit OpenGl instruction is line drawing mode, and the edge point flags Edgeflag[2], Edgeflag[1], and Edgeflag[0] sent by the primitive command reception and triangle vertex coordinate extraction unit are split into corresponding line primitive commands and sent to the lower-level pipeline units such as Figure 8 shown. Figure 8The figure shows the case where all three edges of the triangle are boundary edges, that is, Edgeflag[2], Edgeflag[1], and Edgeflag[0] are all 1, and the corresponding buffer_wr is 1. When one of the vertices is an internal edge, that is, when one of the bits [2:0] of Edgeflag is 0, the corresponding buffer_wr is 0, and the corresponding triangle vertex is discarded after being split into line primitives and is no longer sent to the lower-level pipeline. If Edgeflag[2] and Edgeflag[1] are valid and Edgeflag[0] is invalid among the three vertices of the current triangle, it will be split into three lines (vertex1vetex2, vertex2vetex3, vertex3vetex1), where the buffer_wr corresponding to lines vertex1vetex2 and vertex2vetex3 is 1 and sent to the lower-level pipeline unit, and the buffer_wr corresponding to line vertex3vetex1 is 0 and discarded, and the splitting of the other two valid vertices is similar; if Edgeflag[2] is valid and Edgeflag[1] and Edgeflag[0] are invalid among the three vertices of the current triangle, it will be split into three lines (vertex1vetex2, vertex2vetex3, vertex3vetex1), where the buffer_wr corresponding to line vertex1vetex2 is 1 and sent to the lower-level pipeline unit, and the buffer_wr corresponding to lines vertex2vetex3 and vertex3vetex1 is 0 and discarded, and the splitting of the other two valid vertices is similar.
[0044] When the currently received triangle is a complex mode command, it is determined to be a front triangle by the triangle front and back judgment unit and the front drawing mode configured by the GP parameter configuration unit OpenGl instruction is the point drawing mode, and the edge point flags Edgeflag[2], Edgeflag[1], and Edgeflag[0] sent by the primitive command reception and triangle vertex coordinate extraction unit are split into corresponding point primitive commands and sent to the lower-level pipeline units such as Fig. 9 shown.
[0045] When the currently received triangle is a complex mode command, it is determined to be a front triangle by the triangle front and back judgment unit and the front drawing mode configured by the GP parameter configuration unit OpenGl instruction is the line drawing mode, and the edge point flags Edgeflag[2], Edgeflag[1], and Edgeflag[0] sent by the primitive command reception and triangle vertex coordinate extraction unit are split into corresponding line primitive commands and sent to the lower-level pipeline units such as Fig.10 shown.
[0046] When the currently received triangle is a complex mode command, it is judged as a front triangle by the triangle front and back judgment unit and the front drawing mode configured by the GP parameter configuration unit OpenGl instruction is the point drawing mode, and the edge point flags Edgeflag[2], Edgeflag[1], and Edgeflag[0] sent by the primitive command reception and triangle vertex coordinate extraction unit are split into corresponding point primitive commands and sent to the lower-level pipeline units such as Fig.11 shown.
[0047] When the currently received triangle is a complex mode command, it is judged as a front triangle by the triangle front and back judgment unit and the front drawing mode configured by the GP parameter configuration unit OpenGl instruction is the line drawing mode, and the edge point flags Edgeflag[2], Edgeflag[1], and Edgeflag[0] sent by the primitive command reception and triangle vertex coordinate extraction unit are split into corresponding line primitive commands and sent to the lower-level pipeline units such as Fig.12 shown.
[0048] When the front drawing mode configured by the OpenGl instruction is the fill mode, the original primitive command is sent to the lower-level pipeline unit as received.
[0049] All the complex mode examples above are based on the front side. If it is the back side, the 13th and 14th bits of buffer_word need to be changed to 0, and the 11th and 12th bits need to be changed to 1; the 10th bit x can be 0 or 1, depending on whether the 0-th texture is valid; the 4th bit is changed to 0. The 16th bit of buffer_word corresponds to the start of the application-level primitive. If it is the start of the application-level primitive, it is 1, otherwise it is 0.
[0050] The content of the present invention and the technical content not specifically described in the above embodiments are the same as the prior art.
[0051] The above are only specific embodiments disclosed in the present invention, but the protection scope of the present invention is not limited thereto. The protection scope of the present invention shall be based on the protection scope of the claims.
Claims
1. A pipeline-based backside blanking circuit for a graphics processor, characterized in that: The pipeline-based graphics processor back surface blanking circuit includes a primitive command receiving and triangle vertex coordinate extraction unit, a triangle front and back surface judgment unit, a specified surface culling unit and a triangle primitive splitting and command assembling unit which are connected in sequence, and the GP parameter configuration unit is respectively connected to the triangle front and back surface judgment unit, the specified surface culling unit and the triangle primitive splitting and command assembling unit.
2. The pipeline-based backside blanking circuit for a graphics processor according to claim 1, characterized in that: The primitive command receiving and triangle vertex coordinate extraction unit decodes and analyzes according to the received vertex commands of the previous primitives. There are three types of primitives sent to this level by the previous pipeline, namely point primitives, line primitives and triangle primitives. After decoding and analysis, the received point primitives and line primitives are directly transmitted to the triangle primitive splitting and command assembly unit according to the number of pipeline beats consumed by the triangle front and back face judgment unit and the specified face culling unit. If it is a triangle primitive after decoding and analysis, the three vertex coordinates (X1, Y1) (X2, Y2) (X3, Y3) of the triangle are extracted and sent to the lower-level triangle front and back face judgment unit. At the same time, the vertex boundary points and edge marks of the triangle primitives are transmitted downward to the triangle primitive splitting and command assembly unit according to the pipeline beats.
3. The pipeline-based backside blanking circuit for a graphics processor according to claim 2, characterized in that: The triangle front and back side judgment unit calculates the A value according to the current triangle vertex rotation direction configured by the OpenGl command, and the triangle vertex coordinates (X1, Y1)(X2, Y2)(X3, Y3) output by the primitive command reception and triangle vertex coordinate extraction unit according to A=X1(Y2-Y3)+X2(Y3-Y1)+X3(Y1-Y2); when the triangle vertex rotation direction is counterclockwise and the A value is greater than 0, the triangle is judged to be the front side, otherwise it is the back side; when the triangle vertex rotation direction is clockwise and the A value is less than 0, the triangle is judged to be the front side, otherwise it is the back side.
4. The pipeline-based backside blanking circuit for a graphics processor according to claim 3, characterized in that: The GP parameter configuration unit is used to configure the rotation direction of the currently received triangle vertex through OpenGl instructions, remove the front, back or front and back triangles, whether to turn on the hidden function and the front and back drawing mode parameters of the triangle.
5. The pipeline-based backside blanking circuit for a graphics processor according to claim 4, characterized in that: The designated face culling unit determines whether to turn on the hidden face function and cull the front face, back face, or the front and back face parameters according to the front and back face flags of the triangle calculated by the triangle front and back face judgment unit and the GP parameter configuration unit; when the hidden face function is turned off, all triangles are sent to the lower-level unit regardless of whether the received triangle is a front face triangle or a back face triangle, and whether the front face triangle, back face triangle, or the front and back face triangles are culled; when the hidden face function is turned on, the received triangle is the front face, and the front face triangle is culled, then no triangle is sent to the lower-level unit; the back face triangle is processed in the same way as the front face; when the hidden face function is turned on, the received triangle has both the front face and the back face, and both the front and back face triangles are culled, then no triangle is sent to the lower-level unit.
6. The pipeline-based backside blanking circuit for a graphics processor according to claim 5, characterized in that: The triangle primitive splitting and command assembly unit reassembles the triangle primitive command according to the un-culled triangles sent by the specified face triangle culling unit, the current triangle front and back drawing mode configured by the GP parameter configuration unit, and whether the triangle vertices received by the primitive command and transmitted by the triangle vertex coordinate extraction unit are boundary points and boundary edges.
7. The pipeline-based backside blanking circuit for a graphics processor according to claim 6, characterized in that: After the front and back face judgment of the previous triangle and the culling of the specified triangle face, the triangle transmitted to the triangle primitive splitting and command assembly unit is the front face and the triangle front face drawing mode configured by the OpenGl instruction is point drawing or line drawing, and according to the boundary points and boundary edge flags transmitted by the primitive command reception and triangle vertex coordinate extraction unit, it is split into corresponding point primitives and line primitive commands and sent to the lower-level pipeline unit; when the front triangle drawing mode configured by the OpenGl instruction is the fill mode, the boundary points and boundary edge flags received by the primitive command reception and triangle vertex coordinate extraction unit are no longer concerned, and the original triangle primitive command is directly sent to the lower-level pipeline unit according to the received format; when the calculated triangle is the back face, the processing method is the same as the front face.
8. A method for implementing the pipeline-based backside blanking circuit of a graphics processor according to claim 1, characterized in that: The method comprises the following steps: 1) The primitive command receiving and triangle vertex coordinate extraction unit decodes and analyzes the received primitive vertex commands of the previous stage. There are three types of primitives sent to this stage by the previous stage pipeline, namely point primitives, line primitives and triangle primitives. After decoding and analysis, the received point primitives and line primitives are directly transmitted to the triangle primitive splitting and command assembly unit according to the number of pipeline beats consumed by the triangle front and back face judgment unit and the specified face removal unit. If the decoding and analysis shows that it is a triangle primitive, the three vertex coordinates (X1, Y1) (X2, Y2) (X3, Y3) of the triangle are extracted and sent to the lower-level triangle front and back face judgment unit. At the same time, the vertex boundary points and edge marks of the triangle primitives are transmitted downward to the triangle primitive splitting and command assembly unit according to the pipeline beats; 2) The triangle front and back face judgment unit calculates the A value according to the current triangle vertex rotation direction configured by the OpenGl command, and the triangle vertex coordinates (X1, Y1) (X2, Y2) (X3, Y3) received by the primitive command and output by the triangle vertex coordinate extraction unit according to A = X1 (Y2-Y3) + X2 (Y3-Y1) + X3 (Y1-Y2); when the triangle vertex rotation direction is counterclockwise and the A value is greater than 0, the triangle is judged to be the front face, otherwise it is the back face; when the triangle vertex rotation direction is clockwise and the A value is less than 0, the triangle is judged to be the front face, otherwise it is the back face; 3) The designated face culling unit determines whether to enable the hidden function and cull the front face, back face, or front and back face parameters according to the front and back face flags of the triangles calculated by the triangle front and back face judgment unit and the GP parameter configuration unit; when the hidden function is turned off, all triangles are sent to the lower-level unit regardless of whether the received triangles are front face triangles or back face triangles, and whether the front face triangles, back face triangles, or front and back face triangles are culled; when the hidden function is turned on, the received triangle is the front face, and the front face triangles are culled, then no triangle is sent to the lower-level unit; the back face triangles are processed in the same way as the front face; when the hidden function is turned on, the received triangles have both the front face and the back face, and both the front and back face triangles are culled, then no triangle is sent to the lower-level unit; 4) The triangle primitive splitting and command assembly unit reassembles the triangle primitive command according to the un-eliminated triangles sent by the designated face triangle elimination unit, the current triangle front and back drawing mode configured by the GP parameter configuration unit, and whether the triangle vertices transmitted by the primitive command reception and triangle vertex coordinate extraction unit are boundary points and boundary edges; 5) After the front and back faces of the previous triangle are judged and the specified triangle faces are culled, the triangle transmitted to the triangle primitive splitting and command assembly unit is the front face and the triangle front drawing mode configured by the OpenGl instruction is point drawing or line drawing, and according to the boundary points and boundary edge flags transmitted by the primitive command reception and triangle vertex coordinate extraction unit, it is split into corresponding point primitives and line primitive commands and sent to the lower-level pipeline unit; when the front triangle drawing mode configured by the OpenGl instruction is the fill mode, the boundary points and boundary edge flags received by the primitive command reception and triangle vertex coordinate extraction unit are no longer concerned, and the original triangle primitive command is directly sent to the lower-level pipeline unit according to the received format; when the calculated triangle is the back face, the processing method is the same as the front face.
9. The pipeline-based backface culling method for a graphics processor according to claim 8, characterized in that: The GP parameter configuration unit is used to configure the rotation direction of the currently received triangle vertex through OpenGl instructions, remove the front, back or front and back triangles, whether to turn on the hidden function and the front and back drawing mode parameters of the triangle.