Multi-channel simulation image generation system based on FPGA parallel compression

Abstract

The invention belongs to the technical field of image simulation, and provides a multichannel simulation image generation system based on FPGA (Field Programmable Gate Array) parallel compression, which comprises a CPU (Central Processing Unit) processing module (1) and an FPGA board card module (2), the CPU processing module (1) comprises a simulation process guide control assembly (4), a simulation picture generation module (5), a three-dimensional model generation module (6) and a resource management module (9); the simulation process guide and control assembly (4) is used for importing simulation data (3); and the resource management module (9) is used for analyzing and converting the imported simulation data (3) and loading a corresponding target unmanned aerial vehicle three-dimensional model (10) and map information (11) according to an analysis result. According to the technical scheme, the FPGA board card capable of being standardized is inserted into the computer system host, and the multi-channel simulation image generation system based on FPGA parallel compression is formed.

Description

Technical Field

[0001] The invention belongs to the technical field of image simulation, and in particular relates to a multi-channel simulation image generation system based on FPGA parallel compression. Background Art

[0002] Scene image simulation technology can be simulated and modeled according to the theoretical model of target and background characteristics to generate full-band images. It has the significant advantages of diversified and comprehensive simulation scenes and is the basic requirement for current research in multiple fields such as image processing algorithms, neural network learning sample generation, and command decision-making use case analysis. However, with the increasing complexity of theoretical models, fidelity algorithms, image rendering, and application scenario dimensions, the computing power required for simulation image generation is also increasing, and there is even a need to send multiple systems to run simultaneously. Correspondingly, the system running speed has become one of the important indicators of the simulation image generation system and one of the important references for system pricing. In pursuit of higher efficiency, parallel computing methods have been introduced in the development of computing and processing technology. The advantages of parallel computing are: saving time and cost; solving larger and more complex problems; providing concurrency; and making better use of parallel hardware. Parallel processor structure and parallel processing algorithm are the basic methods to achieve parallelism, and parallel algorithms can be realized through the parallel operation of multiple types of processors such as multi-core processors, DSP chips, and FPGA chips.

[0003] Each logic gate in the FPGA chip performs a certain logic operation at each clock cycle. Therefore, FPGA is essentially a large-scale parallel computing device. Compared with microprocessors, the main advantage of FPGA is that it can perform logic operations and assignments on a large number of variables at the same time, which is very suitable for developing parallel computing applications. However, compared with computer system programming, hardware programming capabilities such as FPGA and DSP require high development capabilities, few development resources, high development costs, long cycles, and difficult upgrades. Therefore, traditional parallel computing capabilities to improve the performance of simulation systems require a lot of manpower and material costs.

[0004] Analyzing the computational process of image generation, first of all, the graphic data directly generated by the model is a numerical matrix based on pixels, and the amount of data is extremely large. It is necessary to use standard coding compression to form a standard image format file before transmitting it to the outside. Although compression technology is very mature, it often takes up a lot of computing resources. On the other hand, due to the high degree of standardization of computer systems, their transmission capacity is limited, which is another factor that restricts the efficiency of image transmission in traditional simulation systems. Summary of the invention

[0005] 1. Technical issues to be resolved

[0006] The technical problem to be solved by the present invention is that in the field of scene simulation image generation, the computing power required for simulation image generation is increasing, and the requirements for simulation system performance are greatly increased. The traditional parallel computing capability to improve the performance of the simulation system requires a lot of manpower and material costs.

[0007] (II) Technical solution

[0008] In order to solve the above technical problems, the present invention provides a multi-channel simulation image generation system based on FPGA parallel compression, comprising a CPU processing module 1 and an FPGA board module 2;

[0009] The CPU processing module 1 includes a simulation process control component 4, a simulation picture generation module 5, a three-dimensional model generation module 6, and a resource management module 9; the simulation process control component 4 is used to import simulation data 3; the resource management module 9 is used to parse and convert the imported simulation data 3, and load the corresponding target drone three-dimensional model 10 and map information 11 according to the analysis results, and send the target drone three-dimensional model 10 and map information 11 data to the three-dimensional model generation module 6; the three-dimensional model generation module 6 generates a three-dimensional scene according to the received data and renders it to obtain a data matrix of the simulation picture seen by the preset image detection device; the simulation process control component 4 packages the simulation picture data matrix data and the corresponding device interface information and transmits them to the FPGA board module 2;

[0010] The FPGA board module 2 includes a simulation process management component 12, an image compression component 13, and a transmission component 18; the simulation process management component 12 is used to receive a simulation image matrix data file with header file information, and divide the file into header file information and data information segments, the header file information contains the channel coding information that the image needs to be sent; the data information segment enters the image compression component 13, and is used to form a compressed image in a specified format for transmission; the compressed image and the original header file are packaged and enter the transmission component 18, the transmission component 18 first parses the header file, and then performs data packetization 19 according to the TCP / IP protocol, and then transmits it to one or more network communication IP cores 20 specified by the header file; the network communication IP core 20 is used to fill in the protocol header file, generate an electrical signal, and finally output it to the 4 infrared detector processors included in the external system array 22 through the chip pins 21 corresponding to the bound one or more transmission channels.

[0011] Among them, the three-dimensional model generation module 6 includes a geometric vision model 7 and a physical property model 8; the geometric vision model 7 generates a real-time three-dimensional shape of the target and background according to the detector field of view data and target state information; the physical property model 8 gives color information to the target and background through theoretical and empirical models according to the target's infrared parameters and atmospheric environment information.

[0012] The image compression component 13 includes PDCT, quantizer, entropy encoder, and data compression.

[0013] (III) Beneficial effects

[0014] Compared with the prior art, the present invention has the following beneficial effects: a standardized FPGA board is inserted into the computer system host to form a multi-channel simulation image generation system based on FPGA parallel compression. The image compression and multi-channel transmission functions are solidified on the FPGA board, and the CPU computing power is reserved for model calculation and simulation image generation, thereby significantly improving the speed and efficiency of image generation. It can be applied to any application scenario, is fast and simple, does not require hardware development technology background, and greatly saves development costs. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 It is a schematic diagram of the principle of the five-degree-of-freedom laser scanning device of the present invention.

[0016] In the figure: 1-CPU processing module, 2-FPGA board module, 3-simulation data, 4-simulation process control component, 5-simulation image generation module, 6-3D model generation module, 7-geometric scene model, 8-physical property model, 9-resource management module, 10-3D model, 11-map data, 12-simulation process management component, 13-image compression component, 14-PDCT, 15-quantizer, 16-entropy encoder, 17-data compression, 18-transmission component, 19-data packetization, 20-network communication IP core, 21-chip pins, 22-external system array. DETAILED DESCRIPTION

[0017] In order to make the purpose, content, and advantages of the present invention more clear, the specific implementation methods of the present invention are further described in detail below in conjunction with the accompanying drawings and examples.

[0018] See also Figure 1 In the embodiments described below, the multi-channel simulation image generation system based on FPGA parallel compression can generate infrared simulation images in real time and transmit them to the four-way infrared detector processor for image processing to realize dynamic simulation function.

[0019] First, the simulation goal is to realize the infrared scene image of the UAV flying along a certain track against the background of mountains and forests, and transmit it to the four-way infrared detector image processor at a rate of 20Hz to simulate and evaluate its ability to realize specific image processing functions.

[0020] According to the system workflow stages, different stages work simultaneously on different hardware cores through time overlap. The image compression link is selected for the practice of image parallel computing, and the image compression work is implemented by FPGA chips to practice the parallel practice of heterogeneous multi-core systems.

[0021] The system is divided into two parts for computing power: CPU processing module 1 and FPGA board module 2. The CPU processing module 1 is mainly used for 3D model calculation and 2D image rendering; the FPGA board module 2 is responsible for compressing the generated images and transmitting them in multiple channels.

[0022] The CPU processing module 1 imports the simulation data 3 according to the control instructions of the simulation process control component 4, including the target parameter information, environmental factor information, background map resource information and image sending device interface information and other necessary input data of the task to be simulated; the resource management module 9 analyzes and converts the acquired data, and loads the corresponding target drone three-dimensional model 10, map information 11 mountain landforms, etc. according to the analysis results, and sends the data to the three-dimensional model generation module 6, the geometric vision model 7 generates the real-time three-dimensional form of the target and the background according to the detector field of view data, target state and other information, and the physical property model 8 gives the target and the background color information through theoretical and empirical models according to the infrared parameters of the target, atmospheric environment information, etc.; then the simulation picture generation module 6 renders according to the generated three-dimensional scene to obtain the data matrix of the simulation picture seen by the preset image detection device. The simulation process control component 4 packages the simulation picture data matrix data and the corresponding device interface information and transmits them to the FPGA board module 2.

[0023] According to the instruction of the simulation process management component 12, the FPGA board module 2 receives the simulation picture matrix data file with header information, and divides the file into header information and data information segments. The header information contains the channel coding information that the picture needs to be sent. The data information segment enters the image compression component 13, performs PDCT 14 image conversion, quantizer 15 pixel quantization, entropy encoder 16 encoding, data compression 17, and forms a compressed image in a specified format for transmission. The compressed image and the original header file are packaged into the transmission component 18. The transmission component 18 first parses the header file, and then performs data packetization 19 according to the TCP / IP protocol, and then transmits it to one or more network communication IP cores 20 specified by the header file. The network communication IP core 20 is responsible for filling in the protocol header file, generating an electrical signal, and finally outputting it to the 4 infrared detector processors contained in the external system array 22 through the chip pins 21 corresponding to the bound one or more transmission channels. Thus, the transmission of multi-channel simulation images based on FPGA parallel compression is realized.

[0024] If the traditional method is used, it is difficult or requires extremely high computing power configuration to achieve a simulation image generation speed of 80 frames / s. The multi-channel simulation image generation system based on FPGA parallel compression of the present invention can achieve this capability with basic configuration and can expand its use of multi-channel transmission.

[0025] The above is only a preferred embodiment of the present invention. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the technical principles of the present invention. These improvements and modifications should also be regarded as the scope of protection of the present invention.

Claims

1. A multi-channel simulation image generation system based on FPGA parallel compression, characterized in that: It includes a CPU processing module (1) and an FPGA board module (2); The CPU processing module (1) comprises a simulation process control component (4), a simulation picture generation module (5), a three-dimensional model generation module (6), and a resource management module (9); the simulation process control component (4) is used to import simulation data (3); the resource management module (9) is used to parse and convert the imported simulation data (3), and load the corresponding target unmanned aerial vehicle three-dimensional model (10) and map information (11) according to the analysis result, and send the target unmanned aerial vehicle three-dimensional model (10) and map information (11) data to the three-dimensional model generation module (6); the three-dimensional model generation module (6) generates a three-dimensional scene according to the received data and renders it to obtain a data matrix of the simulation picture seen by the preset image detection device; the simulation process control component (4) packages the simulation picture data matrix data and the corresponding device interface information and transmits them to the FPGA board module (2); The FPGA board module (2) includes a simulation process management component (12), an image compression component (13), and a transmission component (18); The simulation process management component (12) is used to receive a simulation picture matrix data file with header file information, and divide the file into header file information and data information segments, wherein the header file information contains channel coding information that the picture needs to be sent; The data information segment enters the image compression component (13) to form a compressed image in a specified format for transmission; the compressed image and the original header file are packaged and enter the transmission component (18), the transmission component (18) first parses the header file, then performs data packetization according to the TCP / IP protocol (19), and then transmits it to one or more network communication IP cores (20) specified by the header file; the network communication IP core (20) is used to fill in the protocol header file, generate an electrical signal, and finally output it to four infrared detector processors included in the external system array (22) through the chip pins (21) corresponding to the bound one or more transmission channels.

2. The multi-channel simulation image generation system based on FPGA parallel compression as claimed in claim 1, characterized in that: The three-dimensional model generation module (6) includes a geometrical scene model (7) and a physical property model (8); the geometrical scene model (7) generates a real-time three-dimensional shape of the target and the background according to the detector field of view data and the target state information; the physical property model (8) assigns color information to the target and the background through theoretical and empirical models according to the infrared parameters of the target and the atmospheric environment information.

3. The multi-channel simulation image generation system based on FPGA parallel compression as claimed in claim 1, characterized in that: The image compression component (13) includes PDCT, quantizer, entropy encoder, and data compression.

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