Gate driving circuit and its driving method, display device

Abstract

This disclosure provides a gate driving circuit and its driving method, as well as a display device, relating to the field of display technology. The gate driving circuit includes multiple cascaded shift register units. Each shift register unit includes a scan input module, a first node, and a first node reset module. The output of a delay circuit is connected to the first node. The delay circuit is configured to output a signal to the first node with the same effective pulse as the first node reset control signal when there is no signal at the reset input terminal. By incorporating a delay circuit in the shift register unit, connected to the first node, this disclosure allows the output of a signal with the same effective pulse as the first node reset control signal to the first node when there is no signal at the reset input terminal. This causes the first node potential to jump to a normal potential, enabling the corresponding shift register unit to operate normally. This improves the performance of the gate driving circuit and enhances the display effect of the display device.

Description

Technical Field

[0001] This disclosure relates to the field of display technology, and in particular to a gate driving circuit and its driving method, and a display device. Background Technology

[0002] With the development of the display field, various industries have increasingly higher requirements for display effects and functions. In some display devices, different display areas have different driving frequencies. Due to the different frequencies of different display areas, some components may not work properly in the boundary area, affecting product performance and display effect.

[0003] Therefore, how to improve the above problems has become one of the urgent technical issues to be addressed at this stage. Summary of the Invention

[0004] To address the aforementioned technical problems, this disclosure provides a gate driving circuit and its driving method, as well as a display device, to improve the performance and display effect of the display panel.

[0005] In a first aspect, this disclosure provides a gate driving circuit, comprising:

[0006] Multiple cascaded shift register units;

[0007] The shift register unit includes a scan input module, a scan input terminal, a first node, a first node reset module, and a reset input terminal;

[0008] The control terminal of the scanning input module is connected to the scanning input terminal, the first terminal is connected to the scanning control signal, and the second terminal is connected to the first node; the scanning input module is used to charge the first node according to the signal from the scanning input terminal; the control terminal of the first node reset module is connected to the reset input terminal, the first terminal is connected to the first node reset control signal, and the second terminal is connected to the first node; the first node reset module is used to reset the first node according to the signal from the reset input terminal.

[0009] At least a portion of the shift register unit includes a delay circuit, the output of which is connected to the first node;

[0010] The delay circuit is configured such that when there is no signal at the reset input terminal, the output terminal of the delay circuit outputs a signal to the first node that is the same as the effective pulse of the reset control signal of the first node.

[0011] In a second aspect, this disclosure provides a driving method for a gate driving circuit, used to drive the gate driving circuit as described above, the driving method including: at least one frame of working time, including a delay circuit start-up phase;

[0012] During the startup phase of the delay circuit, the output terminal of the delay circuit outputs a signal to the first node that is identical to the effective pulse of the first node reset control signal.

[0013] Thirdly, this disclosure provides a display device including the gate driving circuit described above.

[0014] The technical solution provided in this disclosure has the following advantages compared with the prior art:

[0015] This disclosure provides a gate driving circuit and its driving method, as well as a display device. The gate driving circuit includes multiple cascaded shift register units. Each shift register unit includes a scan input module, a scan input terminal, a first node, a first node reset module, and a reset input terminal. The control terminal of the first node reset module is connected to the reset input terminal, a first terminal is connected to a first node reset control signal, and a second terminal is connected to the first node. The first node reset module is used to reset the first node according to the signal from the reset input terminal. At least some of the shift register units include a delay circuit, the output terminal of which is connected to the first node. The delay circuit is configured such that when there is no signal at the reset input terminal, its output terminal outputs a signal to the first node that is identical to the effective pulse of the first node reset control signal. This disclosure provides a delay circuit in the shift register unit, connected to the first node. When there is no signal at the reset input, the delay circuit outputs a signal identical to the effective pulse of the first node's reset control signal to the first node, causing the first node's potential to jump to a normal potential, thus resetting and stabilizing the first node's potential. Devices operating under the first node's potential control can be normally shut down, and the corresponding shift register unit can operate normally. This helps to improve the characteristic drift phenomenon of the shift register unit, thereby stabilizing the performance of each stage of the shift register unit in the gate drive circuit, improving the performance of the gate drive circuit, and enhancing the display effect of the display device. Attached Figure Description

[0016] The accompanying drawings, which are incorporated in and form a part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure.

[0017] To more clearly illustrate the technical solutions in the embodiments of this disclosure or the prior art, the accompanying drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, for those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0018] Figure 1 The diagram shown is a schematic of a display device in the prior art;

[0019] Figure 2The diagram shown is a schematic representation of a display device provided in an embodiment of this disclosure;

[0020] Figure 3 The diagram shown is a schematic representation of a shift register unit provided in an embodiment of this disclosure.

[0021] Figure 4 The diagram shown is a schematic representation of a delay circuit provided in an embodiment of this disclosure.

[0022] Figure 5 The diagram shown is a schematic diagram of a delay circuit provided in an embodiment of this disclosure;

[0023] Figure 6 As shown Figure 5 The timing diagram of the provided delay circuit;

[0024] Figure 7 The diagram shown is a schematic diagram of a shift register unit provided in an embodiment of this disclosure;

[0025] Figure 8 As shown Figure 7 A timing diagram of a shift register unit in a computer. Detailed Implementation

[0026] To better understand the above-mentioned objectives, features, and advantages of this disclosure, the solutions disclosed herein will be further described below. It should be noted that, unless otherwise specified, the embodiments and features described herein can be combined with each other.

[0027] Numerous specific details are set forth in the following description in order to provide a full understanding of this disclosure, but this disclosure may also be implemented in other ways different from those described herein; obviously, the embodiments in the specification are only some, and not all, of the embodiments of this disclosure.

[0028] The inventors discovered during their research that in some display devices, different display areas have different driving frequencies. For example, Figure 1 The diagram shown is a schematic of a display device in the prior art. Please refer to it. Figure 1The display device 000 includes a first display area AA1' and a second display area AA2'. The first display area AA1' plays video and is driven at a high frequency. The second display area AA2' plays static images without video and is driven at a low frequency to save power. The gate driving circuit of the display device 000 scans the pixels in the display device 000 along the first direction D1'. The driving frequency of the first display area AA1' is greater than the driving frequency of the second display area AA2'. In the boundary area between the first display area AA1' and the second display area AA2', some devices in the gate driving circuit do not receive the shutdown signal, which causes the voltage of some devices to be out of control, resulting in an increase in temperature and thus characteristic drift, affecting the performance and display effect of the display device 000.

[0029] Therefore, how to improve the above problems has become one of the urgent technical issues to be addressed at this stage.

[0030] To address the aforementioned technical problems, this disclosure provides a gate driving circuit and its driving method, as well as a display device, to improve the performance and display effect of the display panel.

[0031] Figure 2 The diagram shown is a schematic representation of a display device provided in an embodiment of this disclosure. Figure 3 The diagram shown is a schematic representation of a shift register unit provided in an embodiment of this disclosure. Please refer to the provided text. Figure 2 and Figure 3 This disclosure provides a gate driving circuit 200, including: multiple cascaded shift register units 210; each shift register unit 210 includes a scan input module 211, a scan input terminal Gn-1, a first node P, a first node reset module 212, and a reset input terminal Gn+1; the control terminal of the scan input module 211 is connected to the scan input terminal Gn-1, the first terminal is connected to the scan control signal FW, and the second terminal is connected to the first node P; the scan input module 211 is used to charge the first node P according to the signal from the scan input terminal Gn-1; the control terminal of the first node reset module 212 is connected to the scan input terminal Gn+1. The first node reset module 212 is used to reset the first node P according to the signal from the reset input terminal Gn+1. The at least part of the shift register unit 210 includes a delay circuit 213, the output of which is connected to the first node P. The delay circuit 213 is configured such that when there is no signal at the reset input terminal Gn+1, the output of the delay circuit 213 outputs a signal to the first node P that is the same as the effective pulse of the first node reset control signal BW.

[0032] Specifically, this disclosure provides a gate driving circuit 200, which includes multiple shift register units 210 cascaded together. Each shift register unit 210 includes a scan input module 211, a first node P, and a first node reset module 212. The scan input module 211 is connected to a scan input terminal Gn-1, a scan control signal FW, and the first node P. Under the control of the scan input terminal Gn-1, the scan input module 211 transmits the scan control signal FW to the first node P. The scan input terminal Gn-1 of the first-stage shift register unit is provided by other driving signals (e.g., a start signal STV). The scan input terminals Gn-1 of other stages of shift register units (excluding the first stage) are connected to the output signals of the previous stage shift register unit 210. The first node reset module 212 is connected to the reset input terminal Gn+1, the first node reset control signal BW, and the first node P. Under the control of the reset input terminal Gn+1, the first node reset module 212 transmits the first node reset control signal BW to the first node P. The reset input terminal Gn+1 is connected to the output signal of the next-level shift register unit 210.

[0033] It should be noted that the scan control signal FW and the first node reset control signal BW control the scanning direction of the gate drive circuit 200. The scanning direction includes forward scanning and reverse scanning. For example, the gate drive circuit 200 includes n levels of gate drive units (n≥2, and n is an integer). Forward scanning involves turning on each level sequentially from the 1st level to the nth level; reverse scanning involves turning on each level sequentially from the nth level to the 1st level. Optionally, during forward scanning, the scan control signal FW is connected to a high-level signal, and the first node reset control signal BW is connected to a low-level signal; during reverse scanning, the scan control signal FW is connected to a low-level signal, and the first node reset control signal BW is connected to a high-level signal. This disclosure is only illustrated by example and is not limited thereto.

[0034] The inventors discovered during their research that when the driving frequencies of two adjacent cascaded shift register units 210 are the same, the devices in the shift register unit 210 can operate normally. However, when the driving frequencies of two adjacent cascaded shift register units 210 are different, the control terminal of the first node reset module 212 may fail to receive a valid signal, i.e., there is no signal input at the reset input terminal Gn+1. Consequently, the first node reset module 212 cannot be shut down, resulting in the first node P voltage failing to reset and becoming unstable, thus causing characteristic drift of the shift register unit 210. It should be noted that characteristic drift of the shift register unit 210 refers to the phenomenon where the performance parameters of the shift register unit 210 deviate from their initial design values.

[0035] The drift of the shift register unit 210 characteristics can affect the performance and display effect of the display device 100. Therefore, this disclosure provides a delay circuit 213 in the shift register unit 210. The delay circuit 213 is connected to the first node P and is also connected to the reset input terminal Gn+1. When there is no signal at the reset input terminal Gn+1, it outputs a signal with the same effective pulse as the first node reset control signal BW to the first node P, causing the potential of the first node P to jump to the normal potential, resetting the first node P, stabilizing the potential of the first node P, and enabling the device operating under the potential control of the first node P to shut down normally. The corresponding shift register unit 210 can work normally, which helps to improve the characteristic drift phenomenon of the shift register unit 210, thereby stabilizing the performance of each stage of the shift register unit 210 in the gate drive circuit, which helps to improve the performance of the gate drive circuit 200, and improves the display effect of the display device 100.

[0036] Please refer to Figure 2 and Figure 3 In one optional embodiment of this disclosure, the display device 100 includes a first display area AA1 and a second display area AA2. The display device 100 scans along a first direction D1. The frequency of the first display area AA1 is greater than the frequency of the second display area AA2. In the boundary region between the first display area AA1 and the second display area AA2, when there is no signal at the reset input terminal Gn+1, the first node reset module 212 cannot reset the potential of the first node P. The delay circuit 213 provided in this disclosure outputs a signal with the same effective pulse as the first node reset control signal BW to the first node P when there is no signal at the reset input terminal Gn+1, causing the potential of the first node P to jump to a normal potential. The corresponding shift register unit 210 can then work normally, thereby improving the performance of the gate drive circuit 200 and improving the display effect of the display device 100.

[0037] Please continue to refer to this. Figure 2 and Figure 3 In another optional embodiment of this disclosure, the display device 100 scans along the second direction D2, the frequency of the first display area AA1 is greater than the frequency of the second display area AA2, and in the boundary area between the first display area AA1 and the second display area AA2, the reset input terminal Gn+1 signal of the shift register unit 210 is normal, and the delay circuit 213 has no output.

[0038] Figure 4 The diagram shown is a schematic representation of a delay circuit according to an embodiment of this disclosure. Please refer to it. Figures 2-4Optionally, the delay circuit 213 includes a working control module 2131, a charging control module 2132, a delay module 2133, a delay pull-down control module 2134, a delay pull-down module 2135, a delay reset module 2136, a first delay node Y1, and a second delay node Y2; the control terminal of the working control module 2131 is connected to the reset input terminal Gn+1, the first terminal is connected to the first level signal VGL, and the second terminal is connected to the first delay node Y1; the control terminal of the charging control module 2132 is connected to the scan input terminal Gn-1, the first terminal is connected to the second level signal VGH, the second terminal is connected to the first terminal of the delay module 2133, and the second terminal of the delay module 2133 is connected to the first delay node Y1; the delay pull-down control module 2134 includes The first submodule 21341 and the second submodule 21342 are as follows: the control terminal of the first submodule 21341 is connected to the first delay node Y1, the first terminal is connected to the second level signal VGH, and the second terminal is connected to the second delay node Y2; the control terminal of the second submodule 21342 is connected to the second level signal VGH, the first terminal is connected to the first level signal VGL, and the second terminal is connected to the second delay node Y2; the control terminal of the delay pull-down module 2135 is connected to the second delay node Y2, the first terminal is connected to the first level signal VGL, and the second terminal is connected to the output terminal Pout of the delay circuit 213; the control terminal of the delay reset module 2136 is connected to the delay reset control signal RST, the first terminal is connected to the first level signal VGL, and the second terminal is connected to the first delay node Y1.

[0039] Specifically, this disclosure provides a gate driving circuit 200, which includes multiple cascaded shift register units 210, at least some of which include a delay circuit 213. In the delay circuit 213, a working control module 2131 transmits a first-level signal VGL to a first delay node Y1 based on the signal from the reset input terminal Gn+1. The signal from the first delay node Y1 determines whether a valid signal is output to the output terminal Pout. Therefore, the working control module 2131 is the module that actually determines whether the delay circuit 213 functions. A charging control module 2132, under the control of the scan input terminal Gn-1, transmits a second-level signal VGH to the delay module 2133. When the charging control module 2132 is turned on, the second-level signal VGH is transmitted to the delay module 2133 to charge it. The delay pull-down control module 2134 includes a first submodule 21341 and a second submodule 21342. Under the control of the first delay node Y1, the first submodule 21341 transmits the second level signal VGH to the second delay node Y2; the second submodule 21342, under the control of the second level signal VGH, transmits the first level signal VGL to the second delay node Y1. The first submodule 21341 and the second submodule 21342 mutually control the signal of the second delay node Y1. The second delay node Y2 controls the conduction and deactivation of the delay pull-down module 2135. The delay pull-down module 2135 is in the deactivated state by default. Therefore, the second submodule 21342 is in the normally open state and transmits the signal controlling the deactivated delay pull-down module 2135 to the second delay node Y2. When the first submodule 21341 is activated, it transmits the signal controlling the activated delay pull-down module 2135 to the second delay node Y2. The delay reset module 2136 is used to transmit the first level signal VGL to the first delay node Y1 under the control of the delay reset control signal RST, so as to reset the delay circuit 213.

[0040] Optionally, the first level signal VGL can be a low level signal, and the second level signal VGH can be a high level signal. It should be noted that this disclosure is only for illustrative purposes and is not intended to be limiting.

[0041] Figure 5 The diagram shown is a schematic of a delay circuit provided in an embodiment of this disclosure. (Refer to...) Figures 2-5Furthermore, this disclosure provides an optional implementation in which the working control module 2131 includes a working control transistor Ma, the gate of which is connected to the reset input terminal Gn+1, the first terminal of which is connected to the first level signal VGL, and the second terminal of which is connected to the first delay node Y1; the charging control module 2132 includes a charging control transistor Mb, the gate of which is connected to the scan input terminal Gn-1, the first terminal of which is connected to the second level signal VGH, and the second terminal of which is connected to the delay module 2133; the delay module 2133 includes a first capacitor C1 and a first resistor R1, the first plate of which is connected to the second terminal of the charging control transistor Mb, and the second plate of which is connected to the first delay node Y1; the first plate of the first resistor R1 is connected to the first capacitor C1. The first electrode plate and the second electrode plate are connected to the second electrode plate of the first capacitor C1; the delay pull-down control module 2134 includes a first delay pull-down control transistor Mc and a second delay pull-down control transistor Md. The gate of the first delay pull-down control transistor Mc is connected to the first delay node Y1, the first electrode is connected to the second level signal VGH, and the second electrode is connected to the second delay node Y2; the gate of the second delay pull-down control transistor Md is connected to the second level signal VGH, the first electrode is connected to the first level signal VGL, and the second electrode is connected to the second delay node Y2; the delay pull-down module 2135 includes a delay pull-down transistor Me. The gate of the delay pull-down transistor Me is connected to the second delay node Y2, the first electrode is connected to the first level signal VGL, and the second electrode is connected to the output terminal Pout of the delay circuit 213.

[0042] Specifically, this embodiment provides a more specific implementation of the delay circuit 213. The working control module 2131 includes a working control transistor Ma, the charging control module 2132 includes a charging control transistor Mb, the delay module 2133 includes a first capacitor C1 and a first resistor R1, the delay pull-down control module 2134 includes a first delay pull-down control transistor Mc and a second delay pull-down control transistor Md, the delay pull-down module 2135 includes a delay pull-down transistor Me, and the delay reset module 2136 includes a delay reset transistor Mf. Under the control of the reset input terminal Gn+1, the working control transistor Ma transmits the first level signal VGL to the first delay node Y1. Under the control of the scan input terminal Gn-1, the charging control transistor Mb charges the delay module 2133. Under the control of the first delay node Y1, the first delay pull-down control transistor Mc transmits the second level signal VGH to the second delay node Y2. Under the control of the second level signal VGH, the second delay pull-down control transistor Md transmits the first level signal VGL to the second delay node Y2. Under the control of the potential of the second delay node Y2, the delay pull-down transistor Me transmits the first level signal VGL to the output terminal Pout of the delay circuit 213.

[0043] It should be noted that this disclosure uses N-type transistors in the delay circuit 213 as an example for illustration, but it is not limited thereto. In some other embodiments of this disclosure, at least one transistor in the delay circuit 213 may also be a P-type transistor. Figure 6 As shown Figure 5 Please refer to the timing diagram of the provided delay circuit. Figure 5 and Figure 6 This disclosure is aimed at Figure 5 The delay circuit in and Figure 6 The timing diagram illustrates the working principle and timing of the delay circuit 213. Specifically, the working periods of the delay circuit 213 include a first period S1, a second period S2, and a third period S3. In the first period S1, the reset input terminal Gn+1 signal is output normally, and the reset output terminal Gn+1 corresponding to each stage shift register unit 211 can receive a valid signal. The gate of the working control transistor Ma can continuously receive a high-level signal, the working control transistor Ma is turned on, and the delay circuit 213 has no effect. Figure 6 Within the timing range shown, after the first time period S1, the reset input terminal Gn+1 has no valid signal. In the second time period S2, the scan input terminal Gn-1 outputs a high-level signal, the gate of the charging control transistor Mb receives the high-level signal, and the charging control transistor Mb turns on, charging the first capacitor C1. In the third time period S3, the scan input terminal Gn-1 outputs a low-level signal, the reset input terminal Gn+1 has no valid signal, the first capacitor C1 discharges, the first delayed pull-down control transistor Mc turns on, the second level signal VGH is transmitted to the gate of the delayed pull-down transistor Me, the delayed pull-down transistor Me turns on, and the first level signal VGL is transmitted to the output terminal of the delay circuit 213 through the delayed pull-down transistor.

[0044] It should be noted that the delay circuit 213 provided in the above embodiment pulls the first node P potential low at the corresponding time when there is no input to the reset input terminal Gn+1 signal, which is beneficial to the normal operation of the gate drive circuit 200 and improves the performance and display effect of the display device 100.

[0045] Please refer to Figure 6 Optionally, the aspect ratio of the working control transistor Ma is Ra, and the aspect ratio of the first delay pull-down control transistor Mc is Rc, where Ra ≥ 2Rc.

[0046] Specifically, the working control transistor Ma is the transistor that first determines whether the delay circuit 213 outputs a valid signal. The gate of the working control transistor Ma is connected to the reset input terminal Gn+1, the first terminal is connected to the first level signal VGL, and the second terminal is connected to the first delay node Y1. Under the control of the voltage at the first delay node Y1, the gate of the first delay pull-down control transistor Mc controls whether the delay pull-down transistor Ma outputs a valid signal to the output terminal Pout. Therefore, the working control transistor Ma is an important transistor that controls whether the entire delay circuit 213 works. When the reset input terminal Gn+1 signal is normal, the working control transistor Ma is turned on and outputs the first level signal VGL to the first delay node Y1. The first level signal VGL controls the first delay pull-down transistor Mc to be turned off. At this time, the delay circuit 213 does not work. Therefore, in order not to affect the normal operation of the shift register unit 210, this disclosure sets the width-to-length ratio Ra of the working control transistor Ma to be greater than or equal to twice the width-to-length ratio Rc of the first delay pull-down control transistor Mc. Thus, the voltage required for the working control transistor Ma to conduct is smaller. When the reset input Gn+1 signal is normal, the working control transistor Ma can conduct, and the delay circuit 213 does not need to operate. This helps to avoid the first delay pull-down control transistor Mc from being mis-conducted, thereby ensuring the normal operation of the shift register unit 210 and improving the reliability of the display device 100. This disclosure provides an optional implementation where Ra = 2Rc; another optional implementation where Ra = 2.5Rc; and yet another optional implementation where Ra = 3Rc.

[0047] It's important to note that the width-to-length ratio (W / L) of a transistor refers to the ratio of its channel width (W) to its channel length (L). A larger W / L ratio results in a wider channel, allowing for a larger current flow at the same gate voltage. This translates to stronger current-driving capability, leading to faster switching speeds and higher signal transmission efficiency. The W / L ratio also affects the transistor's threshold voltage. A larger W / L ratio results in a more uniform electric field distribution between the source and drain, making it easier for electrons to be injected into the channel from the source, thus requiring a lower voltage to turn the transistor on.

[0048] Please continue to refer to this. Figure 6 Optionally, the width-to-length ratio of the first delayed pull-down control transistor Mc is Rc, and the width-to-length ratio of the second delayed pull-down control transistor Md is Rd, where Rc ≥ 2Rd.

[0049] Specifically, the delay pull-down control module 2134 includes a first delay pull-down control transistor Mc and a second delay pull-down control transistor Md. The first delay pull-down control transistor Mc is used to transmit a signal to the second delay node Y2 to turn on the delay pull-down transistor Me, and the second delay pull-down transistor Md is used to transmit a signal to the second delay node Y2 to turn off the delay pull-down transistor Me. To ensure the proper conduction of the delayed pull-down transistor Me, the width-to-length ratio Rc of the first delayed pull-down control transistor Mc is set to be less than or equal to twice the width-to-length ratio Rd of the second delayed pull-down control transistor Md. This results in a lower on-state voltage of the first delayed pull-down control transistor Mc than that of the second delayed pull-down control transistor Md, leading to higher signal transmission efficiency of the first delayed pull-down control transistor Mc. This facilitates adjusting the potential of the second delay node Y2 to a level sufficient to conduct the delayed pull-down transistor Me, better ensuring the function of the delay circuit 213. Furthermore, it helps to improve the characteristic drift of the shift register unit 210, thereby improving the performance and display effect of the display device 100. This disclosure provides an optional embodiment where Rc = 2Rd; another optional embodiment where Rc = 3Rd; and yet another optional embodiment where Rc = 3.2Rd.

[0050] Please refer to Figure 2 and Figure 3 In one optional embodiment of this disclosure, each shift register unit 210 includes a delay circuit 213.

[0051] Specifically, this disclosure provides a scenario where the delay circuit 213 is used in a transitional phase where, during the process of the gate drive circuit 200 providing signals to the shift register unit 210, the drive signal switches from high frequency to low frequency. In the transition region, the reset input terminal Gn+1 of some shift register units 210 will have no signal. The delay circuit 213 is used to output a signal to the first node P that is the same as the effective pulse of the first node reset control signal BW when there is no signal at the reset input terminal Gn+1. In this embodiment, a delay circuit 213 is provided in each shift register unit 210, so that the switching from high frequency to low frequency can be realized at any location of the display device 100, and is not limited to a certain area.

[0052] Figure 7 The diagram shown is a schematic representation of a shift register unit provided in an embodiment of this disclosure. Please refer to it. Figure 2 , Figure 3 and Figure 7Optionally, the shift register unit 210 further includes a scan output module 30, a pull-down module 40, a pull-down control module 50, a pull-up module 60, and a second node Q; the control terminal of the scan output module 30 is connected to the first node P, the first terminal is connected to the first clock signal CK, and the second terminal is connected to the scan output terminal Gout; the scan output module 30 is used to transmit the first clock signal CK to the scan output terminal Gout according to the potential of the first node P; the pull-down module 40 is connected to the first node P, the second node Q, the first level signal VGL, and the scan output terminal Gout respectively; the pull-down module 40 is used to transmit the first level signal VGL to the first node P and the scan output terminal Gout according to the potential of the second node Q; the pull-down control module 50 is connected to the second node Q and the second level signal VGH respectively; the pull-down control module 50 is used to transmit the second level signal VGH to the second node Q; the pull-up module 60 is connected to the first node P, the second node Q, the first level signal VGL, and the pull-down control module 50 respectively, and is used to transmit the first level signal VGL to the second node Q.

[0053] Specifically, the shift register unit 210 includes a scan input module 211, a scan output module 30, a first node P, a first node reset module 212, a pull-down module 40, a pull-down control module 50, a pull-up module 60, and a second node Q. The scan input module 211 is electrically connected to the scan input terminal Gn-1, the scan control signal FW, and the first node P, and is used to charge the first node P according to the signal from the scan input terminal Gn-1. The scan output terminal Gout is electrically connected to the first node P, the first clock signal CK, and the scan output terminal Gout, and is used to control the output of the first clock signal CK to the scan output terminal Gout according to the potential of the first node P. The pull-down module 40 is electrically connected to the first node P, the second node Q, the first level signal VGL, and the scan output terminal Gout, and is used to control the transmission of the first level signal VGL to the first node P and the scan output terminal Gout according to the potential of the second node Q. The pull-down control module 50 is electrically connected to the second node Q and the second level signal VGH, and is used to control the transmission of the second level signal VGH to the second node Q. The pull-up module 60 is connected to the first node P, the second node Q, the first level signal VGL, and the pull-down control module 50, respectively, and is used to transmit the first level signal VGL to the second node Q.

[0054] When the input signal received by the scan input terminal Gn-1 is an enable signal that enables the scan input module 211 to conduct, the scan input module 211 charges the first node P according to the scan control signal FW. This allows the potential of the first node P to control the conduction of the scan output module 30, enabling the scan output module 30 to transmit the first clock signal CK to the scan output terminal Gout. When the first clock signal CK is at an enable level, the scan signal output by the scan output terminal Gout is at an enable level; when the first clock signal CK is at a disable level, the scan signal output by the scan output terminal Gout is at a disable level. When the first node P controls the scan output module 30 to conduct, it also controls the pull-up module 60 to conduct, causing the pull-up module 60 to transmit the first level signal VGL to the second node Q. The disable level of the second node Q will control the pull-down module 40 to close, so the first level signal VGL will not be transmitted to the first node P through the pull-down module 40, thus not affecting the scan output signal output by the scan output module 30. When it is necessary to discharge the first node P, the pull-down control module 50 transmits the second-level signal VGH to the second node Q, so that the potential of the second node Q can control the pull-down module 40 to conduct. The pull-down module 40 then transmits the first-level signal VGL to the first node P, thereby discharging the first node P. The shift register unit 210 also includes a first node reset module 212. The control terminal of the first node reset module 212 is connected to the reset input terminal Gn+1. The reset input terminal Gn+1 is connected to the scan output terminal Gout of the next-level shift register unit 210. When the next-level shift register unit 210 outputs an enable signal, the first node P is reset, thereby stabilizing the potential of the first node P.

[0055] In some cases, when the reset input Gn+1 fails to output a signal normally, the potential of the first node P becomes unstable, causing the shift register unit 210 to drift and affecting the performance and display effect of the display device 100. Therefore, this disclosure provides a delay circuit 213 that outputs a signal identical to the effective pulse of the first node reset control signal BW to the first node P when there is no signal at the reset input Gn+1, causing the potential of the first node P to jump to a normal potential. This allows the corresponding shift register unit 210 to work normally, thereby improving the performance of the gate drive circuit 200 and the display effect of the display device 100.

[0056] Please continue to refer to this. Figure 2 , Figure 3 and Figure 7This disclosure provides an optional implementation in which the scan input module 211 includes a first transistor M1, the gate of which is connected to the scan input terminal Gn-1, the first electrode of which is connected to the scan control signal FW, and the second electrode of which is connected to the first node P; the first node reset module 212 includes a second transistor M2, the gate of which is connected to the reset input terminal Gn+1, the first electrode of which is connected to the reset control signal BW, and the second electrode of which is connected to the first node P; the scan output terminal Gout includes a third transistor M3 and a storage capacitor Cst, the gate of which is connected to the first node P, the first electrode of which is connected to the first clock signal CK, and the second electrode of which is connected to the scan output terminal Gout; the storage capacitor Cst is connected between the gate and the second electrode of the third transistor M3; the pull-down module 40 includes a fourth transistor M4 and a fifth transistor M5, the gate of which is connected to the second node P. Q, the first terminal is connected to the first level signal VGL, and the second terminal is connected to the first node P; the gate of the fifth transistor M5 is connected to the second node Q, the first terminal is connected to the first level signal VGL, and the second terminal is connected to the scan output terminal Gout; the pull-down control module 50 includes the sixth transistor M6 and the seventh transistor M7, the gate and the first terminal of the sixth transistor M6 are connected to the second level signal VGH, the second terminal is connected to the gate of the seventh transistor M7, the first terminal of the seventh transistor M7 is connected to the second level signal VGH, and the second terminal is connected to the second node Q; the pull-up module 60 includes the eighth transistor M8 and the ninth transistor M9, the gate of the eighth transistor M8 is connected to the first node P, the first terminal is connected to the first level signal VGL, and the second terminal is connected to the second node Q; the gate of the ninth transistor M9 is connected to the first node P, the first terminal is connected to the first level signal VGL, and the second terminal is connected to the pull-down control module 50.

[0057] Specifically, this embodiment further refines the structure of the shift register unit 210, such as... Figure 7 As shown, the scan input module 211 includes a first transistor M1, the first node reset module 212 includes a second transistor M2, the scan output terminal Gout includes a third transistor M3 and a storage capacitor Cst, the pull-down module 40 includes a fourth transistor M4 and a fifth transistor M5, the pull-down control module 50 includes a sixth transistor M6 and a seventh transistor M7, and the pull-up module 60 includes an eighth transistor M8 and a ninth transistor M9. It should be noted that this embodiment is only described using the example of N-type transistors in the shift register unit 210, and is not intended to be limiting. Figure 8 As shown Figure 7 For a timing diagram of the shift register unit in the image, please refer to [reference needed]. Figure 7 and combined Figure 8 The operation of the shift register unit 210 is as follows:

[0058] In stage t1, the scan signal received by the scan input terminal Gn-1 from the scan output terminal Gout of the previous stage shift register unit 210 is at a high level, which turns on the first transistor M1. The high level of the scan control signal FW is transmitted to the first node P, making the first node P high. The eighth transistor M8 and the ninth transistor M9 are turned on. The first level signal VGL is transmitted to the second node Q via the eighth transistor M8 and to the gate of the seventh transistor M7 via the ninth transistor M9. The seventh transistor M7, the fourth transistor M4 and the fifth transistor M5 are turned off. The third transistor M3 is turned on. The signal of the first clock signal CK is at a low level. The first clock signal CK is transmitted to the scan output terminal Gout, which makes the scan output terminal Gout output a low level scan signal.

[0059] In stage t2, the scan signal received by the scan input terminal Gn-1 from the scan output terminal Gout of the previous stage scan shift register 210 is at a low level, and the first clock signal CK is at a high level. Since there is no low-level signal input, the first node P remains at a high level as in stage t1. The third transistor M3, the eighth transistor M8, and the ninth transistor M9 remain in the conducting state. Under the control of the eighth transistor M8, the first level signal VGL is input to the second node Q, and the second node Q is at a low level. Since the first clock signal CK is at a high level, this high-level first clock signal CK is transmitted to the scan output terminal Gout through the third transistor M3, causing the scan output terminal Gout to output a high-level scan signal. Due to the bootstrap effect of the storage capacitor Cst, the potential of the first node P further increases.

[0060] In stage t3, the scan signal received by the reset input Gn+1 from the scan output Gout of the next-stage scan shift register 210 is at a high level, the first clock signal CK is at a low level, the second transistor M2 is turned on, the low level of the first node reset control signal BW is written to the first node P, making the first node P low level, the third transistor M3, the eighth transistor M8 and the ninth transistor M9 are turned off, and the seventh transistor M7 is turned on under the control of the second level signal VGH transmitted by the sixth transistor M6, so that the second level signal VGH is transmitted to the second node Q through the seventh transistor M7, thereby controlling the fourth transistor M4 and the fifth transistor M5 to turn on, so that the first level signal VGL is transmitted to the first node P and the scan output Gout, and the scan output Gout stably outputs a low level scan signal.

[0061] After stage t3, since the scan control signal FW is always high, and the first node P and the scan output terminal Gout have been discharged through the second transistor M2 in stage t2, the eighth transistor M8 is in the off state at this time, so the second node Q will not be discharged, which enables the scan output terminal Gout to stably output a low-level scan signal until the non-scanning stage of the scan cycle is entered.

[0062] In stage t3, if the reset input terminal Gn+1 fails to receive the first node reset control signal BW, the potential of the first node P will not decrease. As a result, at the start of the scanning phase of the next scanning cycle, the potential of the first node P will no longer be its initial potential, but a drifted potential. This causes the initial potential when charging the first node P to become a drifted potential. Under the premise of a fixed charging time, if charging starts with the drifted potential of the first node P, the potential of the first node P after charging will be different from the initial potential that the first node P should have been at. In severe cases, this will cause the potential control scanning output module 30 of the first node P to be turned on prematurely, thereby making the scanning signal output by its scanning output terminal Gout inaccurate.

[0063] Therefore, this disclosure sets up a delay circuit 213, which outputs a signal with the same effective pulse as the first node reset control signal BW to the first node P when there is no signal at the reset input terminal Gn+1, so that the potential of the first node P jumps to the normal potential, and the corresponding shift register unit 210 can work normally, thereby improving the performance of the gate drive circuit 200 and improving the display effect of the display device 100.

[0064] Alternatively, please continue to refer to Figure 7 The shift register unit 210 also includes a tenth transistor M10 and an eleventh transistor M11; the gate of the tenth transistor M10 is connected to the reset signal terminal RESET, the first terminal is connected to the first level signal VGL, and the second terminal is connected to the first node P; the gate of the eleventh transistor M11 is connected to the turn-off signal terminal Goff, the first terminal is connected to the first level signal VGL, and the second terminal is connected to the scan output terminal Gout.

[0065] Specifically, the shift register unit 210 also includes a tenth transistor M10 and an eleventh transistor M11. Under the control of the RESET signal terminal, the tenth transistor M10 transmits the first level signal VGL to the first node P; under the control of the Goff signal terminal, the eleventh transistor M11 transmits the first level signal VGL to the scan output terminal Gout. Thus, the RESET signal terminal and the Goff signal terminal can be at a high level before or after the enable level of the scan signal output by each level of the scan shift register unit 210, causing the tenth transistor M10 and the eleventh transistor M11 to conduct, controlling the first node P and the scan output terminal Gout to remain at a low level, thereby preventing other signal interference from affecting the output signal of the scan output terminal Gout, which helps to improve the reliability and display effect of the display device.

[0066] Please refer to Figure 2 and Figure 3 Based on the same inventive concept, this disclosure provides a driving method for a gate driving circuit, used to drive any of the gate driving circuits 200 provided in the embodiments of this disclosure. The driving method includes: at least one frame of working time, including a delay circuit start-up phase, during the delay circuit start-up phase, the output terminal of the delay circuit 213 outputs a signal with the same effective pulse as the first node reset control signal BW to the first node P.

[0067] Specifically, this disclosure provides a driving method for a gate driving circuit, which includes a delay circuit startup phase during at least one frame of operation. During the delay circuit startup phase, when there is no signal at the reset input terminal Gn+1, a signal identical to the effective pulse of the first node reset control signal BW is output to the first node P, causing the potential of the first node P to jump to the normal potential. The corresponding shift register unit 210 can then work normally, thereby improving the performance of the gate driving circuit 200 and the display effect of the display device 100.

[0068] Please refer to Figure 2 This disclosure provides an optional implementation in which a scanning phase is included within one frame of working time; during the scanning phase, the scanning output terminals of each shift register unit 210 sequentially output enable signals for the scanning signals.

[0069] It should be noted that the scanning principle and timing of the shift register unit 210 are described in the embodiments of the gate drive circuit provided in this disclosure, and will not be repeated here.

[0070] Please continue to refer to this. Figure 2 Based on the same inventive concept, this disclosure also provides a display device 100, including any of the gate driving circuits 200 in the embodiments of this disclosure.

[0071] It should be noted that the embodiments of the display device 100 provided in this disclosure can be referred to the embodiments of the gate driving circuit 200 provided in this disclosure, which will be repeated without further description. The display device 100 provided in this disclosure can be any product and component with display function, such as a mobile phone, tablet computer, television, touch screen, laptop computer, or navigator.

[0072] As can be seen from the above embodiments, the gate driving circuit and driving method and display device provided in this disclosure achieve at least the following beneficial effects:

[0073] This disclosure provides a gate driving circuit and its driving method, as well as a display device. The gate driving circuit includes multiple cascaded shift register units. Each shift register unit includes a scan input module, a scan input terminal, a first node, a first node reset module, and a reset input terminal. The control terminal of the first node reset module is connected to the reset input terminal, a first terminal is connected to a first node reset control signal, and a second terminal is connected to the first node. The first node reset module is used to reset the first node according to the signal from the reset input terminal. At least some of the shift register units include a delay circuit, the output terminal of which is connected to the first node. The delay circuit is configured such that when there is no signal at the reset input terminal, its output terminal outputs a signal to the first node that is identical to the effective pulse of the first node reset control signal. This disclosure provides a delay circuit in the shift register unit, connected to the first node. When there is no signal at the reset input, the delay circuit outputs a signal identical to the effective pulse of the first node's reset control signal to the first node, causing the first node's potential to jump to a normal potential, thus resetting and stabilizing the first node's potential. Devices operating under the first node's potential control can be normally shut down, and the corresponding shift register unit can operate normally. This helps to improve the characteristic drift phenomenon of the shift register unit, thereby stabilizing the performance of each stage of the shift register unit in the gate drive circuit, improving the performance of the gate drive circuit, and enhancing the display effect of the display device.

[0074] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0075] The above description is merely a specific embodiment of this disclosure, enabling those skilled in the art to understand or implement it. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of this disclosure. Therefore, this disclosure is not to be limited to the embodiments described herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A gate drive circuit characterized by comprising: The application relates to a shift register unit, comprising: a plurality of cascaded shift register units; the shift register unit comprises a scan input module, a scan input end, a first node, a first node reset module and a reset input end; the control end of the scan input module is connected with the scan input end, the first end is connected with a scan control signal, and the second end is connected with the first node; the scan input module is used for charging the first node according to the signal of the scan input end; the control end of the first node reset module is connected with the reset input end, the first end is connected with a first node reset control signal, and the second end is connected with the first node; the first node reset module is used for resetting the first node according to the signal of the reset input end; at least part of the shift register units comprises a delay circuit, and the output end of the delay circuit is connected with the first node; the delay circuit is configured to output the same signal as the effective pulse of the first node reset control signal to the first node when the reset input end has no signal; the delay circuit comprises a working control module, a charging control module, a delay module, a delay pull-down control module, a delay pull-down module, a delay reset module, a first delay node and a second delay node; the control end of the working control module is connected with the reset input end, the first end is connected with a first level signal, and the second end is connected with the first delay node; the control end of the charging control module is connected with the scan input end, the first end is connected with a second level signal, and the second end is connected with the first end of the delay module; the second end of the delay module is connected with the first delay node; the delay pull-down control module comprises a first submodule and a second submodule; the control end of the first submodule is connected with the first delay node, the first end is connected with the second level signal, and the second end is connected with the second delay node; the control end of the second submodule is connected with the second level signal, the first end is connected with the first level signal, and the second end is connected with the second delay node; the control end of the delay pull-down module is connected with the second delay node, the first end is connected with the first level signal, and the second end is connected with the output end of the delay circuit; the control end of the delay reset module is connected with a delay reset control signal, the first end is connected with the first level signal, and the second end is connected with the first delay node.

2. The gate drive circuit according to claim 1, characterized by the working control module comprises a working control transistor; the gate of the working control transistor is connected with the reset input end, the first pole is connected with the first level signal, and the second pole is connected with the first delay node; the charging control module comprises a charging control transistor; the gate of the charging control transistor is connected with the scan input end, the first pole is connected with the second level signal, and the second pole is connected with the delay module; the delay module comprises a first capacitor and a first resistor; the first plate of the first capacitor is connected with the second pole of the charging control transistor, and the second plate is connected with the first delay node; the first pole of the first resistor is connected with the first plate of the first capacitor, and the second pole is connected with the second plate of the first capacitor. The delay pull-down control module comprises a first delay pull-down control transistor and a second delay pull-down control transistor, a gate of the first delay pull-down control transistor is connected to the first delay node, a first pole is connected to the second level signal, and a second pole is connected to the second delay node; a gate of the second delay pull-down control transistor is connected to the second level signal, a first pole is connected to the first level signal, and a second pole is connected to the second delay node; The delay pull-down module comprises a delay pull-down transistor, a gate of the delay pull-down transistor is connected to the second delay node, a first pole is connected to the first level signal, and a second pole is connected to an output end of the delay circuit.

3. The gate drive circuit according to claim 2, characterized by The width-length ratio of the operation control transistor is Ra, the width-length ratio of the first delay pull-down control transistor is Rc, and Ra is greater than or equal to 2Rc.

4. The gate drive circuit according to claim 2, characterized by The width-length ratio of the first delay pull-down control transistor is Rc, the width-length ratio of the second delay pull-down control transistor is Rd, and Rc is greater than or equal to 2Rd.

5. The gate drive circuit according to claim 1, characterized by Each of the shift register units comprises the delay circuit.

6. The gate drive circuit according to claim 1, characterized by The shift register unit further comprises a scan output module, a pull-down module, a pull-down control module, a pull-up module and a second node. The control end of the scan output module is connected to the first node, the first end is connected to a first clock signal, and the second end is connected to a scan output end; the scan output module is used for transmitting the first clock signal to the scan output end according to the potential of the first node; The pull-down module is connected to the first node, the second node, the first level signal and the scan output end respectively; the pull-down module is used for transmitting the first level signal to the first node and the scan output end according to the potential of the second node; The pull-down control module is connected to the second node and a second level signal respectively; The pull-down control module is used for transmitting the second level signal to the second node; The pull-up module is connected to the first node, the second node, the first level signal and the pull-down control module respectively, and is used for transmitting the first level signal to the second node.

7. The gate drive circuit according to claim 6, characterized in that The scan input module comprises a first transistor, a gate of the first transistor is connected to the scan input end, a first pole is connected to a scan control signal, and a second pole is connected to the first node; The first node reset module comprises a second transistor, a gate of the second transistor is connected to a reset input end, a first pole is connected to a first node reset control signal, and a second pole is connected to the first node; The scan output end comprises a third transistor and a storage capacitor, a gate of the third transistor is connected to the first node, a first pole is connected to the first clock signal, and a second pole is connected to the scan output end; the storage capacitor is connected between the gate and the second pole of the third transistor; The pull-down module comprises a fourth transistor and a fifth transistor, a gate of the fourth transistor is connected to the second node, a first pole is connected to the first level signal, and a second pole is connected to the first node; a gate of the fifth transistor is connected to the second node, a first pole is connected to the first level signal, and a second pole is connected to the scan output end; The pull-down control module comprises a sixth transistor and a seventh transistor, a gate and a first electrode of the sixth transistor are connected to the second level signal, a second electrode of the sixth transistor is connected to a gate of the seventh transistor, a first electrode of the seventh transistor is connected to the second level signal, and a second electrode of the seventh transistor is connected to the second node; The pull-up module comprises an eighth transistor and a ninth transistor, a gate of the eighth transistor is connected to the first node, a first electrode of the eighth transistor is connected to the first level signal, and a second electrode of the eighth transistor is connected to the second node; a gate of the ninth transistor is connected to the first node, a first electrode of the ninth transistor is connected to the first level signal, and a second electrode of the ninth transistor is connected to the pull-down control module.

8. The gate drive circuit according to claim 6, characterized by The shift register unit further comprises a tenth transistor and an eleventh transistor; a gate of the tenth transistor is connected to a clear signal terminal, a first electrode of the tenth transistor is connected to the first level signal, and a second electrode of the tenth transistor is connected to the first node; a gate of the eleventh transistor is connected to a close signal terminal, a first electrode of the eleventh transistor is connected to the first level signal, and a second electrode of the eleventh transistor is connected to the scan output terminal.

9. A driving method of a gate driving circuit, characterized by, The driving method is used for driving the gate drive circuit in any one of claims 1-8, and the driving method comprises: at least one frame working time, including a delay circuit starting stage; In the delay circuit starting stage, the output terminal of the delay circuit outputs a signal same as the effective pulse of the first node reset control signal to the first node.

10. The driving method of the gate driving circuit according to claim 9, wherein In one frame working time, it further comprises a scanning stage; In the scanning stage, the scan output terminals of the shift register units of all levels output the enable signals of the scanning signals in sequence.

11. A display device comprising: The gate drive circuit comprises any one of claims 1-8.

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