Display driving circuit, electronic equipment and display method

Abstract

The invention discloses a display driving circuit, electronic equipment and a display method, and relates to the technical field of terminals. The display driving circuit comprises a plurality of rows of pixel circuits and a plurality of emission signal generation circuits. And each row of pixel circuits comprises a plurality of pixel circuits. The output end of each pixel circuit is connected with the anode of one OLED, and the anode voltage input end is connected with driving voltage. The input end of each emission signal generation circuit is connected with a scanning signal output by the corresponding GOA circuit, the output end of each emission signal generation circuit is used for outputting an emission signal to one row of pixel circuits, and the scanning signal is used for driving the pixel circuits. The transmitting signal is used for controlling the connection or disconnection of at least one TFT between the anode voltage input end and the output end of the pixel circuit. The emission signal generation circuit is used for generating an emission signal by using the scanning signal. By means of the scheme, display driving can be achieved without an EOA unit, occupied space is reduced, and frames on the two sides of a display screen of the electronic device can be reduced.

Description

Technical Field

[0001] The present application relates to the field of terminal technology, and in particular to a display driving circuit, an electronic device and a display method. Background Art

[0002] At present, scan drive circuits are widely used in display devices to provide drive signals to pixel circuits for display. The scan drive circuits are arranged on both sides of the display area, and the scan drive circuits include a gate driver on array (GOA) unit and an emission driver on array (EOA) unit.

[0003] The display driver IC (DDIC) of the electronic device needs to send a clock signal and an input signal to the GOA unit and the EOA unit respectively. The current EOA unit and the input signal line of the EOA unit need to occupy a large space, which requires a large area on both sides of the display panel to arrange the EOA unit and the input signal line of the EOA unit, resulting in a wide frame on both sides of the display screen of the electronic device. Summary of the invention

[0004] In order to solve the above problems, the present application provides a display driving circuit, an electronic device and a display method, which can realize display driving without an EOA unit, reduce space occupation, and facilitate reducing the borders on both sides of the display screen of the electronic device.

[0005] In the first aspect, the present application provides a display driving circuit, which includes: multiple rows of pixel circuits and multiple emission signal generating circuits. Each row of pixel circuits includes multiple pixel circuits. The output end of each pixel circuit is connected to the anode of an organic light emitting diode OLED, and the anode voltage input end of each pixel circuit is connected to the driving voltage. The input end of each emission signal generating circuit is connected to the scanning signal output by the corresponding array substrate gate drive GOA circuit, and the output end of each emission signal generating circuit is used to output an emission signal to a row of pixel circuits, the scanning signal is used to drive the pixel circuit, and the emission signal is used to control the connection or disconnection of at least one thin film transistor TFT between the anode voltage input end and the output end of the pixel circuit. The emission signal generating circuit is used to generate an emission signal using the scanning signal.

[0006] Using this solution, the traditional EOA unit does not need to produce the emission signal by itself. Instead, the emission signal required to control the pixel circuit is generated by multiplexing the scanning signal output by the GOA circuit through the emission signal generation circuit. The circuit structure of the emission signal generation circuit is simpler than that of the complex EOA unit, and there is no need for the DDIC to output a clock signal to the EOA circuit. Therefore, the required layout area is reduced, which facilitates reducing the border size of the display panel.

[0007] In a possible implementation, the emission signal generating circuit of the Nth row includes a first TFT, a second TFT and a first capacitor, N is a positive integer greater than p, and p is an integer greater than 2; the drain of the first TFT is connected to the gate of the first TFT, the drain of the first TFT is connected to the scan signal output by the GOA circuit of the N+qth row or connected to a low level, q is an integer greater than or equal to 1; the source of the first TFT is connected to the source of the second TFT and the output end of the emission signal generating circuit; the drain of the second TFT is connected to the scan signal output by the GOA circuit of the Npth row or connected to a high level, and the gate of the second TFT is connected to the scan signal output by the GOA circuit of the N-2th row.

[0008] In a possible implementation, the display driving circuit further includes: a GOA unit. The GOA unit includes multiple rows of GOA circuits. The transmission signal generation circuit is integrated in the GOA circuit of the row where the transmission signal generation circuit is located. This implementation further improves the integration level of the display driving circuit and reduces the required layout area.

[0009] In a possible implementation, the display driving circuit further includes a plurality of control circuits: each pixel circuit includes at least one control circuit. The at least one control circuit is located between the anode voltage input terminal of the pixel circuit and the output terminal of the pixel circuit. The control terminal of the at least one control circuit is connected to the display driving chip DDIC.

[0010] This implementation improves the pixel circuit by controlling the on / off between the anode voltage input terminal and the output terminal of the pixel circuit through the control circuit, thereby enabling the display driving circuit to switch between the DC mode and the PWM mode, and has high practicality.

[0011] In a possible implementation, the pixel circuit includes a third TFT and a fourth TFT. The third TFT is located between the anode voltage input terminal and the output terminal of the pixel circuit, and is used to control the magnitude of the current output by the pixel circuit to the OLED. The drain of the fourth TFT is connected to the reset voltage, the source of the fourth TFT is connected to the output terminal of the pixel circuit, the source of the fourth TFT is connected between the source of the third TFT and the output terminal of the pixel circuit, and the fourth TFT is used to reset the anode voltage of the OLED when turned on. The multiple control circuits include at least the following two control circuits: a first control circuit and a second control circuit. The first control circuit is located between the anode voltage input terminal and the drain of the third TFT. The second control circuit is located between the source of the third TFT and the source of the fourth TFT.

[0012] In a possible implementation, the at least one TFT includes the following two TFTs: a fifth TFT and a sixth TFT. The fifth TFT is located between the anode voltage input terminal and the drain of the third TFT; the sixth TFT is located between the source of the third TFT and the source of the fourth TFT; and the emission signal is used to control the fifth TFT and the sixth TFT to be turned on or off at the same time.

[0013] In a possible implementation manner, the first control circuit includes a seventh TFT, and the second control circuit includes an eighth TFT.

[0014] In the second aspect, the present application also provides an electronic device, which includes an array substrate gate drive GOA unit, a display driver chip DDIC and a display driver circuit; the display driver circuit includes: multiple rows of pixel circuits and multiple emission signal generation circuits. The GOA unit includes multiple rows of GOA circuits; each row of pixel circuits includes multiple pixel circuits; the output end of each pixel circuit is connected to the anode of an organic light emitting diode OLED, and the anode voltage input end of each pixel circuit is connected to the driving voltage; the input end of each emission signal generation circuit is connected to the scanning signal output by the corresponding GOA circuit, and the output end of each emission signal generation circuit is used to output an emission signal to a row of pixel circuits, the scanning signal is used to drive the pixel circuit, and the emission signal is used to control at least one thin film transistor TFT between the anode voltage input end and the output end of the pixel circuit to be connected or disconnected. The emission signal generation circuit is used to generate an emission signal using a scanning signal. DDIC is used to control the GOA circuit to generate a scanning signal.

[0015] In a possible implementation, the emission signal generating circuit of the Nth row includes a first thin film transistor TFT, a second TFT and a first capacitor, N is a positive integer greater than p, and p is an integer greater than 2. The drain of the first TFT is connected to the gate of the first TFT, the drain of the first TFT is connected to the scan signal output by the GOA circuit of the N+qth row or connected to a low level, and q is an integer greater than or equal to 1. The source of the first TFT is connected to the source of the second TFT and the output end of the emission signal generating circuit. The drain of the second TFT is connected to the scan signal output by the GOA circuit of the Npth row or connected to a high level, and the gate of the second TFT is connected to the scan signal output by the GOA circuit of the N-2th row.

[0016] In a possible implementation manner, the transmit signal generation circuit is integrated in a GOA circuit in the same row as the transmit signal generation circuit.

[0017] In a possible implementation, the display driving circuit further includes a plurality of control circuits: each pixel circuit includes at least one control circuit. The at least one control circuit is located between the anode voltage input terminal of the pixel circuit and the output terminal of the pixel circuit. The control terminal of the at least one control circuit is connected to the DDIC. The DDIC is used to control the at least one control circuit to be turned on or off.

[0018] In a possible implementation, the pixel circuit includes a third TFT and a fourth TFT. The third TFT is located between the anode voltage input terminal and the output terminal of the pixel circuit, and is used to control the magnitude of the current output by the pixel circuit to the OLED. The drain of the fourth TFT is connected to the reset voltage, the source of the fourth TFT is connected to the output terminal of the pixel circuit, the source of the fourth TFT is connected between the source of the third TFT and the output terminal of the pixel circuit, and the fourth TFT is used to reset the anode voltage of the OLED when turned on. The multiple control circuits include at least the following two control circuits: a first control circuit and a second control circuit; the first control circuit is located between the anode voltage input terminal and the drain of the third TFT; the second control circuit is located between the source of the third TFT and the source of the fourth TFT.

[0019] In a possible implementation, the at least one TFT includes the following two TFTs: a fifth TFT and a sixth TFT. The fifth TFT is located between the anode voltage input terminal and the drain of the third TFT; the sixth TFT is located between the source of the third TFT and the source of the fourth TFT. The emission signal is used to control the fifth TFT and the sixth TFT to be turned on or off at the same time.

[0020] In a possible implementation, the first control circuit includes a seventh TFT, and the second control circuit includes an eighth TFT. The DDIC is used to determine a current OLED brightness adjustment mode, and send a control signal to the first control circuit and the second control circuit according to the OLED brightness adjustment mode.

[0021] In a third aspect, the present application further provides a display method, which is applied to a DDIC and is used to control the display driving circuit provided in the first aspect above, and the method includes:

[0022] A clock signal and an input signal are sent to the GOA circuit, so that the transmission signal generation circuit generates a transmission signal using the scanning signal output by the GOA circuit.

[0023] In a possible implementation, the display driving circuit further includes a plurality of control circuits: each pixel circuit includes at least one control circuit; at least one control circuit is located between an anode voltage input terminal of the pixel circuit and an output terminal of the pixel circuit; a control terminal of at least one control circuit is connected to a display driving chip DDIC, and the method further includes:

[0024] Determine a current OLED brightness adjustment mode, and send a control signal to at least one control circuit according to the OLED brightness adjustment mode.

[0025] In a possible implementation, determining the current OLED brightness adjustment mode specifically includes:

[0026] When the screen brightness is lower than a first preset brightness, determining that the OLED brightness adjustment mode is a pulse width modulation (PWM) adjustment mode;

[0027] When the screen brightness is higher than or equal to the first preset brightness, it is determined that the OLED brightness adjustment mode is a direct current (DC) adjustment mode.

[0028] In a possible implementation, sending a control signal to at least one control circuit according to the OLED brightness adjustment mode specifically includes:

[0029] When it is determined that the OLED brightness adjustment mode is a pulse width modulation (PWM) adjustment mode, determining a first frequency and a first duty cycle according to the current screen brightness;

[0030] A control signal is generated according to the first frequency and the first duty cycle, and the control signal is sent to at least one control circuit, where the control signal is a PWM signal.

[0031] In a possible implementation, sending a control signal to at least one control circuit according to the OLED brightness adjustment mode specifically includes:

[0032] When it is determined that the OLED brightness adjustment mode is a pulse width modulation (PWM) adjustment mode, determining a first duty cycle according to the current screen brightness;

[0033] A control signal is generated according to the first frequency and the first duty cycle, and the control signal is sent to at least one control circuit, where the control signal is a PWM signal.

[0034] In a possible implementation, sending a control signal to at least one control circuit according to the OLED brightness adjustment mode specifically includes:

[0035] When it is determined that the OLED brightness adjustment mode is the direct current (DC) adjustment mode, a control signal is sent to at least one control circuit, where the control signal is used to control the at least one control circuit to remain turned on. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] Figure 1 A schematic diagram of a display driver architecture provided for related solutions;

[0037] Figure 2 A schematic diagram of a display driving circuit provided in an embodiment of the present application;

[0038] Figure 3 A schematic diagram of another display driving circuit provided in an embodiment of the present application;

[0039] Figure 4 A schematic diagram of a GOA unit provided in an embodiment of the present application;

[0040] Figure 5 Schematic diagram of the signal waveform provided in the embodiment of the present application Figure 1 ;

[0041] Figure 6 Schematic diagram of the principle provided by the embodiment of this application Figure 1 ;

[0042] Figure 7 Schematic diagram of the display driver architecture provided in the embodiment of the present application Figure 1 ;

[0043] Figure 8 Schematic diagram of the display driver architecture provided in the embodiment of the present application Figure 2 ;

[0044] Fig. 9 Schematic diagram of the display driver architecture provided in the embodiment of the present application Figure 3 ;

[0045] Fig.10 A schematic diagram of a GOA circuit integrated with a transmission signal generating circuit provided in an embodiment of the present application;

[0046] Fig.11 Schematic diagram of the display driver architecture provided in the embodiment of the present application Figure 4 ;

[0047] Fig.12 A circuit diagram of a control circuit provided in an embodiment of the present application Figure 1 ;

[0048] Fig.13 A schematic diagram of another display driving circuit provided in an embodiment of the present application;

[0049] Fig.14 A circuit diagram of a control circuit provided in an embodiment of the present application Figure 2 ;

[0050] Fig.15 A schematic diagram of another display driving circuit provided in an embodiment of the present application;

[0051] Fig.16 A flow chart of a display method provided in an embodiment of the present application;

[0052] Fig.17 A flowchart of another display method provided in an embodiment of the present application. DETAILED DESCRIPTION

[0053] The terms "first", "second", etc. in this application description are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated.

[0054] In the present application, unless otherwise clearly specified and limited, the term "connection" should be understood in a broad sense. For example, "connection" can be a fixed connection, a detachable connection, or an integral connection; it can be a direct connection or an indirect connection through an intermediate medium.

[0055] In order to enable persons skilled in the art to more clearly understand the solution of the present application, the application scenario of the technical solution of the present application is first described below.

[0056] See also Figure 1 , which is a schematic diagram of a display driver architecture provided by a related solution.

[0057] The electronic device 10 includes a processor 11 , a DDIC 12 , and a display panel 13 .

[0058] The processor 11 may specifically be an application processor (AP). When the electronic device 10 runs an application (APP), the processor 11 sends control instructions and display data to a display driver IC (DDIC) 12 .

[0059] The DDIC 12 provides a clock signal, an input signal and grayscale data to a display panel 13 .

[0060] The display panel 13 specifically includes: a GOA unit 131a, a GOA unit 131b, an EOA unit 132a, an EOA unit 132b, and a display unit 132. The GOA unit 131a and the GOA unit 131b are located on both sides of the display unit 132, and the EOA unit 132a and the EOA unit 132b are located on both sides of the display unit 132.

[0061] The display unit 132 includes a plurality of pixel circuits, each of which is used to control an organic light-emitting diode (OLED).

[0062] DDIC12 needs to provide the clock signal GCK and the input signal GSTV of the GOA unit 131a and the GOA unit 131b respectively. The GOA unit 131a and the GOA unit 131b include multiple rows of GOA circuits. When the GOA circuit of a row outputs a row scan signal, DDIC12 stores the grayscale data (Data) in the pixel circuit of the row corresponding to the GOA circuit through the data line. Data is specifically voltage data.

[0063] DDIC12 also needs to provide clock signal ECK and input signal ESTV to EOA unit 132a and EOA unit 132b respectively. EOA unit 132a and EOA unit 132b are used to output light control signals to make the pixel circuits of the corresponding rows emit light according to grayscale data. The level of grayscale data determines the brightness of OLED light.

[0064] The circuit structure of the EOA unit 132a and the EOA unit 132b itself is relatively complex, requiring the use of a large number of TFTs, and their input signal lines need to occupy a large space, resulting in a large area on both sides of the display panel 13. This will cause wider borders on both sides of the display screen of the electronic device, reducing the user experience of the electronic device.

[0065] In order to solve the above technical problems, the present application provides a display driving circuit, an electronic device and a display method. The emission signal generating circuit of the display driving circuit generates the emission signal required to control the pixel circuit by multiplexing the scanning signal output by the GOA circuit, and does not require the traditional EOA unit to independently generate the emission signal, which can reduce the hardware cost, effectively reduce the size of the frame, and thus improve the user experience of the electronic device.

[0066] An embodiment of the present application provides a display driving circuit, which is described in detail below with reference to the accompanying drawings.

[0067] See also Figure 2 , which is a schematic diagram of a display driving circuit provided in an embodiment of the present application.

[0068] The display driving circuit is used to drive each OLED of the screen of the electronic device to emit light, thereby realizing display. The electronic device includes a plurality of OLEDs arranged in Q rows and P columns. Wherein, P and Q are both integers greater than 2.

[0069] The display driving circuit 200 includes Q emission signal generating circuits 201. Each emission signal generating circuit 201 is used to output an emission signal EM to P pixel circuits 200 in the same row. The emission signal EM is used to control the anode voltage input terminal of the pixel circuit 200 and the control switch between the output terminal of the pixel circuit 200 to be turned on.

[0070] Each transmission signal generating circuit 201 is connected to the scanning signal output terminal of the GOA circuit. The transmission signal generating circuit 201 is used to generate a transmission signal EM according to the scanning signal output by the GOA circuit.

[0071] Each pixel circuit 200 is connected to at least one control circuit 202 , and the output end of each pixel circuit 200 is connected to an anode of an OLED. Figure 2 In the description, it is taken as an example that each pixel circuit 200 is connected to a control circuit 202 .

[0072] The control circuit 202 is also used to connect to the DDIC to obtain the control signal EM pulse. The control circuit 202 is located between the anode voltage input terminal of the pixel circuit 200 and the output terminal of the pixel circuit 200, and is used to control the on-off between the anode voltage input terminal and the output terminal.

[0073] At present, the brightness adjustment modes of OLED of electronic devices include direct current (DC) mode and pulse width modulation (PWM) mode. Usually, when the screen brightness is relatively high, the DC mode is used for dimming; when the screen brightness is relatively low, the PWM mode is used for dimming.

[0074] When the display driving circuit drives the OLED to display and is currently in DC mode, the emission signal generating circuit 201 generates an emission signal EM using the scanning signal output by the GOA circuit to turn on the control switch between the anode voltage input terminal and the output terminal of the pixel circuit 200, and the DDIC control circuit 202 turns on the anode voltage input terminal and the output terminal of the pixel circuit 200. At this time, the anode voltage input terminal of the pixel circuit 200 is connected to the anode voltage, and the output terminal outputs the driving voltage and driving current to the anode of the OLED to make the OLED emit light. The pixel circuit 200 can control the size of the driving current, thereby realizing the adjustment of the brightness of the OLED.

[0075] When the display driving circuit drives the OLED to display and is currently in PWM mode, the emission signal generating circuit 201 generates an emission signal EM using the scanning signal output by the GOA circuit to turn on the control switch between the anode voltage input terminal and the output terminal of the pixel circuit 200, and the DDIC control circuit 202 turns on the anode voltage input terminal and the output terminal of the pixel circuit 200 according to the first frequency and the first duty cycle. At this time, the anode voltage input terminal of the pixel circuit 200 is connected to the anode voltage, and the output terminal outputs the driving voltage and driving current to the anode of the OLED according to the first frequency and the first duty cycle, thereby achieving the PWM dimming effect.

[0076] In summary, the technical solution provided by the embodiment of the present application is that the emission signal generation circuit 201 uses the scanning signal output by the GOA circuit to generate the emission signal required to control the pixel circuit, and does not require the traditional EOA unit to generate the emission signal, which can effectively reduce the border size of the display panel. In addition, the pixel circuit is improved, and the on-off between the anode voltage input terminal and the output terminal of the pixel circuit is controlled by the control circuit, so that the display drive circuit can switch between the DC mode and the PWM mode, which has high practicality.

[0077] The following is an explanation in conjunction with a specific implementation method.

[0078] See also Figure 3 , which is a schematic diagram of another display driving circuit provided in an embodiment of the present application.

[0079] The display driving circuit includes: an 8T1C pixel circuit 20 , a first control circuit 21 , a second control circuit 22 and a transmission signal generating circuit 23 .

[0080] The EM signal output terminal of the emission signal generating circuit 23 is used to connect the gates of T5 and T6 of a row of 8T1C pixel circuits 20 .

[0081] The 8T1C pixel circuit 20 specifically includes eight thin film transistors (TFTs), namely T1 - T8 , and a capacitor C2 .

[0082] The first control circuit 21 includes one TFT, specifically T9.

[0083] The second control circuit 22 includes one TFT, specifically T10.

[0084] The emission signal generating circuit 23 includes two TFTs, specifically T11 and T12, and a capacitor C1.

[0085] The connection relationship between the components of the display driving circuit is described in detail below.

[0086] The drain of T1 is connected to the source of T2, the source of T5, and the source of T8. The gate of T1 is connected to the first end of C2 and the source of T4. The source of T1 is connected to the drain of T3 and the drain of T6. The second end of C2 is connected to the input voltage V DD , the V DD is a fixed voltage value. T1 is a TFT used to achieve brightness adjustment, which can control the current flowing through itself to change with the change of Vg.

[0087] The drain of T2 is used to connect the data signal line, and then obtain the grayscale data V from DDIC Data The gate of T2 is connected to the P-type scanning signal terminal of the GOA in the Nth row.

[0088] The gate of T3 is connected to the N-type scanning signal terminal of the GOA in the Nth row, and the source of T3 is connected to the first end of C2 and the source of T4.

[0089] The drain of T4 is connected to the first reset voltage V init1 The gate of T4 is connected to the N-type scanning signal terminal of the GOA in the N-1th row.

[0090] The drain of T5 is connected to the source of T9 , and the gate of T5 is connected to the emission signal EM output by the emission signal generating circuit 23 .

[0091] The gate of T6 is connected to the emission signal EM output by the emission signal generating circuit 23. The source of T6 is connected to the drain of T10.

[0092] The drain of T7 is connected to the second reset voltage V init2 The gate of T7 is connected to the reset signal SP2, and the source of T7 is the output terminal of the 8T1C pixel circuit 20, which is used to output voltage and current to the anode of the OLED corresponding to the controlled pixel.

[0093] The drain of T8 is connected to the third reset voltage V init3 The gate of T8 is connected to the reset signal SP2.

[0094] The drain of T9 is connected to the anode voltage input terminal, which is used to provide V DD , the V DD The gate of T9 is connected to the pulse emission signal EM pulse output by DDIC.

[0095] The drain of T10 is connected to the source of T6 , the gate of T10 is connected to the pulse emission signal EM pulse output by DDIC , and the source of T10 is connected to the source of T7 and the output end of the 8T1C pixel circuit 20 .

[0096] The drain of T11 is connected to the gate of T11 and the P-type scanning signal terminal of the GOA circuit in the N+1th row, and the source of T11 is connected to the output terminal of the emission signal generating circuit 23 .

[0097] The drain of T12 is connected to the P-type scanning signal terminal of the GOA circuit in the N-3th row. The gate of T12 is connected to the P-type scanning signal terminal of the GOA circuit in the N-2th row. The source of T12 is connected to the output terminal of the emission signal generating circuit 23.

[0098] C1 is connected in parallel between the drain and source of T12.

[0099] V init1 、V init2 , and V init3 The voltage is provided by DDIC.

[0100] The following is an example in which T3 and T4 are specifically N-type metal oxide semiconductor field effect transistors (negative channel metal oxide semiconductor, NMOS), and the other TFTs are specifically P-type metal oxide semiconductor field effect transistors (positive channel metal oxide semiconductor, PMOS). The display driving circuit can be applied to a low temperature polycrystalline oxide (LTPO) screen. The LTPO screen is an organic light-emitting diode (OLED) screen.

[0101] When the TFT is a PMOS, when the gate of the TFT is connected to a high level, the TFT is turned off; when the gate of the TFT is connected to a low level, the TFT is turned on. When the TFT is an NMOS, when the gate of the TFT is connected to a high level, the TFT is turned on; when the gate of the TFT is connected to a low level, the TFT is turned off.

[0102] The principle of display drive control implemented by the present application scheme is described in detail below.

[0103] The present application improves the existing pixel circuit and multiplexes the GOUT timing signals output by the adjacent multiple rows of GOA circuits to generate the EM signal required for display driving, without the need for a traditional EOA unit. In order to facilitate those skilled in the art to more clearly understand the technical solution of the present application, the working principle of the GOA unit is first described below.

[0104] See also Figure 4 , which is a schematic diagram of a GOA unit provided in an embodiment of the present application.

[0105] The GOA unit includes K rows of GOA circuits, where K is an integer greater than 3. Each GOA circuit includes a plurality of TFTs, and the scan signal outputted from the output end of each GOA circuit acts on a corresponding row of gate lines, that is, is used to drive the pixel circuit included in the row of gate lines.

[0106] Taking GOA circuit 1 as an example, GOA circuit 1 generates output signal S1 and scan signal G1 under the action of the initial input signal (Scan input) and clock signal SCK1 / SCK2 provided by DDIC. GOA circuit 1 outputs scan signal G1 to the corresponding gate line to control the start of the gate line. In addition, GOA circuit 1 uses output signal S1 as the input signal of the next GOA module, that is, GOA circuit 2. The scan signal G1 and output signal S1 output by GOA circuit 1 can be understood as the same signal divided into two outputs, that is, the scan signal G1 and the output signal S1 are generally the same.

[0107] The GOA circuit 2 uses the output signal S1 of the GOA circuit 1 as an input signal, and under the action of the clock signal SCK1 / SCK2, generates a scan signal G2 and provides it to the corresponding gate line, and uses the output signal S2 as an input signal of the GOA circuit 3. And so on, until the GOA circuit K generates a scan signal GN and provides it to the gate line.

[0108] In the above embodiments, it is taken as an example that each row of the GOA unit includes a GOA circuit.

[0109] In one possible implementation, the GOA circuit can be used to output a P-type scan signal, that is, when the GOA circuit has no output, the scan signal end is in a high level state, and when the GOA circuit outputs a scan signal, the scan signal end is switched to a low level state.

[0110] In another possible implementation, the GOA circuit can be used to output an N-type scanning signal, that is, when the GOA circuit has no output, the scanning signal end is in a low level state, and when the GOA circuit outputs a scanning signal, the scanning signal end is switched to a high level state.

[0111] In addition, each row in the GOA unit may also include two or more GOA circuits. For example, each row in the GOA unit includes two GOA circuits. At this time, of the two GOA circuits in each row, one GOA circuit is used to output a P-type scan signal, and the other GOA circuit is used to output an N-type scan signal. The P-type scan signal and the N-type scan signal are complementary in waveform.

[0112] for Figure 3The display driving circuit of the LTPO screen shown in the figure includes two GOA circuits in each row of the GOA unit used, which are used to provide P-type scanning signals and N-type scanning signals respectively.

[0113] See also Figure 5 , which is a schematic diagram of the signal waveform provided by the embodiment of the present application Figure 1 .

[0114] The display driving circuit of the electronic device includes multiple rows. The embodiment of the present application takes a display driving circuit in the Nth row as an example for explanation. The display driving circuit is used to drive an OLED in the Nth row to emit light.

[0115] SCK1 and SCK2 are the clock signals output by DDIC to the GOA circuit.

[0116] G(N-3) is the output voltage of the P-type scan signal end of the GOA circuit in the N-3th row; G(N-2) is the output voltage of the P-type scan signal end of the GOA circuit in the N-2th row; G(N-1) is the output voltage of the P-type scan signal end of the GOA circuit in the N-1th row; GN is the output voltage of the P-type scan signal end of the GOA circuit in the Nth row; G(N+1) is the output voltage of the P-type scan signal end of the N+1th row.

[0117] The signal output by the transmission signal generation circuit 23 to T5 and T6 is EM.

[0118] During the T1 time period, the GOA circuit of the N-2th row outputs a P-type scanning signal, and the P-type scanning signal terminal level is pulled down. For the emission signal generating circuit 23, the P-type scanning signal G(N-2) connected to the gate of T12 begins to be pulled down at T1 time, and T12 is turned on at this time. Since the GOA circuits of the N-3th row and the N+1th row do not output the P-type scanning signal at this time, the P-type scanning signal terminals of the GOA circuits of the N-3th row and the N+1th row are high level, EM starts to output a high level, and T11 is turned off. And the capacitor C1 is charged.

[0119] During the time period T2-T3, the GOA circuit of the N-2th row stops outputting the P-type scanning signal, and the scanning signal end of the GOA circuit of the N-2th row stops being pulled low and returns to a high level, so that the gate level of T12 is pulled high and T12 is turned off. At this time, the capacitor C1 is discharged, and EM is maintained at a high level during the time periods T2 and T3.

[0120] In the time period of T4, the GOA circuits of the N-2nd and N-3rd rows do not output the P-type scanning signal. At this time, the P-type scanning signal terminals of the GOA circuits of the N-2nd and N-3rd rows are at a high level, and T12 is turned off. The GOA circuit of the N+1th row outputs a P-type scanning signal, which pulls down the level of the P-type scanning signal terminal, so that the drain and gate levels of T11 are switched from a high level to a low level, T11 is turned on, and the capacitor C1 is charged, so that EM is switched to a low level.

[0121] In the time period of T5, the GOA circuit of the N+1th row stops outputting the P-type scanning signal, at which time the P-type scanning signal terminal of the GOA circuit of the N+1th row is at a high level, the drain of T11 and the gate of T11 are connected to a high level, and T11 is disconnected. The capacitor C1 is discharged to maintain EM at a low level in the time period of T5.

[0122] Based on the above principle, using the emission signal generating circuit 23 provided in the embodiment of the present application, during the time period T1-T3, the EM signal connected to the gates of T5 and T6 is at a high level, and T5 and T6 are disconnected.

[0123] The working principles of the 8T1C pixel circuit 20 , the first control circuit 21 and the second control circuit 22 are described below.

[0124] The N-type scanning signal output by the GOA circuit and Figure 5 The P-type scanning signals shown are complementary in waveform.

[0125] See also Figure 6 , which is a schematic diagram of the principle provided by the embodiment of the present application Figure 1 .

[0126] In the time period of T1, G(N-1) is at a high level, and the gate of T4 is then disconnected after being connected to a low level. GN is at a high level, and the gate of T3 is then disconnected after being connected to a low level.

[0127] In the time period of T2, G(N-1) is at a low level, and then the gate of T4 is connected to a high level and then turned on. The first reset voltage V init1 Connect C2 to reset the voltage point Vg and initialize. The gate of T8 is connected to a low level, V init2 The anode voltage of the OLED is reset to turn off the OLED.

[0128] In the time period of T3, G(N-1) is high, then the gate of T4 is connected to a low level and then disconnected. GN is low, then the gate of T2 is connected to a low level and then turned on, and the gate of T3 is connected to a high level and then turned on. At this time, the GOA circuit of the Nth row outputs two types of scanning signals, so that the V output by DDIC DataCapacitor C2 is charged through T2, T1 and T3. For the charging circuit, see Figure 6 The circuit in ①. V Data Represents grayscale, that is, V Data The size corresponds to different OLED brightness, which corresponds to different screen brightness of electronic devices.

[0129] In the T4 period, the EM signal connected to the gates of T5 and T6 is switched to a low level, and T5 and T6 are turned on. GN is a high level, and then the gate of T2 is disconnected after connecting to a high level, and the gate of T3 is disconnected after connecting to a low level.

[0130] At this time V DD It can reach the anode of OLED through T9, T5, T1, T6 and T10 in sequence to drive OLED to emit light. The power supply circuit on the anode voltage side can be seen in Figure 6 At the same time, capacitor C2 is discharged to maintain voltage Vg, and then the brightness of OLED is controlled by providing voltage Vg to the gate of T1.

[0131] The DC mode mainly uses V Data Dimming is performed. OLED is current driven, and this dimming method adjusts the brightness by changing the size of the direct current. When the DDIC determines that it is in DC mode, the DDIC outputs V to the pixel circuit. Data To achieve the adjustment of brightness. At this time, DDIC controls the EM pulse signal to maintain a low level, so that the gates of T9 and T10 are continuously connected to a low level, and T9 and T10 remain open. DDIC uses different sizes of V Data After charging the capacitor C2, the voltage of Vg in the time period T4 is different, so that the current in the circuit ② can be controlled to be different, so as to achieve the control of the brightness of the OLED.

[0132] In a possible implementation, different screen brightness and V Data The corresponding relationship is stored in the DDIC. When the DDIC controls the display driving circuit, the corresponding V is determined according to the current screen brightness adjusted by the user. Data , when the GOA circuit outputs the scanning signal Figure 6 When the circuit ① in the Data Charge C2 to achieve data writing.

[0133] PWM mode means that the OLED is turned on and off by controlling the PWM signal. By adjusting the duty cycle of the PWM signal, the on time of the OLED is changed, thereby adjusting the brightness. The higher the duty cycle of the PWM signal, the longer the OLED is on, and the higher the brightness; the lower the duty cycle of the PWM signal, the shorter the OLED is on, and the darker the brightness. The gates of T9 and T10 are connected to the EM pulse signal output by the DDIC, which is used to control the number of times the OLED is turned on in one frame.

[0134] When DDIC determines that it is in PWM mode, the EM pulse signal sent by DDIC to the gates of T9 and T10 is a PWM signal, the frequency of the PWM signal is the first frequency, and the duty cycle is the first duty cycle. When T9 and T10 are connected to the PWM pulse signal, T9 and T10 are periodically turned on and off, so that loop ② is synchronously turned on and off periodically, thereby realizing PWM dimming.

[0135] The embodiment of the present application does not specifically limit the first frequency and the first duty cycle. In actual applications, the first frequency can be fixedly set to 1440 Hz, 1920 Hz or 2160 Hz, etc., or adjusted between multiple frequencies.

[0136] In a possible implementation, the correspondence between different screen brightnesses and the first frequency and the first duty cycle can be pre-calibrated. For example, when the screen brightness is A, the corresponding first frequency is F1, and the corresponding first duty cycle is D1; ​​when the screen brightness is B, the corresponding first frequency is F2, and the corresponding first duty cycle is D2. The correspondence is stored in the DDIC, and when the DDIC controls the display driving circuit, the corresponding first frequency and the first duty cycle are determined according to the current screen brightness adjusted by the user, and the EM pulse signal for controlling T9 and T10 is generated according to the first frequency and the first duty cycle, thereby realizing PWM dimming.

[0137] In another possible implementation, the first frequency of the electronic device during PWM dimming is fixed, and the corresponding relationship between different screen brightness and the first duty cycle can be pre-calibrated. For example, when the screen brightness is A, the corresponding first duty cycle is D1; ​​when the screen brightness is B, the corresponding first duty cycle is D2. The corresponding relationship is stored in the DDIC, and when the DDIC controls the display driving circuit, the corresponding first duty cycle is determined according to the current screen brightness adjusted by the user, and the EM pulse signal for controlling T9 and T10 is generated according to the first frequency and the first duty cycle, thereby realizing PWM dimming.

[0138] Based on the above description, the solution of the embodiment of the present application can generate EM signals by multiplexing the scanning signals of multiple rows of GOA circuits and multiplexing pixel circuits without the need for traditional EOA units, and output EM pulse signals through DDIC, so that the OLED display can switch between DC mode and PWM mode to achieve screen brightness adjustment in different scenarios.

[0139] In the above embodiment, the drain of T11 and the drain of T12 of the transmission signal generating circuit 23 may also be connected to the P-type scanning signal output by other row GOA circuits, which is described in detail below.

[0140] The drain of T12 can be connected to the P-type scanning signal output by the GOA circuit of the Npth row, where p is an integer greater than or equal to 3. It is ensured that when the P-type scanning signal output by the GOA circuit of the N-2th row is switched to a low level, the drain of T12 is connected to a high level. At this time, after T12 is turned on, the high level can charge C1 and make the transmission signal generating circuit 23 output a high level.

[0141] In addition, the gate and drain of T11 can be connected to the P-type scanning signal output by the GOA circuit in the N+qth row, where q is an integer greater than or equal to 1. When q increases, delayed conduction of T5 and T6 is achieved.

[0142] The layout of the transmission signal generating circuit is described in detail below.

[0143] See also Figure 7 , which is a schematic diagram of the display driver architecture provided in the embodiment of the present application Figure 1 .

[0144] In a possible implementation, the emission signal generating unit 133 may be disposed on one side of the display panel, and the emission signal generating unit 133 includes a plurality of rows of emission signal generating circuits, and the number of rows of the emission signal generating circuits is the same as the number of rows of pixels. The EM signal output by the emission signal generating circuit of the Nth row is output to T5 and T6 of the pixel driving circuit of the Nth row.

[0145] In this implementation, the transmission signal generation circuit for generating the EM signal only includes two TFTs and a capacitor C1. Compared with the EOA unit currently used to generate the EM signal, the number of components in the circuit is greatly reduced, thereby reducing the occupied layout area and facilitating the reduction of the border of the display panel.

[0146] See also Figure 8 , which is a schematic diagram of the display driver architecture provided in the embodiment of the present application Figure 2 .

[0147] In another possible implementation, the emission signal generation circuit is centrally arranged in the emission signal generation unit 133a and the emission signal generation unit 133b. The emission signal generation unit 133a and the emission signal generation unit 133b respectively include multiple rows of emission signal generation circuits, and the number of rows of the emission signal generation circuits is the same as the number of rows of pixels. The emission signal generation circuit of the Nth row of the emission signal generation unit 133a is used to output EM signals to half of the pixel driving circuits in the Nth row; the emission signal generation circuit of the Nth row of the emission signal generation unit 133b is used to output EM signals to the other half of the pixel driving circuits in the Nth row.

[0148] This implementation reduces the occupied layout area and facilitates reducing the border of the display panel. At the same time, the transmission signal generation unit is arranged on both sides of the display panel to make the border widths on both sides of the display panel the same, thereby achieving a symmetrical design.

[0149] In another possible implementation, the transmission signal generation circuit may be integrated into the GOA circuit to further reduce the occupied space, which is described below in conjunction with a specific implementation.

[0150] See also Fig. 9 and Fig.10 .in, Fig. 9 Schematic diagram of the display driver architecture provided in the embodiment of the present application Figure 3 ; Fig.10 A schematic diagram of a GOA circuit integrated with a transmission signal generating circuit provided in an embodiment of the present application.

[0151] Fig. 9 The GOA unit on one side of the display panel integrates an emission signal generating unit, and the GOA unit 134 with the integrated emission signal generating unit can output a scanning signal and an EM signal to each row of pixel circuits. Specifically, the emission signal generating circuit is integrated in the GOA circuit of each row of the GOA unit.

[0152] Fig.10 FIG. 8 shows a 8T2C GOA circuit, which includes 8 TFTs, namely M1 to M8, and 2 capacitors, namely C2 and C3.

[0153] At this time, the drain of T12 of the transmission signal generating circuit 23 is connected to the high level VGH, the drain of T11 is connected to the low level VGL, and the connection mode of the remaining parts remains unchanged.

[0154] When the GOA circuit of the N-2th row outputs a P-type scanning signal and pulls the P-type scanning signal terminal level low, the gate of T12 is pulled low, and T12 is turned on. Since the GOA circuit of the N+1th row does not output a P-type scanning signal at this time, the P-type scanning signal terminal of the GOA circuit of the N+1th row is at a high level, and T11 is turned off. EM starts to output a high level, and VGH charges the capacitor C1.

[0155] When the GOA circuit of the N-2th row stops outputting the P-type scanning signal, the scanning signal terminal of the GOA circuit of the N-2th row stops pulling down and returns to a high level, so that T12 is turned off. At this time, the capacitor C1 discharges and maintains EM at a high level.

[0156] When the GOA circuit of the N+1th row outputs a P-type scanning signal, the P-type scanning signal terminal level is pulled down, so that the drain and gate levels of T11 are switched from high level to low level, and T11 is turned on. At this time, VGL charges the capacitor C1, so that EM switches to a low level.

[0157] When the GOA circuit of the N+1th row stops outputting the P-type scanning signal, the P-type scanning signal terminal of the GOA circuit of the N+1th row is at a high level, T11 is disconnected, and the capacitor C1 is discharged to maintain EM at a low level.

[0158] In summary, the transmission signal generating circuit 23 is integrated into the GOA circuit, and the transmission signal generating circuit 23 can continue to generate normally. Figure 5 The EM signal shown is used to drive the pixel circuit for display. This implementation method improves the integration level of the display panel and further reduces the space occupied.

[0159] See also Fig.11 , which is a schematic diagram of the display driver architecture provided in the embodiment of the present application Figure 4 .

[0160] Fig.11 The GOA units on both sides of the display panel are integrated with emission signal generating units. Specifically, the GOA circuit of each row of the GOA unit is integrated with an emission signal generating circuit. Among them, the GOA unit 134a integrated with the emission signal generating unit can output the scanning signal and the EM signal to half of the pixel circuits in each row; the GOA unit 134b integrated with the emission signal generating unit can output the scanning signal and the EM signal to the other half of the pixel circuits in each row.

[0161] For details on how the GOA circuits in each row 134a and 134b are integrated with the transmission signal generating circuit 23, see Fig.10 , I will not go into details here.

[0162] See also Fig.12 , which is a circuit diagram of the control circuit provided in an embodiment of the present application.

[0163] In the above description, two TFTs, T9 and T10, are added to the 8T1C pixel circuit 20. Other implementations of the control circuit are described below.

[0164] like Fig.12 As shown in part (1) of FIG. 1 , T9 may also be arranged below T5; or as shown in FIG. Fig.12 As shown in part (2) of FIG. 1 , T10 can also be set above T6; or as Fig.12 As shown in part (3) of FIG, T9 is set below T5, and T10 is set above T6. This is because a simple position swap will not affect the on-off control of T9 and T10 for loop ②. T9 and T10 can achieve redundant control of loop ②, ensuring the effectiveness of OLED control.

[0165] In addition, only one of T9 and T10 can be set to reduce hardware cost and space occupation, that is, the on-off control of loop ② can be realized. Fig.12 As shown in part (4) of FIG. 1 , only T9 is set, and T9 is located above T5; or as shown in FIG. Fig.12 As shown in part (5) of FIG. 1 , only T9 is set, and T9 is located below T5; or as shown in FIG. Fig.12 As shown in part (6) of FIG. 1 , only T10 is set, and T10 is located below T6; or as shown in FIG. 1 . Fig.12 As shown in part (7) of FIG. 1 , only T10 is set, and T10 is located above T6.

[0166] The above embodiments illustrate the implementation of the display driving circuit when it is applied to the LTPO screen and includes an 8T1C pixel circuit. The following describes the implementation of the display driving circuit when it is applied to the LTPO screen and includes a 7T1C pixel circuit.

[0167] See also Fig.13 , which is a schematic diagram of another display driving circuit provided in an embodiment of the present application.

[0168] The display driving circuit includes: a 7T1C pixel circuit 30 , a first control circuit 31 , a second control circuit 32 and a transmission signal generating circuit 33 .

[0169] The EM signal output terminal of the emission signal generating circuit 33 is used to connect the gates of T5 and T6 of a row of 7T1C pixel circuits 30 .

[0170] The 7T1C pixel circuit 30 includes 7 TFTs, namely T1 to T7, and a capacitor C2.

[0171] The first control circuit 31 includes one TFT, specifically T8.

[0172] The second control circuit 32 includes one TFT, specifically T9.

[0173] The emission signal generating circuit 33 includes two TFTs, specifically T10 and T11, and a capacitor C1.

[0174] The connection relationship between the components of the display driving circuit is described in detail below.

[0175] The drain of T1 is connected to the source of T2 and the source of T5. The gate of T1 is connected to the first end of C2 and the source of T4. The source of T1 is connected to the drain of T3 and the drain of T6.

[0176] The second end of C2 is connected to the input voltage V DD , the V DD is a fixed voltage value.

[0177] The drain of T2 is used to connect the data signal line, and then obtain the grayscale data V from DDIC Data The gate of T2 is connected to the P-type scanning signal terminal of the GOA in the Nth row.

[0178] The gate of T3 is connected to the N-type scanning signal terminal of the GOA in the Nth row, and the source of T3 is connected to the first end of C2 and the source of T4.

[0179] The drain of T4 is connected to the first reset voltage V init1 The gate of T4 is connected to the N-type scanning signal terminal of the GOA in the N-1th row.

[0180] The drain of T5 is connected to the source of T8 , and the gate of T5 is connected to the emission signal EM output by the emission signal generating circuit 23 .

[0181] The gate of T6 is connected to the emission signal EM output by the emission signal generating circuit 23. The source of T6 is connected to the drain of T9.

[0182] The drain of T7 is connected to the second reset voltage V init2 The gate of T7 is connected to the reset signal Reset, and the source of T7 is the output terminal of the 7T1C pixel circuit 30, which is used to output voltage and current to the anode of the OLED corresponding to the controlled pixel.

[0183] The drain of T8 is connected to the input voltage V DD , the V DD The gate of T8 is connected to the pulse emission signal EM pulse output by DDIC.

[0184] The drain of T9 is connected to the source of T6 , the gate of T9 is connected to the pulse emission signal EM pulse output by DDIC , and the source of T9 is connected to the source of T7 and the output end of the 7T1C pixel circuit 30 .

[0185] The drain of T10 is connected to the gate of T10 and to the P-type scanning signal terminal of the GOA circuit in the N+1th row, and the source of T10 is connected to the output terminal of the emission signal generating circuit 33 .

[0186] The drain of T11 is connected to the P-type scanning signal terminal of the GOA circuit in the N-3th row. The gate of T11 is connected to the P-type scanning signal terminal of the GOA circuit in the N-2th row. The source of T12 is connected to the output terminal of the emission signal generating circuit 33.

[0187] C1 is connected in parallel between the drain and source of T11.

[0188] V init1 and V init2 The voltage can be provided by DDIC.

[0189] The following description is made by taking as an example that T3 and T4 are specifically NMOS tubes and the other TFTs are specifically PMOS tubes.

[0190] for Fig.13 The display driving circuit of the LTPO screen shown in the figure includes two GOA circuits in each row of the GOA unit used, which are used to provide P-type scanning signals and N-type scanning signals respectively.

[0191] The electronic device includes a plurality of rows of display driving circuits. The embodiment of the present application is described by taking a display driving circuit in the Nth row as an example. The display driving circuit is used to drive an OLED in the Nth row to emit light.

[0192] Continue to see Figure 5 The signal waveform is shown.

[0193] The signal output by the transmission signal generation circuit 23 to T5 and T6 is EM.

[0194] During the T1 time period, the GOA circuit of the N-2th row outputs a P-type scanning signal, pulls down the P-type scanning signal terminal level, and the P-type scanning signal G(N-2) connected to the gate of T11 starts to be pulled down at T1 time, and T11 is turned on at this time. Since the GOA circuits of the N-3th row and the N+1th row do not output a P-type scanning signal at this time, the P-type scanning signal terminals of the GOA circuits of the N-3th row and the N+1th row are at a high level, and T10 is turned off. At this time, the EM signal is at a high level, and the capacitor C1 is charged.

[0195] During the time period T2-T3, the GOA circuit of the N-2th row stops outputting the P-type scanning signal, and the scanning signal end of the GOA circuit of the N-2th row stops being pulled low and returns to a high level, so that the gate level of T11 is pulled high and T11 is turned off. At this time, the capacitor C1 is discharged, and the EM signal is maintained at a high level during the time periods T2 and T3.

[0196] In the time period of T4, the GOA circuits of the N-2nd and N-3rd rows do not output the P-type scanning signal. At this time, the P-type scanning signal terminals of the GOA circuits of the N-2nd and N-3rd rows are at a high level, and T11 is turned off. The GOA circuit of the N+1th row outputs a P-type scanning signal, which pulls down the level of the P-type scanning signal terminal, so that the drain and gate levels of T10 are switched from a high level to a low level, T10 is turned on, and the capacitor C1 is charged, so that the EM signal is switched to a low level.

[0197] In the time period of T5, the GOA circuit of the N+1th row stops outputting the P-type scanning signal. At this time, the P-type scanning signal terminal of the GOA circuit of the N+1th row is at a high level, the drain of T10 and the gate of T10 are connected to a high level, and T10 is disconnected. The capacitor C1 is discharged to maintain the EM signal at a low level in the time period of T5.

[0198] Based on the above principle, using the emission signal generating circuit 23 provided in the embodiment of the present application, during the time period T1-T3, the EM signal connected to the gates of T5 and T6 is at a high level, and T5 and T6 are disconnected.

[0199] The working principles of the 7T1C pixel circuit 30 , the first control circuit 31 and the second control circuit 32 are described below.

[0200] The N-type scanning signal output by the GOA circuit and Figure 5 The P-type scanning signals shown are complementary in waveform.

[0201] In the time period of T1, G(N-1) is at a high level, and the gate of T4 is then disconnected after being connected to a low level. GN is at a high level, and the gate of T3 is then disconnected after being connected to a low level.

[0202] In the time period of T2, G(N-1) is at a low level, and then the gate of T4 is connected to a high level and then turned on. The first reset voltage V init1 Connect C2 to reset the voltage point Vg and achieve initialization. The gate of T7 is connected to the reset signal Reset to a low level, V init2 The anode voltage of the OLED is reset to turn off the OLED.

[0203] In the time period of T3, G(N-1) is high, then the gate of T4 is connected to a low level and then disconnected. GN is low, then the gate of T2 is connected to a low level and then turned on, and the gate of T3 is connected to a high level and then turned on. At this time, the GOA circuit of the Nth row outputs two types of scanning signals, so that the V output by DDIC Data Capacitor C2 is charged through T2, T1 and T3. For the charging circuit, see Fig.13 The circuit in ①. V DataRepresents grayscale, that is, V Data The size corresponds to different OLED brightness, which corresponds to different screen brightness of electronic devices.

[0204] In the T4 period, the EM signal connected to the gates of T5 and T6 is switched to a low level, and T5 and T6 are turned on. GN is a high level, and then the gate of T2 is disconnected after connecting to a high level, and the gate of T3 is disconnected after connecting to a low level.

[0205] At this time V DD The anode of OLED can be reached through T8, T5, T1, T6 and T9 in sequence to drive OLED to emit light. The power supply circuit on the anode voltage side can be found in Fig.13 At the same time, capacitor C2 is discharged to maintain voltage Vg, and then the brightness of OLED is controlled by providing voltage Vg to the gate of T1.

[0206] When the DDIC determines that the electronic device is in DC mode, the DDIC outputs V Data To achieve the adjustment of brightness. At this time, DDIC controls the EM pulse signal to maintain a low level, so that the gates of T8 and T9 are continuously connected to a low level, and T8 and T9 remain open. DDIC uses different sizes of V Data After charging the capacitor C2, the voltage of Vg in the time period T4 is different, so that the current in the circuit ② can be controlled to be different, so as to achieve the control of the brightness of the OLED.

[0207] In a possible implementation, different screen brightness and V Data The corresponding relationship is stored in the DDIC. When the DDIC controls the display driving circuit, the corresponding V is determined according to the current screen brightness adjusted by the user. Data , when the GOA circuit outputs the scanning signal Fig.13 When the circuit ① in the Data Charge C2 to achieve data writing.

[0208] When DDIC determines that it is in PWM mode, the EM pulse signal sent by DDIC to the gates of T8 and T9 is a PWM signal, the frequency of the PWM signal is the first frequency, and the duty cycle is the first duty cycle. When T8 and T9 are connected to the PWM pulse signal, T8 and T9 are periodically turned on and off, so that loop ② is synchronously turned on and off periodically, thereby realizing PWM dimming.

[0209] The embodiment of the present application does not specifically limit the first frequency and the first duty cycle. In actual applications, the first frequency can be fixedly set to 1440 Hz, 1920 Hz or 2160 Hz, etc., or adjusted between multiple frequencies.

[0210] In a possible implementation, the correspondence between different screen brightnesses and the first frequency and the first duty cycle can be pre-calibrated. For example, when the screen brightness is A, the corresponding first frequency is F1, and the corresponding first duty cycle is D1; ​​when the screen brightness is B, the corresponding first frequency is F2, and the corresponding first duty cycle is D2. The correspondence is stored in the DDIC, and when the DDIC controls the display driving circuit, the corresponding first frequency and the first duty cycle are determined according to the current screen brightness adjusted by the user, and the EM pulse signal for controlling T8 and T9 is generated according to the first frequency and the first duty cycle, thereby realizing PWM dimming.

[0211] In another possible implementation, the first frequency of the electronic device during PWM dimming is fixed, and the corresponding relationship between different screen brightness and the first duty cycle can be pre-calibrated. For example, when the screen brightness is A, the corresponding first duty cycle is D1; ​​when the screen brightness is B, the corresponding first duty cycle is D2. The corresponding relationship is stored in the DDIC, and when the DDIC controls the display driving circuit, the corresponding first duty cycle is determined according to the current screen brightness adjusted by the user, and the EM pulse signal for controlling T8 and T9 is generated according to the first frequency and the first duty cycle, thereby realizing PWM dimming.

[0212] The drain of T11 can be connected to the P-type scanning signal output by the GOA circuit of the Npth row, where p is an integer greater than or equal to 3. It is ensured that when the P-type scanning signal output by the GOA circuit of the N-2th row is switched to a low level, the drain of T11 is connected to a high level. At this time, after T11 is turned on, the high level can charge C1 and make the transmission signal generation circuit 33 output a high level.

[0213] The gate and drain of T10 can be connected to the P-type scanning signal output by the GOA circuit in the N+qth row, where q is an integer greater than or equal to 1. When q increases, delayed conduction of T5 and T6 is achieved.

[0214] The transmission signal generating circuit 33 can be arranged separately on the display panel, or integrated in the GOA circuit, which is not specifically limited in the embodiment of the present application. Figures 7 to 11 The description in , will not be repeated here. The difference is that Fig.10 Replace T12 in with T11, Fig.10 Replace T11 with T10.

[0215] In the above description, two TFTs T8 and T9 are added to the 7T1C pixel circuit 30. Other implementations of the control circuit are described below.

[0216] See also Fig.14 , which is a circuit diagram of a control circuit provided in an embodiment of the present application Figure 2 .

[0217] like Fig.14 As shown in part (1) of FIG. 8 , T8 may also be arranged below T5; or as shown in FIG. Fig.14 As shown in part (2) of FIG. 1 , T9 can also be set above T6; or as Fig.14 As shown in part (3) of FIG, T8 is set below T5, and T9 is set above T6. This is because a simple position swap will not affect the on-off control of T8 and T9 for loop ②. T8 and T9 can achieve redundant control of loop ②, ensuring the effectiveness of OLED control.

[0218] In addition, only one of T8 and T9 can be set to reduce hardware cost and space occupation, that is, the on-off control of loop ② can be realized. Fig.14 As shown in part (4) of FIG. 1 , only T8 is set, and T8 is located above T5; or as shown in FIG. Fig.14 As shown in part (5) of FIG. 1 , only T8 is set, and T8 is located below T5; or as shown in FIG. Fig.14 As shown in part (6) of FIG. 1 , only T9 is set, and T9 is located below T6; or as shown in FIG. Fig.14 As shown in part (7) of FIG. 1 , only T9 is set, and T9 is located above T6.

[0219] Based on the above description, the solution of the embodiment of the present application can generate EM signals by multiplexing the scanning signals of multiple rows of GOA circuits and multiplexing the 7T1C pixel circuit without the need for a traditional EOA unit, and outputs the EM pulse signal through the DDIC, so that the OLED display can switch between DC mode and PWM mode to achieve screen brightness adjustment in different scenarios.

[0220] The above embodiments illustrate the implementation of the display driving circuit when applied to the LTPO screen. The following describes the implementation of the display driving circuit when applied to the low temperature polysilicon (LTPS) screen. The pixel circuit of the LTPS screen adopts a 7T1C pixel circuit as an example for description.

[0221] See also Fig.15 , which is a schematic diagram of another display driving circuit provided in an embodiment of the present application.

[0222] The display driving circuit comprises: a 7T1C pixel circuit 40, a first control circuit 41, a second control circuit 42 and an emission signal generating circuit 43. The EM signal output terminal of the emission signal generating circuit 43 is used to connect the gates of T5 and T6 of a row of 7T1C pixel circuits 40.

[0223] The 7T1C pixel circuit 40 includes 7 TFTs, namely T1 to T7, and a capacitor C2.

[0224] The first control circuit 41 includes one TFT, specifically T8.

[0225] The second control circuit 42 includes one TFT, specifically T9.

[0226] The emission signal generating circuit 43 includes two TFTs, specifically T10 and T11, and a capacitor C1.

[0227] When the display panel uses the 7T1C pixel circuit 40 , each row of the used GOA units includes one GOA circuit for providing a P-type scanning signal.

[0228] The connection relationship between the components of the display driving circuit is described in detail below.

[0229] The drain of T1 is connected to the source of T2 and the source of T5. The gate of T1 is connected to the first end of C2 and the source of T4. The source of T1 is connected to the drain of T3 and the drain of T6.

[0230] The second end of C2 is connected to the input voltage V DD , the V DD is a fixed voltage value.

[0231] The drain of T2 is used to connect the data signal line, and then obtain the grayscale data V from DDIC Data The gate of T2 is connected to the P-type scanning signal terminal of the GOA in the Nth row.

[0232] The gate of T3 is connected to the P-type scanning signal terminal of the GOA in the Nth row, and the source of T3 is connected to the first end of C2 and the source of T4.

[0233] The drain of T4 is connected to the first reset voltage V init1 The gate of T4 is connected to the P-type scanning signal terminal of the GOA in the N-1th row.

[0234] The drain of T5 is connected to the source of T8 , and the gate of T5 is connected to the emission signal EM output by the emission signal generating circuit 23 .

[0235] The gate of T6 is connected to the emission signal EM output by the emission signal generating circuit 23. The source of T6 is connected to the drain of T9.

[0236] The drain of T7 is connected to the second reset voltage V init2 The gate of T7 is connected to the reset signal Reset, and the source of T7 is the output terminal of the 7T1C pixel circuit 30, which is used to output voltage and current to the anode of the OLED corresponding to the controlled pixel.

[0237] The drain of T8 is connected to the input voltage V DD , the V DD The gate of T8 is connected to the pulse emission signal EM pulse output by DDIC.

[0238] The drain of T9 is connected to the source of T6 , the gate of T9 is connected to the pulse emission signal EM pulse output by DDIC , and the source of T9 is connected to the source of T7 and the output end of the 7T1C pixel circuit 30 .

[0239] The drain of T10 is connected to the gate of T10 and to the P-type scanning signal terminal of the GOA circuit in the N+1th row, and the source of T10 is connected to the output terminal of the emission signal generating circuit 33 .

[0240] The drain of T11 is connected to the P-type scanning signal terminal of the GOA circuit in the N-3th row. The gate of T11 is connected to the P-type scanning signal terminal of the GOA circuit in the N-2th row. The source of T12 is connected to the output terminal of the emission signal generating circuit 33.

[0241] C1 is connected in parallel between the drain and source of T11.

[0242] V init1 and V init2 The voltage can be provided by DDIC.

[0243] The following description is made by taking the example that T1-T11 are all NMOS transistors.

[0244] The electronic device includes a plurality of rows of display driving circuits. The embodiment of the present application is described by taking a display driving circuit in the Nth row as an example. The display driving circuit is used to drive an OLED in the Nth row to emit light.

[0245] Continue to see Figure 5 The signal waveform is shown.

[0246] at this time, Fig.15 The signal output by the transmission signal generating circuit 43 to T5 and T6 is EM.

[0247] During the T1 period, the GOA circuit of the N-2th row outputs a P-type scanning signal, pulls down the P-type scanning signal terminal level, and the gate of T11 is connected to a low level, and T11 is turned on. Since the GOA circuits of the N-3th row and the N+1th row do not output a P-type scanning signal at this time, the P-type scanning signal terminals of the GOA circuits of the N-3th row and the N+1th row are at a high level, and T10 is turned off. At this time, the EM signal is at a high level, and the capacitor C1 is charged.

[0248] During the time period T2-T3, the GOA circuit of the N-2th row stops outputting the P-type scanning signal, and the scanning signal end of the GOA circuit of the N-2th row stops pulling down and returns to a high level, so that T11 is turned off. At this time, the capacitor C1 discharges, and the EM signal is maintained at a high level during the time periods T2 and T3.

[0249] In the time period of T4, the GOA circuits of the N-2nd and N-3rd rows do not output the P-type scanning signal. At this time, the P-type scanning signal terminals of the GOA circuits of the N-2nd and N-3rd rows are at a high level, and T11 is turned off. The GOA circuit of the N+1th row outputs a P-type scanning signal, which pulls down the level of the P-type scanning signal terminal, so that the drain and gate levels of T10 are switched from a high level to a low level, T10 is turned on, and the capacitor C1 is charged, so that the EM signal is switched to a low level.

[0250] In the time period of T5, the GOA circuit of the N+1th row stops outputting the P-type scanning signal. At this time, the P-type scanning signal terminal of the GOA circuit of the N+1th row is at a high level, the drain of T10 and the gate of T10 are connected to a high level, and T10 is disconnected. The capacitor C1 is discharged to maintain the EM signal at a low level in the time period of T5.

[0251] The working principles of the 7T1C pixel circuit 40 , the first control circuit 41 and the second control circuit 42 are described below.

[0252] In the time period of T1, G(N-1) is at a high level, and the gate of T4 is connected to a high level and then disconnected. GN is at a high level, and the gates of T2 and T3 are connected to a low level and then disconnected.

[0253] In the time period of T2, G(N-1) is at a low level, and then the gate of T4 is connected to a low level and then turned on. The first reset voltage V init1 Connect C2 to reset the voltage point Vg and achieve initialization. The gate of T7 is connected to the reset signal Reset to a low level, V init2 The anode voltage of the OLED is reset to turn off the OLED.

[0254] During the time period of T3, G(N-1) is high, and the gate of T4 is connected to a low level and then disconnected. GN is low, and the gates of T2 and T3 are connected to a low level and then turned on. V Data Capacitor C2 is charged through T2, T1 and T3. For the charging circuit, see Fig.15 The circuit in ①. V Data Represents grayscale, that is, V Data The size corresponds to different OLED brightness, which corresponds to different screen brightness of electronic devices.

[0255] In the T4 period, the EM signal connected to the gates of T5 and T6 is switched to a low level, and T5 and T6 are turned on. GN is a high level, and the gates of T2 and T3 are connected to a high level and then disconnected.

[0256] At this time V DD The anode of OLED can be reached through T8, T5, T1, T6 and T9 in sequence to drive OLED to emit light. The power supply circuit on the anode voltage side can be found in Fig.15 At the same time, capacitor C2 is discharged to maintain voltage Vg, and then the brightness of OLED is controlled by providing voltage Vg to the gate of T1.

[0257] When the DDIC determines that the electronic device is in DC mode, the DDIC outputs V Data To achieve the adjustment of brightness. At this time, DDIC controls the EM pulse signal to maintain a low level, so that the gates of T8 and T9 are continuously connected to a low level, and T8 and T9 remain open. DDIC uses different sizes of V Data After charging the capacitor C2, the voltage of Vg in the time period T4 is different, so that the current in the circuit ② can be controlled to be different, so as to achieve the control of the brightness of the OLED.

[0258] In a possible implementation, different screen brightness and V Data The corresponding relationship is stored in the DDIC. When the DDIC controls the display driving circuit, the corresponding V is determined according to the current screen brightness adjusted by the user. Data , when the GOA circuit outputs the scanning signal Fig.13 When the circuit ① in the Data Charge C2 to achieve data writing.

[0259] When DDIC determines that it is in PWM mode, the control signal EM pulse sent by DDIC to the gates of T8 and T9 is a PWM signal, the frequency of the PWM signal is the first frequency, and the duty cycle is the first duty cycle. When T8 and T9 are connected to the PWM pulse signal, T8 and T9 are periodically turned on and off, so that loop ② is synchronously periodically turned on and off, thereby realizing PWM dimming.

[0260] The embodiment of the present application does not specifically limit the first frequency and the first duty cycle. In actual applications, the first frequency can be fixedly set to 1440 Hz, 1920 Hz or 2160 Hz, etc., or adjusted between multiple frequencies.

[0261] In a possible implementation, the correspondence between different screen brightnesses and the first frequency and the first duty cycle can be pre-calibrated. For example, when the screen brightness is A, the corresponding first frequency is F1, and the corresponding first duty cycle is D1; ​​when the screen brightness is B, the corresponding first frequency is F2, and the corresponding first duty cycle is D2. The correspondence is stored in the DDIC, and when the DDIC controls the display driving circuit, the corresponding first frequency and the first duty cycle are determined according to the current screen brightness adjusted by the user, and the EM pulse signal for controlling T8 and T9 is generated according to the first frequency and the first duty cycle, thereby realizing PWM dimming.

[0262] In another possible implementation, the first frequency of the electronic device during PWM dimming is fixed, and the corresponding relationship between different screen brightness and the first duty cycle can be pre-calibrated. For example, when the screen brightness is A, the corresponding first duty cycle is D1; ​​when the screen brightness is B, the corresponding first duty cycle is D2. The corresponding relationship is stored in the DDIC, and when the DDIC controls the display driving circuit, the corresponding first duty cycle is determined according to the current screen brightness adjusted by the user, and the EM pulse signal for controlling T8 and T9 is generated according to the first frequency and the first duty cycle, thereby realizing PWM dimming.

[0263] The drain of T11 can be connected to the P-type scanning signal output by the GOA circuit of the Npth row, where p is an integer greater than or equal to 3. It is ensured that when the P-type scanning signal output by the GOA circuit of the N-2th row is switched to a low level, the drain of T11 is connected to a high level. At this time, after T11 is turned on, the high level can charge C1 and make the transmission signal generating circuit 43 output a high level.

[0264] The gate and drain of T10 can be connected to the P-type scanning signal output by the GOA circuit in the N+qth row, where q is an integer greater than or equal to 1. When q increases, delayed conduction of T5 and T6 is achieved.

[0265] The transmission signal generating circuit 43 may be arranged separately on the display panel, or may be integrated in the GOA circuit, which is not specifically limited in the present embodiment. Figures 7 to 11 The description in , will not be repeated here. The difference is that Fig.10 Replace T12 in with T11, Fig.10 Replace T11 with T10.

[0266] In the above description, two TFTs T8 and T9 are added to the 7T1C pixel circuit 40. In other possible implementations, the loop ① portion of the control circuit may also adopt the same Fig.14 Any of the implementation methods shown will not be described in detail here.

[0267] To summarize, the display driving circuit of the embodiment of the present application can generate an EM signal by multiplexing the scanning signals of multiple rows of GOA circuits and multiplexing the 7T1C pixel circuit without the need for a traditional EOA unit, and outputs the EMpulse signal through the DDIC, so that the OLED display can switch between DC mode and PWM mode to achieve adjustment of the screen brightness in different scenarios.

[0268] In the above description of the present application, the display driving circuit capable of realizing both DC dimming and PWM dimming modes is taken as an example. In actual applications, the control circuit may not be provided, that is, the DDIC does not send an EM pulse signal to the display driving circuit. In this case, the display driving circuit can only realize DC dimming.

[0269] In addition, in the above embodiments, N is an integer greater than p, and the GOA circuits of the first p rows are not connected to the pixel circuits, that is, they are not used to drive the pixel circuits, but are only used to output scanning signals. Similarly, the GOA circuits of the last m rows are also not connected to the pixel circuits, but are only used to output scanning signals.

[0270] Based on the display driving circuit provided in the above embodiments, an embodiment of the present application further provides an electronic device using the display driving circuit, which is described in detail below with reference to the accompanying drawings.

[0271] For specific implementation methods of electronic devices, please refer to Figure 7 , Figure 8 , Fig. 9 and Fig.11 .

[0272] The electronic device 10 includes a processor 11 , a DDIC 12 , a display driving circuit and a display panel 13 .

[0273] The processor 11 may include one or more processing units, for example, the processor 110 may include an application processor (AP), and the operating system, user interface and application programs on the electronic device are all executed on the AP. The processor 11 may also be provided with a memory for storing instructions and data.

[0274] The processor 11 is used to send control instructions and picture data to the DDIC 12 , so that the DDIC 12 outputs a clock signal, a first control signal, and a second control signal to a display driving circuit 40 of a display panel 13 .

[0275] The display screen of the display panel may adopt organic light-emitting diode (OLED), low temperature polycrystalline oxide (LTPO), low temperature polycrystalline silicon (LTPS), etc.

[0276] The display panel further includes a GOA unit for generating a scanning signal.

[0277] The display driving circuit specifically includes: a plurality of rows of pixel circuits and a plurality of emission signal generating circuits.

[0278] The GOA unit includes multiple rows of GOA circuits, and each row of pixel circuits includes multiple pixel circuits.

[0279] The output end of each pixel circuit is connected to an anode of an organic light emitting diode (OLED), and the anode voltage input end of each pixel circuit is connected to a driving voltage.

[0280] The input end of each emission signal generating circuit is connected to the scanning signal output by the corresponding GOA circuit, and the output end of each emission signal generating circuit is used to output an emission signal to a row of pixel circuits. The scanning signal is used to drive the pixel circuit, and the emission signal is used to control the connection or disconnection of at least one TFT between the anode voltage input end and the output end of the pixel circuit.

[0281] The transmission signal generating circuit is used for generating a transmission signal by using the scanning signal.

[0282] The emission signal generating circuit may be integrated in the GOA circuit of the row where the emission signal generating circuit is located. The display driving circuit may also include a plurality of control circuits, and each pixel circuit includes at least one of the control circuits. At least one control circuit is located between the anode voltage input terminal of the pixel circuit and the output terminal of the pixel circuit, and the control terminal of at least one control circuit is connected to the DDIC. The DDIC is used to control the at least one control circuit to be turned on or off.

[0283] With this electronic device, the traditional EOA unit does not need to produce the emission signal by itself. Instead, the emission signal generation circuit reuses the scanning signal output by the GOA circuit to generate the emission signal required to control the pixel circuit. The circuit structure of the emission signal generation circuit is simpler than that of the complex EOA unit, and the DDIC is not required to output the clock signal to the EOA circuit, thereby reducing the required layout area and facilitating the reduction of the frame size of the display panel. In addition, the solution can also improve the pixel circuit, and the control circuit controls the on-off between the anode voltage input terminal and the output terminal of the pixel circuit, so that the display drive circuit can switch between the DC mode and the PWM mode, which has high practicality.

[0284] The embodiment of the present application further provides a display method, which can be applied to control the display driving circuit provided in the above embodiment, and is described in detail below with reference to the accompanying drawings.

[0285] The following first describes a display method when the electronic device is in a DC regulation mode.

[0286] See also Fig.16 , which is a flow chart of a display method provided in an embodiment of the present application.

[0287] The method comprises the following steps:

[0288] S11: The user adjusts the screen brightness of the electronic device.

[0289] S12: DDIC determines that the OLED brightness adjustment mode is the DC adjustment mode according to the current screen brightness.

[0290] In a possible implementation, when the screen brightness is higher than or equal to a first preset brightness, the OLED brightness adjustment mode is determined to be a DC adjustment mode.

[0291] S13: The DDIC sends a control signal to the control circuit, and sends a clock signal and an input signal to the GOA unit.

[0292] The DDIC sends a control signal to the control circuit according to the OLED brightness adjustment mode to keep the control circuit turned on. When the control circuit includes a first control circuit and a second control circuit, the DDIC controls both the first control circuit and the second control circuit to remain turned on.

[0293] The DDIC sends a clock signal and an input signal to the GOA unit, thereby controlling the GOA unit to generate a scan signal, which can be used to drive the pixel circuit. The emission signal generation circuit uses the scan signal to generate an emission signal EM and outputs it to the pixel circuit.

[0294] S14: The GOA unit outputs a scanning signal to the pixel circuit and the emission signal generating circuit.

[0295] S15: The transmission signal generating circuit generates a transmission signal using the scanning signal.

[0296] S16: The emission signal generating circuit outputs the emission signal to the pixel circuit.

[0297] S17: The pixel circuit adjusts the brightness of the OLED under the control of the scanning signal and the emission signal.

[0298] When the DDIC determines that it is in DC regulation mode, the DDIC outputs V Data To achieve the adjustment of brightness. At this time, the DDIC control circuit remains open. DDIC uses different sizes of V Data After charging the capacitor in the pixel circuit, the gate of the TFT in the power supply circuit on the anode side of the OLED can be maintained at a corresponding voltage, thereby controlling the current on the anode side of the OLED to achieve control of the brightness of the OLED.

[0299] The above steps in the embodiment of the present application are only for convenience of explanation and do not constitute a limitation on the technical solution of the present application. In other implementations, when the display driving circuit used in the electronic device does not include a control unit, the electronic device only supports DC dimming, then the above S12 step can be deleted, and the "DDIC sends a control signal to the control circuit" in S13 can also be deleted.

[0300] The following first describes a display method when the electronic device is in a PWM regulation mode.

[0301] See also Fig.17 , which is a flow chart of another display method provided in an embodiment of the present application.

[0302] S21: The user adjusts the screen brightness of the electronic device.

[0303] S22: DDIC determines that the OLED brightness adjustment mode is the PWM adjustment mode according to the current screen brightness.

[0304] In a possible implementation, when the screen brightness is lower than a first preset brightness, the OLED brightness adjustment mode is determined to be a pulse width modulation (PWM) adjustment mode.

[0305] S23: DDIC generates a control signal according to the screen brightness.

[0306] In a possible implementation, the DDIC determines a first frequency and a first duty cycle according to the current screen brightness, generates a control signal according to the first frequency and the first duty cycle, and sends the control signal to the at least one control circuit. The control signal is a PWM signal.

[0307] In another possible implementation, the first frequency of the electronic device when performing PWM regulation is a fixed frequency, for example, 1440 Hz, 1920 Hz, or 2160 Hz. At this time, the DDIC determines the first duty cycle according to the current screen brightness, generates a control signal according to the first frequency and the first duty cycle, and sends the control signal to the at least one control circuit. The control signal is a PWM signal.

[0308] S24: The DDIC sends a control signal to the control circuit, and sends a clock signal and an input signal to the GOA unit.

[0309] The DDIC sends a clock signal and an input signal to the GOA unit, thereby controlling the GOA unit to generate a scan signal, which can be used to drive the pixel circuit. The emission signal generation circuit uses the scan signal to generate an emission signal EM and outputs it to the pixel circuit.

[0310] S25: The GOA unit outputs a scanning signal to the pixel circuit and the emission signal generating circuit.

[0311] S26: The transmission signal generating circuit generates a transmission signal using the scanning signal.

[0312] S27: The emission signal generating circuit outputs the emission signal to the pixel circuit.

[0313] S28: The pixel circuit adjusts the brightness of the OLED under the control of the scanning signal, the emission signal and the control signal.

[0314] When the DDIC determines that it is in PWM mode at this time, the DDIC sends a PWM signal to the control circuit, the frequency of the PWM signal is the first frequency, and the duty cycle is the first duty cycle. When the control circuit is connected to the PWM pulse signal, periodic on and off occurs, so that the power supply circuit on the anode side of the OLED is synchronously periodically on and off, thereby realizing PWM dimming.

[0315] In summary, by using the method provided in the embodiment of the present application, the scanning signal output by the GOA circuit can be used to generate the emission signal required to control the pixel circuit, and the traditional EOA unit is not required to generate the emission signal, which can effectively reduce the frame size of the display panel. And the on-off between the anode voltage input terminal and the output terminal of the pixel circuit is controlled by the control circuit, so that the display driving circuit can switch between the DC mode and the PWM mode, which has high practicality.

[0316] References to "one embodiment" or "some embodiments" etc. described in this specification mean that a particular feature, structure or characteristic described in conjunction with the embodiment is included in one or more embodiments of the present application. Thus, the phrases "in one embodiment", "in some embodiments", "in some other embodiments", "in some other embodiments", etc. that appear at different places in this specification do not necessarily refer to the same embodiment, but mean "one or more but not all embodiments", unless otherwise specifically emphasized in other ways. The terms "including", "comprising", "having" and their variations all mean "including but not limited to", unless otherwise specifically emphasized in other ways.

[0317] It should be understood that in the present application, "at least one (item)" means one or more, and "plurality" means two or more. "And / or" is used to describe the association relationship of associated objects, indicating that three relationships may exist. For example, "A and / or B" can mean: only A exists, only B exists, and A and B exist at the same time, where A and B can be singular or plural. The character " / " generally indicates that the objects associated before and after are in an "or" relationship. "At least one of the following" or similar expressions refers to any combination of these items, including any combination of single or plural items. For example, at least one of a, b or c can mean: a, b, c, "a and b", "a and c", "b and c", or "a and b and c", where a, b, c can be single or multiple.

[0318] As described above, the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present application.

Claims

1. A display driving circuit, characterized in that: The display driving circuit comprises: a plurality of rows of pixel circuits and a plurality of emission signal generating circuits; Each row of pixel circuits includes a plurality of the pixel circuits; The output end of each pixel circuit is connected to the anode of an organic light emitting diode (OLED), and the anode voltage input end of each pixel circuit is connected to a driving voltage; The input end of each of the emission signal generating circuits is connected to the scanning signal output by the corresponding array substrate gate driving GOA circuit, and the output end of each of the emission signal generating circuits is used to output an emission signal to a row of pixel circuits, the scanning signal is used to drive the pixel circuits, and the emission signal is used to control at least one thin film transistor TFT between the anode voltage input end and the output end of the pixel circuit to be connected or disconnected; The transmission signal generating circuit is used to generate the transmission signal using the scanning signal.

2. The display driving circuit according to claim 1, characterized in that: The emission signal generating circuit of the Nth row includes a first TFT, a second TFT and a first capacitor, wherein N is a positive integer greater than p, and p is an integer greater than 2; The drain of the first TFT is connected to the gate of the first TFT, the drain of the first TFT is connected to the scan signal output by the GOA circuit of the N+qth row or is connected to a low level, where q is an integer greater than or equal to 1; The source electrode of the first TFT is connected to the source electrode of the second TFT and the output end of the emission signal generating circuit; The drain of the second TFT is connected to the scan signal output by the GOA circuit of the Npth row or to a high level, and the gate of the second TFT is connected to the scan signal output by the GOA circuit of the N-2th row.

3. The display driving circuit according to claim 2, characterized in that: The display driving circuit further includes: a GOA unit; The GOA unit includes a plurality of rows of GOA circuits; The transmit signal generating circuit is integrated in the GOA circuit of the row where the transmit signal generating circuit is located.

4. The display driving circuit according to any one of claims 1 to 3, characterized in that: The display driving circuit further comprises a plurality of control circuits: each of the pixel circuits comprises at least one of the control circuits; The at least one control circuit is located between the anode voltage input terminal of the pixel circuit and the output terminal of the pixel circuit; The control end of at least one of the control circuits is connected to the display driver chip DDIC.

5. The display driving circuit according to claim 4, characterized in that: The pixel circuit includes a third TFT and a fourth TFT; The third TFT is located between the anode voltage input terminal and the output terminal of the pixel circuit, and is used to control the magnitude of the current output by the pixel circuit to the OLED; The drain of the fourth TFT is connected to a reset voltage, the source of the fourth TFT is connected to the output end of the pixel circuit, the source of the fourth TFT is connected between the source of the third TFT and the output end of the pixel circuit, and the fourth TFT is used to reset the anode voltage of the OLED when it is turned on; The multiple control circuits include at least the following two control circuits: a first control circuit and a second control circuit; The first control circuit is located between the anode voltage input terminal and the drain of the third TFT; The second control circuit is located between the source electrode of the third TFT and the source electrode of the fourth TFT.

6. The display driving circuit according to claim 5, characterized in that: The at least one TFT includes the following two TFTs: a fifth TFT and a sixth TFT; The fifth TFT is located between the anode voltage input terminal and the drain of the third TFT; The sixth TFT is located between the source electrode of the third TFT and the source electrode of the fourth TFT; The emission signal is used to control the fifth TFT and the sixth TFT to be turned on or turned off simultaneously.

7. The display driving circuit according to claim 5, characterized in that: The first control circuit includes a seventh TFT, and the second control circuit includes an eighth TFT.

8. An electronic device, characterized in that: include: Array substrate gate drive GOA unit, display driver chip DDIC and display driver circuit; The display driving circuit comprises: a plurality of rows of pixel circuits and a plurality of emission signal generating circuits; The GOA unit includes a plurality of rows of GOA circuits; Each row of pixel circuits includes a plurality of the pixel circuits; The output end of each pixel circuit is connected to the anode of an organic light emitting diode (OLED), and the anode voltage input end of each pixel circuit is connected to a driving voltage; The input end of each of the emission signal generating circuits is connected to the scanning signal output by the corresponding GOA circuit, and the output end of each of the emission signal generating circuits is used to output an emission signal to a row of pixel circuits, the scanning signal is used to drive the pixel circuits, and the emission signal is used to control at least one thin film transistor TFT between the anode voltage input end and the output end of the pixel circuit to be connected or disconnected; The transmission signal generating circuit is used to generate the transmission signal using the scanning signal; The DDIC is used to control the GOA circuit to generate the scanning signal.

9. The electronic device according to claim 8, characterized in that: The emission signal generating circuit of the Nth row includes a first thin film transistor TFT, a second TFT and a first capacitor, wherein N is a positive integer greater than p, and p is an integer greater than 2; The drain of the first TFT is connected to the gate of the first TFT, the drain of the first TFT is connected to the scan signal output by the GOA circuit of the N+qth row or is connected to a low level, where q is an integer greater than or equal to 1; The source electrode of the first TFT is connected to the source electrode of the second TFT and the output end of the emission signal generating circuit; The drain of the second TFT is connected to the scan signal output by the GOA circuit of the Npth row or to a high level, and the gate of the second TFT is connected to the scan signal output by the GOA circuit of the N-2th row.

10. The electronic device according to claim 9, characterized in that: The transmit signal generating circuit is integrated in the GOA circuit of the row where the transmit signal generating circuit is located.

11. The electronic device according to any one of claims 8 to 10, characterized in that: The display driving circuit further includes a plurality of control circuits, and each of the pixel circuits includes at least one of the control circuits; The at least one control circuit is located between the anode voltage input terminal of the pixel circuit and the output terminal of the pixel circuit; The control end of at least one of the control circuits is connected to the DDIC; The DDIC is used to control at least one of the control circuits to be turned on or off.

12. The electronic device according to claim 11, characterized in that: The pixel circuit includes a third TFT and a fourth TFT; The third TFT is located between the anode voltage input terminal and the output terminal of the pixel circuit, and is used to control the magnitude of the current output by the pixel circuit to the OLED; The drain of the fourth TFT is connected to a reset voltage, the source of the fourth TFT is connected to the output end of the pixel circuit, the source of the fourth TFT is connected between the source of the third TFT and the output end of the pixel circuit, and the fourth TFT is used to reset the anode voltage of the OLED when it is turned on; The multiple control circuits include at least the following two control circuits: a first control circuit and a second control circuit; The first control circuit is located between the anode voltage input terminal and the drain of the third TFT; The second control circuit is located between the source electrode of the third TFT and the source electrode of the fourth TFT.

13. The electronic device according to claim 12, characterized in that: The at least one TFT includes the following two TFTs: a fifth TFT and a sixth TFT; The fifth TFT is located between the anode voltage input terminal and the drain of the third TFT; The sixth TFT is located between the source electrode of the third TFT and the source electrode of the fourth TFT; The emission signal is used to control the fifth TFT and the sixth TFT to be turned on or turned off simultaneously.

14. The electronic device according to claim 13, characterized in that: The first control circuit includes a seventh TFT, and the second control circuit includes an eighth TFT; The DDIC is used to determine a current OLED brightness adjustment mode, and send a control signal to the first control circuit and the second control circuit according to the OLED brightness adjustment mode.

15. The electronic device according to claim 14, characterized in that: The DDIC is specifically used to determine a first frequency and a first duty cycle according to the current screen brightness when it is determined that the OLED brightness adjustment mode is a pulse width modulation (PWM) adjustment mode; generate the control signal according to the first frequency and the first duty cycle, and send the control signal to the first control circuit and the second control circuit, wherein the control signal is a PWM signal.

16. The electronic device according to claim 14, characterized in that: The DDIC is specifically used to determine the first duty cycle according to the current screen brightness when it is determined that the OLED brightness adjustment mode is a pulse width modulation (PWM) adjustment mode; generate the control signal according to the first frequency and the first duty cycle, and send the control signal to the first control circuit and the second control circuit, wherein the control signal is a PWM signal.

17. The electronic device according to claim 14, characterized in that: The DDIC is specifically used to send the control signal to the first control circuit and the second control circuit when it is determined that the OLED brightness adjustment mode is a direct current (DC) adjustment mode, so that the first control circuit and the second control circuit remain turned on.

18. The electronic device according to claim 14, characterized in that: The DDIC is specifically used to determine that the OLED brightness adjustment mode is a pulse width modulation (PWM) adjustment mode when the screen brightness is lower than a first preset brightness; and to determine that the OLED brightness adjustment mode is a direct current (DC) adjustment mode when the screen brightness is higher than or equal to the first preset brightness.

19. A display method, characterized in that: For controlling the display driving circuit according to claim 1, the method comprises: A clock signal and an input signal are sent to the GOA circuit, so that the transmission signal generation circuit generates the transmission signal using the scanning signal output by the GOA circuit.

20. The display method according to claim 19, characterized in that: The display driving circuit further comprises a plurality of control circuits: each pixel circuit comprises at least one control circuit; the at least one control circuit is located between the anode voltage input terminal of the pixel circuit and the output terminal of the pixel circuit; The control end of at least one of the control circuits is connected to a display driver chip DDIC, and the method further comprises: Determine a current OLED brightness adjustment mode, and send a control signal to the at least one control circuit according to the OLED brightness adjustment mode.

21. The display method according to claim 20, characterized in that: The determining of the current OLED brightness adjustment mode specifically includes: When the screen brightness is lower than a first preset brightness, determining that the OLED brightness adjustment mode is a pulse width modulation (PWM) adjustment mode; When the screen brightness is higher than or equal to the first preset brightness, it is determined that the OLED brightness adjustment mode is a direct current (DC) adjustment mode.

22. The display method according to claim 20, characterized in that: The sending a control signal to the at least one control circuit according to the OLED brightness adjustment mode specifically includes: When it is determined that the OLED brightness adjustment mode is a pulse width modulation (PWM) adjustment mode, determining a first frequency and a first duty cycle according to the current screen brightness; The control signal is generated according to the first frequency and the first duty cycle, and is sent to the at least one control circuit, wherein the control signal is a PWM signal.

23. The display method according to claim 20, characterized in that: The sending a control signal to the at least one control circuit according to the OLED brightness adjustment mode specifically includes: When it is determined that the OLED brightness adjustment mode is a pulse width modulation (PWM) adjustment mode, determining a first duty cycle according to the current screen brightness; The control signal is generated according to the first frequency and the first duty cycle, and is sent to the at least one control circuit, wherein the control signal is a PWM signal.

24. The display method according to claim 20, characterized in that: The sending a control signal to the at least one control circuit according to the OLED brightness adjustment mode specifically includes: When it is determined that the OLED brightness adjustment mode is a direct current (DC) adjustment mode, the control signal is sent to the at least one control circuit, where the control signal is used to control the at least one control circuit to remain turned on.

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