Gate drive circuit and display panel

Abstract

The invention discloses a gate drive circuit and a display panel, and the gate drive circuit comprises a plurality of cascaded gate drive units, and each gate drive unit at least comprises a first output unit which is used for outputting a first pulse signal; the second output unit is used for outputting a second pulse signal; the cascade unit is connected with the first output unit of the gate driving unit of the previous stage and is used for receiving the first pulse signal of the previous stage; the first driving unit is arranged between the cascade unit and the control end of the first output unit; and the second driving unit is arranged between the cascade unit and the control end of the second output unit and is used for enabling the second output unit to output a high-potential pulse of the second pulse signal when the first output unit outputs the low-potential pulse of the first pulse signal. Through the circuit, output of different scanning signals is realized.

Description

Technical Field

[0001] The present invention relates to the field of display panels, and in particular to a gate driving circuit and a display panel. Background Art

[0002] With the development of display technology, OLED (Organic Light Emitting Display) has begun to move towards the small-size mainstream display market. Small-size OLED display products usually use GOA (gate on array) circuits to generate and process the scanning signals required by pixel driving circuits.

[0003] In order to achieve the low refresh function, it is necessary to extend the holding time of the gate voltage of the driving transistor in principle. The current mainstream solution is to introduce a new material with lower Ioff (leakage current) characteristics, indium gallium zinc oxide (IGZO) to make transistors, or to use phosphorus channel doping process to make different types of transistors.

[0004] To further reduce leakage, MOS (transistor) with IGZO as the substrate is injected with P to form NMOS (N-type transistor) with lower carrier mobility rate. NMOS needs to be driven by positive pulses, which is opposite to other PMOS (P-type transistors). Therefore, in the design of GOA circuit, in addition to the switching pulse (EM) and low-level pulse (Pscan), an additional GOA circuit for generating high-level pulses (Nscan) needs to be designed. However, the additional design of a GOA circuit for generating high-level pulses will occupy a large amount of border area. Summary of the invention

[0005] The main technical problem solved by the present application is to provide a gate drive circuit and a display panel to achieve the output of different scanning signals.

[0006] To solve the above problems, the present application provides a gate driving circuit in the first aspect, wherein the gate driving circuit includes: a plurality of cascaded gate driving units, each of the gate driving units includes at least: a first output unit, used to output a first pulse signal; wherein the first pulse signal is a low-potential pulse signal with a normal high potential; a second output unit, used to output a second pulse signal; wherein the second pulse signal is a high-potential pulse signal with a normal low potential; a cascade unit, connected to the first output unit of the gate driving unit of the previous level, used to receive the first pulse signal of the previous level; a first driving unit, arranged between the cascade unit and the control end of the first output unit, used to provide a driving signal to the first output unit according to the cascade signal of the cascade unit, so that the first output unit outputs the first pulse signal; a second driving unit, arranged between the cascade unit and the control end of the second output unit, used to provide a driving signal to the second output unit according to the cascade signal of the cascade unit, so that the second output unit outputs the second pulse signal, and the second output unit outputs a high-potential pulse of the second pulse signal when the first output unit outputs a low-potential pulse of the first pulse signal.

[0007] Wherein, the pulse width of the second pulse signal is greater than the pulse width of the first pulse signal.

[0008] Wherein, the first output unit includes a first sub-output unit and a first pulse output holding unit; the input end of the first sub-output unit is connected to the first jump signal line, and the control end of the first sub-output unit is connected to the output end of the first driving unit, which is used to output the high potential pulse and the low potential pulse of the first pulse signal according to the driving signal provided by the first driving unit; the input end of the first pulse output holding unit is connected to the high potential signal line, and the control end of the first pulse output holding unit is connected to the output end of the first driving unit, which is used to keep outputting the high potential pulse of the first pulse signal according to the driving signal provided by the first driving unit; the second output unit includes a second sub-output unit and a second pulse output holding unit; the input end of the second sub-output unit is connected to the high potential signal line, and the control end of the second sub-output unit is connected to the output end of the second driving unit, which is used to output the high potential pulse of the second pulse signal according to the driving signal provided by the second driving unit; the input end of the second pulse output holding unit is connected to the low potential signal line, and the control end of the second pulse output holding unit is connected to the output end of the second driving unit, which is used to keep outputting the low potential pulse of the second pulse signal according to the driving signal provided by the second driving unit.

[0009] Wherein, the first driving unit includes: a first storage unit, a first electrode plate of the first storage unit is connected to the output end of the cascade unit, the control end of the first sub-output unit, and the control end of the first pulse output holding unit, and a second electrode plate of the first storage unit is connected to the output end of the first output unit, and is used to store the voltage signal charged by the cascade unit and control the first sub-output unit or the first pulse output holding unit to work according to the stored voltage signal; a first charging control unit, the first charging control unit is arranged between the cascade unit and the first electrode plate of the first storage unit, and is used to control the cascade unit to charge the voltage signal into the first storage unit.

[0010] Wherein, the control end of the first charging control unit is connected to the low-potential signal line.

[0011] Wherein, the second driving unit comprises: a second storage unit, wherein the first electrode plate of the second storage unit is connected to the output end of the cascade unit and the input end of the first charging control unit, and the second electrode plate of the second storage unit is connected to the low potential signal line, and is used to store the voltage signal charged by the cascade unit or the first storage unit; a second charging control unit, wherein the second charging control unit is arranged between the output end of the cascade unit and / or the input end of the first charging control unit and the second storage unit, and is used to control the cascade unit and / or the first storage unit to charge the voltage signal to the second storage unit; a third storage unit, wherein the first electrode plate of the third storage unit The third storage unit is connected to the first plate of the second storage unit, the control end of the second sub-output unit, and the control end of the second pulse output holding unit. The second plate of the third storage unit is connected to the high-potential signal line, and is used to store the voltage signal charged into the second storage unit and control the second sub-output unit or the second pulse output holding unit to work according to the stored voltage signal; the third charging control unit is arranged between the first plate of the second storage unit and the third storage unit, the control end of the second sub-output unit, and the control end of the second pulse output holding unit, and is used to control the second storage unit to charge the voltage signal into the first plate of the third storage unit.

[0012] The control end of the cascade unit is connected to a second jump signal line; wherein the signal jump frequency on the second jump signal line is the same as that on the first jump signal line, but the phase is opposite.

[0013] Wherein, the control end of the second charging control unit is connected to the third jump signal line; wherein, the high potential signal pulse width on the third jump signal line is greater than the low potential signal pulse width on the first jump signal line or the high potential signal pulse width on the second jump signal line; wherein, the high potential signal pulse width on the third jump signal line is the same as the high potential pulse width of the second pulse signal.

[0014] Wherein, the control end of the third charging control unit is connected to the first jump signal line.

[0015] To solve the above problem, the present application provides a display panel in a second aspect, wherein the display panel includes the gate driving circuit described in any embodiment of the first aspect.

[0016] The beneficial effect of the present application is that, by designing the cascade unit, while minimizing the use of input signals, a GOA circuit can output different first pulse signals and second pulse signals to different types of transistors (TFTs) in the pixel unit, thereby saving circuit expenses and reducing the border width. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0018] Figure 1 A schematic diagram of the structure of an embodiment of a gate driving circuit provided in the present application; Figure 2 A timing diagram of the first pulse signal and the second pulse signal provided in the present application; Figure 3 A schematic structural diagram of a first specific embodiment of a gate driving unit provided in the present application; Figure 4 A schematic structural diagram of a second specific embodiment of a gate driving unit provided in the present application; Figure 5 A schematic diagram of the circuit structure of a specific embodiment of the gate driving unit provided in this application; Figure 6 A driving timing diagram of a specific embodiment of a gate driving unit provided in this application; Figure 7 A circuit diagram of the first driving stage of a specific embodiment of a gate driving unit provided in the present application; Figure 8A circuit diagram of the second driving stage of a specific embodiment of a gate driving unit provided in the present application; Fig. 9 A circuit diagram of the third driving stage of a specific embodiment of a gate driving unit provided in the present application; Fig.10 A circuit diagram of a fourth driving stage of a specific embodiment of a gate driving unit provided in the present application; Fig.11 A circuit diagram of a fifth driving stage of a specific embodiment of a gate driving unit provided in the present application; Fig.12 A schematic structural diagram of an embodiment of a display panel provided in the present application.

[0019] First output unit 11; second output unit 12; cascade unit 20; first drive unit 31; second drive unit 32; previous stage first pulse signal Pscan(n-1); first pulse signal Pscan(n); second pulse signal Nscan(n); First sub-output unit 111; first pulse output holding unit 112; second sub-output unit 121; second pulse output holding unit 122; high potential signal line VGH; low potential signal line VGL; first storage unit C1; first charging control unit 311; second storage unit C2; second charging control unit 312; third storage unit C3; third charging control unit 313; first jump signal line CK; second jump signal line XCK; third jump signal line CK2; A first transistor T1; a second transistor T2; a third transistor T3; a fourth transistor T4; a fifth transistor T5; a sixth transistor T6; a seventh transistor T7; and an eighth transistor T8; Display panel 100 ; display area 101 ; non-display area 102 . DETAILED DESCRIPTION

[0020] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0021] The terms used in the embodiments of the present application are only for the purpose of describing specific embodiments, and are not intended to limit the present application. The singular forms of "a", "said", and "the" used in the embodiments of the present application and the appended claims are also intended to include plural forms, unless otherwise clearly indicated above, and "multiple" generally includes at least two, but does not exclude the inclusion of at least one.

[0022] It should be understood that the term "and / or" used in this article is only a description of the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. In addition, the character " / " in this article generally indicates that the objects associated with each other are in an "or" relationship. The terms "first", "second", etc. in the specification and claims of this application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence.

[0023] It should be understood that the terms "include", "comprises" or any other variations used herein are intended to cover non-exclusive inclusion, so that a process, method, article or device that includes a series of elements includes not only those elements, but also includes other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of more restrictions, the elements defined by the sentence "includes..." do not exclude the presence of other identical elements in the process, method, article or device that includes the elements.

[0024] It should be noted that if the embodiments of the present application involve directional indications (such as up, down, left, right, front, back...), such directional indications are only used to explain the relative position relationship, movement status, etc. between the components under a certain specific posture (as shown in the accompanying drawings). If the specific posture changes, the directional indication will also change accordingly.

[0025] Reference to "embodiments" herein means that a particular feature, structure, or characteristic described in conjunction with the embodiments may be included in at least one embodiment of the present application. The presence of the phrase at each location in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment that is mutually exclusive with other embodiments. It is explicitly and implicitly understood by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0026] It should be noted that the high potential signal line VGH is used to transmit a high potential voltage signal; the low potential signal line VGL is used to transmit a low potential voltage signal. The input end of the transistor is also the source of the transistor, the output end of the transistor is also the drain of the transistor, and the control end of the transistor is also the gate of the transistor, wherein the source and drain of the transistor can be interchanged. Turning off, cutting off or disconnecting a transistor have the same meaning.

[0027] The present application provides a gate driving circuit, which includes: a plurality of cascaded gate driving units, for details, please refer to Figure 1 , Figure 1 This is a schematic diagram of the structure of an embodiment of the gate drive circuit provided by the present application. Figure 1 As shown, each gate driving unit at least includes: a first output unit 11 , a second output unit 12 , a cascade unit 20 , a first driving unit 31 , and a second driving unit 32 .

[0028] The first output unit 11 is used to output a first pulse signal Pscan(n), and the second output unit 12 is used to output a second pulse signal Nscan(n). The first pulse signal Pscan(n) is a low-potential pulse signal with a normal high potential. The second pulse signal Nscan(n) is a high-potential pulse signal with a normal low potential.

[0029] The cascade unit 20 is connected to the first output unit 11 of the previous-stage gate driving unit GOA(n-1) and is used to receive the previous-stage first pulse signal Pscan(n-1).

[0030] The first driving unit 31 is disposed between the cascade unit 20 and the control end of the first output unit 11, and is used to provide a driving signal to the control end of the first output unit 11 according to the cascade signal of the cascade unit 20, so that the first output unit 11 outputs the first pulse signal Pscan(n). The cascade signal includes a high potential pulse signal and a low potential pulse signal of the first pulse signal Pscan(n-1) of the previous stage.

[0031] The second driving unit 32 is arranged between the cascade unit 20 and the control end of the second output unit 12, and is used for providing a driving signal to the control end of the second output unit 12 according to the cascade signal of the cascade unit 20, so that the second output unit 12 outputs the second pulse signal Nscan(n), and when the first output unit 11 outputs the low-voltage pulse of the first pulse signal Pscan(n), the second output unit 12 outputs the high-voltage pulse of the second pulse signal Nscan(n), that is, the first pulse signal Pscan(n) and the second pulse signal Nscan(n) are triggered and outputted at the same time.

[0032] In a specific embodiment, the pulse width of the second pulse signal Nscan(n) is greater than the pulse width of the first pulse signal Pscan(n). Figure 2 , Figure 2 This is a timing diagram of the first pulse signal and the second pulse signal provided in this application. Figure 2As shown, the low-potential pulse of the first pulse signal Pscan(n) and the high-potential pulse of the second pulse signal Nscan(n) are triggered and outputted simultaneously, and the pulse width of the second pulse signal Nscan(n) is greater than the pulse width of the first pulse signal Pscan(n). Specifically, the pulse width of the second pulse signal Nscan(n) can be adjusted according to design requirements. The pulse width of the second pulse signal Nscan(n) refers to the duration (duty cycle) of the high-potential output phase of the second pulse signal Nscan(n). The pulse width of the first pulse signal Pscan(n) refers to the duration of the low-potential output phase of the first pulse signal Pscan(n).

[0033] like Figure 2 As shown, the driving timing includes a P output stage and an N output stage. In the P output stage, the first pulse signal Pscan(n) outputs a low potential pulse (low potential voltage), and in other stages, the output of a high potential voltage is maintained. In the N output stage, the second pulse signal Nscan(n) outputs a high potential pulse (low potential voltage), and in other stages, the output of a low potential voltage is maintained.

[0034] In a preferred embodiment, the pulse width of the second pulse signal Nscan(n) is one or more times the pulse width of the first pulse signal Pscan(n).

[0035] Further, the first output unit 11 includes a first sub-output unit 111 and a first pulse output holding unit 112. The second output unit 12 includes a second sub-output unit 121 and a second pulse output holding unit 122. For details, please refer to Figure 3 , Figure 3 This is a schematic diagram of the structure of the first specific embodiment of the gate driving unit provided in this application. Figure 3 As shown, the input end of the first sub-output unit 111 is connected to the first jump signal line CK, and the control end of the first sub-output unit 111 is connected to the output end of the first driving unit 31, and is used to output the high potential pulse and the low potential pulse of the first pulse signal Pscan(n) according to the driving signal provided by the first driving unit 31. The driving signal includes a high potential voltage and a low potential voltage.

[0036] The input end of the first pulse output holding unit 112 is connected to the high potential signal line VGH, and the control end of the first pulse output holding unit 112 is connected to the output end of the first driving unit 31, and is used to maintain the output of the high potential pulse of the first pulse signal Pscan(n) according to the driving signal provided by the first driving unit 31. Specifically, the first pulse output holding unit 112 maintains the output of the high potential voltage (that is, the high potential pulse / voltage of the first pulse signal Pscan(n)) in the holding stage after the P output stage of the first pulse signal Pscan(n). The first pulse output holding unit 112 remains turned on in the holding stage after the P output stage of the first pulse signal Pscan(n).

[0037] The input end of the second sub-output unit 121 is connected to the high potential signal line VGH, and the control end of the second sub-output unit 121 is connected to the output end of the second driving unit 32, and is used to output a high potential pulse of the second pulse signal Nscan(n) according to the driving signal provided by the second driving unit 32. The driving signal includes a high potential voltage and a low potential voltage.

[0038] The input end of the second pulse output holding unit 122 is connected to the low potential signal line VGL, and the control end of the second pulse output holding unit 122 is connected to the output end of the second driving unit 32, and is used to maintain the output of the low potential pulse of the second pulse signal Nscan(n) according to the driving signal provided by the second driving unit 32. Specifically, the second pulse output holding unit 122 maintains the output of the low potential voltage in the holding stage after the N output stage of the second pulse signal Nscan(n), that is, the second pulse output holding unit 122 remains turned on in the holding stage after the N output stage.

[0039] See further Figure 4 , Figure 4 This is a schematic diagram of the structure of the second specific embodiment of the gate driving unit provided in this application. Figure 4 As shown, the first driving unit 31 includes a first storage unit C1 and a first charging control unit 311 .

[0040] Specifically, the first plate of the first storage unit C1 is connected to the output end of the cascade unit 20, the control end of the first sub-output unit 111, and the control end of the first pulse output holding unit 112, and the second plate of the first storage unit C1 is connected to the output end of the first output unit 11 (that is, the output end of the first sub-output unit 111 and the output end of the first pulse output holding unit 112). The first storage unit C1 is used to store the voltage signal (including the high potential voltage and the low potential voltage) charged to the first plate of the first storage unit C1 by the cascade unit 20, and control the first sub-output unit 111 or the first pulse output holding unit 112 to work according to the stored voltage signal. Specifically, when the first sub-output unit 111 is controlled to work, the first pulse output holding unit 112 is controlled not to work; when the first pulse output holding unit 112 is controlled to work, the first sub-output unit 111 is controlled not to work.

[0041] Specifically, the first sub-output unit 111 and the first pulse output holding unit 112 include a group of transistors with opposite driving characteristics, one is an N-type transistor and the other is a P-type transistor.

[0042] The first charging control unit 311 is disposed between the cascade unit 20 and the first electrode plate of the first storage unit C1, and is used to control the cascade unit 20 to charge the voltage signal into the first storage unit C1. The second electrode plate of the first storage unit C1 is also connected to the output end of the first output unit 11 (or the first sub-output unit 111), so that the first storage unit C1 has a storage function, and controls the output state (working state) of the first sub-output unit 111. It should be noted that, in the first stage (sampling stage), the first jump signal line CK outputs a high potential, the first pulse signal Pscan(n) is controlled to output a high potential pulse through the first sub-output unit 111, the second plate of the first storage unit C1 is a high potential, and the first plate of the first storage unit C1 can store a low potential; in the second stage (P output stage), the first jump signal line CK outputs a low potential, the first pulse signal Pscan(n) is controlled to output a low potential pulse through the first sub-output unit 111, the second plate of the first storage unit C1 is a low potential, and during the low potential output process, the low potential of the first plate of the first storage unit C1 gradually decreases, so that the control end (gate) of the first charging control unit 311 is pulled down to ensure that the transistor in the first charging control unit 311 is turned on. In other embodiments, the second plate of the first storage unit C1 can also be connected to a fixed signal line, such as a high potential signal line VGH, and a low potential signal line VGL, which is not limited here.

[0043] In this specific embodiment, the control end of the first charging control unit 311 is connected to the low potential signal line VGL. The first charging control unit 311 maintains a normally on state under the control of the low potential signal line VGL, wherein the second driving unit 32 is arranged at the end of the first charging control unit 311 away from the first storage unit C1, and the first storage unit C1 also provides a driving signal to the second driving unit 32 through the first charging control unit 311.

[0044] The second driving unit 32 includes a second storage unit C2 , a second charging control unit 312 , a third storage unit C3 , and a third charging control unit 313 .

[0045] The first electrode plate of the second storage unit C2 is connected to the output end of the cascade unit 20 and the input end of the first charging control unit 311, and the second electrode plate of the second storage unit C2 is connected to the low potential signal line VGL for storing the voltage signal charged by the cascade unit 20 or the first storage unit C1.

[0046] The second charging control unit 312 is arranged between the output end of the cascade unit 20 and / or the input end of the first charging control unit 311 and the second storage unit C2, and is used to control the cascade unit 20 and / or the input end of the first charging control unit 311 and the second storage unit C2, and is used to control the cascade unit 20 and / or the first storage unit C1 to charge the voltage signal to the first electrode plate of the second storage unit C2.

[0047] The first electrode plate of the third storage unit C3 is connected to the first electrode plate of the second storage unit C2, the control end of the second sub-output unit 121, and the control end of the second pulse output holding unit 122. The second electrode plate of the third storage unit C3 is connected to the high potential signal line VGH, and is used to store the voltage signal charged by the second storage unit C2 and control the second sub-output unit 121 or the second pulse output holding unit 122 to work according to the stored voltage signal. Specifically, when the second sub-output unit 121 is controlled to work, the second pulse output holding unit 122 is controlled not to work; when the second pulse output holding unit 122 is controlled to work, the second sub-output unit 121 is controlled not to work.

[0048] The third charging control unit 313 is arranged between the first electrode plate of the second storage unit C2 and the first electrode plate of the third storage unit C3, the control end of the second sub-output unit 121, and the control end of the second pulse output holding unit 122, and is used to control the second storage unit C2 to charge the voltage signal into the first electrode plate of the third storage unit C3.

[0049] Further, the control end of the cascade unit 20 is connected to the second jump signal line XCK. The second jump signal line XCK has the same signal jump frequency and opposite phase to the first jump signal line CK. Specifically, the first jump signal line CK and the second jump signal line XCK both jump between a high potential and a low potential, wherein when the first jump signal line CK outputs a high potential, the second jump signal line XCK outputs a low potential; when the first jump signal line CK outputs a low potential, the second jump signal line XCK outputs a high potential. The pulse widths of the high potential and the low potential on the first jump signal line CK and the second jump signal line XCK are the same.

[0050] Furthermore, the control end of the second charging control unit 312 is connected to the third jump signal line CK2. The high potential signal pulse width on the third jump signal line CK2 is the same as the high potential pulse width of the second pulse signal Nscan(n). The high potential pulse width of the second pulse signal Nscan(n) is controlled by the high potential signal pulse width on the third jump signal line CK2. It should be noted that the pulse width of the second pulse signal Nscan(n) refers to the high potential pulse width of the second pulse signal Nscan(n), and the pulse width of the first pulse signal Pscan(n) refers to the low potential pulse width of the first pulse signal Pscan(n).

[0051] In a preferred embodiment, the high potential signal pulse width on the third jump signal line CK2 is greater than the low potential signal pulse width on the first jump signal line CK or the high potential signal pulse width on the second jump signal line XCK. The high potential signal pulse width on the third jump signal line CK2 is greater than the low potential signal pulse width on the third jump signal line CK2.

[0052] In a further embodiment, the control end of the third charging control unit 313 is connected to the first jump signal line CK. In other embodiments, the control end of the third charging control unit 313 may also be connected to the second jump signal line XCK, which is not limited here.

[0053] The present application also provides a gate drive unit circuit structure. Figure 5 , Figure 5 This is a schematic diagram of the circuit structure of a specific embodiment of the gate drive unit provided in this application. Figure 5 shown.

[0054] The cascade unit 20 includes a first transistor T1, the first charging control unit 311 includes a second transistor T2, the first sub-output unit 111 includes a third transistor T3, the first pulse output holding unit 112 includes a fourth transistor T4, the second charging control unit 312 includes a fifth transistor T5, the third charging control unit 313 includes a sixth transistor T6, the second sub-output unit 121 includes a seventh transistor T7, and the second pulse output holding unit 122 includes an eighth transistor T8.

[0055] In this specific embodiment, the fourth transistor T4 and the seventh transistor T7 are N-type transistors, and the other transistors are P-type transistors.

[0056] This application also provides a driving timing diagram of a specific embodiment of a gate driving unit. Figure 6 , Figure 6 This is a driving timing diagram of a specific embodiment of the gate driving unit provided in this application. The driving phase includes a sampling phase, a P output phase, an N output phase, a P holding phase, and an N holding phase. For further details, please refer to Figure 7~Figure 11 . Figure 7 This is a circuit diagram of the first driving stage of a specific embodiment of the gate driving unit provided in the present application. Figure 8 This is a circuit diagram of the second driving stage of a specific embodiment of the gate driving unit provided in the present application. Fig. 9 This is a circuit diagram of the third driving stage of a specific embodiment of the gate driving unit provided in this application. Fig.10 This is a circuit diagram of the fourth driving stage of a specific embodiment of the gate driving unit provided in this application. Fig.11 This is a circuit diagram of the fifth driving stage of a specific embodiment of the gate driving unit provided in the present application.

[0057] In the first stage (also called the sampling stage), the previous stage first pulse signal Pscan(n-1) is a low potential signal, the first jump signal line CK transmits a high potential signal, the second jump signal line XCK transmits a low potential signal, and the third jump signal line CK2 transmits a low potential signal. The second jump signal line XCK controls the first transistor T1 to be turned on, and the low potential signal line VGL controls the second transistor T2 to be turned on. The low potential pulse signal of the previous stage first pulse signal Pscan(n-1) is transmitted to the gate of the third transistor T3, the gate of the fourth transistor T4, and the first plate of the first storage unit C1 through the first transistor T1 and the second transistor T2 and stored; at the same time, the low potential signal controls the third transistor T3 to be turned on and the fourth transistor T4 to be turned off, and the high potential signal of the first jump signal line CK is output through the third transistor T3, so that the first pulse signal Pscan(n) outputs a high potential pulse. The third jump signal line CK2 controls the fifth transistor T5 to turn on, and the low-potential pulse signal of the previous first pulse signal Pscan(n-1) is charged into the first electrode plate of the second storage unit C2 through the fifth transistor T5 and stored. The first electrode plate of the third storage unit C3 stores a high-potential signal in the previous frame, controls the seventh transistor T7 to turn on, and the eighth transistor T8 to turn off. The low-potential signal on the low-potential signal line VGL is output through the seventh transistor T7, so that the second pulse signal Nscan(n) is output as a low-potential pulse. For details, please refer to Figure 7 , Figure 7 The solid line in the middle represents signal transmission, the dotted line represents no signal transmission, the red line represents high-potential signal transmission, and the blue line represents low-potential signal transmission.

[0058] In the second stage (also called the P output stage or the N output stage), the first pulse signal Pscan(n-1) of the previous stage is a high potential signal, the first jump signal line CK transmits a low potential signal, the second jump signal line XCK transmits a high potential signal, and the third jump signal line CK2 transmits a high potential signal. The second jump signal line XCK controls the first transistor T1 to be turned off, the low potential signal line VGL controls the second transistor T2 to remain turned on, the first plate of the first storage unit C1 stores a low potential voltage signal in the previous stage, thereby controlling the third transistor T3 to be turned on, and the fourth transistor T4 to be turned off. The first jump signal line CK transmits a low potential pulse signal through the third transistor T3, so that the first pulse signal Pscan(n) is output as a low potential pulse. At the same time, the third jump signal line CK2 controls the fifth transistor T5 to be turned off. At the same time, the first jump signal line CK controls the sixth transistor T6 to be turned off, and the low potential voltage stored in the first plate of the second storage unit C2 in the previous stage is charged to the first plate of the third storage unit C3 through the sixth transistor T6, and controls the eighth transistor T8 to be turned on, and the seventh transistor T7 to be turned off. The high potential signal line VGH outputs a high potential signal through the eighth transistor T8, so that the second pulse signal Nscan(n) is output as a high potential pulse. Figure 8 , Figure 8 The solid line in the middle represents signal transmission, the dotted line represents no signal transmission, the red line represents high-potential signal transmission, and the blue line represents low-potential signal transmission.

[0059] In the third stage (also called the N output stage or the P holding stage), the first pulse signal Pscan(n-1) of the previous stage is a high potential signal, the first jump signal line CK transmits a high potential signal, the second jump signal line XCK transmits a low potential signal, and the third jump signal line CK2 transmits a high potential signal. The second jump signal line XCK controls the first transistor T1 to be turned on, and the low potential signal line VGL controls the second transistor T2 to be turned on. The low potential pulse signal of the first pulse signal Pscan(n-1) of the previous stage is transmitted to the gate of the third transistor T3, the gate of the fourth transistor T4, and the first plate of the first storage unit C1 through the first transistor T1 and the second transistor T2 and stored. At the same time, the third transistor T3 is turned off and the fourth transistor T4 is turned on, that is, the fourth transistor T4 is working. The high potential signal of the high potential signal line VGH is output to the output end of the first output unit through the fourth transistor T4, and the working output of the fourth transistor T4 is maintained in the subsequent stage, so that the first pulse signal Pscan(n) maintains the output of the high potential pulse unchanged in the P holding stage after the second stage. The third jump signal line CK2 controls the fifth transistor T5 to be turned off, the first jump signal line CK controls the sixth transistor T6 to be turned off, the first electrode plate of the third storage unit C3 stores a low potential signal in the previous stage, thereby controlling the eighth transistor T8 to be turned on, and the seventh transistor T7 to be turned off, and the high potential signal line VGH outputs a high potential signal through the eighth transistor T8, so that the second pulse signal Nscan(n) is output as a high potential pulse. For details, please refer to Fig. 9 , Fig. 9 The solid line in the middle represents signal transmission, the dotted line represents no signal transmission, the red line represents high-potential signal transmission, and the blue line represents low-potential signal transmission.

[0060] In the fourth stage (also called the P hold stage or the N hold stage), the first pulse signal Pscan(n-1) of the previous stage is a high potential signal, the first jump signal line CK transmits a low potential signal, the second jump signal line XCK transmits a high potential signal, and the third jump signal line CK2 transmits a low potential signal. The second jump signal line XCK controls the first transistor T1 to be turned off, the low potential signal line VGL controls the second transistor T2 to be turned on, the first plate of the first storage unit C1 stores a high potential voltage in the previous stage, thereby controlling the third transistor T3 to remain turned off, the fourth transistor T4 to remain turned on, the high potential signal of the high potential signal line VGH is output to the output end of the first output unit through the fourth transistor T4, and the working output of the fourth transistor T4 is maintained in the subsequent stage, so that the first pulse signal Pscan(n) maintains the output of the high potential pulse unchanged in the P hold stage after the second stage. The third jump signal line CK2 controls the fifth transistor T5 to be turned on, and the first jump signal line CK controls the sixth transistor T6 to be turned on. In the N holding stage, the high potential voltage stored on the first plate of the first storage unit C1 in the previous stage is transmitted to the first plate of the second storage unit C2 through the fifth transistor T5 and stored, and then transmitted to the first plate of the third storage unit C3 through the sixth transistor T6 and stored. At the same time, the seventh transistor T7 is controlled to be turned on and the eighth transistor T8 is turned off. The low potential signal line VGL is output to the output end of the second output unit through the seventh transistor T7, so that the second pulse signal Nscan(n) is output as a low potential pulse, and the seventh transistor T7 is kept working in the subsequent stage, so that the second pulse signal Nscan(n) is kept output as a low potential pulse. For details, please refer to Fig.10 , Fig.10 The solid line in the middle represents signal transmission, the dotted line represents no signal transmission, the red line represents high-potential signal transmission, and the blue line represents low-potential signal transmission.

[0061] In the fifth stage (also called the P holding stage or the N holding stage), the first pulse signal Pscan(n-1) of the previous stage is a high potential signal, the first jump signal line CK transmits a high potential signal, the second jump signal line XCK transmits a low potential signal, and the third jump signal line CK2 transmits a high potential signal. The second jump signal line XCK controls the first transistor T1 to be turned on, and the low potential signal line VGL controls the second transistor T2 to be turned on. The low potential pulse signal of the first pulse signal Pscan(n-1) of the previous stage is transmitted to the gate of the third transistor T3, the gate of the fourth transistor T4 and the first plate of the first storage unit C1 through the first transistor T1 and the second transistor T2 and stored. At the same time, the third transistor T3 is turned off and the fourth transistor T4 is turned on, that is, the fourth transistor T4 is working. The high potential signal of the high potential signal line VGH is output to the output end of the first output unit through the fourth transistor T4, and the working output of the fourth transistor T4 is maintained in the subsequent stage, so that the first pulse signal Pscan(n) keeps outputting a high potential pulse unchanged in the P holding stage after the second stage. The third jump signal line CK2 controls the fifth transistor T5 to be turned off, and the first jump signal line CK controls the sixth transistor T6 to be turned off. In the N holding stage, the first electrode plate of the third storage unit C3 stores a high potential signal in the previous stage, thereby controlling the seventh transistor T7 to be turned on and the eighth transistor T8 to be turned off. The low potential signal line VGL is output to the output end of the second output unit through the seventh transistor T7, so that the second pulse signal Nscan(n) is output as a low potential pulse, and the seventh transistor T7 is kept working in the subsequent stage, so that the second pulse signal Nscan(n) is kept output as a low potential pulse. For details, please refer to Fig.11 , Fig.11 The solid line in the middle represents signal transmission, the dotted line represents no signal transmission, the red line represents high-potential signal transmission, and the blue line represents low-potential signal transmission.

[0062] Among them, the sampling stage is the first stage, the P output stage includes the second stage, the N output stage includes the second stage and the third stage, the P holding stage includes at least the third stage to the fifth stage, and the N holding stage includes at least the fourth stage and the fifth stage. It should be noted that the P holding stage is the stage after the third stage (including the third stage, the fourth stage, the fifth stage, etc.), the N holding stage is the stage after the fourth stage (including the fourth stage, the fifth stage, etc.), and the timing diagrams of the subsequent sixth stage and seventh stage refer to the timing diagrams of the fourth stage and the fifth stage, which are not limited here.

[0063] The N output stage is controlled by the width of the high potential pulse signal output by the third jump signal line CK2.

[0064] The present application also provides a display panel. Fig.12 , Fig.12This is a schematic diagram of the structure of an embodiment of a display panel provided by the present application. Fig.12 As shown, the display panel 100 includes a display area 101 and a non-display area 102. The non-display area 102 on one side or opposite sides of the display panel 100 is provided with a gate driving circuit as described in any of the above embodiments, and the gate driving circuit includes a plurality of cascaded gate driving units. The gate driving circuit sequentially transmits a first scanning signal and a second scanning signal to each row of pixel units in the display area 101. The first scanning signal is a first pulse signal Pscan(n) of a low potential pulse with a normal high potential, and the second scanning signal is a second pulse signal Nscan(n) of a high potential pulse with a normal low potential.

[0065] Furthermore, the driving circuit in each pixel unit of the display area 101 includes an N-type transistor and a P-type transistor. By sequentially outputting the first scanning signal and the second scanning signal to the driving unit of the pixel unit, the requirement of outputting different scanning signals to different types of transistors (TFTs) in the pixel unit is met.

[0066] The present application designs the above-mentioned gate drive circuit to minimize the use of input signals while enabling a GOA circuit to output different scanning signals to different types of transistors (TFTs) in the pixel unit, thereby saving circuit expenses and reducing the border width.

[0067] The above are merely embodiments of the present application and are not intended to limit the patent scope of the present application. Any equivalent structure or equivalent process transformation made using the contents of the present application specification and drawings, or directly or indirectly applied in other related technical fields, are also included in the patent protection scope of the present application.

Claims

1. A gate drive circuit, characterized in that: include: A plurality of cascaded gate drive units, each of the gate drive units at least comprising: A first output unit, configured to output a first pulse signal; wherein the first pulse signal is a low potential pulse signal with a normal high potential; A second output unit, used to output a second pulse signal; wherein the second pulse signal is a high potential pulse signal with a normal low potential; A cascade unit, connected to the first output unit of the gate driving unit of the previous stage, and used for receiving the first pulse signal of the previous stage; A first driving unit is provided between the cascade unit and a control end of the first output unit, and is used for providing a driving signal to the first output unit according to a cascade signal of the cascade unit, so that the first output unit outputs the first pulse signal; A second driving unit is arranged between the cascade unit and the control end of the second output unit, and is used to provide a driving signal to the second output unit according to the cascade signal of the cascade unit, so that the second output unit outputs the second pulse signal, and makes the second output unit output a high-potential pulse of the second pulse signal when the first output unit outputs a low-potential pulse of the first pulse signal.

2. The gate driving circuit according to claim 1, characterized in that: A pulse width of the second pulse signal is greater than a pulse width of the first pulse signal.

3. The gate drive circuit according to claim 1 or 2, characterized in that: The first output unit includes a first sub-output unit and a first pulse output holding unit; The input end of the first sub-output unit is connected to the first jump signal line, and the control end of the first sub-output unit is connected to the output end of the first driving unit, and is used to output the high potential pulse and the low potential pulse of the first pulse signal according to the driving signal provided by the first driving unit; The input end of the first pulse output holding unit is connected to the high potential signal line, and the control end of the first pulse output holding unit is connected to the output end of the first driving unit, and is used to keep outputting the high potential pulse of the first pulse signal according to the driving signal provided by the first driving unit; The second output unit includes a second sub-output unit and a second pulse output holding unit; The input end of the second sub-output unit is connected to the high potential signal line, and the control end of the second sub-output unit is connected to the output end of the second driving unit, for outputting a high potential pulse of the second pulse signal according to the driving signal provided by the second driving unit; The input end of the second pulse output holding unit is connected to the low-potential signal line, and the control end of the second pulse output holding unit is connected to the output end of the second driving unit, for maintaining the output of the low-potential pulse of the second pulse signal according to the driving signal provided by the second driving unit.

4. The gate driving circuit according to claim 3, characterized in that: The first driving unit comprises: a first storage unit, wherein a first electrode plate of the first storage unit is connected to an output end of the cascade unit, a control end of the first sub-output unit, and a control end of the first pulse output holding unit, and a second electrode plate of the first storage unit is connected to an output end of the first output unit, and is used to store a voltage signal charged by the cascade unit and control the first sub-output unit or the first pulse output holding unit to work according to the stored voltage signal; A first charging control unit is disposed between the cascade unit and the first electrode plate of the first storage unit, and is used to control the cascade unit to charge the voltage signal into the first storage unit.

5. The gate driving circuit according to claim 4, characterized in that: The control end of the first charging control unit is connected to the low potential signal line.

6. The gate driving circuit according to claim 5, characterized in that: The second driving unit comprises: A second storage unit, wherein a first electrode plate of the second storage unit is connected to an output end of the cascade unit and an input end of the first charging control unit, and a second electrode plate of the second storage unit is connected to the low potential signal line, and is used to store a voltage signal charged by the cascade unit or the first storage unit; a second charging control unit, which is disposed between the output end of the cascade unit and / or the input end of the first charging control unit and the second storage unit, and is used to control the cascade unit and / or the first storage unit to charge a voltage signal into the second storage unit; a third storage unit, wherein a first electrode plate of the third storage unit is connected to a first electrode plate of the second storage unit, a control end of the second sub-output unit, and a control end of the second pulse output holding unit, and a second electrode plate of the third storage unit is connected to the high-potential signal line, and is used to store a voltage signal charged in the second storage unit and control the second sub-output unit or the second pulse output holding unit to work according to the stored voltage signal; A third charging control unit is arranged between the first electrode plate of the second storage unit and the third storage unit, the control end of the second sub-output unit, and the control end of the second pulse output holding unit, and is used to control the second storage unit to charge the voltage signal into the first electrode plate of the third storage unit.

7. The gate driving circuit according to claim 6, characterized in that: The control end of the cascade unit is connected to the second jump signal line; The signal jumping frequency of the second jumping signal line is the same as that of the first jumping signal line, but the phase is opposite.

8. The gate driving circuit according to claim 7, characterized in that: The control end of the second charging control unit is connected to the third jump signal line; Wherein, the high potential signal pulse width on the third jump signal line is greater than the low potential signal pulse width on the first jump signal line or the high potential signal pulse width on the second jump signal line; The high potential signal pulse width on the third jump signal line is the same as the high potential pulse width of the second pulse signal.

9. The gate driving circuit according to claim 8, characterized in that: The control end of the third charging control unit is connected to the first jump signal line.

10. A display panel, characterized in that: The display panel comprises the gate driving circuit according to any one of claims 1 to 9.

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