Memory device and method of operating sot-MRAM cell matrix

Abstract

The embodiment of the invention provides a memory device and a method for operating a SOT-MRAM cell matrix. In a matrix of SOT-MRAM cells, a first row is selected for writing and a second row is selected for reading. The first SOT-MRAM cells of the first row and the second SOT-MRAM cells of the second row are in a first column, and the third SOT-MRAM cells of the first row and the fourth SOT-MRAM cells of the second row are in a second column. And the directions of currents written into the first SOT-MRAM unit and the third SOT-MRAM unit are opposite. The first sense amplifier is configured to detect a voltage change of a first read bit line charged with a first read current in the second SOT-MRAM cell. The second sense amplifier is configured to detect a voltage change of a second read bit line discharged with a second read current in the fourth SOT-MRAM cell.

Description

Technical Field

[0001] Embodiments of the present invention generally relate to the field of electronic circuits, and more particularly, to memory devices and methods of operating a SOT-MRAM cell matrix. Background Art

[0002] MRAM ("Magnetoresistive Random Access Memory") is a non-volatile memory technology that uses magnetic states to store information. In MRAM, information is stored by controlling the magnetic orientation of a ferromagnetic material. The basic structure of an MRAM cell includes a magnetic tunnel junction, which includes two ferromagnetic layers separated by a tunnel barrier layer. The resistance of the magnetic tunnel junction depends on the relative arrangement of the magnetic polarizations of the two ferromagnetic layers. In spin-orbit torque MRAM ("SOT-MRAM"), a conductive layer is deposited near the magnetic tunnel junction in the memory cell, and a current flows through the conductive layer to generate a spin-orbit torque that is used to manipulate the magnetic state of the magnetic tunnel junction of the memory cell. Summary of the invention

[0003] An embodiment of the present invention provides a memory device, comprising: a spin-orbit torque magnetic memory SOT-MRAM cell matrix, each SOT-MRAM cell having a magnetic tunnel junction MTJ structure and a spin-orbit torque SOT conductor, wherein each SOT-MRAM cell in a first row is set to a write mode, and each SOT-MRAM cell in a second row is set to a read mode; a first write bit line, a first source bit line, and a first read bit line, coupled to a first SOT-MRAM cell and a second SOT-MRAM in a first column, wherein the first write bit line and the first source bit line are configured to have a first current, and the first current passes through the SOT conductor in the first SOT-MRAM cell in the first row; and a first sense amplifier, configured to detect a first current on the first read bit line. a second write bit line, a second source bit line, and a second read bit line coupled to a third SOT-MRAM cell and a fourth SOT-MRAM in a second column, the second write bit line and the second source bit line being configured to have a second current passing through the SOT conductor in the third SOT-MRAM cell in the first row, wherein the first current and the second current are opposite in flow direction; and a second sense amplifier configured to detect a voltage change on the second read bit line when the second read bit line is discharged with the second read current passing through the MTJ structure of the fourth SOT-MRAM cell in the second row.

[0004] Another embodiment of the present invention provides a memory device, comprising: a matrix of spin-orbit torque magnetic memory SOT-MRAM cells, each SOT-MRAM cell having a write port, a read port, and a source port; a first write bit line and a first read bit line, associated with a first column of SOT-MRAM cells, wherein the write port of each SOT-MRAM cell in the first column is connected to the first write bit line, and the read port of each SOT-MRAM cell in the first column is connected to the first read bit line; a second write bit line and a second read bit line, associated with a second column of SOT-MRAM cells, wherein the write port of each SOT-MRAM cell in the second column is connected to the first write bit line, and the read port of each SOT-MRAM cell in the second column is connected to the first read bit line; A write port is connected to the second write bit line, and the read port of each SOT-MRAM cell in the second column is connected to the second read bit line; a write circuit is configured to output a first current to the first write bit line, and is configured to output a second current to the second write bit line, wherein the first current and the second current are opposite in flow direction; a first sense amplifier is configured to detect a voltage change on the first read bit line when the first read bit line is charged by the first sense amplifier; and a second sense amplifier is configured to detect a voltage change on the second read bit line while the second read bit line is discharged after the second read bit line is precharged by the second sense amplifier.

[0005] Another embodiment of the present invention provides a method for operating a spin-orbit torque magnetic memory SOT-MRAM cell matrix, each SOT-MRAM cell having a magnetic tunnel junction MTJ structure and a spin-orbit torque SOT conductor, the method comprising: applying a voltage to drive each SOT-MRAM cell in a first row into a write mode; applying a voltage to drive each SOT-MRAM cell in a second row into a read mode; generating a first current through the SOT conductor in a first SOT-MRAM cell in the first row; when the first read bit line is charged using the first read current through the MTJ structure in a second SOT-MRAM cell in the second row, detecting the first read bit line by a first sense amplifier. a voltage change on a read bit line, wherein the first SOT-MRAM cell and the second SOT-MRAM cell are located in a first column; generating a second current through the SOT conductor in a third SOT-MRAM cell in the first row, wherein the first current and the second current are in opposite directions of flow; and detecting the voltage change on the second read bit line by a second sense amplifier when the second read bit line is discharged with a second read current through the MTJ structure in a fourth SOT-MRAM cell in the second row after the second read bit line is precharged by the second sense amplifier, wherein the third SOT-MRAM cell and the fourth SOT-MRAM cell are located in a second column. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Various aspects of the present invention will be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, the various components are not drawn to scale. In fact, the sizes of the various components may be arbitrarily increased or reduced for clarity of discussion.

[0007] Figure 1A is a circuit diagram of an integrated circuit having a SOT-MRAM cell according to some embodiments.

[0008] Figure 1B According to some embodiments Figure 1A A circuit diagram of an example implementation of a SOT MRAM used in an integrated circuit.

[0009] FIG. 2A to FIG. 2B is a circuit diagram of a sense amplifier coupled to a SOT-MRAM cell and a reference cell according to some embodiments.

[0010] Figure 3 is a timing diagram of various signals in an integrated circuit having a SOT-MRAM cell according to some embodiments.

[0011] Figure 4is a flow chart of a method of manufacturing a memory device according to some embodiments. DETAILED DESCRIPTION

[0012] The present invention provides many different embodiments or examples for realizing the different features of the present disclosure. Specific examples of components and arrangements are described below to simplify the present invention. Of course, these are merely examples and are not intended to limit the present invention. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are formed in direct contact, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component may not be in direct contact. In addition, the present invention may repeat reference numerals and / or characters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0013] Furthermore, for ease of description, spatially relative terms such as "below," "beneath," "lower," "above," "upper," etc. may be used herein to describe the relationship of one element or component to another (or additional) elements or components as shown in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein should likewise be interpreted accordingly.

[0014] In some embodiments, in a matrix of SOT-MRAM cells, each SOT-MRAM cell has a magnetic tunnel junction ("MTJ") structure and a spin-orbit torque ("SOT") conductor. When each SOT-MRAM cell in a first row is driven into a write mode and each SOT-MRAM cell in a second row is driven into a read mode, as a first current is generated to pass through the SOT conductor in the first SOT-MRAM cell in the first row, when the first read bit line is charged with the first read current through the MTJ structure in the second SOT-MRAM cell in the second row, the first sense amplifier is configured to detect a voltage change on the first read bit line. The first SOT-MRAM cell and the second SOT-MRAM cell are located in a first column. In addition, as a second current is generated to pass through the SOT conductor in the third SOT-MRAM cell in the first row, after the second read bit line is precharged by the second sense amplifier, when the second read bit line is discharged with the second read current through the MTJ structure in the fourth SOT-MRAM cell in the second row, the second sense amplifier is configured to detect a voltage change on the second read bit line. The third SOT-MRAM cell and the fourth SOT-MRAM cell are located in the second column. Here, the first current through the SOT conductor in the first SOT-MRAM cell and the second current through the SOT conductor in the third SOT-MRAM cell flow in opposite directions.

[0015] Figure 1A is a circuit diagram of an integrated circuit 80 having a SOT-MRAM cell according to some embodiments. Figure 1A In the embodiment, the SOT-MRAM cells are arranged in a matrix having N rows and M columns, where N and M are positive integers (e.g., N=1024 and M=4096). Figure 1B , which is an example implementation of a SOT-MRAM cell. Four example SOT-MRAM cells (i.e., 100ik, 100im, 100jk, and 100jm) in the matrix are explicitly shown in the figure, while the remaining SOT-MRAM cells in the matrix are not explicitly shown in the figure. SOT-MRAM cells 100ik and 100im are located in the i-th row of the matrix, while SOT-MRAM cells 100jk and 100jm are located in the j-th row of the matrix. SOT-MRAM cells 100ik and 100jk are located in the k-th column of the matrix, while SOT-MRAM cells 100im and 100jm are located in the m-th column of the matrix.

[0016] The integrated circuit 80 includes a plurality of write word lines and a plurality of read word lines. Two examples of write word lines (i.e., WWL[i] and WWL[j]) and two examples of read word lines (i.e., RWL[i] and RWL[j]) are explicitly shown in the figure, and each write word line extending in a direction parallel to the row is associated with a row of SOT-MRAM cells, so the number of write word lines matches the number of rows. Each read word line extending in a direction parallel to the row is also associated with a row of SOT-MRAM cells, so the number of read word lines also matches the number of rows.

[0017] Integrated circuit 80 includes a plurality of write bit lines, a plurality of read bit lines, and a plurality of source bit lines. Two examples of write bit lines (i.e., WBL[k], WBL[m]), two examples of read bit lines (i.e., RBL[k] and RBL[m]), and two examples of source bit lines (i.e., SL[k] and SL[m]) are explicitly shown in the figure. Each write bit line, each read bit line, and each source bit line extend in a direction parallel to the columns. Each write bit line is associated with a column of SOT-MRAM cells, so the number of write bit lines matches the number of columns. Each read word line is associated with a column of SOT-MRAM cells, so the number of read bit lines matches the number of columns. Each source bit line is associated with a column of SOT-MRAM cells, so the number of source bit lines matches the number of columns.

[0018] Each SOT-MRAM cell, for example Figure 1B The SOT-MRAM cell 100 in is a memory device that uses magnetic states to store information. The SOT-MRAM cell 100 includes a magnetic tunnel junction structure ("MTJ structure") 150, a spin-orbit torque conductor ("SOT conductor") 160, a write switch transistor S1, and a read switch transistor S2. The MTJ structure 150 is coupled to a read bit line RBL through a channel of the read switch transistor S2, and the gate of the read switch transistor S2 is connected to a read word line RWL. The SOT conductor 160 has a first terminal 161, which is coupled to a write bit line WBL through a channel of the write switch transistor S1, and the gate of the write switch transistor S1 is connected to a write word line WWL. The SOT conductor 160 has a second terminal 162 that is directly connected to a source bit line SL.

[0019] The channel terminal of the write switch transistor S1 connected to the write bit line WBL forms the write port 110 of the SOT-MRAM cell 100. The channel terminal of the read switch transistor S2 connected to the read bit line RBL forms the read port 120 of the SOT-MRAM cell 100. The second terminal 162 of the SOT conductor 160 forms the source port 130 of the SOT-MRAM cell 100.

[0020] In the SOT-MRAM cell 100, the MTJ structure 150 has a free layer 152, a pinned layer 158, and a tunnel barrier layer 155. The tunnel barrier layer 155 is sandwiched between the free layer 152 and the pinned layer 158. Each of the free layer 152 and the pinned layer 158 is a conductive layer made of a ferromagnetic material, but the tunnel barrier layer 155 is a thin insulating layer made of a high resistance material. The thickness of the tunnel barrier layer 155 is thin enough to allow electrons quantum mechanically to tunnel through the thin insulating layer between the two ferromagnetic layers. The tunneling probability is affected by the relative arrangement of the magnetic moments of the two ferromagnetic layers.

[0021] When the magnetic moment of the pinned layer 158 is normally oriented, the magnetic moment of the free layer 152 is manipulated by an external magnetic field, an applied current, or other means. When the magnetic moment of the free layer 152 is parallel to the magnetic moment of the pinned layer 158, the tunneling probability is higher, resulting in a lower resistance. Conversely, when the magnetic moment of the free layer 152 is antiparallel to the magnetic moment of the pinned layer 158, the tunneling probability is reduced, resulting in a higher resistance. Two different resistance values ​​based on the relative orientation of the magnetic moments of the two ferromagnetic layers are used to represent binary information 0 ("0") and binary information 1 ("1") in the MRAM cell.

[0022] In the SOT-MRAM cell 100, the magnetic moment of the free layer 152 is controlled by a current passing through a SOT conductor 160, which is deposited near the free layer 152. The free layer 152 is also in conductive contact with the SOT conductor 160. When a current flows through the SOT conductor 160, the spin-orbit torque effect induces a flow of electron spins within the SOT conductor 160. The spin-orbit torque generated by the spin current applies a torque to the magnetic moment of the free layer 152 in the MTJ structure 150. Under conditions where the spin-orbit torque becomes sufficiently strong, the magnetic moment in the free layer 152 can be redirected or flipped in the magnetization direction by the spin-orbit torque. A sufficiently large current passing through the SOT conductor 160 determines the direction of the magnetic moment in the free layer 152. Since the resistance of the magnetic tunnel junction depends on the direction of the magnetic moment in the free layer 152, the write current applied to the SOT conductor 160 provides a mechanism to set the resistance of the magnetic tunnel junction, thereby writing binary information into the MRAM cell.

[0023] In the SOT-MRAM cell 100, a write current is applied to the SOT conductor 160 through the channel of the write switch transistor S1 coupled to the first terminal 161 of the SOT conductor 160. The resistance value of the magnetic tunnel junction is detected based on the value of the current simultaneously transmitted to the SOT conductor 160 through the channel of the read switch transistor S2 and the MTJ structure 150 in series.

[0024] The SOT-MRAM cell 100 can operate in three operation modes: a write mode, a read mode, and a separation mode. To set the SOT-MRAM cell 100 to the write mode, a write-on voltage on the write word line WWL is applied to the gate of the write switch transistor S1 to drive the write switch transistor S1 to a conductive state, and a read-off voltage on the read word line RWL is applied to the gate of the read switch transistor S2 to drive the read switch transistor S2 to a non-conductive state. To set the SOT-MRAM cell 100 to the read mode, a read-on voltage on the read word line RWL is applied to the gate of the read switch transistor S2 to drive the read switch transistor S2 into a conductive state, and a write-off voltage on the write word line WWL is applied to the gate of the write switch transistor S1 to drive the write switch transistor S1 into a non-conductive state. To set the SOT-MRAM cell 100 to the separation mode, a write-off voltage on the write word line WWL is applied to the gate of the write switch transistor S1 to drive the write switch transistor S1 into a non-conducting state, and a read-off voltage on the read word line RWL is applied to the gate of the read switch transistor S2 to drive the read switch transistor S2 into a non-conducting state.

[0025] The write operation to the SOT-MRAM cell 100 includes setting the SOT-MRAM cell 100 to a write mode. During the write operation, in response to the write switch transistor S1 being driven into a conductive state, the first terminal 161 of the SOT conductor 160 is conductively connected to the write bit line WBL through the channel of the write switch transistor S1, and the voltage difference between the voltage on the write bit line WBL and the voltage on the source bit line SL determines the direction of the current flowing in the SOT conductor 160. In some embodiments, in order to write a first binary value (e.g., a value of "1") to the SOT MRAM cell 100, a positive voltage VW is applied to the write bit line WBL and a ground voltage VGND is applied to the source bit line SL, which causes a positive current to flow from the first terminal 161 of the SOT conductor 160 to the second terminal 162. To write a second binary value (e.g., value "0") to the SOT-MRAM cell 100, a ground voltage VGND is applied to the write bit line WBL and a positive voltage VW is applied to the source bit line SL, which causes a negative current to flow from the second terminal 162 of the SOT conductor 160 to the first terminal 161 (i.e., equivalently, a positive current to flow from the first terminal 161 to the second terminal 162). The positive current flowing from the first terminal 161 to the second terminal 162 and the negative current flowing from the second terminal 162 to the first terminal 161 are opposite in flow direction.

[0026] A read operation on the SOT-MRAM cell 100 includes setting the SOT-MRAM cell 100 to a read mode. During the read operation, in response to the read switch transistor S2 being driven into a conductive state, the MTJ structure 150 is conductively connected to the read bit line RBL through the channel of the read switch transistor S2, and a read current flowing from the read bit line RBL to the source bit line SL through the MTJ structure 150 and the SOT conductor 160 is detected, thereby measuring the resistance of the MTJ structure 150 and reading the binary value stored in the SOT-MRAM cell 100.

[0027] The SOT-MRAM cell 100 is set to a separation mode to prevent the MTJ structure 150 in the SOT-MRAM cell 100 from being affected by electrical signals on various bit lines, and to prevent the MTJ structure 150 in the SOT-MRAM cell 100 from inadvertently affecting electrical signals on various bit lines. The electrical signals on the various bit lines include voltages and / or currents carried by the write bit line WBL, the read bit line RBL, or the source bit line SL.

[0028] In an integrated circuit 80 having a matrix of SOT-MRAM cells, as Figure 1A As shown, each row of SOT-MRAM cells is associated with a corresponding write word line and a corresponding read word line. The gate of the write switch transistor S1 in each SOT-MRAM cell in the row is connected to the corresponding write word line WWL, and the gate of the read switch transistor S2 in each SOT-MRAM cell in the row is connected to the corresponding read word line RWL.

[0029] For example, the gate of the write switch transistor S1 in each SOT-MRAM cell in the i-th row is connected to the write word line WWL[i], and the gate of the read switch transistor S2 in each SOT-MRAM cell in the i-th row is connected to the read word line RWL[i]. Similarly, the gate of the write switch transistor S1 in each SOT-MRAM cell in the j-th row is connected to the write word line WWL[j], and the gate of the read switch transistor S2 in each SOT-MRAM cell in the j-th row is connected to the read word line RWL[j].

[0030] In an integrated circuit 80 having a matrix of SOT-MRAM cells, as Figure 1AAs shown, each column of the SOT-MRAM cell is associated with a corresponding write bit line, a corresponding read bit line, and a source bit line. The first terminal of the SOT conductor in each SOT-MRAM cell in the column is coupled to the corresponding write bit line through the channel of the write switch transistor S1. The second terminal of the SOT conductor in each SOT-MRAM cell in the column is directly connected to the corresponding source bit line SL. The MTJ structure in each SOT-MRAM cell in the column is coupled to the corresponding read bit line through the channel of the read switch transistor S2.

[0031] For example, the first terminal of the SOT conductor in each SOT-MRAM cell in the kth column is coupled to the write bit line WBL[k] through the channel of the write switch transistor S1, the second terminal of the SOT conductor in each SOT-MRAM cell in the kth column is directly connected to the source bit line SL[k], and the MTJ structure in each SOT-MRAM cell in the kth column is coupled to the read bit line RBL[k] through the channel of the read switch transistor S2. Similarly, the first terminal of the SOT conductor in each SOT-MRAM cell in the mth column is coupled to the write bit line WBL[m] through the channel of the write switch transistor S1, the second terminal of the SOT conductor in each SOT-MRAM cell in the mth column is directly connected to the source bit line SL[m], and the MTJ structure in each SOT-MRAM cell in the mth column is coupled to the read bit line RBL[m] through the channel of the read switch transistor S2.

[0032] By selecting a row of SOT-MRAM cells to write once, the Figure 1A A write operation is performed on the SOT-MRAM cell matrix in the matrix. Assuming that the integer N is the number of rows in the matrix, for positive integers n≤N, the nth row of SOT-MRAM cells is selected for writing by setting the SOT-MRAM cells in the nth row to a write mode, whereby the nth row becomes the selected row subject to the write operation. In some embodiments, in addition to setting the SOT-MRAM cells in the nth row to a write mode, the SOT-MRAM cells in all the remaining N-1 rows are set to a separation mode. In some alternative embodiments, in addition to setting the SOT-MRAM cells in the nth row to a write mode, the SOT-MRAM cells in another row are set to a read mode, and the SOT-MRAM cells in all the remaining N-2 rows are set to a separation mode. In the example Figure 1A In the example shown, when the SOT-MRAM cells in the i-th row (ie, n=i) are set to write mode and the SOT-MRAM cells in the j-th row are set to read mode, all SOT-MRAM cells in the remaining N-2 rows are set to separation mode.

[0033] exist Figure 1AIn FIG. 8 , the selection of a selected row for a write operation and the selection of a selected row for a read operation are controlled by WL driver and control circuits 82 and 84 .

[0034] During a write operation on a selected row of SOT-MRAM cells, a write operation is performed on each individual SOT-MRAM cell in the selected row by applying a desired voltage on the write bit line WBL and / or source bit line SL coupled to the individual SOT-MRAM cells. The voltage required on the write bit line WBL and / or source bit line SL depends on the binary value to be written to the individual SOT-MRAM cells. Figure 1A In one example shown, the selected row for the write operation is the i-th row, and examples of the SOT-MRAM cells in the selected row for the write operation include the SOT-MRAM cell 100ik in the k-th column and the SOT-MRAM cell 100im in the m-th column. In order to write a binary value "0" to the SOT-MRAM cell 100ik, a ground voltage VGND is applied to the write bit line WBL[k] coupled to the SOT-MRAM cell 100ik, and a positive voltage VW is applied to the source bit line SL[k] coupled to the SOT-MRAM cell 100ik, thereby inducing a current to flow from the source bit line SL[k] to the write bit line WBL[k]. In order to write a binary value "1" into the SOT-MRAM cell 100im, a positive voltage VW is applied to the write bit line WBL[m] coupled to the SOT-MRAM cell 100im, and a ground voltage VGND is applied to the source bit line SL[m] coupled to the SOT-MRAM cell 100im, thereby inducing a current flowing from the write bit line WBL[m] to the source bit line SL[m].

[0035] exist Figure 1A In the embodiment, the required voltages applied to various write bit lines and various source bit lines SL are provided by the write circuit 85. The current generated by the write circuit 85 includes a current flowing from the source bit line SL[k] to the write bit line WBL[k] and a current flowing from the write bit line WBL[m] to the source bit line SL[m].

[0036] By selecting one row of SOT-MRAM cells at a time, the Figure 1AA read operation of the SOT-MRAM cell matrix in . Assuming that the integer N is the number of rows in the matrix, for positive integers n≤N, the nth row of SOT-MRAM cells is selected for reading by setting the SOT-MRAM cells in the nth row to a read mode, whereby the nth row becomes the selected row subject to the read operation. In some embodiments, in addition to setting the SOT-MRAM cells in the nth row to a read mode, the SOT-MRAM cells in all the remaining N-1 rows are set to a separation mode. In some alternative embodiments, in addition to setting the SOT-MRAM cells in the nth row to a read mode, the SOT-MRAM cells in another row are set to a write mode, and the SOT-MRAM cells in all the remaining N-2 rows are set to a separation mode. In the case Figure 1A In the example shown, when the SOT-MRAM cells in the jth row (ie, n=j) are set to read mode and the SOT-MRAM cells in the ith row are set to write mode, all SOT-MRAM cells in the remaining N-2 rows are set to separation mode.

[0037] During a read operation performed on the SOT-MRAM cells of the selected row, a read operation is performed on each SOT-MRAM cell in the selected row by detecting a voltage change on a read bit line RBL coupled to the SOT-MRAM cells of the selected row, and the voltage change is detected by a sense amplifier SA coupled to the read bit line RBL. Figure 1A In one example shown, the selected row for the read operation is the jth row, and examples of the SOT-MRAM cells for the read operation of the selected row include the SOT-MRAM cell 100jk in the kth column and the SOT-MRAM cell 100jm in the mth column. The read operation on the SOT-MRAM cell 100jk is performed by detecting a voltage change on the read bit line RBL[k] using the sense amplifier SA[k], as shown in FIG. Figure 2A The read operation of the SOT-MRAM cell 100jm is performed by detecting the voltage change on the read bit line RBL[m] using the sense amplifier SA[m], as shown in FIG. Figure 2B As shown schematically in FIG.

[0038] FIG. 2A to FIG. 2B is a circuit diagram of a sense amplifier coupled to a SOT-MRAM cell and a reference cell according to some embodiments. Each sense amplifier (e.g., Figure 2A SA[k] or Figure 2BSA[m] in FIG. 1 includes PMOS transistors TP1 and TP2, NMOS transistors TN1 and TN2, and a differential amplifier LSA. The gates of the PMOS transistors TP1 and TP2 are connected together and configured to receive a precharge enable signal. The gates of the NMOS transistors TN1 and TN2 are connected together and configured to receive a precharge enable signal PRE0. The channels of the PMOS transistor and the NMOS transistor TN1 are connected together at a connection node INP, which is also connected to a first input terminal of the differential amplifier LSA. The channel of the PMOS transistor TP2 is connected to the channel of the NMOS transistor TN2 at a connection node INN, which is also connected to a second input terminal of the differential amplifier LSA.

[0039] The connection node INP is coupled to the read bit line (eg, Figure 2A RBL[k] in , or Figure 2B The connection node INN is coupled to the reference bit line RBL[Ref] through the channel of the coupling transistor TC2. The channel of the coupling transistor TR1, the reference cell Ref_Cell, and the channel of the coupling transistor TR1 are connected in series between the channel of the coupling transistor TC2 and the constant voltage node (maintained at Figure 2A The voltage VW and Figure 2B In some embodiments, the reference cell Ref_Cell is used with Figure 1A The SOT-MRAM cell 100 has the same cell structure as that of the SOT-MRAM cell 100 .

[0040] exist Figure 2A In the embodiment, during the read operation of the SOT-MRAM cell 100jk, each of the coupling transistor TC1 and the read switch transistor S2 is in the on state, and the bit line capacitance (not shown in the figure) associated with the read bit line RBL[k] is charged by the current through the MTJ structure in the SOT-MRAM cell 100jk, which causes a voltage change at the connection node INP coupled to the first input terminal of the differential amplifier LSA. In addition, during the read operation, each of the coupling transistors TC2, TR1 and TR2 is also in the on state, and the bit line capacitance (not shown in the figure) associated with the reference bit line RBL[Ref] is charged by the current through the MTJ structure in the reference cell Ref_Cell, which causes a voltage change at the connection node INN connected to the second input terminal of the differential amplifier LSA.

[0041] The voltage change at the first input terminal of the differential amplifier LSA is related to the resistance value of the MTJ structure in the SOT-MRAM cell 100jk: the smaller the resistance value, the faster the voltage change at the first input terminal of the differential amplifier LSA. The voltage change at the first input terminal of the differential amplifier LSA is compared with the voltage change at the second input terminal of the differential amplifier LSA, where the voltage change at the second input terminal is related to the resistance value of the MTJ structure in the reference cell Ref_Cell. That is, the output voltage at the output SO of the differential amplifier LSA is related to the difference between the resistance of the MTJ structure in the SOT-MRAM cell 100jk and the resistance of the MTJ structure in the reference cell Ref_Cell. Based on the output voltage at the output SO of the differential amplifier LSA, the binary value stored in the SOT-MRAM cell 100jk is read out.

[0042] exist Figure 2B In the embodiment, the read operation on the SOT-MRAM cell 100jm includes two steps. In the first step, the bit line capacitance (not shown in the figure) associated with the read bit line RBL[m] is precharged to a predetermined value. In the second step, the voltage discharge on the bit line capacitance (not shown in the figure) associated with the read bit line RBL[m] is detected by the sense amplifier SA[m].

[0043] In one example, during a first step of a read operation on the SOT-MRAM cell 100jm, each of the NMOS transistors TN1 and TN2 is driven to a non-conductive state using a precharge enable signal PRE0, and then each of the PMOS transistors TP1 and TP2 is driven to a conductive state using a precharge enable signal PRE, and a bit line capacitance associated with the read bit line RBL[m] is precharged to a voltage equal to the first power supply voltage VDD.

[0044] During the second step of the read operation on the SOT-MRAM cell 100jm, as shown in FIG. Figure 2B As shown, each of the coupling transistor TC1 and the read switch transistor S2 is in the on state, and the bit line capacitance (not shown in the figure) associated with the read bit line RBL[m] is discharged by the current through the MTJ structure in the SOT-MRAM cell 100jm, which causes a voltage change at the connection node INP coupled to the first input terminal of the differential amplifier LSA. In addition, during the second step of the read operation, each of the coupling transistors TC2, TR1 and TR2 is also in the on state, and the bit line capacitance (not shown in the figure) associated with the reference bit line RBL[Ref] is charged by the current through the MTJ structure in the reference cell Ref_Cell, which causes a voltage change at the connection node INN connected to the second input terminal of the differential amplifier LSA.

[0045] During the second step of the read operation on the SOT-MRAM cell 100jm, the voltage change at the first input terminal of the differential amplifier LSA is related to the resistance value of the MTJ structure in the SOT-MRAM cell 100jm: the smaller the resistance value, the faster the voltage change at the first input terminal of the differential amplifier LSA. The voltage change at the first input terminal of the differential amplifier LSA is compared with the voltage change at the second input terminal of the differential amplifier LSA, where the voltage change at the second input terminal is related to the resistance value of the MTJ structure in the reference cell Ref_Cell. That is, the output voltage at the output SO of the differential amplifier LSA is related to the difference between the resistance of the MTJ structure in the SOT-MRAM cell 100jm and the resistance of the MTJ structure in the reference cell Ref_Cell. Based on the output voltage at the output SO of the differential amplifier LSA, the binary value stored in the SOT-MRAM cell 100jm is read out.

[0046] Figure 3 is a timing diagram of various signals in an integrated circuit having a SOT-MRAM cell according to some embodiments. Figure 3 The signals shown include a master clock signal CLK configured to synchronize various components of the integrated circuit, a coupling control signal VCLP configured to control the conduction state of coupling transistors TC1 and TC2 (eg, FIG. 2A to FIG. 2B ), a precharge control signal (such as FIG. 2A to FIG. 2B ) and a precharge control signal PRE0 (as shown) configured to control the conduction state of the NMOS transistors TN1 and TN2 FIG. 2A to FIG. 2B shown). Figure 3 The signals shown include read on / read off voltages on read word line RWL, write on / write off voltages on write word line WWL, voltages applied to source bit line SL and write bit line WBL. FIG. 2A to FIG. 2B In the embodiment, the lower power supply voltage VSS is implemented as the voltage VGND that drives the source bit line SL or the write bit line WBL. Figure 3 The signals shown include the voltage on the read bit line RBL for two different resistance values ​​of the MTJ structure, the voltage at the connection node INP corresponding to the two different resistance values ​​of the MTJ structure, and the voltage at the connection node INP corresponding to the two different resistance values ​​of the MTJ structure. FIG. 2A to FIG. 2B The voltage at the connection node INN associated with the read bit line RBL[Ref] in . Figure 3 The two signals SAEN and SO at the bottom are the sense amplifier enable signal and the voltage at the output SO of the differential amplifier LSA, respectively.

[0047] exist Figure 3In the process, between time t1 and t2, a read operation is performed on the SOT-MRAM cell 100jk (eg, Figure 2A As shown, the voltage at the output SO of the differential amplifier LSA is detected to determine the voltage change rate at the voltage rising edge at the connection node INP due to the current through the MTJ structure in the SOT-MRAM cell 100jk charging the voltage on the bit line capacitance (i.e., the voltage change rate at the read bit line RBL[k]). Different voltage change rates at the read bit line RBL[k] are associated with different binary values ​​stored in the SOT-MRAM cell 100jk. Therefore, based on the measurement of the voltage at the output SO of the differential amplifier LSA, the binary value stored in the SOT-MRAM cell 100jk is read out.

[0048] exist Figure 3 In the process, between time t2 and time t3, a read operation is performed on the SOT-MRAM cell 100jm (eg, Figure 2B As shown, the voltage at the output SO of the differential amplifier LSA is detected to determine the rate of change of the voltage at the falling edge of the voltage at the connection node INP (i.e., the rate of change of the voltage at the read bit line RBL[m]) due to the discharge of the voltage on the bit line capacitance by the current through the MTJ structure in the SOT-MRAM cell 100jm. Different discharge rates of the voltage at the read bit line RBL[m] are associated with different binary values ​​stored in the SOT-MRAM cell 100jm. Therefore, based on the measurement of the voltage at the output SO of the differential amplifier LSA, the binary value stored in the SOT-MRAM cell 100jm is read out.

[0049] exist Figure 1A In the jth row, the SOT-MRAM cell 100jk (e.g. Figure 2A ) and SOT-MRAM cell 100jm (as shown Figure 2B ) are two example SOT-MRAM cells in a selected row for a read operation. SOT-MRAM cell 100jk is associated with a corresponding SOT-MRAM cell 100ik in the same k-th column, and SOT-MRAM cell 100jm is associated with a corresponding SOT-MRAM cell 100im in the same m-th column. Both SOT-MRAM cell 100ik and SOT-MRAM cell 100im are located in the i-th row, which is the selected row for a write operation.

[0050] exist Figure 1A, the SOT-MRAM cell 100jk in the j-th row is associated with a corresponding SOT-MRAM cell 100ik (in the same k-th column and i-th row), which is configured to receive a binary value of "0" when the i-th row is selected for writing. When the binary value "0" is written to the SOT-MRAM cell 100ik, a read operation on the SOT-MRAM cell 100jk is performed between time t1 and t2, and a voltage change at the read bit line RBL[k] due to the voltage charging on the bit line capacitor is detected. In addition to the SOT-MRAM cell 100jk, a read operation is performed on some other SOT-MRAM cells in the j-th row between time t1 and t2 to detect a voltage change caused by the voltage charging on the corresponding bit line capacitor. Each SOT-MRAM cell in the jth row undergoing a read operation between times t1 and t2 is associated with a corresponding SOT-MRAM cell in the ith row (in the same column) that is configured to receive a binary value of “0” when the ith row is selected for writing.

[0051] exist Figure 1A , the SOT-MRAM cell 100jm in the j-th row is associated with a corresponding SOT-MRAM cell 100im (in the same m-th column and i-th row), which is configured to receive a binary value of "1" when the i-th row is selected for writing. When the binary value "1" is written to the SOT-MRAM cell 100im, a read operation on the SOT-MRAM cell 100jm is performed between time t2 and t3, and a voltage change at the read bit line RBL[m] due to the discharge of the voltage on the bit line capacitor is detected. In addition to the SOT-MRAM cell 100jm, a read operation on some other SOT-MRAM cells in the j-th row is also performed between time t2 and t3 to detect a voltage change caused by the discharge of the voltage on the corresponding bit line capacitor. Each SOT-MRAM cell in the jth row undergoing a read operation between times t2 and t3 is associated with a corresponding SOT-MRAM cell in the ith row (in the same column) that is configured to receive a binary value of “1” when the ith row is selected for writing.

[0052] Figure 4 is a flow chart of a method 400 of manufacturing a memory device according to some embodiments. Figure 4 The order in which the operations of method 400 are described is for illustration only; the operations of method 400 may be performed in different Figure 4 It should be understood that the Figure 4Additional operations are performed before, during, and / or after the illustrated method 400 , and some other processes are only briefly described herein. The method 400 includes operations 410 , 420 , 430 , 440 , 445 , and 450 .

[0053] In operation 410 of method 400, each SOT-MRAM cell in the first row is driven into a write mode, and each SOT-MRAM cell in the second row is driven into a read mode. Figure 1A In the example embodiment shown, at least the SOT-MRAM cells 100ik and 100im in the i-th row are driven into a write mode, and at least the SOT-MRAM cells 100jk and 100jm in the j-th row are driven into a read mode.

[0054] In operation 420 of method 400, a first current is generated and passed through a SOT conductor in a first SOT-MRAM cell in a first row. Figure 1A In the example embodiment shown, a current is generated through the SOT conductors in the SOT-MRAM cells 100ik in the i-th row, and the generated current flows from the source bit line SL[k] to the write bit line WBL[k].

[0055] In operation 430 of method 400, when the first read bit line is charged using a first read current passing through the MTJ structure in the second SOT-MRAM cell in the second row, a voltage change on the first read bit line is detected by the first sense amplifier. Figure 1A and Figure 2A In the exemplary embodiment shown, the read bit line RBL[k] is charged by the current passing through the MTJ structure in the SOT-MRAM cell 100jk in the kth row, which causes a voltage change at the connection node INP coupled to the first input of the differential amplifier LSA. When the voltage change at the connection node INP causes an output voltage change at the output SO of the differential amplifier LSA, the voltage change on the read bit line RBL[k] is detected.

[0056] In operation 440 of method 400, a second current is generated and passed through the SOT conductor in the third SOT-MRAM cell of the first row. Figure 1A In the example embodiment shown, a current is generated through the SOT conductors in the SOT-MRAM cells 100im in the i-th row, and the generated current flows from the write bit line WBL[m] to the source bit line SL[m].

[0057] In operation 445 of method 400, a second read bit line connected to a fourth SOT-MRAM cell in the second row is charged to a predetermined reference voltage. Figure 1A and Figure 2B In the example embodiment shown, in response to the PMOS transistors TP1 and TP2 being driven into a conductive state and the NMOS transistors TN1 and TN2 being maintained in a non-conductive state, the read bit line RBL[m] connected to the SOT-MRAM cell 100jm in the j-th row is precharged to a predetermined reference voltage equal to the first power supply voltage VDD.

[0058] In operation 450 of method 400, when the second read bit line is discharged using the second read current through the MTJ structure in the fourth SOT-MRAM cell, the voltage change on the second read bit line is detected by the second sense amplifier. Figure 1A and Figure 2B In the exemplary embodiment shown, the read bit line RBL[m] starts with a predetermined reference voltage equal to the first power supply voltage VDD, and then the read bit line RBL[m] is discharged by the current through the MTJ structure in the SOT-MRAM cell 100jm in the mth row, which causes a voltage change at the connection node INP coupled to the first input terminal of the differential amplifier LSA. When the voltage change at the connection node INP causes an output voltage change at the output SO of the differential amplifier LSA, the voltage change on the read bit line RBL[m] is detected.

[0059] One aspect of the present invention relates to a memory device. The memory device includes a matrix of SOT-MRAM cells, each SOT-MRAM cell having a magnetic tunnel junction ("MTJ") structure and a spin-orbit torque ("SOT") conductor. Each SOT-MRAM cell in a first row is set to a write mode, and each SOT-MRAM cell in a second row is set to a read mode. The memory device also includes a first write bit line, a first source bit line, and a first read bit line coupled to the first SOT-MRAM cell and the second SOT-MRAM in the first column, and a first sense amplifier configured to detect a voltage change on the first read bit line when the first read bit line is charged by a first read current of the MTJ structure in the second SOT-MRAM cell in the second row. The memory device also includes a second write bit line, a second source bit line, and a second read bit line coupled to the third SOT-MRAM cell and the fourth SOT-MRAM in the second column, and a second sense amplifier configured to detect a voltage change on the second read bit line when the second read bit line is discharged with a second read current through the MTJ structure of the fourth SOT-MRAM cell in the second row. The first write bit line and the first source bit line are configured to have a first current through the SOT conductor in the first SOT-MRAM cell in the first row. The second write bit line and the second source bit line are configured to have a second current through the SOT conductor in the third SOT-MRAM cell in the first row. The first current and the second current flow in opposite directions.

[0060] In some embodiments, the MTJ structure includes: a free layer, a pinned layer, and a tunnel barrier layer interposed between the free layer and the pinned layer, wherein the free layer is in conductive contact with a SOT conductor.

[0061] In some embodiments, each of the first SOT-MRAM cell and the third SOT-MRAM cell includes: a write switch transistor having a channel connecting a first terminal of the SOT conductor to one of the first write bit line and the second write bit line, wherein the SOT conductor has a second terminal connected to one of the first source bit line and the second source bit line.

[0062] In some embodiments, each of the second SOT-MRAM cell and the fourth SOT-MRAM cell includes a read switch transistor having a channel connecting the pinned layer of the MTJ structure to one of the first read bit line and the second read bit line.

[0063] In some embodiments, each of the first sense amplifier and the second sense amplifier includes: a differential amplifier; a first PMOS transistor and a first NMOS transistor, each having a channel connected together at a first connection node, the first connection node is also connected to the first input terminal of the differential amplifier; and a second PMOS transistor and a second NMOS transistor, each having a channel connected together at a second connection node, the second connection node is also connected to the second input terminal of the differential amplifier.

[0064] In some embodiments, each of the first sense amplifier and the second sense amplifier further includes: a first coupling transistor having a channel connected between the first input terminal of the differential amplifier and one of the first read bit line and the second read bit line; and a second coupling transistor having a channel connected between the second input terminal of the differential amplifier and a reference bit line connected to a reference cell.

[0065] Another aspect of the present invention relates to a device. The device includes a matrix of SOT-MRAM cells, each of which has a write port, a read port, and a source port. The device also includes a first write bit line and a first read bit line associated with the first column of SOT-MRAM cells, and a second write bit line and a second read bit line associated with the second column of SOT-MRAM cells. The write port of each SOT-MRAM cell in the first column is connected to the first write bit line, and the read port of each SOT-MRAM cell in the first column is connected to the first read bit line. The write port of each SOT-MRAM cell in the second column is connected to the second write bit line, and the read port of each SOT-MRAM cell in the second column is connected to the second read bit line. The device also includes a write circuit, a first sense amplifier, and a second sense amplifier. The write circuit is configured to output a first current to the first write bit line, and is configured to output a second current to the second write bit line. The first current and the second current flow in opposite directions. The first sense amplifier is configured to detect a voltage change on the first read bit line when the first read bit line is charged by the first sense amplifier. The second sense amplifier is configured to detect a voltage change on the second read bit line when the second read bit line is discharged after the second read bit line is precharged by the second sense amplifier.

[0066] In some embodiments, each of the first sense amplifier and the second sense amplifier includes: a differential amplifier; a first PMOS transistor and a first NMOS transistor, each having a channel connected together at a first connection node, the first connection node is also connected to the first input terminal of the differential amplifier; and a second PMOS transistor and a second NMOS transistor, each having a channel connected together at a second connection node, the second connection node is also connected to the second input terminal of the differential amplifier.

[0067] In some embodiments, each of the first sense amplifier and the second sense amplifier further includes: a first coupling transistor having a channel connected between the first input terminal of the differential amplifier and one of the first read bit line and the second read bit line; and a second coupling transistor having a channel connected between the second input terminal of the differential amplifier and a reference bit line connected to a reference cell.

[0068] In some embodiments, the device further includes: a first source bit line connected to a source port of each SOT-MRAM cell in the first column; and a second source bit line connected to a source port of each SOT-MRAM cell in the second column.

[0069] In some embodiments, the write circuit is configured to apply a first voltage to the first write bit line, apply a second voltage to the first source bit line, and apply the first voltage to the first source bit line and apply the second voltage to the second write bit line.

[0070] In some embodiments, each SOT-MRAM cell includes: a spin-orbit torque SOT conductor; and a magnetic tunnel junction MTJ structure having a free layer, a pinned layer, and a tunnel barrier layer sandwiched between the free layer and the pinned layer, wherein the free layer is in conductive contact with the SOT conductor.

[0071] In some embodiments, the device further includes: a write switch transistor having a channel connected between the write port and a first terminal of the SOT conductor, wherein the SOT conductor has a second terminal connected to the source port; and a read switch transistor having a channel connected between the read port and the pinned layer of the MTJ structure.

[0072] In some embodiments, the SOT-MRAM cells of the first column include a first SOT-MRAM cell and a second SOT-MRAM cell, the SOT-MRAM cells of the second column include a third SOT-MRAM cell and a fourth SOT-MRAM cell, and further include: a first write word line connected to the gate of the write switch transistor in the first SOT-MRAM cell and to the gate of the write switch transistor in the third SOT-MRAM cell; a first read word line connected to the gate of the read switch transistor in the first SOT-MRAM cell and to the gate of the read switch transistor in the second SOT-MRAM cell; a second write word line connected to the gate of the write switch transistor in the third SOT-MRAM cell and to the gate of the write switch transistor in the fourth SOT-MRAM cell; and a second read word line connected to the gate of the read switch transistor in the third SOT-MRAM cell and to the gate of the read switch transistor in the fourth SOT-MRAM cell.

[0073] Another aspect of the present invention relates to a method of operating on a matrix of SOT-MRAM cells, each SOT-MRAM cell having a magnetic tunnel junction ("MTJ") structure and a spin-orbit torque ("SOT") conductor. The method includes driving each SOT-MRAM cell in a first row into a write mode, and driving each SOT-MRAM cell in a second row into a read mode. The method also includes generating a first current through a SOT conductor in a first SOT-MRAM cell in the first row, and detecting a voltage change on the first read bit line by a first sense amplifier when the first read bit line is charged with a first read current through the MTJ structure in a second SOT-MRAM cell in the second row. The first SOT-MRAM cell and the second SOT-MRAM cell are located in a first column. The method also includes generating a second current through a SOT conductor in a third SOT-MRAM cell in the first row, and detecting a voltage change on the second read bit line by a second sense amplifier when the second read bit line is discharged with a second read current through the MTJ structure in a fourth SOT-MRAM cell in the second row after the second read bit line is precharged by the second sense amplifier. The third SOT-MRAM cell and the fourth SOT-MRAM cell are located in the second column. The first current and the second current flow in opposite directions.

[0074] In some embodiments, the method further includes: detecting the voltage change on the first read bit line while generating the first current; and detecting the voltage change on the second read bit line while generating the second current.

[0075] In some embodiments, the method further includes: generating the second current simultaneously with generating the first current.

[0076] In some embodiments, driving each SOT-MRAM cell in the first row into the write mode includes driving a write switch transistor in each SOT-MRAM cell in the first row into a conductive state, the write switch transistor having a channel connected between the first terminal of the SOT conductor and a write bit line.

[0077] In some embodiments, driving each SOT-MRAM cell in the second row into the read mode includes driving a read switch transistor in each SOT-MRAM cell in the second row into a conductive state, the read switch transistor having a channel connected between the MTJ structure and a read bit line.

[0078] In some embodiments, the method further includes: driving each SOT-MRAM cell in the remaining rows of the matrix to a separation mode, wherein driving each SOT-MRAM cell in the remaining rows to the separation mode includes driving a write switch transistor and a read switch transistor in each SOT-MRAM cell in the remaining rows to a non-conducting state.

[0079] The foregoing summarizes the features of several embodiments so that those skilled in the art can better understand aspects of the present disclosure. Those skilled in the art should understand that they can easily use the present disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or achieve the same advantages as the embodiments introduced herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they can be subjected to various changes, substitutions and modifications without departing from the spirit and scope of the present disclosure.

Claims

1. A storage device, comprising: A spin-orbit torque magnetic memory SOT-MRAM cell matrix, each SOT-MRAM cell having a magnetic tunnel junction MTJ structure and a spin-orbit torque SOT conductor, wherein each SOT-MRAM cell in a first row is set to a write mode, and each SOT-MRAM cell in a second row is set to a read mode; a first write bit line, a first source bit line, and a first read bit line coupled to a first SOT-MRAM cell and a second SOT-MRAM in a first column, wherein the first write bit line and the first source bit line are configured to have a first current passing through the SOT conductor in the first SOT-MRAM cell in the first row; a first sense amplifier configured to detect a voltage change on the first read bit line when the first read bit line is charged by a first read current through the MTJ structure in the second SOT-MRAM cell in the second row; a second write bit line, a second source bit line, and a second read bit line coupled to a third SOT-MRAM cell and a fourth SOT-MRAM in a second column, the second write bit line and the second source bit line being configured to have a second current passing through the SOT conductor in the third SOT-MRAM cell in the first row, wherein the first current and the second current flow in opposite directions; and The second sense amplifier is configured to detect a voltage change on the second read bit line when the second read bit line is discharged with a second read current through the MTJ structure of the fourth SOT-MRAM cell in the second row.

2. The memory device according to claim 1, wherein: The MTJ structure includes: A free layer, a pinned layer, and a tunnel barrier layer interposed between the free layer and the pinned layer, wherein the free layer is in conductive contact with a SOT conductor.

3. The memory device according to claim 2, wherein: Each of the first SOT-MRAM cell and the third SOT-MRAM cell comprises: A write switch transistor having a channel connecting a first terminal of the SOT conductor to one of the first write bit line and the second write bit line, wherein the SOT conductor has a second terminal connected to one of the first source bit line and the second source bit line.

4. The memory device according to claim 2, wherein: Each of the second SOT-MRAM cell and the fourth SOT-MRAM cell includes: A read switch transistor has a channel connecting the pinned layer of the MTJ structure to one of the first read bit line and a second read bit line.

5. The memory device according to claim 2, wherein: Each of the first sense amplifier and the second sense amplifier includes: Differential amplifier; a first PMOS transistor and a first NMOS transistor, the channels of each having channels connected together at a first connection node, the first connection node also connected to the first input terminal of the differential amplifier; and The second PMOS transistor and the second NMOS transistor respectively have channels connected together at a second connection node, and the second connection node is also connected to the second input terminal of the differential amplifier.

6. A storage device comprising: A matrix of spin-orbit torque magnetic memory SOT-MRAM cells, each SOT-MRAM cell having a write port, a read port and a source port; a first write bit line and a first read bit line associated with a first column of SOT-MRAM cells, wherein the write port of each SOT-MRAM cell in the first column is connected to the first write bit line, and the read port of each SOT-MRAM cell in the first column is connected to the first read bit line; a second write bit line and a second read bit line associated with the SOT-MRAM cells of the second column, wherein the write port of each SOT-MRAM cell in the second column is connected to the second write bit line, and the read port of each SOT-MRAM cell in the second column is connected to the second read bit line; a write circuit configured to output a first current to the first write bit line, and configured to output a second current to the second write bit line, wherein the first current and the second current are opposite in flow direction; a first sense amplifier configured to detect a voltage change on the first read bit line when the first read bit line is charged by the first sense amplifier; and A second sense amplifier is configured to detect a voltage change on the second read bit line when the second read bit line is discharged after the second read bit line is precharged by the second sense amplifier.

7. The device according to claim 6, wherein Each of the first sense amplifier and the second sense amplifier includes: Differential amplifier; a first PMOS transistor and a first NMOS transistor, the channels of each having channels connected together at a first connection node, the first connection node also connected to the first input terminal of the differential amplifier; and The second PMOS transistor and the second NMOS transistor respectively have channels connected together at a second connection node, and the second connection node is also connected to the second input terminal of the differential amplifier.

8. The device according to claim 7, wherein Each of the first sense amplifier and the second sense amplifier further includes: a first coupling transistor having a channel connected between the first input terminal of the differential amplifier and one of the first read bit line and the second read bit line; and A second coupling transistor has a channel connected between the second input terminal of the differential amplifier and a reference bit line connected to a reference cell.

9. A method for operating a matrix of spin-orbit torque magnetic memory SOT-MRAM cells, each SOT-MRAM cell having a magnetic tunnel junction MTJ structure and a spin-orbit torque SOT conductor, the method comprising: applying a voltage to drive each SOT-MRAM cell in the first row into a write mode; applying a voltage to drive each SOT-MRAM cell in the second row into a read mode; generating a first current through the SOT conductor in a first SOT-MRAM cell in the first row; detecting, by a first sense amplifier, a voltage change on the first read bit line when the first read bit line is charged using a first read current passing through the MTJ structure in a second SOT-MRAM cell in the second row, wherein the first SOT-MRAM cell and the second SOT-MRAM cell are located in a first column; generating a second current through the SOT conductor in a third SOT-MRAM cell in the first row, wherein the first current and the second current flow in opposite directions; and After the second read bit line is precharged by the second sense amplifier, a voltage change on the second read bit line is detected by the second sense amplifier when the second read bit line is discharged with a second read current passing through the MTJ structure in the fourth SOT-MRAM cell in the second row, wherein the third SOT-MRAM cell and the fourth SOT-MRAM cell are located in the second column.

10. The method according to claim 9, further comprising: detecting the voltage change on the first read bit line while generating the first current; as well as The voltage change on the second read bit line is detected while the second current is generated.

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