Storage device, control method thereof and electronic equipment
By stacking NVM storage arrays on DRAM storage arrays and sharing peripheral circuits, the problems of traditional DRAM capacity expansion and limited NVM durability are solved, and efficient memory capacity improvement and energy consumption reduction are achieved.
Patent Information
- Application Number
- CN202311499119.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-11-10
- Publication Date
- 2025-05-13
AI Technical Summary
Traditional DRAMs face challenges such as high price and high energy consumption when expanding capacity. Although the new NVM has the advantages of low price and low energy consumption, its durability characteristics are limited and it is difficult to operate frequently.
Using a hybrid memory architecture of DRAM and NVM, the NVM storage array is stacked on the DRAM storage array, and a portion of peripheral circuits are shared. The operation of NVM or DRAM is controlled through row selection circuits and column selection circuits.
Without increasing the storage area, increase the memory capacity, reduce the number of DRAM refreshes, and reduce the power consumption and timing blockage of refreshes.
Smart Images
Figure CN119993223A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of storage technology, and in particular to a storage device and a control method thereof, and an electronic device. Background Art
[0002] The memory (also called main memory) in a computer is generally composed of dynamic random access memory (DRAM). With the evolution of process nodes, the capacity expansion of traditional DRAM faces challenges such as high price and high energy consumption.
[0003] The new non-volatile memory (NVM) combines the fast read and write access of dynamic random access memory (DRAM) with the ability to retain data after the power is turned off. It has the advantages of low price, low energy consumption and no refresh, making it an ideal memory to replace DRAM to provide large-capacity memory. Summary of the invention
[0004] The present application provides a storage device and a control method thereof, and an electronic device, and provides a DRAM-NVM hybrid storage device in which an NVM storage array is stacked on a DRAM storage array.
[0005] The present application provides a storage device, which includes a first storage array, a second storage array, and a peripheral circuit arranged on a substrate. Among them, the first storage array is a dynamic random access memory DRAM storage array, and the second storage array is a non-volatile memory NVM storage array. The first storage array and the second storage array are stacked, and the second storage array is located on the side of the first storage array away from the substrate, so as to increase the storage capacity. The peripheral circuit is arranged in the peripheral area of the first storage array and the second storage array. The peripheral circuit includes a row selection circuit, a column selection circuit, a row decoder, and a sense amplifier. The first storage array or the second storage array is controlled to be connected to the row decoder through the row selection circuit, and the first storage array or the second storage array is controlled to be connected to the sense amplifier through the column selection circuit. In other words, the NVM storage array can share the peripheral circuit with the DRAM storage array, and the operation of the NVM storage array or the DRAM storage array is controlled by the row selection circuit and the column selection circuit.
[0006] In the DRAM-NVM hybrid storage device provided in the present application, the NVM storage array is stacked on the DRAM storage array, and the NVM storage array and the DRAM storage array can share at least part of the peripheral circuit, which can increase the memory capacity without increasing the storage area. When accessing the DRAM-NVM hybrid storage device, the operation of the NVM storage array or the DRAM storage array can be controlled by the row selection circuit and the column selection circuit, thereby reducing the number of refreshes of the DRAM storage array and reducing the power consumption and timing blockage of the DRAM storage array refresh.
[0007] In some possible implementations, the second storage array is a ferroelectric random access memory (FRAM) storage array. FRAM has the advantages of fast read and write speed, low power consumption, and miniaturization, and FRAM has good compatibility with DRAM, making DRAM-FRAM hybrid memory easier to design from the perspective of process integration and circuit structure.
[0008] In some possible implementations, the first storage array includes a plurality of first storage cells, a plurality of first bit lines, and a plurality of first word lines. The plurality of first storage cells in the same row are connected to the same first word line, and the plurality of first storage cells in the same column are connected to the same first bit line. The second storage array includes a plurality of second storage cells, a plurality of second bit lines, and a plurality of second word lines; the plurality of second storage cells in the same row are connected to the same second word line, and the plurality of second storage cells in the same column are connected to the same second bit line. The plurality of first word lines and the plurality of second word lines are connected to a row decoder through a row selection circuit. The plurality of first bit lines and the plurality of second bit lines are connected to a sense amplifier through a column selection circuit.
[0009] In some possible implementations, a plurality of first storage units and a plurality of second storage units are arranged opposite to each other, thereby saving storage area overhead.
[0010] In some possible implementations, the first storage unit includes at least one first transistor and at least one first capacitor, and the first capacitor is located on a side of the first transistor away from the substrate. The second storage unit includes at least one second transistor and at least one second capacitor, and the second capacitor is located on a side of the second transistor away from the first storage array.
[0011] In some possible implementations, the second transistor is a vertical gate-all-around transistor.
[0012] In some possible implementations, the second capacitor is a trench ferroelectric capacitor.
[0013] In some possible implementations, the storage device further includes a plate line; the plate line is located on a side of the plurality of second transistors close to the substrate and is connected to the second transistors. The plate line serves as a common electrode of the plurality of first capacitors in the first storage array, and the plate line is connected to the source or drain of the plurality of second transistors in the second storage array, that is, the first storage array and the second storage array reuse the plate line. In this case, during operation, the plate line can always maintain the same potential (such as VDD / 2 potential), reducing the delay required for level jumps, thereby achieving faster access speeds.
[0014] In some possible implementations, the first storage array includes a first plate line, and the second storage array includes a second plate line. The first plate line is located on a side of the plurality of second transistors close to the substrate, the first plate line includes a planar electrode, and the planar electrode serves as a common electrode of the plurality of first capacitors. The second plate line is located on a side of the first plate line away from the substrate, and the second plate line is connected to the plurality of second capacitors. By setting different plate lines in the first storage array and the second storage array, respectively, the voltages of the first plate line and the second plate line can be flexibly set according to the requirements of the two storage arrays. For example, the second plate line in the second storage array can use a larger voltage to better meet the requirements of the ferroelectric capacitor.
[0015] In some possible implementations, the second plate line is located on a side of the plurality of second capacitors away from the first plate line. The second plate line includes a planar electrode, and the planar electrode is connected to the plurality of second capacitors.
[0016] In some possible implementations, the second plate line is located on a side of the plurality of second capacitors away from the first plate line. The second plate line includes a plurality of strip electrodes, and a single strip electrode is connected as a plurality of second capacitors in the same row or column.
[0017] In some possible implementations, the second plate line is located between the plurality of second transistors and the first plate line. The second plate line includes a plurality of strip electrodes, and a single strip electrode is connected to sources or drains of the plurality of second transistors in the same row or column.
[0018] The present application also provides an electronic device, which includes a circuit board and a storage device provided in any of the possible implementation methods described above, wherein the storage device is electrically connected to the circuit board.
[0019] The present application also provides a control method for a storage device as provided in any of the above possible implementations, the control method may include: obtaining an access request to a first storage array or a second storage array. According to the access request, a first control signal is sent to a row selection circuit, and a second control signal is sent to the column selection circuit; wherein the first control signal and the second control signal are used to indicate that the first storage array or the second storage array is connected to a row decoder and a sense amplifier.
[0020] The present application also provides a computer-readable storage medium, comprising a computer program, which, when executed on an electronic device, enables the electronic device to execute the aforementioned storage device control method.
[0021] The present application also provides a computer program product. When the computer program product is run on a computer, the computer executes the control method of the storage device as described above. BRIEF DESCRIPTION OF THE DRAWINGS
[0022] Figure 1 A schematic diagram of a hierarchical architecture of a DRAM-NVM hybrid memory provided in an embodiment of the present application;
[0023] Figure 2 A schematic diagram of a parallel architecture of a DRAM-NVM hybrid memory provided in an embodiment of the present application;
[0024] Figure 3 A circuit diagram of a DRAM provided in an embodiment of the present application;
[0025] Figure 4 for Figure 3 A structural schematic diagram corresponding to the DRAM;
[0026] Figure 5 A circuit diagram of a DRAM-FRAM hybrid memory provided in an embodiment of the present application;
[0027] Figure 6 for Figure 5 A structural schematic diagram corresponding to the DRAM-FRAM hybrid memory;
[0028] Figure 7 A schematic diagram of the three-dimensional structure of a vertical gate-all-around transistor provided in an embodiment of the present application;
[0029] Figure 8 for Figure 7 Sectional view along position AA';
[0030] Fig. 9 A schematic diagram of a DRAM-FRAM hybrid memory during the manufacturing process provided in an embodiment of the present application;
[0031] Fig.10 A schematic diagram of a DRAM-FRAM hybrid memory during the manufacturing process provided in an embodiment of the present application;
[0032] Fig.11 A partially enlarged stereoscopic schematic diagram of a DRAM-FRAM hybrid memory provided in an embodiment of the present application;
[0033] Fig.12 A timing diagram of a write operation process and a read operation process of a DRAM storage array provided in an embodiment of the present application;
[0034] Fig.13 A timing diagram of a write operation process and a read operation process of a FRAM storage array provided in an embodiment of the present application;
[0035] Fig.14 A circuit diagram of a DRAM-FRAM hybrid memory provided in an embodiment of the present application;
[0036] Fig.15 A circuit diagram of a DRAM-FRAM hybrid memory provided in an embodiment of the present application;
[0037] Fig.16 A circuit diagram of a DRAM-FRAM hybrid memory provided in an embodiment of the present application;
[0038] Fig.17 A circuit diagram of a DRAM-FRAM hybrid memory provided in an embodiment of the present application;
[0039] Fig.18 A schematic diagram of a DRAM-FRAM hybrid memory during the manufacturing process provided in an embodiment of the present application;
[0040] Fig.19 A schematic diagram of a DRAM-FRAM hybrid memory during the manufacturing process provided in an embodiment of the present application;
[0041] Fig. 20 A partially enlarged stereoscopic schematic diagram of a DRAM-FRAM hybrid memory provided in an embodiment of the present application;
[0042] Fig.21 A timing diagram of a write operation process and a read operation process of a FRAM storage array provided in an embodiment of the present application;
[0043] Fig. 22 A flow chart of a control method for a DRAM-FRAM hybrid memory is provided for an embodiment of the present application. DETAILED DESCRIPTION
[0044] In order to make the purpose, technical solutions and advantages of this application clearer, the technical solutions in this application will be clearly and completely described below in conjunction with the drawings in this application. Obviously, the described embodiments are part of the embodiments of this application, not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.
[0045] The terms "first", "second", etc. in the specification embodiments, claims and drawings of the present application are only used for the purpose of distinguishing descriptions, and cannot be understood as indicating or implying relative importance, nor can they be understood as indicating or implying order. "And / or" is used to describe the association relationship of associated objects, indicating that three relationships may exist. For example, "A and / or B" can mean: only A exists, only B exists, and A and B exist at the same time, where A and B can be singular or plural. The character " / " generally indicates that the objects associated before and after are in an "or" relationship. "At least one (item)" means one or more, and "multiple" means two or more. "Installation", "connection", "connected", etc. should be understood in a broad sense, for example, it can be an electrical connection or a mechanical connection; it can be a fixed connection, a detachable connection, or an integral connection; it can be a direct connection, or it can be indirect through an intermediate medium, or it can be the internal connection of two elements. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions, for example, including a series of steps or units. Methods, systems, products or devices are not necessarily limited to those steps or units explicitly listed, but may include other steps or units that are not explicitly listed or inherent to these processes, methods, products or devices. "Up", "down", "left", "right", etc. are only used relative to the orientation of the components in the drawings. These directional terms are relative concepts. They are used for description and clarification relative to the description, which may change accordingly according to the change of the orientation of the components in the drawings.
[0046] An embodiment of the present application provides an electronic device, which may be a consumer electronic product, a household electronic product, a vehicle-mounted electronic product, a financial terminal product, a communication electronic product, etc., and the present application does not impose any restrictions on this.
[0047] Indicatively, the above-mentioned consumer electronic products can be mobile phones, tablet computers, laptop computers, personal computers (PCs), personal digital assistants (PDAs), smart wearable products (e.g., smart watches, smart bracelets, etc.), virtual reality (VR) terminal devices, augmented reality (AR) terminal devices, drones, etc. Home electronic products can be smart door locks, TVs, smart speakers, refrigerators, sweeping robots, etc. Car-mounted electronic products can be car-mounted navigators, car-mounted displays, etc. Financial terminal products can be automated teller machines (ATMs), electronic devices for self-service transactions, etc. Communication electronic products can be servers, storage devices, radars, base stations, and other communication equipment.
[0048] The electronic device includes a printed circuit board (PCB) and a novel storage device electrically connected to the circuit board. The novel storage device adopts a hybrid memory architecture of DRAM and NVM, which can also be called DRAM-NVM hybrid memory or DRAM-NVM hybrid memory. The DRAM-NVM hybrid memory includes a DRAM storage array and an NVM storage array, and the NVM storage array is stacked on the DRAM storage array, thereby increasing the memory capacity of the storage device.
[0049] It is understandable that DRAM memory has the disadvantage of limited capacity expansion due to high price and high energy consumption. Although NVM memory has the advantages of low price, low energy consumption and no need for refresh, it has the problem of low endurance, that is, the number of read and write times it supports within its life is limited.
[0050] Based on this, the new storage device provided in this application adopts a hybrid memory architecture of DRAM and NVM, using NVM memory to make up for the disadvantage of limited DRAM memory capacity, and using DRAM memory to make up for the disadvantage of NVM memory's inability to perform frequent operations, thereby better meeting the needs of storage devices.
[0051] In the novel hybrid storage device provided in the present application, the memory architecture of DRAM and NVM can be designed according to actual needs, and the present application does not impose any limitation on this.
[0052] For example, Figure 1As shown, in some possible implementations, DRAM-NVM hybrid memory can adopt a parallel architecture, and both NVM and DRAM can be used as main memory. In this case, the DRAM memory controller and the NVM memory controller are uniformly managed and allocated by the CPU (central processing unit), and frequently accessed data (hot data) are placed in the DRAM memory, and infrequently accessed data (cold data) are placed in the NVM memory. In this way, there is no need to perform frequent read and write operations on the NVM memory, and the number of refreshes of the DRAM memory can also be reduced, which reduces the power consumption and timing blocking of the DRAM memory refresh.
[0053] For example, Figure 2 As shown, in some possible implementations, the DRAM-NVM hybrid memory can adopt a hierarchical architecture, where NVM can be used as the main memory and DRAM can be used as the cache of NVM. In this case, when the CPU accesses the memory, it can first access the DRAM cache. If it does not hit (that is, there is no data to be found in DRAM), it can then access the NVM memory, thereby eliminating the need for frequent read and write operations on the NVM memory, thereby ensuring its lifespan.
[0054] In addition, in the DRAM-NVM hybrid memory provided in the embodiment of the present application, by stacking the NVM storage array on the DRAM storage array, the NVM storage array can share peripheral circuits with the DRAM storage array, thereby increasing the memory capacity without increasing the storage area.
[0055] It should be noted that the present application does not impose any restrictions on the configuration form of the NVM, and in practice it can be designed as needed.
[0056] Schematically, in the DRAM-NVM hybrid memory provided in the embodiment of the present application, the NVM storage array can be a phase change access memory (PCRAM) storage array, a magnetoresistive random access memory (MRAM) storage array, a ferroelectric random access memory (FRAM) storage array, etc.
[0057] Illustratively, in some possible implementations, the above-mentioned DRAM-NVM hybrid memory can be a DRAM-FRAM hybrid memory. In this case, the DRAM-FRAM hybrid memory includes a DRAM storage array and a FRAM storage array. The FRAM storage array can be stacked on the DRAM storage array, and the FRAM storage array can share peripheral circuits with the DRAM storage array, thereby increasing the memory capacity without increasing the storage area.
[0058] It is understandable that FRAM has the advantages of fast read and write speed, low power consumption, and miniaturization, and FRAM has good compatibility with DRAM. Therefore, DRAM-FRAM hybrid memory is easier to design from the perspective of process integration and circuit structure.
[0059] The hybrid storage device provided in the embodiment of the present application is specifically described below using a DRAM-FRAM hybrid memory as an example.
[0060] Figure 3 A circuit diagram of a DRAM provided in an embodiment of the present application. Figure 4 for Figure 3 A structural schematic diagram corresponding to the DRAM.
[0061] refer to Figure 3 As shown, the DRAM includes a DRAM memory array 10 and a peripheral circuit 11 located in the peripheral area of the DRAM memory array 10. The peripheral circuit 11 may include a row decoder XDEC (X-decoder), a sense amplifier SA (sense amplifier), a column decoder YDEC (Y-decoder), a row driving circuit, a column driving circuit, etc.
[0062] Continue to refer Figure 3 The DRAM memory array 10 includes a plurality of DRAM memory cells 100 arranged in an array, a plurality of word lines WL (word line), and a plurality of bit lines BL (bit line). The word line WL extends in the row direction, and the bit line BL extends in the column direction. Each DRAM memory cell 100 includes at least one transistor T1 (which may be referred to as a first transistor) and at least one capacitor C1 (which may be referred to as a first capacitor), which may be a separately arranged capacitor or a gate capacitor in another transistor, and the present application does not impose any restrictions on this. In the DRAM memory array 10, a plurality of DRAM memory cells 100 located in the same row are connected to a row decoder XDEC through the same word line WL, and a DRAM memory cell 100 located in the same column is connected to a sense amplifier SA and a column decoder YDEC through the same bit line BL.
[0063] It should be noted that the "row" and "column" involved in the embodiments of the present application only refer to two different directions. The drawings of the present application only schematically illustrate that the horizontal direction is the row direction and the vertical direction is the column direction, but are not limited to this; in other possible implementations, the horizontal direction may be the column direction and the vertical direction may be the row direction.
[0064] It should also be noted that Figure 3 The following embodiments are described by taking the DRAM memory cell 100 including a transistor T1 and a capacitor C1 (ie, a 1T1C structure) as an example, but the present invention is not limited thereto. The following embodiments are described by taking the DRAM memory cell 100 using a 1T1C structure as an example.
[0065] Indicative, reference Figure 3 As shown, in the case where the DRAM memory cell 100 adopts a 1T1C structure, in the DRAM memory cell 100, the gate of the transistor T1 is connected to the word line WL, the source (or drain) of the transistor T1 is connected to the bit line BL, the drain (or source) of the transistor T1 is connected to one electrode of the capacitor C1, and the other electrode of the capacitor C1 is connected to the plate line PL.
[0066] It should be noted that, in the transistor involved in the present application, the source and the drain may not be clearly distinguished, and the source and the drain may have a symmetrical structure; that is, of the two poles other than the gate in the transistor involved in the present application, one is the source and the other is the drain.
[0067] For the internal structure of the above DRAM, refer to Figure 4 As shown, in some possible implementation methods, a transistor T1 and a word line WL, a bit line BL, etc. connected to the transistor T1 can be first made on a substrate 1, and then a capacitor C1 can be made. The capacitor C1 can be a stacked capacitor structure, and the stacked capacitor structure can include a first electrode E1 and a second electrode E2 that are stacked. Among them, the second electrode E2 is located above the first electrode E1, and a dielectric layer is provided between the first electrode E1 and the second electrode E2. The first electrode E1 located below can be connected to the drain (or source) of the transistor T1 through a via, and the second electrode E2 can use a planar electrode as a common electrode (equivalent to the plate line PL) of multiple capacitors C1. Of course, the capacitor C1 can also adopt other structures, which is not limited in this application. The following embodiments are all described by taking the stacked capacitor structure as an example.
[0068] Figure 5 A circuit diagram of a DRAM-FRAM hybrid memory provided in an embodiment of the present application. Figure 6 for Figure 5 A structural schematic diagram corresponding to the DRAM-FRAM hybrid memory.
[0069] Indicative, reference Figure 5 and Figure 6 As shown, an embodiment of the present application provides a DRAM-FRAM hybrid memory, on which a FRAM memory array 20 (also referred to as a second memory array) is stacked on the basis of the aforementioned DRAM memory array 10 (also referred to as a first memory array), that is, the FRAM memory array 20 is stacked on a side of the DRAM memory array 10 away from the substrate 1, thereby being able to further increase the storage capacity.
[0070] For the configuration of the DRAM storage array 10, please refer to Figure 3 , Figure 4 As well as the related descriptions in the previous text; of course, the specific structure of the DRAM memory array 10 can also be adjusted as needed, and this application does not limit this. In addition, in order to distinguish the word lines, bit lines, etc. in the DRAM memory array 10 and the FRAM memory array 20, Figure 4 , Figure 5 In the subsequent figures, the word lines in the DRAM memory array 10 may be represented as WLa, the bit lines as BLa, and the plate lines as PLa; the word lines in the FRAM memory array 20 may be represented as WLb, the bit lines as BLb, and the plate lines as PLb.
[0071] refer to Figure 5 As shown, the FRAM memory array 20 includes a plurality of FRAM memory cells 200 arranged in an array, a plurality of word lines WLb, and a plurality of bit lines BLb. Each FRAM memory cell 200 includes at least one transistor T2 (which may be referred to as a second transistor) and at least one capacitor C2 (which may be referred to as a second capacitor), and the capacitor C2 is a ferroelectric capacitor. In the memory array 20, a plurality of FRAM memory cells 200 located in the same row are connected to the same word line WLb, and a plurality of FRAM memory cells 200 located in the same column are connected to the same bit line BLb.
[0072] It should be noted that Figure 5 The FRAM memory cell 200 includes a transistor T2 and a capacitor C2 (i.e., a 1T1C structure) for illustration only, but the present invention is not limited thereto and may also be a 2T2C structure, a 1TnC structure, etc. The following embodiments are all described by taking the DRAM memory cell 100 using a 1T1C structure as an example.
[0073] In some possible implementations, the FRAM memory cells 200 in the FRAM memory array 20 may be arranged in a one-to-one correspondence with the DRAM memory cells 100 in the DRAM memory array 10, that is, the projections of the FRAM memory cells 200 in the FRAM memory array 20 on the substrate 1 and the projections of the DRAM memory cells 100 in the DRAM memory array 10 on the substrate 1 overlap in a one-to-one correspondence, and may overlap completely or partially. In this way, the storage area cost can be saved.
[0074] In order to save storage area to a greater extent, in some possible implementations, multiple FRAM memory cells 200 may be located directly above multiple DRAM memory cells 100, that is, the projections of multiple FRAM memory cells 200 on the substrate 1 completely overlap with the projections of multiple DRAM memory cells 100 on the substrate 1. In this case, the pitch between two adjacent FRAM memory cells 200 is the same as the pitch between two adjacent DRAM memory cells 100. The following embodiments are all described using this as an example.
[0075] In addition, the configuration of the transistor T2 and the capacitor C2 in the FRAM storage unit 200 can be set as required, and the present application does not impose any limitation on this.
[0076] As shown, in some possible implementations, the selection transistor (T2) in the FRAM memory cell 200 can adopt a vertical ring-gate transistor; since the vertical ring-gate transistor has the advantage of occupying a small storage area, the FRAM memory cell 200 can be directly stacked on the DRAM memory cell 100 without increasing the storage area.
[0077] Figure 7 A schematic diagram of a three-dimensional structure of a vertical gate-all-around transistor provided in an embodiment of the present application is shown in FIG. Figure 8 for Figure 7 Cross-section along position AA'.
[0078] Indicative, reference Figure 7 and Figure 8As shown, the selection transistor (T2) in the FRAM storage unit 200 can be a vertical ring-gate transistor, the outermost side of which can be a ring-shaped gate G (gate), and the inner side of the ring-shaped gate G (gate) is a ring-shaped gate dielectric layer GI, and the ring-shaped gate dielectric layer GI can be made of a dielectric material with a high dielectric constant (i.e. HK). The inner side of the ring-shaped gate dielectric layer GI is a ring-shaped channel CH (or a ring-shaped channel); the ring-shaped channel CH can be made of polysilicon (poly). The inner side of the ring-shaped channel CH is filled with a dielectric material, such as SiO2. The ring-shaped channel CH extends downward and upward to form the source S and drain D of the vertical ring-shaped transistor respectively.
[0079] Illustratively, in some possible implementations, the capacitor C2 in the FRAM storage unit 200 may be a trench ferroelectric capacitor, such as a hafnium-based ferroelectric material capacitor, but is not limited thereto, and other types of ferroelectric capacitors may also be used.
[0080] In addition, refer to Figure 5 As shown, in the DRAM-FRAM hybrid memory, a row selection circuit 111 and a column selection circuit 112 can be added to the peripheral circuit 11, so that the DRAM memory array 10 or the FRAM memory array 20 can be selected to be operated (including read operation and write operation) by controlling the row selection circuit 111 and the column selection circuit 112. In this case, the DRAM memory array 10 and the FRAM memory array 20 can reuse the row decoder XDEC, the sense amplifier SA, and the column row decoder YDEC in the peripheral circuit 11. Of course, the DRAM memory array 10 and the FRAM memory array 20 can also reuse the row driver circuit, the column driver circuit, etc. in the peripheral circuit 11.
[0081] Schematically, the multiple word lines WLa in the DRAM memory array 10 and the multiple word lines WLb in the FRAM memory array 20 can be connected to the row decoder XDEC through the row selection circuit 111, and the multiple bit lines BLa in the DRAM memory array 10 and the multiple bit lines BLb in the FRAM memory array 20 can be connected to the sense amplifier SA and the column row decoder YDEC through the column selection circuit 112. In this way, when it is necessary to operate the DRAM memory array 10, the row selection circuit 111 can be controlled to connect the multiple word lines WLa in the DRAM memory array 10 to the row decoder XDEC, and the column selection circuit 112 can be controlled to connect the multiple bit lines BLa in the DRAM memory array 10 to the sense amplifier SA and the column row decoder YDEC to meet the operation of the DRAM memory array 10. When the FRAM memory array 20 needs to be operated, the row selection circuit 111 can be controlled to connect the multiple word lines WLb in the FRAM memory array 20 to the row decoder XDEC, and the column selection circuit 112 can be controlled to connect the multiple bit lines BLb in the FRAM memory array 20 to the sense amplifier SA and the column row decoder YDEC to meet the operation of the FRAM memory array 20.
[0082] The present application does not impose any limitation on the configuration of the row selection circuit 111 and the column selection circuit 112 , as long as the selection of the DRAM memory array 10 and the FRAM memory array 20 can be satisfied.
[0083] In some possible implementations, the row selection circuit 111 may include a plurality of selectors MUX1 (also referred to as first selectors), a group of input terminals (i.e., two input terminals) of the selector MUX1 are respectively connected to a corresponding group of word lines (WLa and WLb), and an output terminal of the selector MUX1 is connected to a row decoder XDEC. According to actual needs, the selector MUX1 may be used to select the word line WLa or the word line WLb to be connected to the row decoder XDEC.
[0084] The above-mentioned correspondingly arranged group of word lines (WLa and WLb) may refer to a word line WLa connected to a row of DRAM memory cells 100, and a word line WLb connected to a row of FRAM memory cells 200 arranged directly above the row of FRAM memory cells 200. Of course, the correspondingly arranged group of word lines (WLa and WLb) may also be any word line WLa and any word line WLb.
[0085] Similar to the arrangement of the row selection circuit 111, the column selection circuit 112 may include a plurality of selectors MUX2 (also referred to as a second selector), a group of input terminals (i.e., two input terminals) of the selector MUX2 are respectively connected to a corresponding group of bit lines (BLa and BLb), and an output terminal of the selector MUX2 is connected to the sense amplifier SA. According to actual needs, the selector MUX2 may be used to select the bit line BLa or the bit line BLb to be connected to the sense amplifier SA.
[0086] The above-mentioned correspondingly arranged group of bit lines (BLa and BLb) may refer to a bit line BLa connected to a certain column of DRAM memory cells 100, and a bit line BLb connected to a column of FRAM memory cells 200 arranged directly above the row of FRAM memory cells 200. Of course, the correspondingly arranged group of bit lines (BLa and BLb) may also be any word line WLa and any word line WLb.
[0087] Figure 5 The example in which the selector (MUX1, MUX2) has two input terminals is used for illustration only, but the present application is not limited thereto.
[0088] Illustratively, in some possible implementations, the selector MUX1 may have multiple groups of input terminals, such as 4 or more input terminals, and the multiple groups of input terminals are connected to multiple groups of word lines (WLa and WLb).
[0089] Illustratively, in some possible implementations, the selector MUX2 may have multiple groups of input terminals, such as 4 or more input terminals, and the multiple groups of input terminals are connected to multiple groups of bit lines (BLa and BLb).
[0090] The DRAM-FRAM hybrid memory provided in the embodiment of the present application is further described below through specific embodiments in combination with the setting of board lines.
[0091] Embodiment 1
[0092] In the DRAM-FRAM hybrid memory provided in the first embodiment, reference is made to Figure 5 and Figure 6 As shown, the FRAM memory array 20 and the DRAM memory array 10 can reuse the plate line PL.
[0093] In terms of process integration:
[0094] refer to Fig. 9As shown in (a), transistors T1, capacitors C2, etc. can be fabricated sequentially on a substrate 1 to form a DRAM memory array 10 and a partial structure of a peripheral circuit 11. The top layer of the DRAM memory array 10 is a plate line PL, which serves as the top electrode of a plurality of capacitors C1 and can be a planar structure.
[0095] Then, refer to Fig. 9 (b) and Fig.11 As shown, a plurality of vertical ring transistors (T2), word lines WLb, and deep holes and signal lines in the peripheral area are made on the plate line PL. The word lines WLb and the signal lines in the peripheral area can be arranged in the same layer. Schematically, the plate line PL can be connected to the signal line arranged in the same layer as the word lines WLb in the peripheral circuit 11 through a via.
[0096] The configuration of the vertical ring transistor (T2) can be referred to the above description, which will not be repeated here. The specific manufacturing process of the vertical ring transistor (T2) can be manufactured according to actual needs in combination with relevant technologies.
[0097] Next, refer to Fig.10 (a) and Fig.11 As shown, a ferroelectric capacitor C2 is made on the vertical ring transistor (T2), and the ferroelectric capacitor C2 is connected to the drain (or source) of the vertical ring transistor (T2).
[0098] Illustratively, the ferroelectric capacitor C2 may be a trench-type hafnium-based ferroelectric material capacitor.
[0099] Next, refer to Fig.10 (b) and Fig.11 As shown, a bit line BLb connected to the ferroelectric capacitor C2 and a deep hole and a signal line in the peripheral area can be made, wherein the bit line BLb can be arranged in the same layer as the signal line in the peripheral area.
[0100] At this point, the stacking of the FRAM memory array 20 on the DRAM memory array 10 is completed.
[0101] In this first embodiment, the plate line PL is located below the multiple vertical annular transistors (T2) (i.e., on the side close to the substrate 1), connected to the source (or drain) of the multiple vertical annular transistors (T2), and provides an electrical signal to the source (or drain) of the transistor; at the same time, the plate line PL serves as a common electrode of the multiple capacitors C1 to provide a common voltage, and provides a common voltage to the multiple capacitors C1.
[0102] As shown, in the case where the FRAM memory array 20 and the DRAM memory array 10 reuse the plate line PL, the operation method on the DRAM memory array 10 side can adopt the operation method of mainstream DRAM products. The write operation of the FRAM memory array 20 can share a set of operation timing and power supply with the DRAM memory array 10, and only the pre-charge process before the read operation is slightly different from the DRAM memory array 10. In addition, since the FRAM memory array 20 and the DRAM memory array 10 reuse the plate line PL, during the operation, the plate line PL can always maintain the same potential (such as VDD / 2 potential), reducing the delay required for the level jump, so as to obtain a faster access speed.
[0103] The following Figure 5 The operation process of the DRAM memory array 10 and the FRAM memory array 20 is briefly described.
[0104] Fig.12 A timing diagram of a write operation process and a read operation process of a DRAM storage array 10 provided in an embodiment of the present application, Fig.13 A timing diagram of a write operation process and a read operation process of a FRAM storage array 20 provided in an embodiment of the present application. Fig.12 The reference bit line BLB in is a reference bit line in a reference memory array corresponding to the DRAM memory array 10 . Fig.13 The reference bit line BLB* in is a reference bit line in a reference memory array corresponding to the FRAM memory array 20 .
[0105] For the DRAM memory array 10:
[0106] Indicative, reference Figure 5 and Fig.12 As shown, the write operation process of the DRAM storage array 10 may include:
[0107] Precharge phase PRE (precharge): the word line WLa is closed, and the bit line BL and the reference bit line BLB are precharged to the VDD / 2 potential.
[0108] Charge sharing stage CS: the word line WLa is turned on (ie, the transistor T1 is turned on), and the internal nodes of the memory cell 100 (bitcell) perform charge sharing.
[0109] Sense amplification stage SE (sense): the sense amplifier SA enable signal is turned on, and the voltage difference between the bit line BLa and the reference bit line BLB is amplified by the sense amplifier SA.
[0110] Write phase (write): The input-output (IO) signal is connected to the internal nodes of the sense amplifier SA and the internal nodes of the memory cell 100 (bitcell) through the bit line BLa, and the voltages of the internal nodes of the sense amplifier SA and the internal nodes of the memory cell 100 (bitcell) are rewritten. If "0" is written, the bit line BLa is pulled down to the VSS voltage (low voltage), and the reference bit line BLB is pulled up to the VDD voltage (high voltage). If "1" is written, the bit line BLa is pulled up to the VDD voltage, and the reference bit line BLB is pulled down to VSS, thereby realizing data writing. Fig.12 The example of writing "1" is used here.
[0111] Precharge phase PRE (precharge): word line WLa is closed, and bit line BLa and reference bit line BLB are precharged to VDD / 2 potential.
[0112] Indicative, reference Figure 5 and Fig.12 As shown, the read operation process of the DRAM storage array 10 may include:
[0113] Precharge phase PRE (precharge): word line WLa is closed, and bit line BLa and reference bit line BLB are precharged to VDD / 2 potential.
[0114] Charge sharing stage CS: the word line WLa is turned on (ie, the transistor T1 is turned on), and the internal nodes of the memory cell 100 (bitcell) perform charge sharing.
[0115] Read phase (read): The input-output circuit (IO circuit) is connected to the internal nodes of the sense amplifier SA and the internal nodes of the memory cell 100 (bitcell) through the bit line BLa. The sense amplifier SA outputs the read signal to the IO circuit and stores it back into the memory cell 100. Fig.12 The example of “read 1” is used in the following description.
[0116] Precharge phase PRE (precharge): word line WLa is closed, and bit line BLa and reference bit line BLB are precharged to VDD / 2 potential.
[0117] For the FRAM memory array 20:
[0118] refer to Fig.12 , Fig.13 As shown, the write operation process of the FRAM storage array 20 is basically the same as the write operation process of the DRAM storage array 10. Regarding the write operation process of the FRAM storage array 20, reference may be made to the write operation process of the aforementioned DRAM storage array 10, which will not be repeated here.
[0119] refer to Figure 5 and Fig.13 As shown, the read operation process of the FRAM storage array 20 may include:
[0120] Precharge phase PRE (precharge): the word line WLb is closed, the bit line BLb is precharged to 0V, and the reference bit line BLB* is precharged to the reference potential VREF.
[0121] Charge sharing stage CS: the word line WLb is turned on (ie, the transistor T2 is turned on), and the internal nodes of the memory cell 100 (bit cell) perform charge sharing.
[0122] Read phase (read): the IO circuit is connected to the internal node of the sense amplifier SA and the internal node of the memory cell 100 (bitcell) through the bit line BLb. The signal read out by the sense amplifier SA is output to the IO circuit and stored in the memory cell 100 again. Fig.13 This is explained using "read 1" as an example.
[0123] Precharge phase PRE (precharge): the word line WLb is closed, and the bit line BLb and the reference bit line BLB* are precharged to the VDD / 2 potential.
[0124] Embodiment 2
[0125] In the DRAM-FRAM hybrid memory provided in the second embodiment, reference Fig.14 , Fig.15 , Fig.16 , Fig.17 As shown, the plate line PLa (also called the first plate line) can be used in the DRAM memory array 10, and the plate line PLb (also called the second plate line) can be used in the FRAM memory array 20, that is, different plate lines can be set in the FRAM memory array 20 and the DRAM memory array 10, respectively.
[0126] Compared with the DRAM memory array 10, when performing read and write operations, the plate line PLa can use a small voltage (VDD / 2) to meet the requirements, while when the FRAM memory array 20 performs read and write operations, the ferroelectric capacitor C2 uses a higher read and write voltage device to have better electrical performance. Therefore, by setting different plate lines in the FRAM memory array 20 and the DRAM memory array 10 respectively, the voltage of the plate line PLb can be flexibly set, and a larger voltage can be used to better meet the needs of the ferroelectric capacitor C2.
[0127] Schematically, the plate lines PLa in the above-mentioned DRAM memory array 10 may adopt a planar structure.
[0128] As shown, the plate line PLb in the FRAM storage array 20 may adopt a planar structure or a stripe structure (see Fig.18 ).
[0129] When the plate line PLb adopts a strip structure, a plurality of plate lines PLb may be provided in the FRAM memory array 20, and a single plate line PLb may be connected to the FRAM memory cells 200 located in the same row or the same column. The specific connection method may be as follows:
[0130] For example, in some possible implementations, reference Fig.14 As shown, the plate line PLb can be a strip structure extending in the row direction, and a single plate line PLb is connected to the top electrodes of multiple capacitors C2 in the same row. In this case, the plate line PLb can be located in the metal layer above the capacitor C2 (i.e., away from the side of the plate line PLa).
[0131] For example, in some possible implementations, reference Fig.15 As shown, the plate line PLb may be a strip structure extending along the column direction, and a single plate line PLb may be connected to the top electrodes of multiple capacitors C2 in the same column. In this case, the plate line PLb may be located in a metal layer above the capacitor C2.
[0132] For example, in some possible implementations, reference Fig.16 As shown, the plate line PLb may be a strip structure extending in the row direction, and a single plate line PLb may be connected to the sources (or drains) of multiple transistors T2 in the same row. In this case, the plate line PLb may be located in a metal layer between the plate line PLa and the transistor T2.
[0133] For example, in some possible implementations, reference Fig.17 As shown, the plate line PLb may be a strip structure extending in the column direction, and a single plate line PLb may be connected to the sources (or drains) of multiple transistors T2 in the same column. In this case, the plate line PLb may be located in a metal layer between the plate line PLa and the transistor T2.
[0134] by Fig.16 Take the schematic DRAM-FRAM hybrid memory as an example, in terms of process integration:
[0135] refer to Fig.18 As shown in (a), transistors T1, capacitors C2, etc. can be fabricated sequentially on a substrate 1 to form a DRAM memory array 10 and a partial structure of a peripheral circuit 11. The top layer of the DRAM memory array 10 is a plate line PLa, which serves as the top electrode of a plurality of capacitors C1 and can be a planar structure.
[0136] Then, refer to Fig.18 As shown in (b), a through hole for leading out the plate line PLa and a through hole located in the peripheral area are made.
[0137] Next, refer to Fig.19 (a) and Fig. 20 As shown, the plate line PLb and the signal line in the peripheral area are manufactured. The plate line PLa can be connected to the signal line in the peripheral circuit 11 arranged in the same layer as the plate line PLb through a via hole.
[0138] Next, refer to Fig.19 (b) and Fig. 20 As shown, firstly, a vertical ring transistor (T2) and a word line WLb are made; then, a ferroelectric capacitor C2 (such as a trench-type hafnium-based ferroelectric material capacitor) and a bit line WLb located above the ferroelectric capacitor C2 are made. Among them, the source (or drain) of the vertical ring transistor (T2) is connected to the plate line PLb, and one electrode of the ferroelectric capacitor C2 is connected to the drain (or source) of the vertical ring transistor (T2). Among them, the setting of the vertical ring transistor (T2) can refer to the relevant description in the previous text, which will not be repeated here.
[0139] At this point, the stacking of the FRAM memory array 20 on the DRAM memory array 10 is completed.
[0140] In the second embodiment, the writing operation or reading operation process of the DRAM storage array 10 is basically the same as that of the first embodiment. For details, please refer to the first embodiment, which will not be described again.
[0141] by Fig.16 Taking the illustrated DRAM-FRAM hybrid memory as an example, the operation process of the FRAM storage array 20 in the second embodiment is briefly described below.
[0142] Fig.21 A timing diagram of a write operation process and a read operation process of a FRAM storage array 20 provided in an embodiment of the present application. Fig.21 The reference bit line BLB* in is a reference bit line in a reference memory array corresponding to the FRAM memory array 20 .
[0143] Indicative, reference Fig.16 and Fig.21 As shown, the write operation process of the FRAM storage array 20 may include:
[0144] Precharge phase PRE (precharge): the word line WLb is closed, the bit line BLb is precharged to the VSS potential (low potential), and the reference bit line BLB* is precharged to the reference potential VREF.
[0145] Charge sharing stage CS (charge sharing): word line WLb is turned on (ie transistor T2 is turned on), bit line BLb maintains low potential VSS, bit line PLb is raised to VDD potential (high potential), and FRAM storage unit 200 (bit cell) is uniformly erased to 0.
[0146] Sense amplification stage SE (sense): the sense amplifier SA enable signal is turned on, and the voltage difference between the bit line BLb and the reference bit line BLB* is amplified by the sense amplifier SA.
[0147] Write phase (write): The bit line PLb is pulled down to the VSS potential (low potential), and the IO circuit is connected to the internal node of the sense amplifier SA and the internal node of the storage cell 200 (bitcell) through the bit line BLb, and rewrites the voltage of the internal node of the sense amplifier SA and the internal node of the storage cell 200 (bitcell). If "0" is written, the bit line BLb is pulled down to the VSS voltage, and the reference bit line BLB* is pulled up to the VDD voltage. If "1" is written, the bit line BLb is pulled up to the VDD voltage, and the reference bit line BLB* is pulled down to VSS, thereby realizing data writing. Fig.13 The example of "writing 1" is used in the following description.
[0148] Precharge phase PRE (precharge): the word line WLb is closed, the bit line BLb is precharged to the VSS potential (low potential), and the reference bit line BLB* is precharged to the reference potential VREF.
[0149] Indicative, reference Fig.16 and Fig.21 As shown, the read operation process of the FRAM storage array 20 may include:
[0150] Precharge phase PRE (precharge): the word line WLb is closed, the bit line BLb is precharged to the VSS potential (low potential), and the reference bit line BLB* is precharged to the reference potential VREF.
[0151] Charge sharing stage CS (charge sharing): word line WLa is turned on (ie transistor T1 is turned on), bit line BLb maintains low potential VSS, bit line PLb is raised to VDD potential (high potential), and internal nodes of memory cell 200 (bitcell) perform charge sharing.
[0152] Sense amplification stage SE (sense): the sense amplifier SA enable signal is turned on, and the voltage difference between the bit line BLb and the reference bit line BLB* is amplified by the sense amplifier SA.
[0153] Read phase (read): the IO circuit is connected to the internal nodes of the sense amplifier SA and the internal nodes of the memory cell 100 (bitcell) through the bit line BLb. The sense amplifier SA outputs the read signal to the IO circuit and stores it back into the memory cell 200 .
[0154] Precharge phase PRE (precharge): the word line WLb is closed, the bit line BLb is precharged to the VSS potential (low potential), and the reference bit line BLB* is precharged to the reference potential VREF.
[0155] In addition, for the DRAM-FRAM hybrid memory provided in the aforementioned embodiments (including Embodiment 1 and Embodiment 2), in the control process, it is necessary to select to operate the DRAM storage array 10 or the FRAM storage array 20 according to actual needs. For example, in some possible implementations, it is necessary to place frequently accessed data (hot data) in the DRAM storage array 10, and then it is necessary to operate the DRAM storage array 10, and to place infrequently accessed data (cold data) in the FRAM storage array 20, and then it is necessary to operate the FRAM storage array 20.
[0156] The following is a brief description of the control method of DRAM-FRAM hybrid memory.
[0157] Schematically, the present application embodiment provides a control method for a DRAM-FRAM hybrid memory, referring to Figure 5 and Fig. 22 As shown, the control method may include:
[0158] Step 01: Obtain an access request to the DRAM storage array 10 or the FRAM storage array 20.
[0159] Step 02: According to the access request, a first control signal is sent to the row selection circuit 111, and a second control signal is sent to the column selection circuit 112; wherein the first control signal and the second control signal are used to indicate that the DRAM storage array 10 or the FRAM storage array 20 is connected to the row decoder XDEC and the sense amplifier SA.
[0160] Illustratively, in some possible implementations, the control method may include: a processor (central processing unit, CPU) generates a first control signal and a second control signal according to a current data access request, and sends them to a row selection circuit 111 and a column selection circuit 112, respectively.
[0161] If the current data is frequently accessed data (hot data), the DRAM memory array 10 is selected, and the row selection circuit 111, under the control of the first control signal (hot data control signal H), connects the multiple word lines WLa in the DRAM memory array 10 to the row decoder XDEC, and the column selection circuit 112, under the control of the second control signal (hot data control signal H), connects the multiple bit lines BLa in the DRAM memory array 10 to the sense amplifier SA to meet the operation of the DRAM memory array 10.
[0162] If the current data is infrequently accessed data (cold data), the FRAM memory array 20 is selected, and the row selection circuit 111 connects the multiple word lines WLb in the FRAM memory array 20 to the row decoder XDEC under the control of the first control signal (cold data control signal C), and the column selection circuit 112 connects the multiple bit lines BLb in the FRAM memory array 20 to the sense amplifier SA under the control of the second control signal (cold data control signal C) to meet the operation of the FRAM memory array 20.
[0163] Among them, all relevant contents of each step involved in the above control method embodiment can be referred to the functional description of the corresponding functional module, and will not be repeated here.
[0164] This embodiment also provides a computer-readable storage medium, in which computer instructions are stored. When the computer instructions are executed on an electronic device, the electronic device executes the above-mentioned related method steps to implement the control of the DRAM-FRAM hybrid memory in the above-mentioned embodiment.
[0165] This embodiment further provides a computer program product. When the computer program product is run on a computer, the computer is caused to execute the above-mentioned related steps to implement the control of the DRAM-FRAM hybrid memory in the above-mentioned embodiment.
[0166] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art who is familiar with the present technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.
Claims
1. A storage device, characterized in that: The invention comprises a first storage array, a second storage array and a peripheral circuit arranged on a substrate: The first storage array and the second storage array are stacked, and the second storage array is located on a side of the first storage array away from the substrate; the peripheral circuit is arranged in the peripheral area of the first storage array and the second storage array; The first storage array is a dynamic random access memory DRAM storage array, and the second storage array is a non-volatile memory NVM storage array; The peripheral circuit includes a row selection circuit, a column selection circuit, a row decoder, and a sense amplifier; The row selection circuit is configured to: control the first storage array or the second storage array to be connected to the row decoder; The column selection circuit is configured to control the first memory array or the second memory array to be connected to the sense amplifier.
2. The storage device according to claim 1, characterized in that The second storage array is a ferroelectric memory FRAM storage array.
3. The storage device according to claim 1 or 2, characterized in that: The first storage array includes a plurality of first storage cells, a plurality of first bit lines, and a plurality of first word lines; a plurality of the first storage cells in the same row are connected to the same first word line, and a plurality of the first storage cells in the same column are connected to the same first bit line; The second storage array includes a plurality of second storage cells, a plurality of second bit lines, and a plurality of second word lines; A plurality of the second storage cells in the same row are connected to the same second word line, and a plurality of the second storage cells in the same column are connected to the same second bit line; The plurality of first word lines and the plurality of second word lines are connected to the row decoder through the row selection circuit; The plurality of first bit lines and the plurality of second bit lines are connected to the sense amplifier through the column selection circuit.
4. The storage device according to claim 3, characterized in that: The plurality of first storage units and the plurality of second storage units are respectively arranged opposite to each other.
5. The storage device according to claim 3 or 4, characterized in that: The first storage unit includes at least one first transistor and at least one first capacitor, wherein the first capacitor is located on a side of the first transistor away from the substrate; The second storage unit includes at least one second transistor and at least one second capacitor, and the second capacitor is located on a side of the second transistor away from the first storage array.
6. The storage device according to claim 5, characterized in that: The second transistor is a vertical gate-all-around transistor.
7. The storage device according to claim 5 or 6, characterized in that: The second capacitor is a trench ferroelectric capacitor.
8. The storage device according to any one of claims 5 to 7, characterized in that: The storage device includes a plate line; the plate line is located on a side of the plurality of second transistors close to the substrate and connected to the second transistors; The plate line serves as a common electrode of the first capacitors, and the plate line is connected to sources or drains of the second transistors in the second storage array.
9. The storage device according to any one of claims 5 to 7, characterized in that: The first storage array includes a first plate line, and the second storage array includes a second plate line; The first plate line is located on a side of the plurality of second transistors close to the substrate, the first plate line comprises a planar electrode, and the planar electrode serves as a common electrode of the plurality of first capacitors; The second plate line is located at a side of the first plate line away from the substrate, and the second plate line is connected to a plurality of the second capacitors.
10. The storage device according to claim 9, characterized in that: The second plate line is located between the plurality of the second transistors and the first plate line; The second plate line includes a plurality of strip electrodes, and a single strip electrode is connected to sources or drains of a plurality of the second transistors in the same row or column.
11. The storage device according to claim 9, characterized in that The second plate line is located at a side of the plurality of second capacitors away from the first plate line; The second plate line includes a planar electrode, and the planar electrode is connected to a plurality of the second capacitors; Alternatively, the second plate line includes a plurality of strip electrodes, and a single strip electrode is connected as a plurality of the second capacitors in the same row or column.
12. An electronic device, characterized in that: It comprises a circuit board and a storage device as claimed in any one of claims 1 to 11, wherein the storage device is electrically connected to the circuit board.
13. A method for controlling a storage device according to any one of claims 1 to 11, characterized in that: include: Obtaining an access request to the first storage array or the second storage array; According to the access request, a first control signal is sent to the row selection circuit, and a second control signal is sent to the column selection circuit; wherein the first control signal and the second control signal are used to indicate that the first storage array or the second storage array is connected to the row decoder and the sense amplifier.
14. A computer-readable storage medium comprising a computer program, characterized in that: When the computer program is executed on an electronic device, the electronic device is caused to execute the storage device control method according to claim 13 .
15. A computer program product, characterized in that When the computer program product is executed on a computer, the computer is caused to execute the storage device control method according to claim 13 .