Hammer defense circuit based on RRAM double-layer counting

Abstract

The invention discloses a row hammer prevention circuit based on RRAM double-layer counting, which comprises a decoder circuit, a group counter circuit, four row counter circuits and a first PMOS tube, and is characterized in that the group counter circuit and the four row counter circuits are respectively realized based on RRAM devices; the decoder circuit is used for converting a 2-bit binary address signal into 4-bit binary decoding signals and outputting the 4-bit binary decoding signals to the four row counter circuits in a one-to-one correspondence manner, and the group counter circuit is used for counting high level of an external enable signal EN and generating a corresponding counting signal REN according to a counting value for outputting. The first POMS tube is used for controlling the counting signal REN to be output to the four row counter circuits, each row counter is used for counting high level output to the row counter circuit by the decoder circuit, outputting a low-level warning signal when the counting value does not reach the counting upper limit, and outputting a low-level warning signal when the counting value reaches the counting upper limit. A high-level warning signal is output; the method has the advantage of low hardware overhead.

Description

Technical Field

[0001] The invention relates to a hammer defense circuit, in particular to a hammer defense circuit based on RRAM double-layer counting. Background Art

[0002] With the development of manufacturing process technology, the storage density of dynamic random access memory has been significantly improved. The interaction between circuit elements will lead to the problem of coupling crosstalk. Researchers have found that dynamic random access memory is susceptible to the row hammer phenomenon: when a certain memory row in the dynamic random access memory (that is, a bit output line in the dynamic random access memory) is activated at a high frequency, it may induce a bit flip in its physically adjacent memory row. As a result, attackers can use this phenomenon to perform an attack on the dynamic random access memory on the computer system, namely a row hammer attack, thereby achieving privilege escalation and access to data in any memory row of the dynamic random access memory.

[0003] At present, the row hammer defense circuit designed based on the row counter tracking strategy can effectively solve the row hammer attack problem of dynamic random access memory. The row hammer defense circuit tracks the number of times each memory row in the dynamic random access memory is activated. Once the number of activations of a certain memory row reaches the preset threshold that triggers a row hammer attack, the memory row is prevented from being activated further.

[0004] However, the existing row hammer defense circuit requires a large number of counters to count a memory row. For example, when the threshold for triggering a row hammer attack is 1,000 times, a 10-bit static random access memory needs to be set to count a memory row, which brings a lot of hardware overhead. Summary of the invention

[0005] The technical problem to be solved by the present invention is to provide a defensive row hammer circuit based on RRAM double-layer counting with low hardware overhead.

[0006] The technical solution adopted by the present invention to solve the above technical problems is: a defensive row hammer circuit based on RRAM double-layer counting, including a decoder circuit, a group counter circuit, four row counter circuits and a first PMOS tube, the four row counter circuits are respectively referred to as a first row counter circuit, a second row counter circuit, a third row counter circuit and a fourth row counter circuit; the group counter circuit and the four row counter circuits are respectively implemented based on RRAM devices, the decoder circuit is used to convert the 2-bit binary address signal outputted externally thereto into a 4-bit binary decoding signal under the control of an external enable signal EN and output it to the four row counter circuits one by one, the first PMOS tube is used to be turned on or off under the control of the signal connected to its gate, when the signal connected to the gate of the first PMOS tube is at a low level, the first PMOS tube is turned on, the group counter circuit is connected to the four row counter circuits through the first PMOS tube, the group counter circuit can output signals to the four row counter circuits, when the signal connected to the gate of the first POMS tube is at a high level, the first POMS tube is turned off, the group counter circuit is connected to the four row counter circuits through the first PMOS tube, the group counter circuit can output signals to the four row counter circuits, when the signal connected to the gate of the first POMS tube is at a high level, the first POMS tube is turned off, the group counter The circuit is disconnected from the four row counter circuits, the group counter circuit cannot output signals to the four row counter circuits, and the group counter circuit cannot affect the working states of the four row counter circuits. The group counter circuit is used to count the high level of the external enable signal EN, and generate a corresponding counting signal R_EN according to the count value and output it to the drain of the first PMOS tube. If the count value does not reach the upper limit of the group counter counting circuit, the counting signal R_EN output by the group counter circuit is a low level. If the count value reaches the upper limit of the count of the group counter circuit, the counting signal R_EN output by the group counter circuit is a high level. The row counter circuit is used to count the high level output by the decoder circuit when the signal output by the decoder circuit is a high level, the counting signal R_EN output by the group counter circuit is a high level, and the signal connected to the gate of the first PMOS is a low level, and output a low level warning signal Alert when the count value does not reach its upper limit, and output a high level warning signal Alert when the count value reaches its upper limit.

[0007] The decoder circuit has three input terminals and four output terminals, and its three input terminals are respectively referred to as its first input terminal, second input terminal and third input terminal, and its four output terminals are respectively referred to as its first output terminal, second output terminal, third output terminal and fourth output terminal; the group counter circuit has five input terminals and one output terminal, and its five input terminals are respectively referred to as its first input terminal, second input terminal, third input terminal, fourth input terminal and fifth input terminal; each of the row counter circuits has five input terminals and one output terminal, and its five input terminals are respectively referred to as its first input terminal, second input terminal, third input terminal, fourth input terminal and fifth input terminal; the first input terminal of the decoder circuit is used to access the first bit A of the 2-bit binary address signal, and the second input terminal of the decoder circuit is used to access the second bit B of the 2-bit binary address signal; the first output terminal of the decoder circuit is used to output The first bit of the 4-bit binary decoded signal is outputted from the decoder circuit; the second output terminal of the decoder circuit is used to output the second bit of the 4-bit binary decoded signal; the third output terminal of the decoder circuit is used to output the third bit of the 4-bit binary decoded signal; the fourth output terminal of the decoder circuit is used to output the fourth bit of the 4-bit binary decoded signal; the third input terminal of the decoder circuit is connected to the first input terminal of the group counter circuit, and its connection terminal is the enable terminal of the defense hammer circuit, which is used to access the external enable signal EN; the second input terminal of the group counter circuit is connected to the power supply VDD; the third input terminal of the group counter circuit is the first refresh terminal of the defense hammer circuit, which is used to access the first refresh signal Ref1 that enables the group counter circuit to be reopened; the fourth input terminal of the group counter circuit is the first reference terminal of the defense hammer circuit, which is used to access the first reference voltage V rfe1; The fifth input end of the group counter circuit is the first control end of the defense hammer circuit, which is used to access the first control signal SA1_CTL for controlling whether the output end of the group counter circuit outputs a signal; the first output end of the decoder circuit is connected to the first input end of the first row counter circuit, the second output end of the decoder circuit is connected to the first input end of the second row counter circuit, the third output end of the decoder circuit is connected to the first input end of the third row counter circuit, the fourth output end of the decoder circuit is connected to the first input end of the fourth row counter circuit, the second input end of the first row counter circuit, the second input end of the second row counter circuit, the second input end of the third row counter circuit and the second input end of the fourth row counter circuit are connected, and the connection end is the second control end of the defense hammer circuit, which is used to access the second control signal SA1_CTL for controlling whether the output end of the group counter circuit outputs a signal. SA2_CTL; the third input terminal of the first row counter circuit, the third input terminal of the second row counter circuit, the third input terminal of the third row counter circuit, the third input terminal of the fourth row counter circuit and the gate of the first PMOS tube are connected, and the connection terminal is the second refresh terminal of the defense row hammer circuit, which is used to access the second refresh signal Ref2 that reopens the row counter circuit; the source of the first PMOS tube is respectively connected to the fourth input terminal of the first row counter circuit, the fourth input terminal of the second row counter circuit, the fourth input terminal of the third row counter circuit and the fourth input terminal of the fourth row counter circuit, the fifth input terminal of the first row counter circuit, the fifth input terminal of the second row counter circuit, the fifth input terminal of the third row counter circuit and the fifth input terminal of the fourth row counter circuit are connected, and the connection terminal is the second reference terminal of the defense row hammer circuit, which is connected to the second reference voltage V rfe2 .

[0008] The group counter circuit includes a first NMOS tube, a second NMOS tube, a third NMOS tube, a fourth NMOS tube, a fifth NMOS tube, a second PMOS tube, a first sensitive amplifier, a first memristor and a second memristor. The first sensitive amplifier has a non-inverting input terminal, an inverting input terminal, an output terminal and an enable terminal. The first memristor and the second memristor both have a top electrode and a bottom electrode. The initial resistance state of the first memristor is a high resistance state, and the initial resistance state of the second memristor is a low resistance state. The drain of the first NMOS tube is connected to the drain of the fourth NMOS tube, and the connection end thereof is the second input terminal of the group counter circuit. The gate of the first NMOS tube and the gate of the fifth NMOS tube are connected to the enable terminal of the first sensitive amplifier, and the connection end thereof is the first input terminal of the group counter circuit. The source of the first NMOS tube is connected to the top electrode of the first memristor. The bottom electrode, the gate of the fifth NMOS tube and the enable terminal of the first sensitive amplifier are connected. The source of the second PMOS tube is connected to the in-phase input terminal of the first sensitive amplifier, the inverting input terminal of the first sensitive amplifier is the fourth input terminal of the group counter circuit, the drain of the second PMOS tube, the top electrode of the second memristor and the drain of the third NMOS tube are connected, the gate of the third NMOS tube, the gate of the second PMOS tube and the gate of the fourth NMOS tube are connected, and their connection end is the third input terminal of the group counter circuit, the source of the third NMOS tube and the source of the fifth NMOS tube are both grounded, the bottom electrode of the second memristor, the source of the fourth NMOS tube and the drain of the fifth NMOS tube are connected, the output terminal of the first sensitive amplifier is connected to the drain of the second NMOS tube, the gate of the second NMOS tube is the fifth input terminal of the group counter circuit, and the source of the second NMOS tube is the output terminal of the group counter circuit.

[0009] Each of the row counter circuits includes a sixth NMOS tube, a seventh NMOS tube, an eighth NMOS tube, a ninth NMOS tube, a third PMOS tube, a fourth PMOS tube, a second sensitive amplifier, a third memristor and a fourth memristor. The second sensitive amplifier has a non-inverting input terminal, an inverting input terminal, an output terminal and an enable terminal. The third memristor and the fourth memristor both have a top electrode and a bottom electrode. The initial resistance state of the third memristor is a high resistance state, and the initial resistance state of the fourth memristor is a low resistance state. The top electrode of the third memristor, the gate of the eighth NMOS tube and the enable terminal of the second sensitive amplifier are connected, and the connection terminal is the first input terminal of the row counter circuit. The source of the sixth NMOS tube is connected to the bottom electrode of the third memristor. The drain of the sixth NMOS tube and the source of the third PMOS tube are connected to the non-inverting input terminal of the second sensitive amplifier. The inverting input terminal of the second sensitive amplifier is the The fifth input terminal of the row counter circuit, the drain of the third PMOS tube, the top electrode of the fourth memristor and the drain of the eighth NMOS tube are connected, the gate of the ninth NMOS tube, the gate of the third PMOS tube and the gate of the fourth PMOS tube are connected, and their connection end is the third input terminal of the row counter circuit, the source of the eighth NMOS tube and the drain of the fourth PMOS tube are both grounded, the bottom electrode of the fourth memristor, the source of the fourth PMOS tube and the source of the ninth NMOS tube are connected, the drain of the ninth NMOS tube is connected to the power supply voltage, the output terminal of the second sensitive amplifier is connected to the drain of the seventh NMOS tube, the gate of the seventh NMOS tube is the second input terminal of the row counter circuit, the source of the seventh NMOS tube is the output terminal of the row counter circuit, and the gate of the sixth NMOS tube is the fourth input terminal of the row counter circuit.

[0010] The first sensitive amplifier includes a fifth PMOS tube, a sixth PMOS tube, a seventh PMOS tube, an eighth PMOS tube, a tenth NMOS tube, an eleventh NMOS tube, a twelfth NMOS tube, a thirteenth NMOS tube and a fourteenth NMOS tube, the source of the fifth PMOS tube, the source of the sixth PMOS tube, the source of the seventh PMOS tube and the source of the eighth PMOS tube are all connected to the power supply voltage, the gate of the fifth PMOS tube, the gate of the eighth PMOS tube and the gate of the fourteenth NMOS tube are connected, and the connection end thereof is the enable end of the first sensitive amplifier, the drain of the fifth PMOS tube, the drain of the sixth PMOS tube, the drain of the tenth NMOS tube, the gate of the seventh PMOS tube and the gate of the eleventh NMOS tube are connected, and the connection end thereof is the enable end of the first sensitive amplifier, The output end of the sensitive amplifier, the drain of the seventh PMOS tube, the drain of the eighth PMOS tube, the drain of the eleventh NMOS tube, the gate of the sixth PMOS tube and the gate of the tenth NMOS tube are connected, the source of the tenth NMOS tube is connected to the drain of the twelfth NMOS tube, the gate of the twelfth NMOS tube is the inverting input end of the first sensitive amplifier, the source of the eleventh NMOS tube is connected to the drain of the thirteenth NMOS tube, the gate of the thirteenth NMOS tube is the non-inverting input end of the first sensitive amplifier, the source of the twelfth NMOS tube, the source of the thirteenth NMOS tube and the drain of the fourteenth NMOS tube are connected, and the source of the fourteenth NMOS tube is grounded; the circuit structure of the second sensitive amplifier is the same as that of the first sensitive amplifier.

[0011] Compared with the prior art, the present invention has the advantage that a row hammer defense circuit is formed by a decoder circuit, a group counter circuit, four row counter circuits and a first PMOS tube. The group counter circuit and the four row counter circuits are respectively implemented based on RRAM devices. Under the control of an enable signal EN, a 2-bit binary address signal outputted externally thereto is converted into a 4-bit binary decoding signal and outputted to the four row counter circuits one by one. The first PMOS tube is used to be turned on or off under the control of a signal connected to its gate. When the signal connected to the gate of the first PMOS tube is at a low level, the first PMOS tube is turned on. The group counter circuit is connected to the four row counter circuits through the first PMOS tube. The group counter circuit can output signals to the four row counter circuits. When the signal connected to the gate of the first POMS tube is at a high level, the first POMS tube is turned off. The group counter circuit is disconnected from the four row counter circuits. The group counter circuit cannot output signals to the four row counter circuits. The group counter circuit cannot affect the working state of the four row counter circuits. The group counter circuit is used to count the high level of the external enable signal EN, and generate a corresponding counting signal R_EN according to the count value and output it to the first PMOS tube. The drain of the S tube, if the count value does not reach the upper limit of the group counter counting circuit, the count signal R_EN output by the group counter circuit is low level, if the count value reaches the upper limit of the group counter circuit, the count signal R_EN output by the group counter circuit is high level; the row counter circuit is used to count the high level output by the decoder circuit when the signal output to it by the decoder circuit is high level, the count signal R_EN output by the group counter circuit is high level and the signal connected to the gate of the first PMOS is low level, and outputs a low level when the count value does not reach its upper limit The invention outputs a warning signal Alert of a low level, and when the count value reaches its count upper limit, a warning signal Alert of a high level is output. Therefore, the present invention only needs to use a one-bit group counter circuit and a four-bit row counter circuit to accurately complete the counting operation of the four-bit output lines in the dynamic random access memory, and output a row hammer attack warning signal to achieve defense against row hammer attacks. Compared with the traditional defense row hammer circuit that needs to rely on multi-bit static random access memory and complex peripheral circuits to count a one-bit output line in the dynamic random access memory, the hardware overhead is significantly reduced, and the hardware overhead is relatively small. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 It is a module block diagram of the defensive hammer circuit based on RRAM double-layer counting of the present invention.

[0013] Figure 2 It is a circuit diagram of a group counter circuit of a hammer defense circuit based on RRAM double-layer counting of the present invention.

[0014] Figure 3It is a circuit diagram of a row counter circuit of a row hammer defense circuit based on RRAM double-layer counting of the present invention.

[0015] Figure 4 A circuit diagram of a first sense amplifier of a defense hammer circuit based on RRAM double-layer counting of the present invention;

[0016] Figure 5 It is a counting and reset function test diagram of the group counter circuit of the defense hammer circuit based on RRAM double-layer counting of the present invention;

[0017] Figure 6 This is a test diagram of the counting and resetting functions of the row counter circuit of the row hammer defense circuit based on RRAM double-layer counting of the present invention. DETAILED DESCRIPTION

[0018] The present invention is further described in detail below with reference to the accompanying drawings.

[0019] Embodiment 1: Figure 1As shown, a defensive row hammer circuit based on RRAM double-layer counting includes a decoder circuit, a group counter circuit, four row counter circuits and a first PMOS tube P1, and the four row counter circuits are respectively referred to as a first row counter circuit, a second row counter circuit, a third row counter circuit and a fourth row counter circuit; the group counter circuit and the four row counter circuits are respectively implemented based on RRAM devices, the decoder circuit is used to convert a 2-bit binary address signal outputted externally thereto into a 4-bit binary decoding signal under the control of an external enable signal EN and output it to the four row counter circuits in a one-to-one correspondence, the first PMOS tube is used to be turned on or off under the control of a signal connected to its gate, when the signal connected to the gate of the first PMOS tube is at a low level, the first PMOS tube is turned on, the group counter circuit is connected to the four row counter circuits through the first PMOS tube P1, the group counter circuit can output signals to the four row counter circuits, when the signal connected to the gate of the first POMS tube is at a high level, the first POMS tube is turned off, and the group counter circuit is connected to the four row counter circuits. The counter circuits are all disconnected, the group counter circuit cannot output signals to the four row counter circuits, and the group counter circuit cannot affect the working states of the four row counter circuits. The group counter circuit is used to count the high level of the external enable signal EN, and generate a corresponding counting signal R_EN according to the count value and output it to the drain of the first PMOS tube P1. If the count value does not reach the upper limit of the group counter counting circuit, the counting signal R_EN output by the group counter circuit is a low level. If the count value reaches the upper limit of the group counter circuit, the counting signal R_EN output by the group counter circuit is a high level. The row counter circuit is used to count the high level output by the decoder circuit when the signal output by the decoder circuit is a high level, the counting signal R_EN output by the group counter circuit is a high level, and the signal connected to the gate of the first PMOS is a low level, and output a low-level warning signal Alert when the count value does not reach its upper limit, and output a high-level warning signal Alert when the count value reaches its upper limit.

[0020] In this embodiment, the working principle of the hammer protection circuit based on RRAM double-layer counting is as follows:

[0021] When the counting signal R_EN output by the group counter circuit is low level and the signal connected to the gate of the first PMOS tube P1 is low level, the first PMOS tube P1 is turned on. Although the group counter circuit outputs the counting signal R_EN to the four row counter circuits, the four row counter circuits do not work.

[0022] When the external enable signal EN is at a low level, the decoder circuit, the group counter circuit and the four row counter circuits do not work.

[0023] When the external enable signal EN is at a high level, the signal connected to the gate of the first PMOS is at a low level, and the 2-bit binary address signal connected to the decoder circuit is 00, the first PMOS tube P1 is turned on, and the decoder circuit outputs a 4-bit binary decoding signal of 0001. At this time, the high level 1 in the 4-bit binary decoding signal is output to the first row counter circuit, and the 3 low levels 0 in the 4-bit binary decoding signal are output to the second row counter circuit, the third row counter circuit and the fourth row counter circuit one by one. The second row counter circuit, the third row counter circuit and the fourth row counter circuit are all not working, and the first row counter circuit enters a standby state. The group counter circuit counts the high level of the external enable signal EN, and generates a corresponding counting signal R_EN according to the count value and outputs it to the drain of the first PMOS tube P1. If the count value does not reach the upper limit of the group counter counting circuit, the counting signal R_EN output by the group counter circuit is a low level. At this time, the first row counter circuit remains in a standby state. When the count value reaches the counting upper limit of the group counter circuit, the group counter circuit The counting signal R_EN output by the counter circuit is at a high level, and the first row counter circuit starts to work. The first row counter circuit counts the high level output by the decoder circuit to it. When the count value of the first row counter circuit does not reach the counting upper limit of the first row counter circuit, the first row counter circuit outputs a low-level warning signal Alert. When the count value reaches the counting upper limit of the first row counter circuit, the first row counter circuit outputs a high-level warning signal Alert. When the first row counter circuit outputs a high-level warning signal Alert, the signal connected to the gate of the first PMOS becomes a high level, the first PMOS is cut off, and the counting signal R_EN output by the group counter circuit cannot be transmitted to the four row counter circuits. The second row counter circuit, the third row counter circuit and the fourth row counter circuit still remain inoperative. At this time, the first row counter circuit performs a reset operation. Afterwards, the external enable signal EN is at a high level, the group counter circuit performs a reset operation, and the defense row hammer circuit based on the RRAM double-layer counting completes this work.

[0024] When the external enable signal EN is at a high level, the signal connected to the gate of the first PMOS is at a low level, and the 2-bit binary address signal connected to the decoder circuit is 01, the first PMOS tube P1 is turned on, and the decoder circuit outputs a 4-bit binary decoding signal of 0010. At this time, the high level 1 in the 4-bit binary decoding signal is output to the second row counter circuit, and the 3 low levels 0 in the 4-bit binary decoding signal are output to the first row counter circuit, the second row counter circuit and the third row counter circuit one by one. The first row counter circuit, the third row counter circuit and the fourth row counter circuit are all not working, and the second row counter circuit enters a standby state. The group counter circuit counts the high level of the external enable signal EN, and generates a corresponding counting signal R_EN according to the count value and outputs it to the drain of the first PMOS tube P1. If the count value does not reach the upper limit of the group counter counting circuit, the counting signal R_EN output by the group counter circuit is a low level. At this time, the first row counter circuit remains in a standby state. When the count value reaches the counting upper limit of the group counter circuit, The counting signal R_EN output by the group counter circuit is at a high level, and the second row counter circuit starts to work. The second row counter circuit counts the high level output by the decoder circuit to it. When the count value of the second row counter circuit does not reach the counting upper limit of the second row counter circuit, the second row counter circuit outputs a low-level warning signal Alert. When the count value reaches the counting upper limit of the second row counter circuit, the second row counter circuit outputs a high-level warning signal Alert. When the second row counter circuit outputs a high-level warning signal Alert, the signal connected to the gate of the first PMOS becomes a high level, the first PMOS is cut off, and the counting signal R_EN output by the group counter circuit cannot be transmitted to the four row counter circuits. The second row counter circuit, the third row counter circuit and the fourth row counter circuit still remain inoperative, and the second row counter circuit performs a reset operation. Afterwards, the external enable signal EN is at a high level, the group counter circuit performs a reset operation, and the defense row hammer circuit based on the RRAM double-layer counting completes this work.

[0025] When the external enable signal EN is at a high level, the signal connected to the gate of the first PMOS is at a low level, and the 2-bit binary address signal connected to the decoder circuit is 10, the first PMOS tube P1 is turned on, and the decoder circuit outputs a 4-bit binary decoding signal of 0100. At this time, the high level 1 in the 4-bit binary decoding signal is output to the third row counter circuit, and the 3 low levels 0 in the 4-bit binary decoding signal are output to the first row counter circuit, the second row counter circuit and the fourth row counter circuit one by one. The first row counter circuit, the second row counter circuit and the fourth row counter circuit are all not working, and the third row counter circuit enters a standby state. The group counter circuit counts the high level of the external enable signal EN, and generates a corresponding counting signal R_EN according to the count value and outputs it to the drain of the first PMOS tube P1. If the count value does not reach the upper limit of the group counter counting circuit, the counting signal R_EN output by the group counter circuit is a low level. At this time, the third row counter circuit remains in a standby state. When the count value reaches the counting upper limit of the group counter circuit, the group counter circuit The counting signal R_EN output by the counter circuit is at a high level, and the third row counter circuit starts to work. The third row counter circuit counts the high level output by the decoder circuit to it. When the count value of the third row counter circuit does not reach the counting upper limit of the third row counter circuit, the third row counter circuit outputs a low level warning signal Alert. When the count value reaches the counting upper limit of the third row counter circuit, the third row counter circuit outputs a high level warning signal Alert. When the third row counter circuit outputs a high level warning signal Alert, the signal connected to the gate of the first PMOS becomes a high level, the first PMOS is cut off, and the counting signal R_EN output by the group counter circuit cannot be transmitted to the four row counter circuits. The first row counter circuit, the second row counter circuit and the fourth row counter circuit still remain inoperative, and the third row counter circuit performs a reset operation. Afterwards, the external enable signal EN is at a high level, the group counter circuit performs a reset operation, and the defense row hammer circuit based on the RRAM double-layer counting completes this work.

[0026] When the external enable signal EN is at a high level, the signal connected to the gate of the first PMOS is at a low level, and the 2-bit binary address signal connected to the decoder circuit is 11, the first PMOS tube P1 is turned on, and the decoder circuit outputs a 4-bit binary decoding signal of 1000. At this time, the high level 1 in the 4-bit binary decoding signal is output to the fourth row counter circuit, and the 3 low levels 0 in the 4-bit binary decoding signal are output to the first row counter circuit, the second row counter circuit and the third row counter circuit one by one. The first row counter circuit, the second row counter circuit and the third row counter circuit do not work, and the fourth row counter circuit enters a standby state. The group counter circuit counts the high level of the external enable signal EN, and generates a corresponding counting signal R_EN according to the count value and outputs it to the drain of the first PMOS tube P1. If the count value does not reach the upper limit of the group counter counting circuit, the count signal R_EN output by the group counter circuit is low. At this time, the fourth row counter circuit remains in a standby state. When the count value reaches the counting upper limit of the group counter circuit, the group counter The counting signal R_EN output by the decoder circuit is high level, the fourth row counter circuit starts to work, the fourth row counter circuit counts the high level of the signal output by the decoder circuit to it, when the count value of the fourth row counter circuit does not reach the counting upper limit of the fourth row counter circuit, the fourth row counter circuit outputs a low level warning signal Alert, when the count value reaches the counting upper limit of the fourth row counter circuit, the fourth row counter circuit outputs a high level warning signal Alert, when the fourth row counter circuit outputs a high level warning signal Alert, the signal connected to the gate of the first PMOS becomes high level, the first PMOS is cut off, the counting signal R_EN output by the group counter circuit cannot be transmitted to the four row counter circuits, the first row counter circuit, the second row counter circuit and the third row counter circuit still remain inoperative, the fourth row counter circuit performs a reset operation, after which the external enable signal EN is high level, the group counter circuit performs a reset operation, and the defense row hammer circuit based on RRAM double-layer counting completes this work.

[0027] Embodiment 2: This embodiment is basically the same as Embodiment 1, except that: in this embodiment, the decoder circuit has three input terminals and four output terminals, and its three input terminals are respectively referred to as its first input terminal, second input terminal and third input terminal, and its four output terminals are respectively referred to as its first output terminal, second output terminal, third output terminal and fourth output terminal; the group counter circuit has five input terminals and one output terminal, and its five input terminals are respectively referred to as its first input terminal, second input terminal, third input terminal, fourth input terminal and fifth input terminal; each row counter circuit has five input terminals and one output terminal, and its five input terminals are respectively referred to as its first input terminal, second input terminal, third input terminal, fourth input terminal and fifth input terminal; the first input terminal of the decoder circuit is used to access the first bit A of the 2-bit binary address signal, and the second input terminal of the decoder circuit is used to access the 2-bit binary The second bit B of the address signal; the first output end of the decoder circuit is used to output the first bit of the 4-bit binary decoded signal, the second output end of the decoder circuit is used to output the second bit of the 4-bit binary decoded signal, the third output end of the decoder circuit is used to output the third bit of the 4-bit binary decoded signal, the fourth output end of the decoder circuit is used to output the fourth bit of the 4-bit binary decoded signal, the third input end of the decoder circuit is connected to the first input end of the group counter circuit, and its connection end is the enable end of the defense hammer circuit, which is used to access the external enable signal EN; the second input end of the group counter circuit is connected to the power supply VDD; the third input end of the group counter circuit is the first refresh end of the defense hammer circuit, which is used to access the first refresh signal Ref1 that enables the group counter circuit to be restarted; the fourth input end of the group counter circuit is the first reference end of the defense hammer circuit, which is used to access the first reference voltage V rfe1; The fifth input end of the group counter circuit is the first control end of the defense row hammer circuit, which is used to access the first control signal SA1_CTL for controlling whether the output end of the group counter circuit outputs a signal; the first output end of the decoder circuit is connected to the first input end of the first row counter circuit, the second output end of the decoder circuit is connected to the first input end of the second row counter circuit, the third output end of the decoder circuit is connected to the first input end of the third row counter circuit, the fourth output end of the decoder circuit is connected to the first input end of the fourth row counter circuit, the second input end of the first row counter circuit, the second input end of the second row counter circuit, the second input end of the third row counter circuit and the second input end of the fourth row counter circuit are connected, and the connection end is the second control end of the defense row hammer circuit, which is used to access the second control signal SA1_CTL for controlling whether the output end of the group counter circuit outputs a signal 2_CTL; the third input terminal of the first row counter circuit, the third input terminal of the second row counter circuit, the third input terminal of the third row counter circuit, the third input terminal of the fourth row counter circuit are connected to the gate of the first PMOS tube P1, and the connection terminal thereof is the second refresh terminal of the defense row hammer circuit, which is used to access the second refresh signal Ref2 for re-enabling the row counter circuit; the source of the first PMOS tube P1 is respectively connected to the fourth input terminal of the first row counter circuit, the fourth input terminal of the second row counter circuit, the fourth input terminal of the third row counter circuit and the fourth input terminal of the fourth row counter circuit, the fifth input terminal of the first row counter circuit, the fifth input terminal of the second row counter circuit, the fifth input terminal of the third row counter circuit and the fifth input terminal of the fourth row counter circuit, and the connection terminal thereof is the second reference terminal of the defense row hammer circuit, which is accessed to the second reference voltage V rfe2 .

[0028] The working principle of the RRAM double-layer counting-based defense hammer circuit of this embodiment is as follows:

[0029] In the initial state, the count values ​​of the group counter circuit and the row counter circuit are both 0. When the external enable signal EN connected to the enable end of the defense row hammer circuit based on RRAM double-layer counting is low, the decoder circuit, the group counter circuit and the four row counter circuits do not work; when the external enable signal EN connected to the enable end of the defense row hammer circuit based on RRAM double-layer counting, the first control signal SA1_CTL connected to the first control end and the second control signal SA2_CTL connected to the second control end are all high, the first refresh signal Ref1 connected to the first refresh end and the second refresh signal Ref2 connected to the second refresh end are both low. When the first PMOS tube P1 is turned on, the group counter circuit is turned on, the high level of the external enable signal EN is counted, and the corresponding count signal R_EN is generated according to the count value and output to the drain of the first PMOS tube P1. If the count value does not reach the upper limit of the group counter counting circuit, the count signal R_EN output by the group counter circuit is low level. If the count value reaches the upper limit of the group counter circuit, the count signal R_EN output by the group counter circuit is high level. Although the group counter circuit outputs the count signal R_EN to the four row counter circuits, no matter what signal the decoder circuit outputs, the four row counter circuits do not work. When the count value reaches the upper limit of the group counter circuit, the count signal R_EN output by the group counter circuit is high level, the external enable signal EN, the first control signal SA1_CTL and the second control signal SA2_CTL remain high level, and the first refresh signal Ref1 and the second refresh signal Ref2 remain low level.At this time, if the 2-bit binary address signal connected to the decoder circuit is 00, the decoder circuit outputs a 4-bit binary decoding signal of 0001, the signal output by the decoder circuit to the first row counter circuit is a high level, and the signals output to the second row counter circuit, the third row counter circuit and the fourth row counter circuit are all low levels, the second row counter circuit, the third row counter circuit and the fourth row counter circuit are all not working, and the first row counter circuit starts working; if the 2-bit binary address signal connected to the decoder circuit is 01, the decoder circuit outputs a 4-bit binary decoding signal of 0010, the signal output by the decoder circuit to the second row counter circuit is a high level, and the signals output to the first row counter circuit, the third row counter circuit and the fourth row counter circuit are all low levels, the first row counter circuit, the third row counter circuit and the fourth row counter circuit are all not working, and the second row counter circuit starts working operation; if the 2-bit binary address signal connected to the decoder circuit is 10, the decoder circuit outputs a 4-bit binary decoding signal of 0100, the signal output by the decoder circuit to the third row counter circuit is high level, the signals output to the first row counter circuit, the second row counter circuit and the fourth row counter circuit are all low level, the first row counter circuit, the second row counter circuit and the fourth row counter circuit are all not working, and the third row counter circuit starts to work; if the 2-bit binary address signal connected to the decoder circuit is 11, the decoder circuit outputs a 4-bit binary decoding signal of 1000, the signal output by the decoder circuit to the fourth row counter circuit is high level, the signals output to the first row counter circuit, the second row counter circuit and the third row counter circuit are all low level, the first row counter circuit, the second row counter circuit and the third row counter circuit are all not working, and the fourth row counter circuit starts to work. When a row counter circuit starts to work, the row counter circuit counts the high level outputted by the decoder circuit. When the count value of the row counter circuit does not reach its upper count limit, the output end of the row counter circuit outputs a low-level warning signal Alert. When the count value reaches its upper count limit, the output end of the row counter circuit outputs a high-level warning signal Alert. When the output end of the row counter circuit outputs a high-level warning signal Alert, the second refresh signal Ref2 becomes high to turn off the first PMOS. At this time, the count signal R_EN outputted by the group counter circuit cannot be transmitted to the four row counter circuits. Except for the row counter circuit, the other three row counter circuits remain inoperative. The row counter circuit performs a reset operation. Afterwards, the first refresh signal Ref1 becomes high, the group counter circuit performs a reset operation, and the defense row hammer circuit based on the RRAM double-layer counting completes this work.

[0030] Embodiment 3: This embodiment is basically the same as Embodiment 2, except that: in this embodiment, Figure 2As shown, the group counter circuit includes a first NMOS tube N1, a second NMOS tube N2, a third NMOS tube N3, a fourth NMOS tube N4, a fifth NMOS tube N5, a second PMOS tube P2, a first sensitive amplifier SA1, a first memristor R1 and a second memristor R2. The first sensitive amplifier SA1 has a non-inverting input terminal, an inverting input terminal, an output terminal and an enable terminal. The first memristor R1 and the second memristor R2 both have a top electrode and a bottom electrode. The initial resistance state of the first memristor R1 is a high resistance state, and the initial resistance state of the second memristor R2 is a low resistance state. The drain of the first NMOS tube N1 is connected to the drain of the fourth NMOS tube N4, and the connection end thereof is the second input terminal of the group counter circuit. The gate of the first NMOS tube N1, the gate of the fifth NMOS tube N5 and the enable terminal of the first sensitive amplifier SA1 are connected, and the connection end thereof is the first input terminal of the group counter circuit. The source of the first NMOS tube N1 is connected to the top electrode of the first memristor R1. , the bottom electrode of the first memristor R1, the source of the second PMOS tube P2 and the non-inverting input terminal of the first sensitive amplifier SA1 are connected, the inverting input terminal of the first sensitive amplifier SA1 is the fourth input terminal of the group counter circuit, the drain of the second PMOS tube P2, the top electrode of the second memristor R2 and the drain of the third NMOS tube N3 are connected, the gate of the third NMOS tube N3, the gate of the second PMOS tube P2 and the gate of the fourth NMOS tube N4 are connected, and their connection end is the third input terminal of the group counter circuit, the source of the third NMOS tube N3 and the source of the fifth NMOS tube N5 are both grounded, the bottom electrode of the second memristor R2, the source of the fourth NMOS tube N4 and the drain of the fifth NMOS tube N5 are connected, the output terminal of the first sensitive amplifier SA1 is connected to the drain of the second NMOS tube N2, the gate of the second NMOS tube N2 is the fifth input terminal of the group counter circuit, and the source of the second NMOS tube N2 is the output terminal of the group counter circuit.

[0031] The working principle of the group counter circuit of this embodiment is as follows: when the external enable signal EN and the first control signal SA1_CTL are both at high levels and the first refresh signal Ref1 is at a low level, the group counter circuit starts counting operation, the first NMOS tube N1, the second NMOS tube N2, the second PMOS tube P2 and the fifth NMOS tube N5 are all turned on, the third NMOS tube N3 and the fourth NMOS tube N4 are all turned off, at this time, the top electrode voltage of the second memristor R2 is higher than the bottom electrode voltage thereof, and the resistance value of the second memristor R2 gradually increases, and when the number of counts of the group counter circuit reaches its upper limit, the resistance state of the second memristor R2 is converted from a low resistance state to a high resistance state, and the voltage of the bottom electrode of the first memristor R1 rises to a value higher than the first reference voltage V rfe1At this time, the signal outputted from the output end of the first sensitive amplifier SA1 is at a high level, and the signal outputted from the output end of the first sensitive amplifier SA1 is transmitted to the source of the second NMOS tube N2 through the drain of the first sensitive amplifier SA1, that is, the R_EN signal outputted from the output end of the group counter circuit is at a high level. Afterwards, when the first refresh signal Ref1 becomes high level, the group counter circuit starts the reset operation, the first NMOS tube N1, the second NMOS tube N2, the fifth NMOS tube N5 and the second PMOS tube P2 are all turned off, the third NMOS tube N3 and the fourth NMOS tube N4 are all turned on, the top electrode voltage of the second memristor R2 is lower than the bottom electrode voltage thereof, and the second memristor R2 is converted from a high resistance state to a low resistance state, completing the reset operation.

[0032] Embodiment 4: This embodiment is basically the same as Embodiment 3, except that: in this embodiment, Figure 3 As shown, each row counter circuit includes a sixth NMOS tube N6, a seventh NMOS tube N7, an eighth NMOS tube N8, a ninth NMOS tube N9, a third PMOS tube P3, a fourth PMOS tube P4, a second sensitive amplifier SA2, a third memristor R3 and a fourth memristor R4. The second sensitive amplifier SA2 has a non-inverting input terminal, an inverting input terminal, an output terminal and an enable terminal. The third memristor R3 and the fourth memristor R4 both have a top electrode and a bottom electrode. The initial resistance state of the third memristor R3 is a high resistance state, and the initial resistance state of the fourth memristor R4 is a low resistance state. The top electrode of the third memristor R3, the gate of the eighth NMOS tube N8 and the enable terminal of the second sensitive amplifier SA2 are connected, and the connection terminal thereof is the first input terminal of the row counter circuit. The source of the sixth NMOS tube N6 is connected to the bottom electrode of the third memristor R3. The drain of the sixth NMOS tube N6, the source of the third PMOS tube P3 and the non-inverting input terminal of the second sensitive amplifier SA2 are connected. , the inverting input terminal of the second sensitive amplifier SA2 is the fifth input terminal of the row counter circuit, the drain of the third PMOS tube P3, the top electrode of the fourth memristor R4 and the drain of the eighth NMOS tube N8 are connected, the gate of the ninth NMOS tube N9, the gate of the third PMOS tube P3 and the gate of the fourth PMOS tube P4 are connected, and their connection end is the third input terminal of the row counter circuit, the source of the eighth NMOS tube N8 and the drain of the fourth PMOS tube P4 are both grounded, the bottom electrode of the fourth memristor R4, the source of the fourth PMOS tube P4 and the source of the ninth NMOS tube N9 are connected, the drain of the ninth NMOS tube N9 is connected to the power supply voltage, the output terminal of the second sensitive amplifier SA2 is connected to the drain of the seventh NMOS tube N7, the gate of the seventh NMOS tube N7 is the second input terminal of the row counter circuit, the source of the seventh NMOS tube N7 is the output terminal of the row counter circuit, and the gate of the sixth NMOS tube N6 is the fourth input terminal of the row counter circuit.

[0033] The working principle of the row counter circuit of this embodiment is as follows: when the signal connected to the first input terminal of the row counter circuit, the second control signal SA2_CTL connected to the second input terminal, and the counting signal RC_EN connected to the fourth input terminal are all high level, and the second refresh signal Ref2 connected to the third input terminal is low level, the row counter circuit starts counting operation, the sixth NMOS tube N6, the seventh NMOS tube N7, the third PMOS tube P3 and the fourth PMOS tube P4 are all turned on, the eighth NMOS tube N8 and the ninth NMOS tube N9 are all turned off, the top electrode voltage of the fourth memristor R4 is higher than the bottom electrode voltage thereof, and the resistance value of the fourth memristor R4 gradually increases. When the number of counts of the row counter circuit reaches its upper limit, the resistance state of the fourth memristor R4 is converted from a low resistance state to a high resistance state. At this time, the voltage at the non-inverting input terminal of the second sensitive amplifier SA2 will rise to a value higher than the second reference voltage V rfe2 , the signal outputted from the output end of the second sensitive amplifier SA2 is at a high level, and the signal outputted from the output end of the second sensitive amplifier SA2 is transmitted to the source of the seventh NMOS tube N7 through the drain of the second sensitive amplifier SA2, that is, the Alert signal outputted from the output end of the row counter circuit becomes at a high level. When the row counter circuit outputs a high-level warning signal Alert, the second refresh signal Ref2 becomes at a high level, the row counter circuit starts a reset operation, the sixth NMOS tube N6, the seventh NMOS tube N7, the third PMOS tube P3, and the fourth PMOS tube P4 are all turned off, the eighth NMOS tube N8 and the ninth NMOS tube N9 are all turned on, the top electrode voltage of the fourth memristor R4 is lower than the bottom electrode voltage thereof, and the fourth memristor R4 is converted from a high-resistance state to a low-resistance state, completing the reset operation.

[0034] Embodiment 5: This embodiment is basically the same as Embodiment 4, except that: in this embodiment, Figure 4As shown, the first sensitive amplifier SA1 includes a fifth PMOS tube P5, a sixth PMOS tube P6, a seventh PMOS tube P7, an eighth PMOS tube P8, a tenth NMOS tube N10, an eleventh NMOS tube N11, a twelfth NMOS tube N12, a thirteenth NMOS tube N13 and a fourteenth NMOS tube N14, the source of the fifth PMOS tube P5, the source of the sixth PMOS tube P6, the source of the seventh PMOS tube P7 and the source of the eighth PMOS tube P8 are all connected to the power supply voltage, the gate of the fifth PMOS tube P5, the gate of the eighth PMOS tube P8 and the gate of the fourteenth NMOS tube N14 are connected, and the connection end thereof is the enable end of the first sensitive amplifier SA1, the drain of the fifth PMOS tube P5, the drain of the sixth PMOS tube P6, the drain of the tenth NMOS tube N10, the gate of the seventh PMOS tube P7 and the gate of the eleventh NMOS tube N11 are connected , and its connection end is the output end of the first sensitive amplifier SA1, the drain of the seventh PMOS tube P7, the drain of the eighth PMOS tube P8, the drain of the eleventh NMOS tube N11, the gate of the sixth PMOS tube P6 and the gate of the tenth NMOS tube N10 are connected, the source of the tenth NMOS tube N10 is connected to the drain of the twelfth NMOS tube N12, the gate of the twelfth NMOS tube N12 is the inverting input end of the first sensitive amplifier SA1, the source of the eleventh NMOS tube N11 is connected to the drain of the thirteenth NMOS tube N13, the gate of the thirteenth NMOS tube N13 is the non-inverting input end of the first sensitive amplifier SA1, the source of the twelfth NMOS tube N12, the source of the thirteenth NMOS tube N13 and the drain of the fourteenth NMOS tube are connected, and the source of the fourteenth NMOS tube N14 is grounded; the circuit structure of the second sensitive amplifier SA2 is the same as that of the first sensitive amplifier SA1.

[0035] The working principle of the first sense amplifier SA1 of the present embodiment is as follows: when the external enable signal EN is at a low level, the first sense amplifier SA1 starts a reset operation, the fifth PMOS tube P5 and the eighth PMOS tube P8 are both turned on, the drain of the fifth PMOS tube P5, the drain of the sixth PMOS tube P6, the drain of the seventh PMOS tube P7 and the drain of the eighth PMOS tube P8 are charged to the power supply voltage VDD, the sixth PMOS tube P6 and the seventh PMOS tube P7 are both turned off, the tenth NMOS tube N10 and the eleventh NMOS tube N11 are both turned on, and the reset operation is completed. When the external enable signal EN is at a high level, the first sensitive amplifier SA1 starts to work, the fifth PMOS tube P5 and the eighth PMOS tube P8 are both turned off, and the fourteenth NMOS tube N14 is turned on. When the gate voltage of the twelfth NMOS tube N12 is higher than the gate voltage of the thirteenth NMOS tube N13, at this time, the conduction degree of the twelfth NMOS tube N12 is higher than the conduction degree of the thirteenth NMOS tube N13, resulting in the discharge speed of the drain of the fifth PMOS tube P5 and the sixth PMOS tube P6 being faster than the drain discharge speed of the seventh PMOS tube P7 and the eighth PMOS tube P8, and the drain voltage of the fifth PMOS tube P5 and the sixth PMOS tube P6 will be lower than the gate voltage of the seventh PMOS tube P7 and the eighth PMOS tube P8. 8, so that the conduction degree of the seventh PMOS tube P7 is higher than that of the sixth PMOS tube P6, the conduction degree of the tenth NMOS tube N10 is higher than that of the eleventh NMOS tube N11, the discharge speed of the drains of the fifth PMOS tube P5 and the sixth PMOS tube P6 is further accelerated through the twelfth NMOS tube N12 and the fourteenth NMOS tube N14, and the power supply voltage VDD is charged to the drains of the seventh PMOS tube P7 and the eighth PMOS tube P8 through the seventh PMOS tube P7, until the drain voltages of the fifth PMOS tube P5 and the sixth PMOS tube P6 drop to the ground GND, and the source voltages of the seventh PMOS tube P7 and the eighth PMOS tube P8 rise to be equal to the power supply voltage VDD.

[0036] In order to verify the performance of the RRAM double-layer counting defense row hammer circuit of the present invention, Spectre is used to perform functional simulation on the RRAM double-layer counting defense row hammer circuit of the present invention under TSMC 28nm process voltage 1V, wherein the count upper limit set by the group counter circuit is 800, and the count upper limit set by each row counter is 200, so as to perform defense when the row hammer attack threshold is 1000 times. The counting and reset function tests of the group counter circuit are as follows: Figure 5 As shown, the counting and reset function test of the row counter circuit is as follows Figure 6 Analysis Figure 5It can be seen that the group counter circuit in the RRAM double-layer counting defense hammer circuit of the present invention can realize 800 counting operations for the high level of the external enable signal EN, and when the number of counts reaches 800 times, the counting signal R_EN output by the group counter circuit is high, and then the group counter circuit is refreshed and the count value is reset. Figure 6 It can be seen that the row counter circuit in the RRAM double-layer counting-based defense row hammer circuit of the present invention can realize 200 counting operations for the high level of the first input terminal, and when the number of counts reaches 200 times, the warning signal Alert output by the row counter circuit is high level, and then the row counter circuit is refreshed and the count value is reset.

Claims

1. A hammer protection circuit based on RRAM double-layer counting, characterized in that The invention comprises a decoder circuit, a group counter circuit, four row counter circuits and a first PMOS tube, wherein the four row counter circuits are respectively referred to as a first row counter circuit, a second row counter circuit, a third row counter circuit and a fourth row counter circuit; the group counter circuit and the four row counter circuits are respectively implemented based on RRAM devices; the decoder circuit is used for converting a 2-bit binary address signal outputted externally thereto into a 4-bit binary decoding signal under the control of an external enable signal EN and outputting the 2-bit binary address signal to the four row counter circuits one by one; the first PMOS tube is used for turning on or off under the control of a signal connected to its gate; when the signal connected to the gate of the first PMOS tube is at a low level, the first PMOS tube is turned on; the group counter circuit is connected to the four row counter circuits through the first PMOS tube; the group counter circuit can output a signal to the four row counter circuits; when the signal connected to the gate of the first PMOS tube is at a high level, the first PMOS tube is turned off; the group counter circuit and the four row counter circuits are all disconnected; the group counter circuit is turned on or off; The counter circuit cannot output signals to the four row counter circuits, and the group counter circuit cannot affect the working states of the four row counter circuits. The group counter circuit is used to count the high level of the external enable signal EN, and generate a corresponding counting signal R_EN according to the count value and output it to the drain of the first PMOS tube. If the count value does not reach the upper limit of the group counter counting circuit, the counting signal R_EN output by the group counter circuit is a low level. If the count value reaches the upper limit of the count of the group counter circuit, the counting signal R_EN output by the group counter circuit is a high level. The row counter circuit is used to count the high level output by the decoder circuit when the signal output by the decoder circuit is a high level, the counting signal R_EN output by the group counter circuit is a high level, and the signal connected to the gate of the first PMOS is a low level, and output a low-level warning signal Alert when the count value does not reach its upper limit, and output a high-level warning signal Alert when the count value reaches its upper limit.

2. The RRAM double-layer counting based anti-hammer circuit according to claim 1, characterized in that The decoder circuit has three input terminals and four output terminals, and its three input terminals are respectively referred to as its first input terminal, second input terminal and third input terminal, and its four output terminals are respectively referred to as its first output terminal, second output terminal, third output terminal and fourth output terminal; the group counter circuit has five input terminals and one output terminal, and its five input terminals are respectively referred to as its first input terminal, second input terminal, third input terminal, fourth input terminal and fifth input terminal; each of the row counter circuits has five input terminals and one output terminal, and its five input terminals are respectively referred to as its first input terminal, second input terminal, third input terminal, fourth input terminal and fifth input terminal; the first input terminal of the decoder circuit is used to access the first bit A of the 2-bit binary address signal, and the second input terminal of the decoder circuit is used to access the second bit B of the 2-bit binary address signal; the first output terminal of the decoder circuit is used to output The first bit of the 4-bit binary decoded signal is outputted from the decoder circuit; the second output terminal of the decoder circuit is used to output the second bit of the 4-bit binary decoded signal; the third output terminal of the decoder circuit is used to output the third bit of the 4-bit binary decoded signal; the fourth output terminal of the decoder circuit is used to output the fourth bit of the 4-bit binary decoded signal; the third input terminal of the decoder circuit is connected to the first input terminal of the group counter circuit, and its connection terminal is the enable terminal of the defense hammer circuit, which is used to access the external enable signal EN; the second input terminal of the group counter circuit is connected to the power supply VDD; the third input terminal of the group counter circuit is the first refresh terminal of the defense hammer circuit, which is used to access the first refresh signal Ref1 that enables the group counter circuit to be reopened; the fourth input terminal of the group counter circuit is the first reference terminal of the defense hammer circuit, which is used to access the first reference voltage V rfe1 ; The fifth input end of the group counter circuit is the first control end of the defense hammer circuit, which is used to access the first control signal SA1_CTL for controlling whether the output end of the group counter circuit outputs a signal; the first output end of the decoder circuit is connected to the first input end of the first row counter circuit, the second output end of the decoder circuit is connected to the first input end of the second row counter circuit, the third output end of the decoder circuit is connected to the first input end of the third row counter circuit, the fourth output end of the decoder circuit is connected to the first input end of the fourth row counter circuit, the second input end of the first row counter circuit, the second input end of the second row counter circuit, the second input end of the third row counter circuit and the second input end of the fourth row counter circuit are connected, and the connection end is the second control end of the defense hammer circuit, which is used to access the second control signal SA1_CTL for controlling whether the output end of the group counter circuit outputs a signal. SA2_CTL; the third input terminal of the first row counter circuit, the third input terminal of the second row counter circuit, the third input terminal of the third row counter circuit, the third input terminal of the fourth row counter circuit and the gate of the first PMOS tube are connected, and the connection terminal is the second refresh terminal of the defense row hammer circuit, which is used to access the second refresh signal Ref2 that reopens the row counter circuit; the source of the first PMOS tube is respectively connected to the fourth input terminal of the first row counter circuit, the fourth input terminal of the second row counter circuit, the fourth input terminal of the third row counter circuit and the fourth input terminal of the fourth row counter circuit, the fifth input terminal of the first row counter circuit, the fifth input terminal of the second row counter circuit, the fifth input terminal of the third row counter circuit and the fifth input terminal of the fourth row counter circuit are connected, and the connection terminal is the second reference terminal of the defense row hammer circuit, which is connected to the second reference voltage V rfe2 .

3. The RRAM double-layer counting based anti-hammer circuit according to claim 2, characterized in that The group counter circuit includes a first NMOS tube, a second NMOS tube, a third NMOS tube, a fourth NMOS tube, a fifth NMOS tube, a second PMOS tube, a first sensitive amplifier, a first memristor and a second memristor. The first sensitive amplifier has a non-inverting input terminal, an inverting input terminal, an output terminal and an enable terminal. The first memristor and the second memristor both have a top electrode and a bottom electrode. The initial resistance state of the first memristor is a high resistance state, and the initial resistance state of the second memristor is a low resistance state. The drain of the first NMOS tube is connected to the drain of the fourth NMOS tube, and the connection end thereof is the second input terminal of the group counter circuit. The gate of the first NMOS tube and the gate of the fifth NMOS tube are connected to the enable terminal of the first sensitive amplifier, and the connection end thereof is the first input terminal of the group counter circuit. The source of the first NMOS tube is connected to the top electrode of the first memristor. The bottom electrode, the gate of the fifth NMOS tube and the enable terminal of the first sensitive amplifier are connected. The source of the second PMOS tube is connected to the in-phase input terminal of the first sensitive amplifier, the inverting input terminal of the first sensitive amplifier is the fourth input terminal of the group counter circuit, the drain of the second PMOS tube, the top electrode of the second memristor and the drain of the third NMOS tube are connected, the gate of the third NMOS tube, the gate of the second PMOS tube and the gate of the fourth NMOS tube are connected, and their connection end is the third input terminal of the group counter circuit, the source of the third NMOS tube and the source of the fifth NMOS tube are both grounded, the bottom electrode of the second memristor, the source of the fourth NMOS tube and the drain of the fifth NMOS tube are connected, the output terminal of the first sensitive amplifier is connected to the drain of the second NMOS tube, the gate of the second NMOS tube is the fifth input terminal of the group counter circuit, and the source of the second NMOS tube is the output terminal of the group counter circuit.

4. The RRAM double-layer counting based anti-hammer circuit according to claim 3, characterized in that Each of the row counter circuits includes a sixth NMOS tube, a seventh NMOS tube, an eighth NMOS tube, a ninth NMOS tube, a third PMOS tube, a fourth PMOS tube, a second sensitive amplifier, a third memristor and a fourth memristor. The second sensitive amplifier has a non-inverting input terminal, an inverting input terminal, an output terminal and an enable terminal. The third memristor and the fourth memristor both have a top electrode and a bottom electrode. The initial resistance state of the third memristor is a high resistance state, and the initial resistance state of the fourth memristor is a low resistance state. The top electrode of the third memristor, the gate of the eighth NMOS tube and the enable terminal of the second sensitive amplifier are connected, and the connection terminal is the first input terminal of the row counter circuit. The source of the sixth NMOS tube is connected to the bottom electrode of the third memristor. The drain of the sixth NMOS tube and the source of the third PMOS tube are connected to the non-inverting input terminal of the second sensitive amplifier. The inverting input terminal of the second sensitive amplifier is the The fifth input terminal of the row counter circuit, the drain of the third PMOS tube, the top electrode of the fourth memristor and the drain of the eighth NMOS tube are connected, the gate of the ninth NMOS tube, the gate of the third PMOS tube and the gate of the fourth PMOS tube are connected, and their connection end is the third input terminal of the row counter circuit, the source of the eighth NMOS tube and the drain of the fourth PMOS tube are both grounded, the bottom electrode of the fourth memristor, the source of the fourth PMOS tube and the source of the ninth NMOS tube are connected, the drain of the ninth NMOS tube is connected to the power supply voltage, the output terminal of the second sensitive amplifier is connected to the drain of the seventh NMOS tube, the gate of the seventh NMOS tube is the second input terminal of the row counter circuit, the source of the seventh NMOS tube is the output terminal of the row counter circuit, and the gate of the sixth NMOS tube is the fourth input terminal of the row counter circuit.

5. The RRAM double-layer counting based anti-hammer circuit according to claim 4, characterized in that The first sensitive amplifier includes a fifth PMOS tube, a sixth PMOS tube, a seventh PMOS tube, an eighth PMOS tube, a tenth NMOS tube, an eleventh NMOS tube, a twelfth NMOS tube, a thirteenth NMOS tube and a fourteenth NMOS tube, the source of the fifth PMOS tube, the source of the sixth PMOS tube, the source of the seventh PMOS tube and the source of the eighth PMOS tube are all connected to the power supply voltage, the gate of the fifth PMOS tube, the gate of the eighth PMOS tube and the gate of the fourteenth NMOS tube are connected, and the connection end thereof is the enable end of the first sensitive amplifier, the drain of the fifth PMOS tube, the drain of the sixth PMOS tube, the drain of the tenth NMOS tube, the gate of the seventh PMOS tube and the gate of the eleventh NMOS tube are connected, and the connection end thereof is the enable end of the first sensitive amplifier, The output end of the sensitive amplifier, the drain of the seventh PMOS tube, the drain of the eighth PMOS tube, the drain of the eleventh NMOS tube, the gate of the sixth PMOS tube and the gate of the tenth NMOS tube are connected, the source of the tenth NMOS tube is connected to the drain of the twelfth NMOS tube, the gate of the twelfth NMOS tube is the inverting input end of the first sensitive amplifier, the source of the eleventh NMOS tube is connected to the drain of the thirteenth NMOS tube, the gate of the thirteenth NMOS tube is the non-inverting input end of the first sensitive amplifier, the source of the twelfth NMOS tube, the source of the thirteenth NMOS tube and the drain of the fourteenth NMOS tube are connected, and the source of the fourteenth NMOS tube is grounded; the circuit structure of the second sensitive amplifier is the same as that of the first sensitive amplifier.

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