Storage Module, Storage Array, Storage Device, and In-Memory Computing Programming Method

Abstract

The present disclosure relates to a storage module, a storage array, a storage device and an in-memory computing programming method. The storage module includes a storage cell and an in-memory computing unit. The storage cell is used to connect word lines, bit lines and source lines, and is configured to: in storage mode, perform data programming, data reading or data deletion based on word lines, bit lines and source lines. The in-memory computing unit is connected to the storage cell and is used to connect timing word lines, computing word lines and computing source lines, and is configured to: in the first stage of the in-memory computing mode, obtain the storage data of the storage cell based on the bit lines and timing word lines; and in the second stage of the in-memory computing mode, perform in-memory computing based on computing word lines and computing source lines. The present disclosure not only has the advantages of non-volatility, high switching ratio, extremely low turn-on current, elimination of DC paths during the computing process and compensation for discharge transistor mismatch, but also can effectively improve the parallelism, linearity and energy efficiency of in-memory computing.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor storage and computing, and in particular to a storage module, a storage array, a storage device, and an in-memory computing programming method. Background Art

[0002] Compute-in-Memory (CIM) is a new technology that breaks through traditional computing architectures. Its core concept is to process data directly within the storage module, rather than the traditional computing model of moving data from storage (RAM) to the processor (CPU / GPU) for computation. By eliminating the "storage wall" (the latency and energy consumption associated with data movement), this technology can significantly improve computing efficiency and energy efficiency. It is particularly suitable for scenarios that require processing massive amounts of data, such as artificial intelligence and big data analytics. Summary of the Invention

[0003] Based on this, the embodiments of the present disclosure provide a storage module, a storage array, a storage device, and an in-memory computing programming method, which not only have the advantages of non-volatility, high switching ratio, extremely low turn-on current, elimination of DC paths during the calculation process, and compensation for discharge transistor mismatch, but also can effectively improve the parallelism, linearity, and energy efficiency of in-memory computing.

[0004] In order to achieve the above-mentioned objectives, in a first aspect, some embodiments of the present disclosure provide a storage module, comprising a storage unit and an in-memory computing unit. The storage unit is used to connect word lines, bit lines and source lines, and is configured to: in a storage mode, perform data programming, data reading or data deletion based on the word lines, the bit lines and the source lines. The in-memory computing unit is connected to the storage unit and is used to connect the timing word lines, the computing word lines and the computing source lines, and is configured to: in a first stage of the in-memory computing mode, obtain the storage data of the storage unit based on the bit lines and the timing word lines; and, in a second stage of the in-memory computing mode, perform in-memory computing based on the computing word lines and the computing source lines.

[0005] In some embodiments of the present disclosure, the memory cell includes: a first transistor and a resistive random access memory, wherein the gate of the first transistor is connected to the word line, the first electrode of the first transistor is connected to the source line, the second electrode of the first transistor is connected to the first terminal of the resistive random access memory, and the second terminal of the resistive random access memory is connected to the bit line.

[0006] In some embodiments of the present disclosure, the in-memory computing unit includes: a second transistor, a third transistor, a capacitor, and a fourth transistor. The gate of the second transistor is connected to the timing word line; the first electrode of the second transistor is connected to the storage unit; the second electrode of the second transistor, the gate of the third transistor, and the first electrode of the capacitor are connected as a recovery node; the first electrode of the third transistor and the second electrode of the capacitor are connected and connected to a ground voltage terminal; the second electrode of the third transistor is connected to the first electrode of the fourth transistor; the gate of the fourth transistor is connected to the computing word line, and the second electrode of the fourth transistor is connected to the computing source line.

[0007] In a second aspect, some embodiments of the present disclosure further provide a storage array comprising a plurality of storage units arranged in an array. The storage units comprise a plurality of storage modules as described in any of the above embodiments and are arranged in rows along a first direction. The recovery nodes of the storage modules in each storage unit are connected to each other and to a shared capacitor, wherein the shared capacitor is configured to, in an in-memory computing mode, obtain storage data corresponding to a target storage module in the storage unit in response to an in-memory computing control instruction.

[0008] In some embodiments of the present disclosure, the storage units are arranged in a row along a second direction, and the second direction intersects with the first direction; wherein, at least one column of the storage units is a virtual column storage unit; and each of the storage modules in the virtual column storage unit stores calibration pre-stored data.

[0009] In a third aspect, some embodiments of the present disclosure further provide a storage device, comprising: a storage array as described in any of the preceding embodiments, a read / write control circuit, and an in-memory calculation control circuit. The read / write control circuit is connected to each of the storage units in the storage array via a bit line driver circuit, a word line driver circuit, and a source line driver circuit, and is configured to: in a storage mode, send storage control instructions to the bit line driver circuit, the word line driver circuit, and the source line driver circuit, respectively, to select a target storage module for data programming, data reading, or data deletion. The in-memory calculation control circuit is connected to each of the storage units in the storage array via a timing word line driver circuit, a calculation word line pulse generation and drive circuit, and a calculation source line processing circuit, and is configured to: in a first phase of the in-memory calculation mode, send a first in-memory calculation control instruction to the timing word line driver circuit to retrieve storage data from multiple target storage modules; and in a second phase of the in-memory calculation mode, send a second in-memory calculation control instruction to the calculation word line pulse generation and drive circuit and the calculation source line processing circuit to perform in-memory calculations on the storage data of the multiple target storage modules.

[0010] In some embodiments of the present disclosure, the memory device further includes a delay circuit connected to the bit line driving circuit and the timing word line driving circuit, and configured to control the charging time of the shared capacitor in the in-memory calculation mode.

[0011] In some embodiments of the present disclosure, the storage device further includes a calculation post-processing circuit connected to the calculation source line processing circuit and configured to: in the in-memory calculation mode, post-process the operation structure of the in-memory calculation and output the post-processing result.

[0012] In a fourth aspect, some embodiments of the present disclosure further provide an in-memory computing programming method, which is applied to the storage device described in any of the above embodiments. The programming method includes:

[0013] Selecting a plurality of target memory modules in a first target row from the memory array as a group to be programmed;

[0014] In a storage mode, performing a first data programming on each of the target memory modules in the to-be-programmed group through the bit line driving circuit, the word line driving circuit, and the source line driving circuit;

[0015] In the first stage of the in-memory calculation mode, the stored data of each target memory module in the to-be-programmed group is restored to the corresponding shared capacitor through the bit line driving circuit and the timing word line driving circuit;

[0016] In the second stage of the in-memory computing mode, the computing word line pulse generation and driving circuit and the computing source line processing circuit are used to control the discharge of the shared capacitor and detect whether the discharge current of the shared capacitor meets a preset condition;

[0017] wherein, in response to the discharge current of the shared capacitor meeting the preset condition, a plurality of target memory modules in a second target row are selected from the memory array as a group to be programmed;

[0018] In response to the discharge current of the shared capacitor not meeting the preset condition, data programming is performed a second time on each of the target storage modules in the group to be programmed in the storage mode, and in the in-memory calculation mode, the storage data of each of the target storage modules in the group to be programmed is restored to the corresponding shared capacitor to detect again whether the discharge current of the shared capacitor meets the preset condition.

[0019] In some embodiments of the present disclosure, a programming accuracy of the second data programming is higher than a programming accuracy of the first data programming.

[0020] The embodiments of the present disclosure may or may have at least the following advantages:

[0021] In an embodiment of the present disclosure, a storage module includes a storage cell and an in-memory computing unit, and the storage cell is configured to connect a word line, a bit line, and a source line so as to perform data programming, data reading, or data deletion based on the word line, the bit line, and the source line in a storage mode. The in-memory computing unit is configured to connect the storage cell, the timing word line, the computing word line, and the computing source line so as to obtain the storage data of the storage cell based on the bit line and the timing word line in a first stage of the in-memory computing mode, and to perform in-memory computing based on the computing word line and the computing source line in a second stage of the in-memory computing mode. The embodiment of the present disclosure easily decouples the working path of the storage module in the storage mode and the in-memory computing mode, thereby facilitating the effective improvement of the parallelism, linearity, and energy efficiency of the in-memory computing while ensuring that the storage module has the advantages of non-volatility, high switching ratio, extremely low turn-on current, elimination of DC paths during the computing process, and compensation for discharge transistor mismatch.

[0022] The details of one or more embodiments of the present disclosure are set forth in the accompanying drawings and the description below. Other features, objects, and advantages of the present disclosure will become apparent from the description, drawings, and claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] In order to more clearly illustrate the embodiments of the present disclosure or the technical solutions in the traditional technology, the following briefly introduces the drawings required for use in the embodiments or the description of the traditional technology. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0024] Figure 1 Schematic diagram of some in-memory computing circuits provided in some embodiments;

[0025] Figure 2 is a structural block diagram of a storage module provided in some embodiments;

[0026] Figure 3 is a schematic diagram of an equivalent circuit of a storage module provided in some embodiments;

[0027] Figure 4 A schematic diagram of the working principle of a storage module in a storage mode provided in some embodiments;

[0028] Figure 5 A schematic diagram of the working principle of a storage module in the first stage of in-memory computing mode provided in some embodiments;

[0029] Figure 6 A waveform diagram of voltage changes of a storage module in the first stage of an in-memory computing mode provided in some embodiments;

[0030] Figure 7 A schematic diagram of the working principle of a storage module in the second stage of the in-memory computing mode provided in some embodiments;

[0031] Figure 8 A waveform diagram of current changes of a storage module in the second stage of an in-memory computing mode provided in some embodiments;

[0032] Figure 9 A structural block diagram of a storage array provided in some embodiments;

[0033] Figure 10 is a structural block diagram of a storage device provided in some embodiments;

[0034] Figure 11 A schematic diagram of the working principle of a storage device in a storage mode provided in some embodiments;

[0035] Figure 12 A schematic diagram of the working principle of a storage device in the first stage of an in-memory computing mode provided in some embodiments;

[0036] Figure 13 A schematic diagram of the working principle of a storage device in the second stage of the in-memory computing mode provided in some embodiments;

[0037] Figure 14 A flowchart of an in-memory computing programming method provided in some embodiments.

[0038] Description of reference numerals:

[0039] HRC-storage module, 1-storage unit, 2-in-memory computing unit, WL-word line, BL-bit line, SL-source line, TWL-timing word line, CWL-computation word line, CSL-computation source line, N0-first transistor, R-resistive random access memory, N1-second transistor, N2-third transistor, N3-fourth transistor, C-capacitor, 3-read and write control circuit, 31-bit line drive circuit, 32-word line drive circuit and source line drive circuit, 33-delay circuit, 4-in-memory computing control circuit, 41-timing word line drive circuit, 42-computation word line pulse generation and drive circuit, 43-computation source line processing circuit, 44-computation post-processing circuit. DETAILED DESCRIPTION

[0040] To facilitate understanding of the present disclosure, a more comprehensive description of the present disclosure will be provided below with reference to the accompanying drawings. The drawings illustrate preferred embodiments of the present disclosure. However, the present disclosure can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to provide a more thorough and comprehensive understanding of the present disclosure.

[0041] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art in the art of the present disclosure. The terms used herein in the specification of the present disclosure are only for the purpose of describing specific embodiments and are not intended to limit the present disclosure.

[0042] It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, and / or portions, these elements, components, regions, layers, and / or portions should not be limited by these terms. These terms are merely used to distinguish one element, component, region, layer, or portion from another element, component, region, layer, or portion. Therefore, a first element, component, region, layer, or portion discussed below may be represented as a second element, component, region, layer, or portion without departing from the teachings of the present invention.

[0043] It should be understood that when an element is considered to be "connected" to another element, it can be directly connected to the other element or connected to the other element through an intervening element. In addition, the "connection" in the following embodiments should be understood as "electrical connection", "communication connection", etc., if there is transmission of electrical signals or data between the connected objects.

[0044] It should be understood that the singular forms "a," "an," and "the" may also include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "include," "comprising," "having," and the like specify the presence of stated features, integers, steps, operations, components, parts, or combinations thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, components, parts, or combinations thereof. At the same time, as used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0045] Examples of non-volatile memory include flash memory (FLASH), resistive random access memory (RRAM), and phase-change random access memory (PCRAM). Examples of volatile memory include static random access memory (SRAM) and dynamic random access memory (DRAM). Non-volatile compute-in-memory (NvCIM) refers to in-memory computing based on non-volatile memory. Compared to in-memory computing based on volatile memory, NvCIM can retain data during power outages, effectively reducing the power consumption required for data backup and recovery.

[0046] Currently, among the emerging non-volatile memories, RRAM has attracted widespread attention due to its advantages of multi-bit storage, high scalability, low power consumption and compatibility with advanced CMOS processes.

[0047] For example, in an existing RRAM-based non-volatile computing in memory (NvCIM) method, please combine Figure 1 As shown in Figure (a), the read current can be accumulated in the memory array according to Kirchhoff's law and read using an analog-to-digital converter (ADC). However, this approach faces multiple challenges: 1) During the computation process, a direct current (DC) path exists between the RRAM and the read circuit, which consumes significant energy and easily undermines the energy efficiency advantage of CIM. 2) The limited on-off ratio of RRAM and the IR drop on the metal lines caused by the large accumulated current can easily lead to nonlinearity and reduce computational accuracy. 3) The peripheral circuitry tends to occupy a large area and consume a lot of power.

[0048] For example, in another existing RRAM-based non-volatile computing in memory (NvCIM) method, please combine Figure 1 As shown in Figure (b), the basic principle is still current summation. However, the discharge of the summation current comes from the parasitic capacitance (C BL), rather than directly from the power supply voltage (VDD). This approach, by quantizing the voltage on the bitline to obtain in-memory computational results, can provide better energy efficiency by eliminating the DC path in the computation process. However, it still has significant limitations: 1) To avoid RRAM read disturb, the maximum voltage on the bitline is limited; 2) the parasitic capacitance on the bitline is insufficient for high-parallel discharge, which is further exacerbated by the limited voltage swing on the bitline; and 3) the discharge current flowing through the RRAM is proportional to the voltage on the bitline, which inherently introduces nonlinearity (although there are methods to mitigate this nonlinearity, it will inevitably incur overhead in area and power consumption).

[0049] In order to solve the above problems, the applicant has found an alternative method to use transistors for discharge, such as Figure 1 This approach decouples the RRAM from the discharge path, eliminating the risk of read disturb. Furthermore, the discharge current can be controlled by the transistor's gate voltage, allowing operation in the transistor's subthreshold region, significantly reducing the discharge current. Furthermore, the transistor's subthreshold swing (SS) can be exploited to enhance the cell's on / off ratio. Furthermore, due to the characteristics of transistors operating in their saturation region, the voltage drop on the bit line has minimal impact on the discharge current. However, transistor mismatch due to process variations can adversely affect the accuracy of in-memory calculations, especially when transistors operate in the subthreshold region. For memory cells constructed from SRAM and DRAM, the voltage at the storage node (denoted as "Q") can be directly applied to the gate of the discharge transistor. However, in addition to their volatility, a significant limitation of these designs is that they lack the ability to eliminate the effects of transistor mismatch. However, for memory cells constructed from non-volatile memory, such as RRAM, information is stored in the form of resistance, requiring the information to be converted to a voltage. This allows the read voltage to be applied to the memory cell, which can then be divided by the transistor and RRAM to establish a stable Q-point voltage. A significant drawback of this approach is the lack of a dielectric to preserve the Q-point voltage. Therefore, once the read voltage across the memory cell is removed, the established Q-point voltage is lost. Therefore, a DC path is still required for the bitline capacitance to discharge through the transistor, which reduces the energy efficiency advantage of this approach. However, this approach can take advantage of the non-volatility and multi-bit storage capabilities of RRAM, allowing fine-tuning of the RRAM to compensate for mismatches in the discharge transistor.

[0050] Based on this, the embodiments of the present disclosure provide a storage module, a storage array, a storage device, and an in-memory computing programming method, which not only have the advantages of non-volatility, high switching ratio, extremely low turn-on current, elimination of DC paths during the calculation process, and compensation for discharge transistor mismatch, but also can effectively improve the parallelism, linearity, and energy efficiency of in-memory computing.

[0051] See also Figure 2 Some embodiments of the present disclosure provide a storage module HRC, including a storage unit 1 and an in-memory computing unit 2.

[0052] The memory cell 1 is used to connect a word line WL, a bit line BL and a source line SL, and is configured to perform data programming, data reading or data deletion based on the word line WL, the bit line BL and the source line SL in a storage mode.

[0053] The in-memory computing unit 2 is connected to the memory cell 1 and is used to connect the timing word line TWL, the computing word line CWL, and the computing source line CSL. It is configured to: in the first stage of the in-memory computing mode, obtain the storage data of the memory cell 1 based on the bit line BL and the timing word line TWL; and, in the second stage of the in-memory computing mode, perform in-memory computing based on the computing word line CWL and the computing source line CSL.

[0054] For example, the in-memory computation includes but is not limited to a multiply-accumulate operation (MAC).

[0055] See also Figure 3 In some embodiments of the present disclosure, the memory unit 1 includes: a first transistor N0 and a resistive memory R (eg Figure 3 1T1R portion in FIG. 1 ). A gate of the first transistor N0 is connected to a word line WL. A first electrode of the first transistor N0 is connected to a source line SL. A second electrode of the first transistor N0 is connected to a first end of the resistive memory R. A second end of the resistive memory R is connected to a bit line BL.

[0056] Please continue reading Figure 3 In some embodiments of the present disclosure, the in-memory computing unit 2 includes: a second transistor N1, a third transistor N2, a capacitor C (e.g. Figure 3 2T1C part) and the fourth transistor N3 (e.g. Figure 3 The gate of the second transistor N1 is connected to the timing word line TWL. The first electrode of the second transistor N1 is connected to the memory cell 1, for example, the first terminal of the resistive memory R in the memory cell 1. The second electrode of the second transistor N1, the gate of the third transistor N2, and the first electrode of the capacitor C are connected to form a restore node Node. The first electrode of the third transistor N2 is connected to the second electrode of the capacitor C and to the ground voltage terminal. The second electrode of the third transistor N2 is connected to the first electrode of the fourth transistor N3. The gate of the fourth transistor N3 is connected to the computing word line CWL. The second electrode of the fourth transistor N3 is connected to the computing source line CSL.

[0057] Here, combined with Figure 3It can be understood that the second transistor N1, the third transistor N2, the capacitor C and the fourth transistor N3 in the in-memory computing unit 2 can be divided into Figure 3 The 2T1C part and the discharge control part are shown in FIG, wherein the second transistor N1, the third transistor N2 and the capacitor C constitute the 2T1C part, and the fourth transistor N3 constitutes the discharge control part.

[0058] It should be added that the above-mentioned storage module HRC has two working modes: storage mode and in-memory computing mode; among them, the in-memory computing mode can be divided into a first stage (such as the recovery stage RESTORE) and a second stage (such as the discharge stage DISCHARGE).

[0059] See also Figure 4 , in storage mode, storage unit 1 (e.g. Figure 3 The 1T1R portion of the resistive switching memory R is activated. By driving the word lines WL, bit lines BL, and source lines SL, data programming (e.g., SET), data reading (READ), or data deletion (e.g., RESET) can be performed on the resistive switching memory R. The driving control of the word lines WL, bit lines BL, and source lines SL can be performed with reference to the driving of the resistive switching memory R in related art, and is not limited in this embodiment of the present disclosure.

[0060] Optionally, in the storage mode, the computing word line CWL, the timing word line TWL, and the computing source line CSL are all connected to the ground voltage terminal.

[0061] See also Figure 5 In the first phase of the in-memory computing mode (e.g., the restore phase RESTORE), the stored data of the memory cell 1 is obtained based on the bit line BL and the timing word line TWL. Specifically, the data stored in the resistive memory R is converted into the charge on the capacitor C.

[0062] For example, the first phase of the in-memory computing mode includes three sub-phases, such as Figure 6 Sub-stage-I, sub-stage-II and sub-stage-III shown in.

[0063] In sub-phase-I, the voltage on the timing word line TWL is pulled up to the power supply voltage VDD (eg, a high-level voltage), the bit line BL is connected to the ground voltage terminal, and the residual charge on the capacitor C is cleared.

[0064] In sub-phase II, the bit line BL is charged to a preset voltage, while the timing word line TWL remains at the power supply voltage VDD. The second transistor N1 is activated, turning on the RRAM R and capacitor C. This allows the restore node Node to be charged via an RC path, improving efficiency based on the RC delay mechanism. The charging rate of the restore node Node can vary significantly depending on the resistance of the RRAM R.

[0065] Optionally, the preset voltage is no greater than 400 mV to ensure that the third transistor N2 can operate in a subthreshold region and prevent read interference on the resistive memory R.

[0066] In sub-phase III, the voltage on the timing word line TWL is pulled low, severing the aforementioned RC path. At this point, the data stored in the resistive random access memory R has been successfully converted into charge on the capacitor C, allowing the second phase of the in-memory computing mode (e.g., the discharge phase DISCHARGE) to proceed.

[0067] Optionally, in the sub-phase-III, the voltage on the bit line BL is maintained at a preset voltage, which helps to ensure that the voltage of the restoration node Node is maintained longer.

[0068] In an example, see Figure 6 , taking the on-off ratio of the resistive memory R as N (i.e., the resistance value of the low resistance state (LRS) of the resistive memory R is 1 / N of its high resistance state (HRS) resistance) as an example, accordingly, the voltage V of the recovery node Node when the resistive memory R is in the aforementioned low resistance state (LRS) is LRS-Node and the voltage V of the restore node Node when the resistive memory R is in the aforementioned high resistance state (HRS) HRS-Node It is possible to show certain differences at the end of sub-stage-III (i.e., the end of the first stage of the in-memory computing mode).

[0069] Here, the resistance ratio of the resistive memory R in the low resistance state (LRS) and the high resistance state (HRS) in the embodiment of the present disclosure is only used to illustrate that at the end of the first stage of the in-memory computing mode, the voltage of the recovery node Node can have obvious differences due to the difference in the data stored in the resistive memory R; and it does not serve as a relevant limitation on the embodiment of the present disclosure.

[0070] For some examples, see Figure 5 The calculation source line CSL is also connected to the CSL pre-charging circuit, and the calculation source line CSL can be charged through the CSL pre-charging circuit in the first stage of the in-memory calculation mode.

[0071] In the second phase of the in-memory computing mode (e.g., the discharge phase DISCHARGE), see Figure 7, performing in-memory calculations based on the calculation word line CWL and the calculation source line CSL. Specifically, after the calculation word line CWL controls the fourth transistor N3 to be turned on, the calculation source line CSL can be discharged through the cascade structure of the third transistor N2 and the fourth transistor N3.

[0072] In the embodiment of the present disclosure, the fourth transistor N3 can realize the following three key functions:

[0073] The fourth transistor N3 serves as an input terminal for in-memory calculation, allowing application of different pulse widths proportional to the input value to change the discharge time, thereby enabling multi-bit multiplication by one-bit calculation to be implemented within a storage module HRC.

[0074] By properly selecting the pulse voltage of the calculation word line CWL, the risk of current degradation of the calculation source line CSL during the discharge process can be minimized, thereby ensuring that the memory calculation of the memory module HRC has a high linearity. For example, when selecting the pulse voltage V CWL = 500mV, calculate the voltage V of the source line CSL CSL The current when discharging to 0.2V is only slightly greater than the voltage V of the source line CSL. CSL The current when discharging to 0.9V is 3.5% lower.

[0075] The fourth transistor N3 can shield the coupling effect from the computing source line CSL to the recovery node Node. For example, under the action of the subthreshold swing (SS) of the third transistor N2, the voltage difference on the recovery node Node (ie, the voltage V HRS-Node and voltage V LRS-Node The difference between the two) can be converted into a discharge current difference ΔI greater than 10×N times in the second stage of the in-memory calculation mode, thereby effectively amplifying the switching ratio (N) of the memory cell, for example Figure 8 As shown in .

[0076] Furthermore, the memory module HRC provided by the embodiments of the present disclosure can suppress the amplitude of the discharge current to below 100 nA, thereby facilitating high parallelism in in-memory computation. Furthermore, in the memory module HRC provided by the embodiments of the present disclosure, the parasitic capacitance of the computation source line CSL is sufficient to achieve high parallelism and can even accumulate during multiple parallel activations of the computation word line CWL, further improving energy efficiency.

[0077] As described above, in the embodiment of the present disclosure, the storage module includes a storage cell 1 and an in-memory computing unit 2, and the storage cell 1 is configured to be connected to the word line WL, the bit line BL, and the source line SL so as to perform data programming, data reading, or data deletion based on the word line WL, the bit line BL, and the source line SL in the storage mode. The in-memory computing unit 2 is configured to be connected to the storage cell 1, the timing word line TWL, the computing word line CWL, and the computing source line CSL so as to obtain the storage data of the storage cell 1 based on the bit line BL and the timing word line TWL in the first stage of the in-memory computing mode, and perform in-memory computing based on the computing word line CWL and the computing source line CSL in the second stage of the in-memory computing mode. The embodiment of the present disclosure easily decouples the working paths of the storage module HRC in the storage mode and the in-memory computing mode, and is convenient for effectively improving the parallelism, linearity, and energy efficiency of the in-memory computing while ensuring that the storage module HRC has the advantages of non-volatility, high switching ratio, extremely low on-current, elimination of DC paths during the computing process, and compensation for discharge transistor mismatch.

[0078] See also Figure 9 Some embodiments of the present disclosure further provide a storage array comprising a plurality of storage units arranged in an array. The storage units comprise a plurality of storage modules HRC as described in any of the above embodiments, arranged in rows along a first direction. The storage array also possesses the technical advantages of the aforementioned storage modules and will not be further elaborated here.

[0079] Optionally, several consecutive storage modules HRC in each row constitute a storage unit. Figure 9 In the example above, eight HRCs are used to form a storage unit, but the present invention is not limited thereto. The number of HRCs in a storage unit can also be other values. However, it is understood that in storage mode, each HRC in a storage unit stores data independently.

[0080] For example, Figure 9 As shown in , for an m×n memory array, taking 8 memory modules HRC forming a memory unit as an example, the number of bit lines BL and calculation word lines CWL connected to each memory module HRC is m, and the number of word lines WL, timing word lines TWL, source lines SL and calculation source lines CSL connected to each memory module HRC is 8n.

[0081] In some embodiments of the present disclosure, the recovery node Node of each storage module HRC in each storage unit is connected and connected to a shared capacitor C0, and the shared capacitor C0 is configured to: in an in-memory computing mode (for example, the first stage of the in-memory computing mode), obtain the storage data of the target storage module HRC in the corresponding storage unit in response to the in-memory computing control instruction.

[0082] Optionally, the shared capacitor C0 includes but is not limited to a metal-oxide-metal (MOM) capacitor.

[0083] In the disclosed embodiment, each memory module HRC within any memory unit independently stores data. Therefore, during the first phase of in-memory computing mode, by activating the timing word line connected to the target memory module, the stored data in the target memory module can be restored to the shared capacitor C0. This helps ensure and improve the storage density of the memory array.

[0084] It is worth mentioning that in some embodiments of the present disclosure, the storage units are arranged in rows along a second direction, where the second direction intersects the first direction. At least one row of storage units is a virtual row of storage units. Each HRC in the virtual row of storage units stores pre-calibrated data.

[0085] Here, the calibration pre-stored data is not valid data for in-memory calculation and can be subtracted from the in-memory calculation result of the storage array to calibrate the in-memory calculation result of the storage array, thereby obtaining better linearity.

[0086] Optionally, the virtual column storage unit is located at the leftmost side of the storage array, which may be the first column from left to right, but is not limited thereto. The virtual column storage unit may also be, for example, the middle column or the rightmost column.

[0087] Optionally, the resistive random access memory R of each storage module HRC in the virtual column storage unit is configured to be in a high resistance state (HRS), so that the leakage current in the in-memory computing mode can be effectively monitored.

[0088] See also Figure 10 Some embodiments of the present disclosure further provide a storage device comprising: a storage array as described in any of the above embodiments, a read / write control circuit 3, and an in-memory calculation control circuit 4. This storage device also possesses the technical advantages of the aforementioned storage array and will not be further elaborated here.

[0089] The read / write control circuit 3 is connected to each storage unit in the storage array through the bit line driving circuit 31, the word line driving circuit and the source line driving circuit 32, and is configured as follows: in the storage mode, storage control instructions are sent to the bit line driving circuit 31, the word line driving circuit and the source line driving circuit 32 respectively to select the target storage module to perform data programming, data reading or data deletion.

[0090] The in-memory calculation control circuit 4 is connected to each storage unit in the storage array through the timing word line driving circuit 41, the calculation word line pulse generation and driving circuit 42 and the calculation source line processing circuit 43, and is configured as follows: in the first stage of the in-memory calculation mode, a first in-memory calculation control instruction is sent to the timing word line driving circuit 41 to obtain the storage data of multiple target storage modules; and in the second stage of the in-memory calculation mode, a second in-memory calculation control instruction is sent to the calculation word line pulse generation and driving circuit 42 and the calculation source line processing circuit 43 to perform in-memory calculation on the storage data of multiple target storage modules.

[0091] Optionally, the word line driving circuit and the source line driving circuit 32 are integrated into an integral structure.

[0092] Optionally, the computational source line processing circuit 43 includes but is not limited to a circuit having a pre-charging function, a voltage comparison function, and a voltage quantization function.

[0093] Please continue reading Figure 10 In some embodiments of the present disclosure, the memory device further includes a delay circuit 33. The delay circuit 33 is connected to the bit line driver circuit 31 and the timing word line driver circuit 41 and is configured to control the charging time of the shared capacitor C0 (i.e., the charging time of the recovery node Node) in the in-memory calculation mode.

[0094] Please continue reading Figure 10 In some embodiments of the present disclosure, the storage device further includes a calculation post-processing circuit 44. The calculation post-processing circuit 44 is connected to the calculation source line processing circuit 43 and is configured to: in the in-memory calculation mode, post-process the operation structure of the in-memory calculation and output the post-processing result.

[0095] Optionally, the calculation post-processing circuit 44 serves as an output circuit of the storage device and can perform post-processing on the stored calculation results (e.g., MAC results), such as activation, biasing, and quantization to a low-precision representation. The present embodiment does not impose any specific restrictions on the circuit structure of the calculation post-processing circuit 44, as long as it can achieve the corresponding post-processing functions.

[0096] It should be added that the above-mentioned storage device has two working modes: storage mode and in-memory computing mode; wherein the in-memory computing mode can be divided into a first stage (eg, a recovery stage RESTORE) and a second stage (eg, a discharge stage DISCHARGE).

[0097] See also Figure 11In storage mode, the read / write control circuit 3, bit line driver circuit 31, word line driver circuit, and source line driver circuit 32 are operational, while the delay circuit 33, in-memory calculation control circuit 4, timing word line driver circuit 41, calculation word line pulse generation and driver circuit 42, calculation source line processing circuit 43, and calculation post-processing circuit 44 are all in the off state. Accordingly, the read / write control circuit 3, through the bit line driver circuit 31, word line driver circuit, and source line driver circuit 32, can drive the corresponding bit lines BL, word lines WL, and source lines SL, respectively, to select a target memory block in the memory array for data programming (SET), data reading (READ), or data erasure (RESET).

[0098] See also Figure 12 In the first stage of in-memory calculation mode, the read / write control circuit 3, bitline driver circuit 31, delay circuit 33, in-memory calculation control circuit 4, and timing wordline driver circuit 41 are operational, while the wordline driver circuit and source line driver circuit 32, calculation wordline pulse generation and driver circuit 42, calculation source line processing circuit 43, and calculation post-processing circuit 44 are all in the off state. Accordingly, the bitline driver circuit 31 activates the bitlines BL in parallel, while the timing wordline driver circuit 41 activates one timing wordline TWL in each memory cell in parallel. Simultaneously, the delay circuit 33 controls the charging time of the shared capacitor C0 (i.e., the charging time of the restoration node Node), restoring the stored data of the selected target memory module in each memory cell to the shared capacitor C0.

[0099] See also Figure 13 In the second stage of the in-memory calculation mode, the in-memory calculation control circuit 4, the calculation word line pulse generation and drive circuit 42, the calculation source line processing circuit 43, and the calculation post-processing circuit 44 are operational, while the read / write control circuit 3, the bit line driver circuit 31, the word line driver circuit and the source line driver circuit 32, the delay circuit 33, and the timing word line driver circuit 41 are all deactivated. Accordingly, the calculation word line pulse generation and drive circuit 42 receives the input value for the in-memory calculation, activates a certain number of calculation word lines CWL in parallel, and generates a pulse signal with a pulse width proportional to the input value. The parasitic capacitance on the calculation source line CSL is discharged through the cascaded structure of the third transistor N2 and the fourth transistor N3 in the corresponding target memory module, causing the corresponding voltage to be converted into a digital value by the calculation source line processing circuit 43, serving as the in-memory calculation result (e.g., MAC result). Optionally, the in-memory calculation result is output after post-processing by the calculation post-processing circuit 44.

[0100] Some embodiments of the present disclosure further provide an in-memory computing programming method, which is applicable to the storage device described in any of the above embodiments. The in-memory computing programming method also possesses the technical advantages of the aforementioned storage device, which will not be described in detail here.

[0101] See also Figure 14 , the programming method includes the following steps S100~S600.

[0102] S100 , selecting a plurality of target memory modules in a first target row from a memory array as a group to be programmed.

[0103] For example, for a memory array consisting of m×n memory units, if row number i is used and numbering starts from 0, the first target row may be the memory unit row corresponding to i = 0. Accordingly, step S100 may be performed as follows: initializing the memory array so that i = 0 (i.e., programming starts from row 0).

[0104] For example, when programming the i-th row of memory cells, the to-be-programmed group Group is first set to be the set of memory modules HRC to be programmed in the i-th row, and each memory cell has only one to-be-programmed memory module HRC as the target memory module.

[0105] S200 , in a storage mode, performing a first data programming on each target memory module in the to-be-programmed group through a bit line driving circuit, a word line driving circuit, and a source line driving circuit.

[0106] Here, the first data programming can be performed by coarsely adjusting the resistance value of the resistive random access memory (R) in the target memory module. This is intended to facilitate faster convergence of the subsequent discharge current when it meets preset conditions. Furthermore, the first data programming operation can be combined with the operation of the memory device in the storage mode described in some of the aforementioned embodiments and will not be further described here.

[0107] S300 , in the first stage of the in-memory calculation mode, the stored data of each target memory module in the to-be-programmed group is restored to the corresponding shared capacitor via the bit line driving circuit and the timing word line driving circuit.

[0108] Here, the operation of restoring the data stored in each target storage module can be implemented in combination with the operation of the first stage of the storage device in the in-memory computing mode in some of the aforementioned embodiments, which will not be described in detail here.

[0109] S400, in the second stage of the in-memory calculation mode, the discharge of the shared capacitor is controlled by the calculation word line pulse generation and driving circuit and the calculation source line processing circuit, and whether the discharge current of the shared capacitor meets the preset conditions is detected.

[0110] Here, the discharge operation of the shared capacitor can be implemented in combination with the second phase of the operation of the storage device in the in-memory computing mode in some of the aforementioned embodiments, which will not be described in detail here.

[0111] For example, the preset condition may be set to match the allowable error range of the discharge current.

[0112] Accordingly, the programming method further includes the following steps S500 and S600.

[0113] S500 , in response to the discharge current of the shared capacitor meeting a preset condition, selecting a plurality of target memory blocks in a second target row from the memory array as a group to be programmed.

[0114] In other words, if the discharge current of the shared capacitor meets the preset condition, the memory cells in the i-th row are programmed successfully, and the memory cells in the (i+1)-th row can be programmed.

[0115] S600, in response to the discharge current of the shared capacitor not meeting the preset condition, in the storage mode, data programming is performed a second time on each target storage module in the programming group, and in the in-memory calculation mode, the storage data of each target storage module in the programming group is restored to the corresponding shared capacitor to detect again whether the discharge current of the shared capacitor meets the preset condition.

[0116] In other words, if the discharge current of the shared capacitor does not meet the preset condition, a second data programming operation is required for the memory cells in row i. After the second data programming operation, the process returns to steps S300 and S400. In this way, through the second data programming cycle, it is possible to ensure that all memory cells in any row are successfully programmed.

[0117] For example, the second data programming has a higher precision than the first data programming. That is, the second data programming can be performed by fine-tuning the resistance of the resistive random access memory (R) in the target memory module, which can be achieved by adjusting parameters such as the amplitude and width of the programming pulse.

[0118] In the embodiment of the present disclosure, by selecting a group to be programmed to perform data programming in the storage mode, and combining it with the in-memory calculation mode to perform in-memory calculation simulation, it can be ensured that the discharge current of the successfully programmed storage unit can meet the preset conditions (that is, be within the error range), thereby effectively compensating for the mismatch of the discharge transistor in the storage module, so as to improve the linearity and calculation accuracy of the in-memory calculation.

[0119] The technical features of the above-mentioned embodiments can be combined arbitrarily. To make the description concise, not all possible combinations of the technical features of the above-mentioned embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0120] The above-described embodiments merely represent several implementation methods of the present disclosure. While the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that a person of ordinary skill in the art may make various modifications and improvements without departing from the spirit of the present disclosure, all of which fall within the scope of protection of the present disclosure. Therefore, the scope of protection of the patent disclosed herein shall be determined by the appended claims.

Claims

1. A storage array, characterized in that: The invention comprises a plurality of storage units arranged in an array; the storage units comprise a plurality of storage modules arranged in a row along a first direction; the storage modules comprise: A memory cell, connected to a word line, a bit line, and a source line, and configured to: in a storage mode, perform data programming, data reading, or data deletion based on the word line, the bit line, and the source line; an in-memory calculation unit connected to the memory cell and used to connect the timing word line, the calculation word line, and the calculation source line, and configured to: in a first phase of an in-memory calculation mode, obtain the storage data of the memory cell based on the bit line and the timing word line; and in a second phase of the in-memory calculation mode, perform in-memory calculation based on the calculation word line and the calculation source line; The in-memory computing unit includes: a second transistor, a third transistor, a capacitor, and a fourth transistor; the gate of the second transistor is connected to the timing word line; the first electrode of the second transistor is connected to the storage unit; the second electrode of the second transistor, the gate of the third transistor, and the first electrode of the capacitor are connected as a recovery node; the first electrode of the third transistor is connected to the second electrode of the capacitor and to a ground voltage terminal; the second electrode of the third transistor is connected to the first electrode of the fourth transistor; the gate of the fourth transistor is connected to the computing word line, and the second electrode of the fourth transistor is connected to the computing source line; Among them, the recovery nodes of each storage module in each storage unit are connected and connected to a shared capacitor, and the shared capacitor is configured to: in an in-memory computing mode, obtain the storage data of the target storage module in the corresponding storage unit in response to an in-memory computing control instruction.

2. The storage array according to claim 1, wherein: The storage units are arranged in a row along a second direction, and the second direction intersects the first direction; wherein at least one row of the storage units is a virtual row of storage units; and each storage module in the virtual row of storage units stores calibration pre-stored data.

3. The storage array according to claim 1, wherein: The memory unit includes: a first transistor and a resistive memory; The gate of the first transistor is connected to the word line, the first electrode of the first transistor is connected to the source line, the second electrode of the first transistor is connected to the first end of the resistive random access memory, and the second end of the resistive random access memory is connected to the bit line.

4. A storage device, characterized in that: include: The storage array according to any one of claims 1 to 3; a read / write control circuit connected to each of the memory cells in the memory array via a bit line driver circuit, a word line driver circuit, and a source line driver circuit, and configured to: in a storage mode, send a storage control instruction to the bit line driver circuit, the word line driver circuit, and the source line driver circuit, respectively, to select the target memory module for data programming, data reading, or data deletion; The in-memory calculation control circuit is connected to each of the storage units in the storage array through a timing word line driving circuit, a calculation word line pulse generating and driving circuit and a calculation source line processing circuit, and is configured to: in the first stage of the in-memory calculation mode, send a first in-memory calculation control instruction to the timing word line driving circuit to obtain the storage data of multiple target storage modules; and in the second stage of the in-memory calculation mode, send a second in-memory calculation control instruction to the calculation word line pulse generating and driving circuit and the calculation source line processing circuit to perform in-memory calculation on the storage data of multiple target storage modules.

5. The storage device according to claim 4, wherein: Also includes: The delay circuit is connected to the bit line driving circuit and the timing word line driving circuit, and is configured to: control the charging time of the shared capacitor in the in-memory calculation mode. The storage device according to claim 5 , wherein: Also includes: The calculation post-processing circuit is connected to the calculation source line processing circuit and is configured to: in the in-memory calculation mode, post-process the operation structure of the in-memory calculation and output the post-processing result.

7. A method for in-memory computing programming, characterized in that: Applicable to the storage device according to any one of claims 4 to 6; the programming method comprises: Selecting a plurality of target memory modules in a first target row from the memory array as a group to be programmed; In a storage mode, performing a first data programming on each of the target memory modules in the to-be-programmed group through the bit line driving circuit, the word line driving circuit, and the source line driving circuit; In the first stage of the in-memory calculation mode, the stored data of each target memory module in the to-be-programmed group is restored to the corresponding shared capacitor through the bit line driving circuit and the timing word line driving circuit; In the second stage of the in-memory computing mode, the computing word line pulse generation and driving circuit and the computing source line processing circuit are used to control the discharge of the shared capacitor and detect whether the discharge current of the shared capacitor meets a preset condition; wherein, in response to the discharge current of the shared capacitor meeting the preset condition, a plurality of target memory modules in a second target row are selected from the memory array as a group to be programmed; In response to the discharge current of the shared capacitor not meeting the preset condition, data programming is performed a second time on each of the target storage modules in the group to be programmed in the storage mode, and the storage data of each of the target storage modules in the group to be programmed is restored to the corresponding shared capacitor in the in-memory calculation mode to again detect whether the discharge current of the shared capacitor meets the preset condition.

8. The in-memory computing programming method according to claim 7, characterized in that: The programming accuracy of the second data programming is higher than the programming accuracy of the first data programming.

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