Programmable fuse trimming circuit and method

Abstract

The invention provides a programmable fuse trimming circuit, a programmable fuse trimming method and a fuse array circuit, the programmable fuse trimming circuit comprises a plurality of fuse unit modules and an end bit fuse module, and each fuse unit module comprises a fuse; the fuse programming control circuit receives an external input signal through a chip pin, controls a circuit working mode according to the external input signal, and reads fuse state information from the fuse unit module in a fuse state reading mode; performing pre-trimming on a fuse wire in the fuse wire unit module in the pre-trimming mode; and in the formal trimming mode, performing trimming operation on the fuse in the corresponding fuse unit module, and burning out the fuse in the fuse module at the end position after the fuse trimming operation is finished. After the to-be-trimmed fuse is determined by programmable read fuse and pre-trimming, formal trimming is performed according to the externally input trimming code, the end-bit fuse is burnt out after the trimming is finished, and a chip circuit cannot be trimmed again, so that the phenomenon of false burning is effectively prevented, and the burning time and cost are reduced.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuit design, and in particular to a programmable fuse trimming circuit and method. Background Art

[0002] During the integrated circuit tape-out process, it is inevitable that it will be affected by process fluctuations and packaging procedures, resulting in deviations between circuit parameters and design target values. The accuracy of the final parameters cannot be fully guaranteed, and may even affect the overall performance indicators of the chip. Secondly, as users have higher and higher requirements for the performance indicators of miniaturized integrated circuits, the high-precision challenges faced by integrated circuits are becoming increasingly obvious. For this reason, the adjustment schemes for various chip parameters have gradually received attention.

[0003] The trimming technologies currently used in the chip production process include: laser trimming, PAD trimming and final test trimming. Laser trimming is to burn the metal fuse by laser technology before the chip is packaged; PAD trimming is also to burn the metal fuse by probe before the chip is packaged; final test trimming is to input the trimming code on the external pin after the chip is packaged, control the internal circuit to generate a large current, and thus burn the fuse. Laser trimming has good accuracy, but it cannot avoid the impact of packaging; PAD trimming requires the design of a special trimming PAD inside the chip for probe testing, which will occupy a large chip area; final test trimming is performed after packaging, and the trimming code is input by reusing the existing chip pins, and no additional PAD port is required, which saves area and can avoid the impact of dicing and packaging on the chip. It is a trimming method with higher accuracy at present. However, at present, with the requirements for chip accuracy and the increase in the number of trimming bits, repeated burn-in and trimming are required, which leads to the phenomenon of mis-burning. At the same time, the burn-in and trimming time will also increase due to the increase in the number of trimming bits, which increases the chip cost. Summary of the invention

[0004] Based on the above records, the present invention proposes a low-cost, programmable, and highly reliable testing solution.

[0005] A programmable fuse trimming circuit comprises: a fuse array circuit, comprising a plurality of fuse unit modules and an end position fuse module, each fuse unit module comprising a fuse; a fuse burning control circuit, connected to the fuse array circuit and receiving an external input signal through a chip pin, for: entering a fuse state reading mode, a pre-trim mode and a formal trimming mode according to the external input signal; reading fuse state information from the fuse unit module in the fuse state reading mode; pre-trimming the fuses in the fuse unit module in the pre-trim mode; performing a fuse trimming operation on the fuses in the corresponding fuse unit module in the formal trimming mode, and burning the fuses in the end position fuse module after the fuse trimming operation is completed.

[0006] Furthermore, the fuse burning control circuit includes a mode control module, a data reading and writing module, a storage module, an analog module, an address information detection module and a burning module; the mode control module is respectively connected to the data reading and writing module, the address information detection module and the burning module, the data reading and writing module is connected to the storage module, the storage module is respectively connected to the analog module and the burning module, and the address information detection module is connected to the burning module; the mode control module receives an external input signal through a chip pin, and controls entering a fuse state reading mode, a pre-adjustment mode and a formal adjustment mode according to the external input signal; the address information detection module is used to: generate a fuse address control signal in the fuse state reading mode and the formal adjustment mode and output it to the fuse unit module for conducting operation; the data The data read-write module is used to: read the fuse status information of the fuse unit module in the fuse status read mode and store it in the storage module, and read the pre-adjustment data information in the pre-adjustment mode and store it in the storage module; the simulation module is used to: receive the fuse status information from the storage module, and perform parameter testing according to the pre-adjustment data information and the fuse status information in the pre-adjustment mode, obtain the parameter test result, determine the fuse to be adjusted according to the parameter test result, and the storage module latches the fuse address information to be adjusted; the burn-write module is used to: generate a burn-adjustment current control signal output according to the fuse address information to be adjusted in the storage module in the formal adjustment mode; the fuse array circuit performs an adjustment operation on the fuse to be adjusted according to the burn-adjustment current control signal and the fuse address control signal.

[0007] Furthermore, the fuse array circuit also includes a second PMOS tube, and each fuse unit module also includes an NMOS tube; the source of the second PMOS tube is connected to the power supply voltage, the drain of the second PMOS tube is connected to the first end of the fuse, and the gate of the second PMOS tube is connected to the fuse information reading operation signal; in the fuse unit module, the source of the NMOS tube is grounded, the gate of the NMOS tube is connected to the fuse address control signal, and the drain of the NMOS tube is connected to the second end of the fuse; the fuse array circuit is provided with a fuse state output end, the fuse state output end is connected to the first end of the fuse, and is used to output the fuse state information.

[0008] Furthermore, the programmable fuse trimming circuit also includes a clock generating module, and the mode control module includes a counter unit and a counting end detection unit; in the fuse status reading mode, the counter unit starts working, and the counting end detection unit is used to: detect the counting state of the counter unit according to the output end signal of the counter unit, and output a counting end signal and a fuse information reading operation signal according to the counting state detection result; in the fuse status reading mode, the address information detection module generates a fuse address control signal according to the output end signal of the counter unit, the data read and write module is used to read the fuse status information of the fuse unit module according to the counting end signal, and the clock generating module generates a first internal clock signal according to the output end signal of the counter unit; the storage module latches the fuse status information read by the data read and write module according to the first internal clock signal.

[0009] Furthermore, the external input signal includes an external data signal; the mode control module also includes a shift register, a read pulse detection unit, a data stream unit, an addressing unit and an inverter; the shift register receives the external data signal and stores it as data information of the shift register; the external data signal includes an unlock input signal, and the shift register stores the unlock input signal as unlock data; the read pulse detection unit is used to generate a first unlock pulse signal and a second unlock pulse signal that do not overlap each other based on the unlock data of the shift register; the data stream unit is used to unlock the latch according to the first unlock pulse signal; the addressing unit is used to unlock the latch according to the second unlock pulse signal; the inverter detects the end of counting The count end signal output by the measuring unit is inverted to form a count end inverted signal; in the pre-adjustment mode, the external data signal received by the shift register includes pre-adjustment input data, the pre-adjustment input data enters the data stream unit and is processed by the data stream unit to form pre-adjustment data information, and the pre-adjustment input data enters the addressing unit and is processed by the addressing unit to form pre-adjustment address information; the data reading and writing module reads the pre-adjustment data information formed by the data stream unit according to the count end inverted signal; the clock generating module processes the pre-adjustment address information formed by the addressing unit to generate a second internal clock signal; the storage module latches the pre-adjustment data information read by the data reading and writing module according to the second internal clock signal.

[0010] Furthermore, the programming module includes a programming pulse detection unit, a combinational logic unit, a timing logic unit and a programming current generating unit; in the formal trimming mode, the external data signal received by the shift register includes a first trimming input data and a second trimming input data, the first trimming input data enters the data stream unit and is processed by the data stream unit to form a first trimming control signal; the first trimming input data enters the addressing unit and is processed by the addressing unit to form a second trimming control signal; the second trimming input data enters the data stream unit and is processed by the data stream unit to form a third trimming control signal; the second trimming input data enters the addressing unit and is processed by the addressing unit to form a fourth trimming control signal; in the formal trimming mode, the programming pulse detection unit generates a first trimming control signal according to the first trimming control signal and the second trimming control signal. The timing logic unit generates a reset signal of the counting end detection unit according to the third and fourth trimming control signals, and the counting end detection unit starts the counter unit according to the reset signal of the counting end detection unit; in the formal trimming mode, the address information detection module generates a fuse address control signal to the fuse unit module according to the output signal of the counter unit, and generates fuse address detection information to the combination logic unit; the combination logic unit performs logic processing according to the fuse address detection information and the fuse address information to be trimmed stored in the storage module, and outputs a fuse address selection signal; the burn-out current generation unit generates a burn-out current control signal according to the trimming start control signal and the fuse address selection signal; the fuse array circuit performs a fuse blowing operation according to the burn-out current control signal.

[0011] Further, the burn-out current generating unit includes a fourth AND gate and a seventh NAND gate; the first input end of the fourth AND gate receives the fuse address selection signal; the second input end of the fourth AND gate receives the trimming start control signal; the output end of the fourth AND gate outputs the second burn-out high current control signal; the first input end of the seventh NAND gate receives the trimming start control signal; the second input end of the seventh NAND gate receives the count end signal output by the count end detection unit; the output end of the seventh NAND gate outputs the first burn-out high current control signal; the fuse array circuit includes an eighth NAND gate and a first PMOS tube; the first burn-out high current control signal enters the eighth NAND gate after being inverted at the first input end of the eighth NAND gate; the second burn-out high current control signal is input to the second input end of the eighth NAND gate; the output end of the eighth NAND gate outputs the burn-out fuse operation control signal; the gate of the first PMOS tube is connected to the output end of the eighth NAND gate, the source of the first PMOS tube is connected to the power supply voltage, and the drain of the first PMOS tube is connected to the fuse unit module.

[0012] Furthermore, the clock generating module includes a clock generating circuit, a third NAND gate, a fourth NAND gate, a sixth NAND gate and a decoder; the clock generating circuit is connected to the output signal of the counter unit, and the output of the clock generating circuit is connected to the second input of the fourth NAND gate; the first input of the fourth NAND gate is connected to the counting end signal, and the output of the fourth NAND gate is connected to the second input of the sixth NAND gate; the first input of the third NAND gate is connected to the output of the decoder, the second input of the third NAND gate is connected to the counting end inverted signal, and the output of the third NAND gate is connected to the first input of the sixth NAND gate; the output of the sixth NAND gate is connected to the storage module; the input of the decoder is connected to the addressing unit, and in the pre-adjustment mode, the decoder processes the pre-adjustment address information formed by the addressing unit to form a decoding signal and outputs it to the third NAND gate, and outputs the second internal clock signal to the storage module after passing through the sixth NAND gate.

[0013] Furthermore, the data reading and writing module includes a first NAND gate, a second NAND gate and a fifth NAND gate; the first input end of the first NAND gate is connected to the fuse state output end of the fuse array circuit, the second input end of the first NAND gate is connected to the counting end signal, and the output end of the first NAND gate is connected to the first input end of the fifth NAND gate; the second input end of the second NAND gate is connected to the output end of the inverter, the output end of the second NAND gate is connected to the second input end of the fifth NAND gate, and the output end of the fifth NAND gate is connected to the storage module; the first input end of the second NAND gate is connected to the data stream unit, and in the pre-adjustment mode, the pre-adjustment data information formed by the data stream unit is output to the first input end of the second NAND gate, and then to the storage module via the output end of the fifth NAND gate.

[0014] The present invention provides a programmable fuse trimming method, using the aforementioned programmable fuse trimming circuit, comprising: step A1, power-on initialization of the programmable fuse trimming circuit; step A2, the fuse burning control circuit obtains an external input signal about reading fuse status information through a chip pin, controls entering a fuse status reading mode, and reads fuse status information from a fuse unit module; step A3, the fuse burning control circuit obtains an external input signal about a pre-trim fuse through a chip pin, controls entering a pre-trim mode, performs parameter testing on the chip circuit, and determines a fuse to be trimmed according to the parameter test result; step A4, the fuse burning control circuit obtains an external input signal about a trimming fuse through a chip pin, controls entering a formal trimming mode, and performs a fuse trimming operation on the fuse to be trimmed; step A5, after the fuse trimming operation is completed, the fuse in the end position fuse module is burned out.

[0015] The beneficial technical effect of the present invention is that: the present invention inputs external signals through chip pins, performs programmable test and adjustment of fuses according to external signals, performs formal adjustment according to external input adjustment code after programmable reading of fuse information and pre-adjustment to determine the fuse to be adjusted, and burns out the fuse in the end position fuse module after the adjustment of the fuse to be adjusted is completed, and the circuit can no longer enter the adjustment mode, effectively preventing the occurrence of mis-burning, reducing the burning time and cost, and improving reliability. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 and Figure 2 A circuit diagram of a specific implementation of a programmable fuse trimming circuit is provided for the present invention; Figure 3 A module schematic diagram of a programmable fuse trimming circuit is provided for the present invention; Figure 4 A flowchart of the steps of a programmable fuse trimming method is provided for the present invention; Figure 5 The present invention is a circuit initialization and termination sequence diagram of a programmable fuse trimming circuit.

[0017] Figure 6 The figure is an overall trimming timing diagram of an implementation mode of a programmable fuse trimming circuit of the present invention. DETAILED DESCRIPTION

[0018] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0019] It should be noted that, in the absence of conflict, the embodiments of the present invention and the features in the embodiments may be combined with each other.

[0020] The present invention will be further described below in conjunction with the accompanying drawings and specific embodiments, but they are not intended to limit the present invention.

[0021] See also Figure 1-Figure 3The present invention provides a programmable fuse trimming circuit, comprising: a fuse array circuit 1, comprising a plurality of fuse unit modules and an end position fuse module, each fuse unit module comprising a fuse; a fuse burning control circuit 2, connected to the fuse array circuit 1, and receiving an external input signal through a chip pin, for: entering a fuse state reading mode, a pre-trim mode and a formal trimming mode according to an external input signal; reading fuse state information from the fuse unit module in the fuse state reading mode; pre-trim the fuses in the fuse unit module in the pre-trim mode; performing a fuse trimming operation on the fuses in the corresponding fuse unit module in the formal trimming mode, and burning the fuses in the end position fuse module after the fuse trimming operation is completed.

[0022] The present invention inputs external signals through chip pins, performs programmable test and adjustment of fuses according to external signals, reads fuse status information and performs pre-adjustment through external signals, and performs formal adjustment according to external input adjustment code after pre-adjustment determines the fuse to be adjusted, effectively preventing the occurrence of mis-burning, reducing burn-in time, reducing costs, and having high reliability. In addition, after the adjustment of the fuse to be adjusted is completed, the fuse in the end position fuse module is burned out, and the circuit can no longer enter the adjustment mode.

[0023] Specifically, Figure 1 As shown, it includes N fuse unit modules from 11-1 to 11-N. Each fuse unit module has a fuse fuse. The first fuse unit module 11-1 has a fuse fuse1, and the Nth fuse unit module 11-N has a fuse fuseN.

[0024] See also Figure 2 and Figure 3Further, the fuse burning control circuit 2 includes a mode control module 21, a data reading and writing module 22, a storage module 23, an analog module 24, an address information detection module 25 and a burning module 26; the mode control module 21 is respectively connected to the data reading and writing module 22, the address information detection module 25 and the burning module 26, the data reading and writing module 22 is connected to the storage module 23, the storage module 23 is respectively connected to the analog module 24 and the burning module 26, and the address information detection module 25 is connected to the burning module 26; the mode control module 21 receives an external input signal through a chip pin, and controls to enter a fuse state reading mode, a pre-adjustment mode and a formal adjustment mode according to the external input signal; the address information detection module 25 is used to: generate a fuse address control signal Con_add in the fuse state reading mode and the formal adjustment mode and output it to the fuse unit module for a conduction operation; the data reading and writing module 22 is used to: in the fuse state In the read mode, the fuse state information Fuse_DATA of the fuse unit module is read and stored in the storage module 23; in the pre-trim mode, the pre-trim data information Pre_trim_DATA is read and stored in the storage module 23; the simulation module 24 is used for: receiving the fuse state information Fuse_DATA from the storage module 23, and performing parameter test according to the pre-trim data information Pre_trim_DATA and the fuse state information Fuse_DATA in the pre-trim mode, obtaining the parameter test result, determining the fuse to be trimmed according to the parameter test result, and the storage module 23 latches the fuse address information to be trimmed; the burning module 26 is used for: generating a burning current control signal output according to the fuse address information to be trimmed in the storage module 23 in the formal trim mode; the fuse array circuit 1 performs trimming operation on the fuse to be trimmed according to the burning current control signal and the fuse address control signal Con_add.

[0025] The present invention multiplexes the reading of fuse information, pre-adjustment and formal adjustment to perform module multiplexing, for example, the mode control module 21 controls the overall circuit to enter three operation modes, the information storage of the three modes multiplexes the storage module 23, the reading of fuse information and formal adjustment multiplexes the address information detection module 25, the reading of fuse information and pre-adjustment multiplexes the data reading and writing module 22, the structure is simple, the reusability is high, the circuit occupancy area is reduced, the chip cost is reduced, the integration is convenient, and the mis-burning adjustment can be effectively prevented. The present invention can better utilize its advantages for products with high precision, comprehensive functions and high complexity.

[0026] Furthermore, the fuse array circuit 1 also includes a second PMOS tube PM2, and each fuse unit module also includes an NMOS tube NM; the source of the second PMOS tube PM2 is connected to the power supply voltage VIN, the drain of the second PMOS tube PM2 is connected to the first end of the fuse fuse, and the gate of the second PMOS tube PM2 is connected to the fuse information reading operation signal Read_sel; in the fuse unit module, the source of the NMOS tube is grounded, the gate of the NMOS tube is connected to the fuse address control signal Con_add, and the drain of the NMOS tube is connected to the second end of the fuse fuse; the fuse array circuit 1 is provided with a fuse state output end, the fuse state output end is connected to the first end of the fuse fuse, and is used to output the fuse state information Fuse_DATA.

[0027] Each fuse unit module has an NMOS tube, such as Figure 1 In the embodiment, the NMOS tube NM-1 of the first fuse unit module 11-1 and the NMOS tube NM-N of the N-th fuse unit module 11-N. The address information detection module 25 transmits the fuse address control signal Con_add to the gate of the NMOS tube, for example, transmits Con_add1 to the gate of the NMOS tube NM-1 of the first fuse unit module 11-1, for example, transmits Con_addN to the gate of the NMOS tube NM-N of the N-th fuse unit module 11-N. If the second PMOS tube PM2 is turned on, the NMOS tube corresponding to the high level of the fuse address control signal Con_add is turned on, and the power supply voltage VIN is applied to the corresponding fuse to form a read current Iread. At this time, the fuse state output terminal outputs the fuse state information Fuse_DATA of the fuse.

[0028] Specifically, each fuse unit module further includes a first buffer, the gate of the NMOS tube is connected to the output end of the first buffer, the input end of the first buffer is connected to the fuse address control signal, and the fuse address control signal is buffered by the first buffer before entering the NMOS tube to reduce the impact on the NMOS tube and protect the NMOS tube. Figure 1 Specifically, the fuse state output terminal is connected to a second buffer 12, which buffers the fuse state information Fuse_DATA of the fuse and then outputs it to protect the fuse burning control circuit 2.

[0029] Furthermore, the programmable fuse trimming circuit also includes a clock generating module 27, and the mode control module 21 includes a counter unit 211 and a counting end detection unit 212; in the fuse status reading mode, the counter unit 211 starts working, and the counting end detection unit 212 is used to: detect the counting state of the counter unit 211 according to the output end signal of the counter unit 211, and output the counting end signal Con1 and the fuse information reading operation signal Read_sel according to the counting state detection result; in the fuse status reading mode, the address information detection module 25 generates a fuse address control signal Con_add according to the output end signal of the counter unit 211, and the data read and write module 22 is used to read the fuse status information Fuse_DATA of the fuse unit module according to the counting end signal Con1, and the clock generating module 27 generates a first internal clock signal according to the output end signal of the counter unit 211; the storage module 23 latches the fuse status information Fuse_DATA read by the data read and write module 22 according to the first internal clock signal.

[0030] The gate of the second PMOS tube PM2 receives the read fuse information operation signal Read_sel, and the second PMOS tube PM2 is turned on at a low level. Therefore, the read fuse information operation signal Read_sel is at a low level only when reading fuse information after power-on, and is at a high level at other times. The high level makes the second PMOS tube non-conductive, that is, the fuse status information reading operation is not performed.

[0031] Furthermore, the external input signal includes an external data signal SDA; the mode control module 21 also includes a shift register 213, a read pulse detection unit 214, a data stream unit, an addressing unit and an inverter INV; the shift register 213 receives the external data signal SDA and stores it as data information of the shift register; the external data signal SDA includes an unlock input signal, and the shift register stores the unlock input signal as unlock data; the read pulse detection unit 214 is used to generate a first unlock pulse signal C1 and a second unlock pulse signal C2 that do not overlap each other based on the unlock data of the shift register 213; the data stream unit is used to unlock the latch according to the first unlock pulse signal C1; the addressing unit Used to unlock the latch according to the second unlocking pulse signal C2; the inverter INV inverts the count end signal Con1 output by the count end detection unit 212 to form a count end inverted signal Con2; in the pre-trim mode, the external data signal SDA received by the shift register 213 includes pre-trim input data, the pre-trim input data enters the data stream unit and is processed by the data stream unit to form pre-trim data information Pre_trimDATA, and the pre-trim input data enters the addressing unit and is processed by the addressing unit to form pre-trim address information; the data read-write module 22 reads the pre-trim data information Pre_trim DATA formed by the data stream unit according to the count end inverted signal Con2; the clock generation module 27 processes the pre-trim address information formed by the addressing unit to generate a second internal clock signal; the storage module 23 latches the pre-trim data information Pre_trim DATA read by the data read-write module 22 according to the second internal clock signal.

[0032] Specifically, both the data stream unit and the addressing unit have latches, so the data stream unit needs to unlock the latch according to the first unlocking pulse signal C1, and the addressing unit needs to unlock the latch according to the second unlocking pulse signal C2 to obtain data information of the shift register.

[0033] Specifically, the external input signal includes an external clock signal SCL and an external data signal SDA. In addition, specifically, the mode control module 21 also includes a system reset unit 28. The fuse burning control circuit 2 also receives an external power-on end signal POK through a chip pin. The input end of the system reset unit 28 receives the external clock signal SCL, the external data signal SDA and the power-on end signal POK. The output end of the system reset unit 28 is connected to the third input end of the shift register 213 and the second input end of the read pulse detection unit 214. The output end of the system reset unit 28 outputs a system reset signal RESET to the shift register 213 and the read pulse detection unit 214 respectively.

[0034] A first input terminal of the shift register 213 is connected to an external clock signal SCL, and a second input terminal of the shift register 213 is connected to an external data signal SDA.

[0035] A first input terminal of the read pulse detection unit 214 is connected to the external clock signal SCL.

[0036] Specifically, the data stream unit includes a first AND gate AND1 and a data stream circuit 2151. A first input terminal of the first AND gate AND1 is connected to a first output terminal of the shift register 213, a second input terminal of the first AND gate AND1 is connected to a second output terminal of the shift register 213, and an output terminal of the first AND gate AND1 is connected to a first input terminal of the data stream circuit 2151.

[0037] The output end of the data flow circuit 2151 is connected to the input end of the data reading and writing module 22. For details, see Figure 2 The first output terminal of the data flow circuit 2151 is connected to the first input terminal of the second NAND gate NAND2. The first output terminal of the data flow circuit 2151 is used to output the pre-trim data information Pre_trim DATA.

[0038] Specifically, the second input terminal of the data flow circuit 2151 is connected to the external clock signal SCL, and the third input terminal of the data flow circuit 2151 is connected to the power-on end signal POK.

[0039] Specifically, the second input terminal of the first AND gate AND1 is also connected to the first output terminal of the read pulse detection unit 214 for acquiring the first unlock pulse signal C1.

[0040] Specifically, the addressing unit includes a second AND gate AND2 and an addressing circuit 2161. The first input terminal of the second AND gate AND2 is connected to the third output terminal of the shift register 213. The second input terminal of the second AND gate AND2 is connected to the second output terminal of the read pulse detection unit 214, for obtaining the second unlock pulse signal C2. The output terminal of the second AND gate AND2 is connected to the first input terminal of the addressing circuit 2161. The second input terminal of the addressing circuit 2161 is connected to the external clock signal SCL, and the third input terminal of the addressing circuit 2161 is connected to the power-on end signal POK.

[0041] The fourth output terminal of the shift register 213 is connected to the third input terminal of the read pulse detection unit 214 .

[0042] Specifically, the data flow circuit and the addressing circuit have latches.

[0043] Furthermore, the programming module 26 includes a programming pulse detection unit 261, a combinational logic unit 262, a timing logic unit 263 and a programming current generating unit; in the formal trimming mode, the external data signal SDA received by the shift register includes a first trimming input data and a second trimming input data, the first trimming input data enters the data stream unit and is processed by the data stream unit to form a first trimming control signal; the first trimming input data enters the addressing unit and is processed by the addressing unit to form a second trimming control signal; the second trimming input data enters the data stream unit and is processed by the data stream unit to form a third trimming control signal; the second trimming input data enters the addressing unit and is processed by the addressing unit to form a fourth trimming control signal; in the formal trimming mode, the programming pulse detection unit 261 generates a trimming start control signal according to the first trimming control signal and the second trimming control signal, and the timing logic unit Element 263 generates a reset signal RN of the counting end detection unit according to the third adjustment control signal and the fourth adjustment control signal, and the counting end detection unit 212 starts the counter unit 211 according to the reset signal RN of the counting end detection unit; in the formal adjustment mode, the address information detection module 25 generates a fuse address control signal Con_add to the fuse unit module according to the output end signal of the counter unit, and generates fuse address detection information Fuse_ADD to the combination logic unit 262; the combination logic unit 262 performs logic processing according to the fuse address detection information Fuse_ADD and the fuse address information to be adjusted stored in the storage module, and outputs a fuse address selection signal; the burn-out current generating unit generates a burn-out current control signal according to the adjustment start control signal and the fuse address selection signal; the fuse array circuit 1 performs a fuse blowing operation according to the burn-out current control signal.

[0044] Specifically, the second output terminal of the data flow circuit 2151 is connected to the first input terminal of the sequential logic unit 263 , and the second output terminal of the addressing circuit 2161 is connected to the second input terminal of the sequential logic unit 263 .

[0045] Specifically, the third output terminal of the data flow circuit 2151 is connected to the first input terminal of the programming pulse detection unit 261 , and the third output terminal of the addressing circuit 2161 is connected to the second input terminal of the programming pulse detection unit 261 .

[0046] The first output terminal of the address information detection module 25 is connected to the first input terminal of the combinational logic unit 262, and outputs the fuse address detection information Fuse_ADD to the combinational logic unit 262. The second output terminal of the address information detection module 25 is connected to the fuse array circuit, and outputs the fuse address control signal Con_add to the fuse array circuit.

[0047] Furthermore, the burn-in current generating unit includes a fourth AND gate AND4 and a seventh NAND gate NAND7; the first input end of the fourth AND gate AND4 receives the fuse address selection signal; the second input end of the fourth AND gate AND4 receives the trim start control signal; the output end of the fourth AND gate AND4 outputs the second burn-in high current control signal Con2_trim; the first input end of the seventh NAND gate NAND7 receives the trim start control signal; the second input end of the seventh NAND gate NAND7 receives the count end signal Con1 output by the count end detection unit 212; the output end of the seventh NAND gate NAND7 outputs the first burn-in high current control signal Con1 _trim; the fuse array circuit includes an eighth NAND gate 13 and a first PMOS tube PM1; the first burn-adjusted high current control signal Con1_trim enters the eighth NAND gate 13 after being inverted at the first input end of the eighth NAND gate 13; the second burn-adjusted high current control signal Con2_trim is input to the second input end of the eighth NAND gate 13; the output end of the eighth NAND gate 13 outputs the burn-fuse operation control signal Trim_sel; the gate of the first PMOS tube PM1 is connected to the output end of the eighth NAND gate 13, the source of the first PMOS tube PM1 is connected to the power supply voltage VIN, and the drain of the first PMOS tube PM1 is connected to the fuse unit module.

[0048] Specifically, when the first PMOS transistor PM1 is turned on, the NMOS transistor corresponding to the high level fuse address control signal Con_add is turned on, and the power supply voltage VIN is applied to the corresponding fuse through the first PMOS transistor PM1, forming a large current Itrim to burn the fuse.

[0049] Furthermore, the clock generation module 27 includes a clock generation circuit 271, a third NAND gate NAND3, a fourth NAND gate NAND4, a sixth NAND gate NAND6 and a decoder 272; the clock generation circuit 271 is connected to the output signal of the counter unit 211, and the output of the clock generation circuit 271 is connected to the second input of the fourth NAND gate NAND4; the first input of the fourth NAND gate NAND4 is connected to the count end signal Con1, and the output of the fourth NAND gate NAND4 is connected to the second input of the sixth NAND gate NAND6; the first input of the third NAND gate NAND3 is connected to the output of the counter unit 211, and the output of the clock generation circuit 271 is connected to the second input of the fourth NAND gate NAND4; The end is connected to the output end of the decoder 272, the second input end of the third NAND gate NAND3 is connected to the counting end inverting signal Con2, the output end of the third NAND gate NAND3 is connected to the first input end of the sixth NAND gate NAND6; the output end of the sixth NAND gate NAND6 is connected to the storage module 23; the input end of the decoder 272 is connected to the addressing unit, and in the pre-adjustment mode, the decoder 272 processes the pre-adjustment address information formed by the addressing unit to form a decoding signal and outputs it to the third NAND gate NAND3, and outputs the second internal clock signal to the storage module 23 after passing through the sixth NAND gate NAND6.

[0050] Specifically, the first output terminal of the addressing circuit 2161 is connected to the input terminal of the decoder 272 .

[0051] Furthermore, the data reading and writing module 22 includes a first NAND gate NAND1, a second NAND gate NAND2 and a fifth NAND gate NAND5; the first input end of the first NAND gate NAND1 is connected to the fuse state output end of the fuse array circuit 1, the second input end of the first NAND gate NAND1 is connected to the count end signal Con1, and the output end of the first NAND gate NAND1 is connected to the first input end of the fifth NAND gate NAND5; the second input end of the second NAND gate NAND2 is connected to the output end of the inverter INV, the output end of the second NAND gate NAND2 is connected to the second input end of the fifth NAND gate NAND5, and the output end of the fifth NAND gate NAND5 is connected to the storage module 23; the first input end of the second NAND gate NAND2 is connected to the data stream unit, and in the pre-trim mode, the pre-trim data information Pre_trim DATA formed by the data stream unit is output to the first input end of the second NAND gate NAND2, and then to the storage module 23 via the output end of the fifth NAND gate NAND5.

[0052] Specifically, the mode control module 21 includes a third AND gate AND3 , a first input terminal of which is connected to the count end signal Con1 , a second input terminal of which is connected to the power-on end signal POK, and an output terminal of which is connected to the input terminal of the calculator unit 211 .

[0053] The first input terminal of the count end detection unit 212 is connected to the output terminal of the calculator unit 211, and the input terminal of the clock generation circuit 271 is connected to the output terminal of the calculator unit 211. The input terminal of the address information detection module 25 is connected to the output terminal of the calculator unit 211.

[0054] The second input terminal of the count end detection unit 212 is connected to the external clock signal SCL, the third input terminal of the count end detection unit 212 is connected to the power-on end signal POK, and the fourth input terminal of the count end detection unit 212 is connected to the reset signal RN of the count end detection unit, that is, connected to the output terminal of the timing logic unit 263.

[0055] The first output terminal of the count end detection unit 212 outputs the count end signal Con1, which is inverted by the inverter INV and outputs the count end inverted signal Con2. The second output terminal of the count end detection unit 212 outputs the read fuse information operation signal Read_sel, which is connected to the gate of the second PMOS tube. The third output terminal of the count end detection unit 212 is connected to the second input terminal of the seventh NAND gate NAND7.

[0056] Specifically, the first input terminal of the storage module 23 is connected to the output terminal of the fifth NAND gate NAND5, the second input terminal of the storage module 23 is connected to the output terminal of the sixth NAND gate NAND6, and the signal output by the sixth NAND gate NAND6 becomes the clock signal CLK of the storage module 23, which is the first internal clock signal in the fuse state reading mode and the second internal clock signal in the pre-adjustment mode. The third input terminal of the storage module 23 is connected to the power-on end signal POK.

[0057] See also Figure 4 The present invention also provides a programmable fuse trimming method, using the aforementioned programmable fuse trimming circuit, characterized in that it includes: step A1, power-on initialization of the programmable fuse trimming circuit; step A2, the fuse burning control circuit obtains an external input signal about reading fuse status information through the chip pin, controls entering the fuse status reading mode, and reads the fuse status information from the fuse unit module; step A3, the fuse burning control circuit obtains an external input signal about the pre-trim fuse through the chip pin, controls entering the pre-trim mode, performs parameter testing on the chip circuit, and determines the fuse to be trimmed according to the parameter test result; step A4, the fuse burning control circuit obtains an external input signal about the trimming fuse through the chip pin, controls entering the formal trimming mode, and performs the fuse trimming operation on the fuse to be trimmed; step A5, after the fuse trimming operation is completed, the fuse in the end position fuse module is burned out.

[0058] Specifically, the fuse status information indicates fuse on / off information.

[0059] As an implementation mode of the present invention, the specific application principle is as follows.

[0060] The input end of the fuse burning control circuit is connected to the output end of the power-on reset module, the external pin 1 and the external pin 2. The output end of the power-on reset module, the external pin 1 and the external pin 2 respectively provide a power-on end signal POK, a clock signal SCL and a data signal SDA. The fuse burning control circuit of the present invention can realize the function of reading the fuse status information of each bit of fuse and burning any bit of fuse.

[0061] That is, after the circuit is powered on, the fuse status information is read, and the simulation module will test whether the chip circuit meets the requirements. If it meets the requirements, the fuse in the end position fuse module will be blown. As an embodiment of the present invention, the end position fuse module is the fuse unit module after N fuse unit modules, that is, it can be the fuse of the last fuse unit module. If it does not meet the requirements, it enters the pre-adjustment stage. In the pre-adjustment stage, each fuse is pre-fused and tested by repeating the four steps of circuit initialization, data stream unit and addressing unit unlocking, input row data encoding (the storage module receives the data stream unit pre-adjustment data information obtained) and input column data encoding (the storage module receives the address information obtained by the addressing unit to form the first internal clock signal) until the test result meets the requirements, and then enters the formal adjustment. The formal adjustment includes two parts: the adjustment start control signal is valid and the fuse address scan chain (that is, the fuse address detection information) is valid. When the adjustment start control signal and the fuse address detection information are valid at the same time, the corresponding position fuse can be blown.

[0062] See also Figure 5 In step A1, while the SCL pin is kept at a high level, the SDA pin is given a falling edge to enter initialization; while the SCL pin is kept at a high level, the SDA pin is given a rising edge to end the circuit state. After the circuit enters initialization, the output signal of the system reset unit changes from low to high. At this time, the shift register and the read pulse detection unit can work normally.

[0063] After the input circuit initialization code, the shift register can output the serial data input by the SDA pin in parallel. The parallel output data can be used as data information of the data flow circuit and address information of the addressing circuit. Both the data flow circuit and the addressing circuit have latches, so when the above data information and address information need to be written to the data flow circuit and the addressing circuit respectively, the latches in the data flow circuit and the addressing circuit need to be unlocked first.

[0064] The latch unlocking process is as follows. After the circuit initialization code is input, a set of specific unlocking codes is input to SDA, so that the read pulse detection unit outputs two non-overlapping first unlocking pulse signals C1 and second unlocking pulse signals C2. The first unlocking pulse signal C1 is given to the first AND gate AND1, and finally to the data flow circuit. The first unlocking pulse signal C1 generated by the read pulse detection unit controls whether the data flow circuit can read the data information of the shift register. The data information can be read when the first unlocking pulse signal C1 is high and effective. At this time, the data flow circuit reads eight bits of data information in parallel, and then outputs and latches the eight bits of data information in parallel until the next first unlocking pulse signal C1 appears, and then reads the data information again. The second unlocking pulse signal C2 is given to the second AND gate AND2, and finally to the addressing circuit. The second unlock pulse signal C2 generated by the read pulse detection unit controls whether the addressing circuit can read the data information of the shift register to obtain the address information. When the second unlock pulse signal C2 is high and effective, the data information of the shift register can be read. At this time, the addressing circuit reads the data information of the shift register to obtain the address information, and then outputs and latches the address information until the second unlock pulse signal C2 appears and reads again to obtain the address information. This is the latch unlocking process.

[0065] The latches of the data flow circuit and the addressing circuit are unlocked to read the external data signal SDA input by the chip pin. After the external data signal SDA is output in parallel through the shift register, it is given to the data flow circuit and the addressing circuit as the data information of the data flow circuit (as fuse row information) and the address signal of the addressing circuit (as fuse column information).

[0066] The overall adjustment timing diagram is as follows: Figure 6 As shown, it includes three parts: reading fuse information, pre-adjustment and formal adjustment.

[0067] In the fuse status reading mode, the counter unit starts working after power-on. At this time, the count end signal Con1 is at a high level, and the count end inverting signal Con2 is at a low level. After detecting that the count is finished, the count end signal Con1 changes from high to low, making the RESET signal of the counter unit invalid, thereby ending the count. When the counter unit is working, the first NAND gate NAND1 can read in the fuse status information Fuse_DATA, and then use it as the data information of the storage module. At the same time, the output of the counter unit is given to the clock generating circuit 271, which is composed of a decoder and a combinational logic circuit to generate the first internal clock signal when reading the fuse information. At this time, the fourth NAND gate NAND4 can read in the first internal clock signal, and then use it as the clock signal CLK of the storage module. When the data information and clock information of the storage module are valid at the same time, a latch can be uniquely determined, and the data information can be transmitted to the latch of the storage module and latched. After that, the fuse status information Fuse_DATA can be read into the analog module. When the counter unit stops working, the data information and clock signal CLK of the storage module are invalid, the reading of the fuse information ends, and the fuse status reading mode ends.

[0068] In the pre-trim mode, when the fuse is pre-trim, the counter unit has stopped working, so the count end signal Con1 is at a low level, and the count end inverted signal Con2 is at a high level.

[0069] After the data flow processing, the data information (fuse row information) of the data flow circuit becomes the pre-adjustment data information. At this time, the second NAND gate NAND2 can read the pre-adjustment data information and then use it as the data information of the storage module. The address information latched by the addressing circuit is processed and then processed by the decoder. The second internal clock signal is read in through the third NAND gate NAND3 as the clock signal CLK of the storage module. When the fuse row and column information is valid at the same time, that is, when the data information and clock information CLK of the memory unit are valid at the same time, a latch can be uniquely determined, and the data information is transferred to the latch and latched. This process is the pre-adjustment of a certain fuse, and then the information (pre-adjustment data information) is given to the simulation module. Finally, the parameters of the fuse are tested to see if they meet the requirements. If not, the process is repeated until all parameters meet the requirements and the pre-adjustment is completed.

[0070] In the formal adjustment mode, the counter restarts to work, so the count end signal Con1 is at a high level, and the count end inverted signal Con2 is at a low level.

[0071] After the above-mentioned pre-adjustment mode is over, the fuse that needs to be actually adjusted, i.e., the fuse to be adjusted, has been determined, and the output of the storage module is used as an input signal of the combinational logic unit. The high effective value represents that the fuse needs to be blown, and the low effective value represents that the fuse does not need to be blown. During the formal adjustment, SDA inputs a set of specific codes (the first adjustment input data), which are processed by the data flow circuit and the addressing circuit and then given to the programming pulse detection unit, which outputs a high-level control signal, indicating that the formal adjustment has begun; then SDA inputs another set of specific codes (the second adjustment input data), which are processed by the data flow circuit and the addressing circuit and then given to the timing logic circuit, generating a reset signal RN of the count end detection unit, causing the count end signal Con1 to output a high level, and the counter unit restarts working. At this time, the other output end of the count end detection unit, i.e., the second output end, and the output end of the programming pulse detection unit are connected. After being processed by the seventh NAND gate NAND7, a low effective signal Con1_trim is output; at the same time, after the output signal of the counter unit is processed by the address information detection module, the fuse address detection information Fuse_add is output. After the fuse address detection information Fuse_add and the fuse address information to be adjusted output by the storage module are logically processed, the fuse bit that really needs to be blown, that is, the fuse address selection signal, is output. After being processed by the fourth AND gate AND4, the signal is output Con2_trim. The high level of Con2_trim represents the blowing of the fuse bit, and the low level represents the non-blowing of the fuse bit. Con1_trim and Con2_trim are given to the fuse array circuit to control the fuse burning current. Finally, after the fuse trimming is completed, a set of specific codes are input through the chip pin (at this time, the external data signal is the end bit fuse trimming input data), and the end bit fuse is blown. After the fuse bit is blown, the chip circuit can no longer enter the trimming mode.

[0072] The above are only preferred embodiments of the present invention, and are not intended to limit the implementation methods and protection scope of the present invention. Those skilled in the art should be aware that all solutions obtained by equivalent substitutions and obvious changes made using the description and illustrations of the present invention should be included in the protection scope of the present invention.

Claims

1. A programmable fuse trimming circuit, characterized in that: include: A fuse array circuit comprises a plurality of fuse unit modules and an end position fuse module, each of the fuse unit modules comprises a fuse; a fuse burning control circuit is connected to the fuse array circuit and receives an external input signal through a chip pin, and is used for: entering a fuse state reading mode, a pre-adjustment mode and a formal adjustment mode according to the external input signal; reading fuse state information from the fuse unit module in the fuse state reading mode; pre-adjusting the fuses in the fuse unit module in the pre-adjustment mode; performing a fuse adjustment operation on the fuses in the corresponding fuse unit module in the formal adjustment mode, and burning out the fuses in the end position fuse module after the fuse adjustment operation is completed; the fuse burning control circuit comprises a mode control module, a data reading and writing module, a storage module, an analog module, an address information detection module and a burning module; the mode control module is respectively connected to the data reading and writing module, the address information detection module and the burning module, the data reading and writing module is connected to the storage module, the storage module is respectively connected to the analog module and the burning module, and the address information detection module is connected to the burning module.

2. A programmable fuse trimming circuit as claimed in claim 1, characterized in that: The mode control module receives an external input signal through the chip pin, and controls the entry into the fuse status reading mode, the pre-adjustment mode and the formal adjustment mode according to the external input signal; the address information detection module is used to: generate a fuse address control signal in the fuse status reading mode and the formal adjustment mode and output it to the fuse unit module for conducting operation; the data read and write module is used to: read the fuse status information of the fuse unit module in the fuse status reading mode and store it in the storage module, and read the pre-adjustment data information in the pre-adjustment mode and store it in the storage module; the analog module The block is used for: receiving the fuse status information from the storage module, and performing parameter test according to the pre-trim data information and the fuse status information in the pre-trim mode, obtaining the parameter test result, determining the fuse to be trimmed according to the parameter test result, and the storage module latches the fuse address information to be trimmed; the burn-write module is used for: generating a burn-out current control signal output according to the fuse address information to be trimmed in the storage module in the formal trim mode; and the fuse array circuit performs trimming operation on the fuse to be trimmed according to the burn-out current control signal and the fuse address control signal.

3. A programmable fuse trimming circuit as claimed in claim 2, characterized in that: The fuse array circuit also includes a second PMOS tube, and each of the fuse unit modules also includes an NMOS tube; the source of the second PMOS tube is connected to the power supply voltage, the drain of the second PMOS tube is connected to the first end of the fuse, and the gate of the second PMOS tube is connected to the fuse information reading operation signal; in the fuse unit module, the source of the NMOS tube is grounded, the gate of the NMOS tube is connected to the fuse address control signal, and the drain of the NMOS tube is connected to the second end of the fuse; the fuse array circuit is provided with a fuse state output end, and the fuse state output end is connected to the first end of the fuse for outputting fuse state information.

4. A programmable fuse trimming circuit as claimed in claim 3, characterized in that: The programmable fuse trimming circuit also includes a clock generation module, and the mode control module includes a counter unit and a count end detection unit; in the fuse status reading mode, the counter unit starts working, and the count end detection unit is used to: detect the counting state of the counter unit according to the output end signal of the counter unit, and output the count end signal and the read fuse information operation signal according to the count state detection result; in the fuse status reading mode, the address information detection module generates a fuse address control signal according to the output end signal of the counter unit, and the data read and write module is used to read the fuse status information of the fuse unit module according to the count end signal, and the clock generation module generates a first internal clock signal according to the output end signal of the counter unit; the storage module latches the fuse status information read by the data read and write module according to the first internal clock signal.

5. A programmable fuse trimming circuit as claimed in claim 4, characterized in that: The external input signal includes an external data signal; the mode control module also includes a shift register, a read pulse detection unit, a data stream unit, an addressing unit and an inverter; the shift register is used to receive the external data signal and store it as data information of the shift register; the external data signal includes an unlock input signal, and the shift register stores the unlock input signal as unlock data; The read pulse detection unit is used to generate a first unlock pulse signal and a second unlock pulse signal that do not overlap each other based on the unlock data of the shift register; The data stream unit is used for unlocking the latch according to the first unlock pulse signal; The addressing unit is used to unlock the latch according to the second unlocking pulse signal; the inverter inverts the count end signal output by the count end detection unit to form a count end inverted signal; in the pre-adjustment mode, the external data signal received by the shift register includes pre-adjustment input data, the pre-adjustment input data enters the data stream unit and is processed by the data stream unit to form pre-adjustment data information, and the pre-adjustment input data enters the addressing unit and is processed by the addressing unit to form pre-adjustment address information; the data reading and writing module reads the pre-adjustment data information formed by the data stream unit according to the count end inverted signal; the clock generating module processes the pre-adjustment address information formed by the addressing unit to generate a second internal clock signal; The storage module latches the pre-adjusted data information read by the data reading and writing module according to the second internal clock signal.

6. A programmable fuse trimming circuit as claimed in claim 5, characterized in that: The programming module includes a programming pulse detection unit, a combinational logic unit, a timing logic unit and a programming current generating unit; in the formal trimming mode, the external data signal received by the shift register includes a first trimming input data and a second trimming input data, the first trimming input data enters the data stream unit and is processed by the data stream unit to form a first trimming control signal; the first trimming input data enters the addressing unit and is processed by the addressing unit to form a second trimming control signal; the second trimming input data enters the data stream unit and is processed by the data stream unit to form a third trimming control signal; the second trimming input data enters the addressing unit and is processed by the addressing unit to form a fourth trimming control signal; in the formal trimming mode, the programming pulse detection unit generates a trimming start signal according to the first trimming control signal and the second trimming control signal. The timing logic unit generates a reset signal of the counting end detection unit according to the third trimming control signal and the fourth trimming control signal, and the counting end detection unit starts the counter unit according to the reset signal of the counting end detection unit; in the formal trimming mode, the address information detection module generates a fuse address control signal to the fuse unit module according to the output end signal of the counter unit, and generates fuse address detection information to the combinational logic unit; the combinational logic unit performs logic processing according to the fuse address detection information and the fuse address information to be trimmed stored in the storage module, and outputs a fuse address selection signal; the burn-out current generation unit generates a burn-out current control signal according to the trimming start control signal and the fuse address selection signal; the fuse array circuit performs a fuse blowing operation according to the burn-out current control signal.

7. A programmable fuse trimming circuit as claimed in claim 6, characterized in that: The burn-out current generating unit comprises a fourth AND gate and a seventh NAND gate; the first input end of the fourth AND gate receives the fuse address selection signal; the second input end of the fourth AND gate receives the trimming start control signal; the output end of the fourth AND gate outputs a second burn-out high current control signal; the first input end of the seventh NAND gate receives the trimming start control signal; the second input end of the seventh NAND gate receives the counting end signal output by the counting end detection unit; the output end of the seventh NAND gate outputs a first burn-out high current control signal; the fuse array circuit comprises an eighth NAND gate and a first PMOS tube; the first burn-out high current control signal enters the eighth NAND gate after being inverted at the first input end of the eighth NAND gate; the second burn-out high current control signal enters the second input end of the eighth NAND gate; the output end of the eighth NAND gate outputs a burn-out fuse operation control signal; the gate of the first PMOS tube is connected to the output end of the eighth NAND gate, the source of the first PMOS tube is connected to the power supply voltage, and the drain of the first PMOS tube is connected to the fuse unit module.

8. The programmable fuse trimming circuit as claimed in claim 6, characterized in that: The clock generation module includes a clock generation circuit, a third NAND gate, a fourth NAND gate, a sixth NAND gate and a decoder; the clock generation circuit is connected to the output end signal of the counter unit, and the output end of the clock generation circuit is connected to the second input end of the fourth NAND gate; the first input end of the fourth NAND gate is connected to the counting end signal, and the output end of the fourth NAND gate is connected to the second input end of the sixth NAND gate; the first input end of the third NAND gate is connected to the output end of the decoder, the second input end of the third NAND gate is connected to the counting end inverted signal, and the output end of the third NAND gate is connected to the first input end of the sixth NAND gate; the output end of the sixth NAND gate is connected to the storage module; the input end of the decoder is connected to the addressing unit, and in the pre-adjustment mode, the decoder processes the pre-adjustment address information formed by the addressing unit to form a decoding signal and outputs it to the third NAND gate, and outputs the second internal clock signal to the storage module after passing through the sixth NAND gate.

9. The programmable fuse trimming circuit as claimed in claim 5, characterized in that: The data reading and writing module includes a first NAND gate, a second NAND gate and a fifth NAND gate; the first input end of the first NAND gate is connected to the fuse state output end of the fuse array circuit, the second input end of the first NAND gate is connected to the counting end signal, and the output end of the first NAND gate is connected to the first input end of the fifth NAND gate; the second input end of the second NAND gate is connected to the output end of the inverter, the output end of the second NAND gate is connected to the second input end of the fifth NAND gate, and the output end of the fifth NAND gate is connected to the storage module; the first input end of the second NAND gate is connected to the data stream unit, and in the pre-adjustment mode, the pre-adjustment data information formed by the data stream unit is output to the first input end of the second NAND gate, and is output to the storage module through the output end of the fifth NAND gate.

10. A method for adjusting a programmable fuse, characterized in that: A programmable fuse trimming circuit as described in any one of claims 1 to 9 is used, characterized in that it includes: step A1, power-on initialization of the programmable fuse trimming circuit; step A2, the fuse burning control circuit obtains an external input signal about reading fuse status information through a chip pin, controls entering a fuse status reading mode, and reads fuse status information from the fuse unit module; step A3, the fuse burning control circuit obtains an external input signal about a pre-trim fuse through a chip pin, controls entering a pre-trim mode, performs a parameter test on the chip circuit, and determines a fuse to be trimmed according to the parameter test result; step A4, the fuse burning control circuit obtains an external input signal about a trimming fuse through a chip pin, controls entering a formal trimming mode, and performs a fuse trimming operation on the fuse to be trimmed; step A5, after the fuse trimming operation is completed, the fuse in the end position fuse module is blown.

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