Memory system and memory device with enhanced column repair capability and method of operating same

Abstract

A memory system and memory device having enhanced column repair capability and a method of operating the same are provided. The memory device includes: a memory cell array having a plurality of normal memory cells and a plurality of redundant memory cells; a fuse array storing an address and a master bit of the defective first memory cell; and a column decoder that selects among a plurality of column selection lines associated with the normal memory cells and a plurality of spare column selection lines associated with the redundant memory cells. The column decoder has a first column repair circuit including a first latch array having a plurality of latch elements storing a column address of a defective first memory cell, and a first comparison logic; a first comparison logic compares outputs of the plurality of latch elements to an external column address and generates a first enable signal indicating whether to repair the defective first memory cell in response to the comparison.

Description

[0001] This application claims priority to Korean Patent Application No. 10-2023-0155525, filed on November 10, 2023, the disclosure of which is incorporated herein by reference. Technical Field

[0002] The present disclosure relates to an integrated circuit device, and more particularly, to an integrated circuit memory system and a memory device and a method of operating the same. Background Art

[0003] Memory devices, such as dynamic random access memory (DRAM), are typically configured to have multiple memory banks therein, and each bank includes a large number of memory cells, and each memory cell includes a cell "access" transistor and a cell capacitor (for storing data). During operation, one or more memory cells within a bank may become defective due to various reasons, and such defects may prevent the memory device from functioning properly, thereby reducing the life of the memory device.

[0004] As the level of integration of the memory device increases, the probability that one or more defects within the memory device may occur increases. Treating the entirety of a memory device containing only a small number of defective cells as a defective product and discarding the defective product may be an inefficient processing solution that reduces the overall product yield. Therefore, a solution that increases the product yield by replacing defective cells with independent memory cells disposed within the memory device is commonly used. In other words, in order to solve the situation where the chip does not operate normally when a defect occurs in a memory cell, an additional memory cell is activated and the defective memory cell is repaired (i.e., replaced) by the additional memory cell. As will be understood by those skilled in the art, the additional memory cell is generally referred to as a redundant memory cell; and the circuit involved in the repair operation is generally referred to as a repair circuit.

[0005] The greater the number of redundant memory cells within a memory device, the higher the yield of the memory device or system. However, as the number of redundant memory cells increases, the significant increase in the size of the repair circuit can burden the layout and chip area. Therefore, it would be advantageous to have a repair scheme that improves product yield while minimizing the size of the repair circuit in the memory device. Summary of the invention

[0006] A technical object of the present disclosure is to provide a memory device having improved efficiency and a method for operating the memory device.

[0007] According to some embodiments of the present disclosure, and in order to achieve technical purposes, a memory device is provided, the memory device comprising: a memory cell array, the memory cell array comprising a plurality of normal memory cells and a plurality of redundant memory cells, the plurality of redundant memory cells being used to replace defective memory cells among the plurality of normal memory cells; a fuse array, configured to: store the address and the main bit of the defective first memory cell in the fuse array; and a column decoder, configured to: select a plurality of column selection lines and a plurality of spare column selection lines. The column decoder may include a first column repair circuit, the first column repair circuit having a first latch array and a first comparison logic in the first column repair circuit, the first latch array comprising a plurality of latch elements, the plurality of latch elements being configured to store the column address of the defective first memory cell in the plurality of latch elements, and the first comparison logic being configured to compare the output of the plurality of latch elements with an external column address. The first comparison logic may be configured to generate a first enable signal based on the output of the plurality of latch elements, and the first enable signal may indicate whether to repair the defective first memory cell.

[0008] According to an additional embodiment of the present disclosure, a method for operating a memory device is provided, the method comprising: sending a column address of a defective first memory cell stored in a fuse array to a first latch array of a first column repair circuit; performing a NOR operation on an output of the first latch array, and outputting a first enable signal based on a NOR operation result; comparing the output of the first latch array with an external column address, and outputting a first address match signal based on the comparison result; and performing a NOR operation on the first enable signal and the first address match signal, and outputting a first column repair signal based on the NOR operation result.

[0009] According to a further embodiment of the present disclosure, a memory system is provided, the memory system comprising: a memory controller configured to send an address of each of read data and write data to a memory device; and the memory device is configured to repair a defective normal memory cell using a redundant memory cell. The memory device comprises: a memory cell array comprising a plurality of normal memory cells and a plurality of redundant memory cells, the plurality of redundant memory cells being used to replace defective memory cells among the plurality of normal memory cells; a fuse array configured to store an address and a master bit of a defective first memory cell in the fuse array; an address register configured to receive an address from the memory controller and send an external column address to a column decoder; and a column decoder configured to select a plurality of column selection lines and a plurality of spare column selection lines. The column decoder may include a first column repair circuit, the first column repair circuit comprising: a first latch array, the first latch array comprising a plurality of latch elements, and the latch elements being configured to store the column address of the defective first memory cell in the plurality of latch elements. A first comparison logic may also be provided, the first comparison logic being configured to compare the outputs of the plurality of latch elements with an external column address. The first comparison logic is further configured to generate a first enable signal based on the outputs of the plurality of latch elements, and the first enable signal indicates whether to repair the defective first memory cell. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] The above and other aspects and features of the present disclosure will become more apparent by describing in detail some embodiments of the present disclosure with reference to the accompanying drawings, in which: Figure 1 is a block diagram of a memory device according to some embodiments; Figure 2 yes Figure 1 an enlarged view of a memory cell array in FIG. Figures 3 to 6 is a block diagram for illustrating repair operations according to some embodiments; Figure 7 is a flow chart for illustrating a repair operation according to some embodiments; Figure 8 is a diagram for illustrating the effects of the present disclosure according to some embodiments; Fig. 9 and Fig.10 is a block diagram for illustrating repair operations according to some embodiments; Fig.11 is a diagram for illustrating the effects of the present disclosure according to some embodiments; Fig.12 is a block diagram for illustrating repair operations according to some embodiments; Fig.13 is a diagram for illustrating the effects of the present disclosure according to some embodiments; Fig.14 is a block diagram for illustrating repair operations according to some embodiments; and Fig.15 is a block diagram of a memory system according to some embodiments. DETAILED DESCRIPTION

[0011] The present invention will now be described more fully with reference to the accompanying drawings, in which preferred embodiments of the invention are shown. However, the present invention may be implemented in many different forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey the scope of the invention to those skilled in the art. Like reference numerals represent like elements throughout.

[0012] It will be understood that although the terms first, second, third, etc. can be used to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish an element, component, region, layer or part from another region, layer or part. Therefore, without departing from the teachings of the present invention, the first element, first component, first region, first layer or first part discussed below may be referred to as the second element, second component, second region, second layer or second part.

[0013] The terms used herein are only for the purpose of describing specific embodiments and are not intended to limit the present invention. As used herein, unless the context clearly indicates otherwise, the singular form is intended to also include the plural form. It will also be understood that the terms "comprise", "include", "have" and their variations are used in this specification to indicate the presence of stated features, steps, operations, elements and / or components, but do not exclude the presence or addition of one or more other features, steps, operations, elements, components and / or their combinations. On the contrary, the term "consisting of..." is used in this specification to indicate stated features, steps, operations, elements and / or components, and excludes additional features, steps, operations, elements and / or components.

[0014] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those of ordinary skill in the art to which the present invention belongs. It will also be understood that, unless expressly defined as such herein, terms (such as those defined in general dictionaries) should be interpreted as having a meaning consistent with their meaning in the context of the relevant art, and will not be interpreted in an idealized or overly formal sense.

[0015] Figure 1is a block diagram of a memory device according to some embodiments. Figure 1 The memory device 100 may include a control logic circuit 110, an address register 120, a memory body control logic circuit 130, a row address multiplexer 140, a refresh counter 145, a column address (CA) latch 150, a row decoder (or a memory body row decoder) 160, a fuse array 180, a column decoder 200, a memory cell array 300, a sense amplifier 192, an input / output (I / O) selection circuit 190, an ECC engine 191, a data input / output buffer 195, etc.

[0016] The memory cell array 300 may include a plurality of memory array banks. The row decoder 160, the column decoder 200, and the sense amplifier 192 may be connected to the memory array banks. As will be appreciated by those skilled in the art, the memory cell array 300 may include a plurality of word lines, a plurality of bit lines, and a plurality of memory cells (MCs) respectively disposed at points where the word lines and the bit lines intersect each other.

[0017] The control logic circuit 110 may receive a command CMD from an external source and control various components within the memory device 100. The address register 120 may receive an address ADDR from an external source. The address ADDR may include a bank address BANK_ADDR, a row address ROW_ADDR, and a column address COL_ADDR. The address register 120 may provide the bank address BANK_ADDR to the bank control logic circuit 130. The address register 120 may provide the row address ROW_ADDR to the row address multiplexer 140. The address register 120 may provide the column address COL_ADDR to the column address latch 150.

[0018] The bank control logic circuit 130 may generate a bank control signal in response to the bank address BANK_ADDR. The bank row decoder 160 may be activated in response to the bank control signal. In addition, the column decoder 200 may be activated in response to the bank control signal corresponding to the bank address BANK_ADDR.

[0019] The row address multiplexer 140 may receive the row address ROW_ADDR from the address register 120 and the refresh row address REF_ADDR from the refresh counter 145. The row address multiplexer 140 may select the row address ROW_ADDR or the refresh row address REF_ADDR and output the selected one as the row address RA. The row address RA may be sent to the row decoder 160. The refresh counter 145 may sequentially output the refresh row address REF_ADDR under the control of the control logic circuit 110.

[0020] The row decoder 160 activated by the bank control logic circuit 130 may decode the row address RA output from the row address multiplexer 140 and activate a word line corresponding to the row address RA. For example, the row decoder 160 may apply a word line driving voltage to the word line corresponding to the row address RA.

[0021] The column address latch 150 may receive the column address COL_ADDR from the address register 120 and temporarily store the received column address COL_ADDR in the column address latch 150. The column address latch 150 may gradually increase the received column address COL_ADDR in a burst mode. The column address latch 150 may provide the temporarily stored column address COL_ADDR or the gradually increased column address COL_ADDR to the column decoder 200.

[0022] The fuse array 180 may store the addresses of defective memory cells found in a wafer test or a package test process in the fuse array 180. Specifically, in the wafer test or the package test process, whether each of all memory cells operates normally may be determined, and the addresses of the detected defective memory cells may be stored in the fuse array 180. The fuse array 180 may include a plurality of fuse elements. Each of the plurality of fuse elements may be a nonvolatile memory in which data may be stored even when power supply thereto is cut off.

[0023] Each of the plurality of fuse elements of the fuse array 180 may be implemented with each of various nonvolatile memories (such as an electrically programmable fuse, a laser programmable fuse, an antifuse, a flash memory, etc.). The laser programmable fuse may be manufactured in a short-circuit state relative to an external circuit, and may be brought into an open state relative to the external circuit by a laser to store the address of a defective memory cell in the fuse array 180. The antifuse may be manufactured in an open state relative to an external circuit, and may be brought into a short-circuit state relative to the external circuit via the fusing of the antifuse (application of a high voltage to the antifuse) to store the address of a defective memory cell in the antifuse. The fuse array 180 may send the column address information of the defective memory cell to the column decoder 200 when the memory device 100 is in operation, and may send the row address information of the defective memory cell to the row decoder 160.

[0024] Among the column decoders 200, the column decoders 200 activated by the bank control logic circuit 130 may activate the sense amplifiers 192 corresponding to the column address COL_ADDR and the bank address BANK_ADDR via the corresponding input / output gating circuit 190 to select the column selection line CSL corresponding to the column address COL_ADDR and select the bit lines BL1 to BLk corresponding to the selected column selection line CSL. The column decoder 200 described below represents the column decoder 200 activated by the bank control logic circuit 130. The input / output gating circuit 190 may include a circuit for gating input / output data, an input data mask logic, a read data latch for storing data output from the memory cell array 300 therein, and a write driver for writing data into the memory cell array 300.

[0025] The codeword CW read out from the bank memory array of the memory cell array 300 may be sensed by the sense amplifier 192 corresponding to the bank memory array. In addition, the codeword CW may be stored in the read data latch. The ECC engine 191 may perform ECC decoding on the codeword CW stored in the read data latch. The data DQ obtained by performing ECC decoding on the codeword CW may be provided to an external component through the data input / output buffer 195.

[0026] The data input / output buffer 195 may provide data DQ to the ECC engine 191 based on the clock signal CLK in a write operation. The data input / output buffer 195 may provide data DQ provided from the ECC engine 191 to an external component based on the clock signal CLK in a read operation. The memory cell array 300 may be connected to the sense amplifier 192. Each of the row decoder 160 and the column decoder 200 may be connected to the memory cell array 300 and the sense amplifier 192.

[0027] Figure 2 yes Figure 1 An enlarged view of an embodiment of a memory cell array in FIG. Figure 2, the normal memory cell area may be connected to a plurality of word lines WL1 to WLl and a plurality of bit lines BL1 to BLk. The redundant memory cell area may be connected to a plurality of word lines WL1 to WLl and a plurality of spare bit lines SBL1 to SBLy. For example, a plurality of redundant memory cells (SMCs) may be arranged at points where a plurality of word lines WL1 to WLl and a plurality of spare bit lines SBL1 to SBLy intersect with each other. In this regard, each of l, k, and y may be a positive integer and may be determined based on the characteristics of the memory device (e.g., capacitance, area, etc. of the bit line), the specifications of the memory device, etc., and "y" represents the total number of spare bit lines. As will be appreciated by those skilled in the art, as the value of y increases, the yield of the memory device may be improved, but the layout area of ​​the memory device may increase.

[0028] Figure 3 is a block diagram for illustrating a repair operation according to some embodiments. Figure 3 , the column decoder 200 may receive an external column address from the column address latch 150. Specifically, the column decoder 200 may include a plurality of column repair circuits, and each of the plurality of column repair circuits may receive an external column address CA<9:4> including, for example, 6 bits from the column address latch 150. Figure 3 Two column repair circuits are shown, but this is merely one example of at least one column repair circuit.

[0029] In one example, the column decoder 200 may select among a plurality of column selection lines associated with normal memory cells and a plurality of spare column selection lines associated with redundant memory cells. The column decoder 200 may select a plurality of bit lines BL0 to BLk by selecting a plurality of column selection lines CSL0 to CSLk. The column decoder may select a plurality of spare bit lines SBL0 to SBLy by selecting a plurality of spare column selection lines SCSL0 to SCSLy. The column decoder 200 may receive a column address of a defective memory cell from the fuse array 180.

[0030] Figure 4 is a block diagram for illustrating a repair operation according to some embodiments. Figure 4 , showing two spare column selection lines (SCSL0 and SCSL1) and 64 column selection lines (CSL0 to CSL63). Each of the two spare column selection lines and the 64 column selection lines may be divided into segments SEG 0 to SEG X (X is a positive integer). The column selection lines may be repaired based on segments. The segment-based column repair method will be described in detail below.

[0031] Figure 5 and Figure 6 is a block diagram for illustrating a repair operation according to some embodiments. Figure 5 and Figure 6, the column decoder 200 may include a plurality of column repair circuits (CRC). Figure 5 The first column repair circuit 200a is shown. The first column repair circuit 200a may include a first latch array 210a and a first comparison logic 220a. The first latch array 210a may include a plurality of latch groups 210a_0 to 210a_x corresponding to the segments, respectively. Therefore, the number of latch groups 210a_0 to 210a_x may be equal to the number of segments. The first latch array 210a may receive a column address of a defective memory cell from the fuse array 180. Specifically, referring to Figure 6 , the latch group 210a_0 corresponding to the segment 0 of each of the plurality of column selection lines may receive the column address of the defective memory cell in the segment 0 of each of the plurality of column selection lines from the fuse array 180. For example, the fuse array 180 may store the column address and the master bit of the defective memory cell.

[0032] Each of the plurality of latch groups 210a_0 to 210a_x of the first latch array 210a may include a plurality of latch elements L1 to L6. Each of the plurality of latch elements may be implemented as a volatile memory cell such as an SRAM (static random access memory). However, the embodiment is not limited thereto, and each of the plurality of latch elements may have a memory type different from the volatile memory cell such as an SRAM (static random access memory). When receiving a column address of a defective memory cell from the fuse array 180, each of the plurality of latch elements may receive the column address of the defective memory cell one bit at a time and latch the received column address. Figure 5 Six latch elements are shown. However, the number of latch elements is not limited thereto, and the number of latch elements may be less than or greater than six.

[0033] The first comparison logic 220a may receive a column address of a defective memory cell from each of the plurality of latch groups of the first latch array 210a, and output a first enable signal and a first address match signal based on the received column address. For example, the first comparison logic 220a may receive a column address of a defective memory cell stored in each of the plurality of latch elements from each of the plurality of latch groups 210a_0 to 210a_x, and compare the received column address with an external column address at a rate corresponding to one bit at a time, and may output a first address match signal based on the comparison result. For example, the first comparison logic 220a may perform an XNOR operation on the received column address of the defective memory cell and an external column address (e.g., CA<9:4>) (e.g., through a plurality of XNOR gates), may perform a NAND operation on all of the XNOR operation results, and may output a first address match signal based on the NAND operation result. In one example, the first comparison logic 220a may generate a first enable signal in response to a comparison of a column address of a defective memory cell with an external column address. In one example, the first comparison logic 220a may generate a first enable signal based on an output of each of a plurality of latch groups 210a_0 to 210a_x. The first comparison logic 220a may receive a column address of a defective memory cell from each of a plurality of latch groups 210a_0 to 210a_x, and may perform a NOR operation on all of the received bits (e.g., through a NOR gate), and may output a first enable signal based on a NOR operation result. The first comparison logic 220a may perform a NOR operation on the first address match signal and the first enable signal, and may output a first column repair signal based on the NOR operation result.

[0034] Figure 7 1 is a flowchart for illustrating a repair operation according to some embodiments. In operation S101, when the memory device starts operating, a repair operation of a defective memory cell starts. As described above, the column decoder 200 receives an external column address from the column address latch 150 in operation S102, and receives a column address of a defective memory cell from the fuse array 180 in operation S103.

[0035] In operation S104, a NOR operation is performed on the output of each latch array, and an enable signal is output based on the NOR operation result. In one example, the enable signal indicates whether to repair a defective memory cell. Therefore, as an example, if the output of the latch array is "000000", "H" may be output based on the NOR operation result of the output of the latch array. However, if "1" exists in at least one bit of the output of the latch array, "L" may be output based on the NOR operation result of the output of the latch array.

[0036] In operation S105, the external column address is compared with the column address of the defective memory cell, and an address match signal is output based on the comparison result. For example, in response thereto, based on the comparison result between the output of the latch array and the external column address (which can be done bit by bit), a match between the output of the latch array and each of the bits of the external column address may produce an "L" output; however, a mismatch between one or more bits may produce an "H" output. This can be obtained by performing a NAND operation on all outputs of the XNOR gate.

[0037] In operation S106, the column repair signal is output as a result of a NOR operation on the enable signal and the address match signal. For example, if there is a "1" in at least one bit in the output of the latch array and the output of the latch array matches the external column address, the enable signal is "L" and the address match signal is "L". Therefore, based on the result of the NOR operation on the enable signal and the address match signal, the column repair signal may be output as "H". If the output of the latch array is "000000", or if the output of the latch array does not match the external column address, the column repair signal may be output as "L".

[0038] If the column repair signal is "H", the column repair circuit may transmit a column selection line disable signal and a spare column selection line enable signal corresponding to the column address to the column decoder 200. As a result, in operation S107, the column decoder 200 selects the spare column selection line. On the contrary, if the column repair signal is "L", the column repair circuit may transmit a column selection line enable signal and a spare column selection line disable signal corresponding to the external column address to the column decoder 200. As a result, in operation S108, the column decoder 200 selects the column selection line corresponding to the external column address.

[0039] The repair operation may be repeatedly performed a number of times corresponding to the number of divided segments. Specifically, when the repair operation corresponding to segment SEG 0 has been completed, the repair operation corresponding to segment SEG 1 may start to be performed. After the repair operation has been repeated a number of times corresponding to the number of divided segments, the repair operation may be completely terminated.

[0040] Figure 8is a diagram for illustrating the effect of the present disclosure according to some embodiments, wherein any column repair circuit may include a latch array and comparison logic, and the latch array may include a plurality of latch groups; each latch group may include a plurality of latch elements storing a column address therein and a master latch element determining whether to perform a repair operation. The master latch element may receive a master bit determining whether to perform a repair operation as an input, latch the master bit, and output an enable signal based on the master bit. For example, if a memory cell corresponding to CSL (column select line) 0 in segment SEG 0 of a memory cell of the memory cell array 300 is defective, a master bit "0" indicating that a repair operation is performed and a column address "000001" of CSL1 may be stored in a latch group corresponding to segment SEG 1 in the latch array.

[0041] When any column repair circuit performs a repair operation on any segment, there may be no defective memory cells in the segment, or the column addresses of all defective memory cells in the segment may be stored in the latch array of another column repair circuit. In this case, the latch group corresponding to the segment may store and latch a default value. For example, if the default value is "000000", the latch group may latch and output "000000" as the default value. In this case, the column repair circuit does not need to perform a repair operation. However, if the column repair circuit determines that a memory cell with a column address of "000000" among the memory cells is defective, the column repair circuit may perform a repair operation when "000000" as an external column address is input into the column repair circuit. Therefore, if the default value "000000" is input into the relevant latch group, the main bit of "H" together with the default value "000000" may be input into the relevant latch group, so that the column repair circuit does not operate, thereby preventing the failure of the memory device.

[0042] In the above embodiments, each of the plurality of latch groups also includes a main latch element that can further increase the layout area occupied by the latch element. As previously described, each of the plurality of latch elements can be implemented as a volatile memory element (such as, SRAM (static random access memory)). SRAM has an access speed that is at least 100 times greater than that of DRAM (dynamic random access memory). However, because SRAM has a relatively complex structure and occupies a large amount of layout space, it may be difficult to improve its integration level. In other words, the main latch element included in the plurality of latch groups can occupy a large amount of space within the chip.

[0043] In some embodiments of the present disclosure, the master latch element may not exist, and the output of the latch element in which the column address of the defective memory cell is stored may be NOR-operated, and an enable signal may be output based on the NOR operation result without the need for the master latch element. In this case, the master bit of the defective memory cell stored in the fuse array 180 may not be sent to the multiple latch elements of the first latch array 210a. Because the master latch element does not exist, the space occupied by the multiple latches may be reduced, and the reduction may advantageously reduce the overall size of the memory device. This reduction in size may mean that the number of chips that can be manufactured per wafer may be increased, thereby increasing the wafer yield.

[0044] In some embodiments of the present disclosure, the master latch element does not exist. Therefore, if the column address of the defective memory cell is "000000", a NOR operation may be performed on the output from the latch element, and thus "H" is output as the NOR operation result. Therefore, the corresponding memory cell cannot be repaired.

[0045] Fig. 9 and Fig.10 is a block diagram for illustrating a repair operation according to some embodiments. Fig. 9 and Fig.10 , a second column repair circuit (200b) is shown. The second column repair circuit 200b may include a second latch array 210b and a second comparison logic 220b. The second latch array may include a plurality of latch groups 210b_0 to 210b_x corresponding to the segments. The number of the plurality of latch groups 210b_0 to 210b_x is equal to the number of segments. The second latch array 210b may receive a column address of a defective memory cell from the fuse array 180. Each of the plurality of latch groups 210b_0 to 210b_x of the second latch array 210b may include a plurality of latch elements L1 to L6.

[0046] Different from Figure 5 In the first column repair circuit 200a shown in FIG. 1 , the latch element L6 receiving the most significant bit among the plurality of latch elements of each of the plurality of latch groups 210b_0 to 210b_x may invert the input of the latch element L6 and latch the inverted input. For example, when receiving "101010" as the column address of the defective memory cell from the fuse array 180, the latch group may latch "001010". Fig. 9 and Fig.10 , it is shown that only the latch element L6 receives the most significant bit, and the input of the latch element L6 is inverted and latched. However, the embodiment is not limited thereto, and each other latch element may also invert the input of each other latch element and latch the inverted input.

[0047] The second comparison logic 220b may receive the column address of the defective memory cell from each of the plurality of latch groups of the second latch array 210b and output the second enable signal and the second address match signal. For example, the second comparison logic 220b may receive the column address of the defective memory cell stored in each of the plurality of latch elements of each of the plurality of latch groups 210b_0 to 210b_x from each of the plurality of latch elements of each of the plurality of latch groups 210b_0 to 210b_x, and may compare the received column address with the external column address one bit at a time, and may output the second address match signal based on the comparison result.

[0048] In this respect, unlike Figure 5 and Figure 6 , since the latch element L6 has received the most significant bit of the column address of the defective memory cell as its input and has inverted the input and latched the inverted input, the second comparison logic 220b should invert the output of the latch element L6 for address comparison.

[0049] The second comparison logic 220b may receive a column address of a defective memory cell from each of the latch groups 210b_0 to 210b_x of the second latch array 210b, may perform a NOR operation on all of the received bits, and may output a second enable signal based on the NOR operation result. The second comparison logic 220b may perform a NOR operation on the second address match signal and the second enable signal, and may output a second column repair signal based on the NOR operation result.

[0050] Fig.11 is a diagram for illustrating the effects of the present disclosure according to some embodiments. As previously described, in some embodiments of the present disclosure, the master latch element may not exist, and the enable signal may be output without the master latch element. Because the master latch element does not exist, the space occupied by multiple latches can be reduced, ultimately reducing the size of the memory device. Therefore, the number of chips that can be manufactured per wafer can be increased, and therefore the yield can be improved.

[0051] In some embodiments of the present disclosure, at least one of the plurality of latch elements included in each of the plurality of latch groups 210b_0 to 210b_x may be configured to invert its input and latch the inverted input. For example, latch element L6 receives the most significant bit of the column address of the defective memory cell, inverts the input of latch element L6 and latches the inverted input in latch element L6. In one example, when the column address "000000" of the defective memory cell is received from the fuse array 180, the latch group may latch "100000". A NOR operation may be performed on "100000", and therefore, an enable signal of "L" may be output based on the NOR operation result. Therefore, unlike some further embodiments as disclosed in the present disclosure, the memory cell may be repaired even if the column address of the defective memory cell is "000000".

[0052] However, when the column address "100000" of the defective memory cell is received from the fuse array 180, the latch group may latch "000000". A NOR operation may be performed on "000000", and thus, an enable signal of "H" may be output based on the NOR operation result. Therefore, unlike some further embodiments as disclosed in the present disclosure, when the column address of the defective memory cell is "100000", the memory cell cannot be repaired.

[0053] Generally, it is known that the probability of a defect occurring in a memory cell in an outermost bit line or word line is higher than the probability of a defect occurring in a memory cell in a non-outermost bit line or word line (i.e., a more inner non-peripheral line). In other words, the probability of a defect occurring in a memory cell having a column address of “000000” may be higher than the probability of a defect occurring in a memory cell having a column address different from the column address of “000000”. In other words, the probability of a defect occurring in a memory cell having a column address of “100000” may be relatively lower than the probability of a defect occurring in a memory cell having a column address of “000000”. As Fig. 9 and Fig.10 The column repair circuit according to some embodiments shown in cannot repair a memory cell having a column address of "100000", but can repair a memory cell having a column address of "000000". In other words, a memory cell having a higher probability of defect occurrence can be repaired. Therefore, the yield of the memory device can be improved, and its productivity can be further improved.

[0054] Fig.12 is a block diagram for illustrating a repair operation according to some embodiments, Fig.12A third column repair circuit 200c and a fourth column repair circuit 200d are shown. In one example, the third column repair circuit 200c and the fourth column repair circuit 200d are different from each other. These third column repair circuits 200c and the fourth column repair circuits 200d may include a third latch array 210c and a fourth latch array 210d and a third comparison logic 220c and a fourth comparison logic 220d, respectively. The third latch array 210c and the fourth latch array 210d may include a plurality of latch groups 210c_0 to 210c_x and a plurality of latch groups 210d_0 to 210d_x, respectively. The plurality of latch groups 210c_0 to 210c_x correspond to the segments, and the number of the plurality of latch groups 210c_0 to 210c_x is equal to the number of segments. The plurality of latch groups 210d_0 to 210d_x correspond to the segments, and the number of the plurality of latch groups 210d_0 to 210d_x is equal to the number of segments. Each of the third latch array 210c and the fourth latch array 210d may receive a column address of a defective memory cell from the fuse array 180. For example, the master bit of the defective memory cell stored in the fuse array 180 may not be sent to the plurality of latch elements of each of the third latch array 210c and the fourth latch array 210d.

[0055] For example, in the third column repair circuit 200c, the latch group 210c_0 corresponding to the segment 0 of each of the plurality of column selection lines may receive the column address of the defective memory cell in the segment 0 of each of the plurality of column selection lines from the fuse array 180. Each of the plurality of latch groups 210c_0 to 210c_x of the third latch array 210c may include a plurality of latch elements L1 to L6. Each of the plurality of latch groups 210d_0 to 210d_x of the fourth latch array 210d may include a plurality of latch elements L1 to L6. Each of the plurality of latch groups 210c_0 to 210c_x of the third latch array 210c may receive the column address of the defective memory cell received from the fuse array 180 as its input, and may latch the received column address. Each of the plurality of latch groups 210d_0 to 210d_x of the fourth latch array 210d may include a plurality of latch elements. Unlike the third latch array, at least one of the plurality of latch elements of each of the plurality of latch groups of the fourth latch array may invert its input and latch the inverted input. In other words, each of the plurality of latch groups of the fourth latch array 210d may receive a column address of a defective memory cell, invert at least one bit of the column address, and latch the column address having at least one bit after inversion.

[0056] In one example, the third comparison logic 220c may generate a third enable signal based on the output of each of the plurality of latch groups 210c_0 to 210c_x of the third latch array 210c. In one example, the fourth comparison logic 220d may generate a fourth enable signal based on the output of each of the plurality of latch groups 210d_0 to 210d_x of the fourth latch array 210d. The third comparison logic 220c may receive the output of each of the plurality of latch groups 210c_0 to 210c_x of the third latch array 210c, and may perform a NOR operation on the output, and may output the third enable signal based on the NOR operation result. The fourth comparison logic 220d may receive the output of each of the plurality of latch groups 210d_0 to 210d_x of the fourth latch array 210d, and may perform a NOR operation on the output, and may output the fourth enable signal based on the NOR operation result. The third comparison logic 220c may receive the output in a non-inverting state of each of the plurality of latch groups 210c_0 to 210c_x of the third latch array 210c as input thereof, compare the output with an external column address, and output a third address match signal based on the comparison result.

[0057] The fourth comparison logic 220d may receive as its input the output of each of the plurality of latch groups 210d_0 to 210d_x of the fourth latch array 210d in which at least one bit of the column address is inverted by at least one latch element, and may invert the output of at least one latch element included in its input. Then, the fourth comparison logic 220d may compare the input including the inverted output of at least one latch element with the external column address, and may output a fourth address match signal based on the comparison result.

[0058] Fig.13 is a diagram for illustrating the effects of the present disclosure according to some embodiments. Here, the third column repair circuit 200c and the fourth column repair circuit 200d may operate in a complementary manner to each other. As previously described, Figure 8 As shown in FIG. 2 , if the column address of the defective memory cell is “000000”, the third column repair circuit 200 c cannot repair the defective memory cell. Figure 8 As shown in FIG. 2 , if the column address of the defective memory cell is “100000”, the third column repair circuit 200 c may be able to repair the defective memory cell.

[0059] like Fig.11 As shown in FIG. 2 , if the column address of the defective memory cell is “000000”, the fourth column repair circuit 200 d may be able to repair the defective memory cell. Fig.11As shown in , if the column address of the defective memory cell is "100000", the fourth column repair circuit 200d cannot repair the defective memory cell. When the address of the defective memory cell found in the wafer test or package test process is stored in the fuse array 180, the address of the defective memory cell may be stored in the fuse array 180 so that the third column repair circuit 200c and the fourth column repair circuit 200d operate in a complementary manner to each other. For example, Fig.13 As shown in , it may be assumed that a defect is detected at CSL 0 in segment SEG 1, and a defect is detected at CSL 32 in segment SEG 2. During a wafer test or package test process, a column address “000000” corresponding to CSL 0 and a column address “100000” corresponding to CSL 32 may be stored in fuse array 180 along with segment information.

[0060] The second latch group 210d_1 of the fourth latch array 210d corresponding to the segment SEG 1 may receive “000000” from the fuse array 180, and may invert the most significant bit of “000000”, and thus output “100000” in an inverted state. The third latch group 210c_2 of the third latch array 210c corresponding to the segment SEG 2 may receive “100000” from the fuse array 180.

[0061] The third column repair circuit 200c and the fourth column repair circuit 200d operate in a complementary manner to each other. Therefore, the third column repair circuit 200c can repair a defective memory cell having a column address "100000" that the fourth column repair circuit 200d cannot repair. The fourth column repair circuit 200d can repair a defective memory cell having a column address "000000" that the third column repair circuit 200c cannot repair. In other words, the third column repair circuit 200c and the fourth column repair circuit 200d can operate in a complementary manner to each other to repair defective memory cells of all column addresses.

[0062] Fig.14 is a block diagram for illustrating a repair operation according to some embodiments. Specifically, Fig.14The fifth column repair circuit 200e and the sixth column repair circuit 200f are shown. In one example, the fifth column repair circuit 200e and the sixth column repair circuit 200f are different from each other. The fifth column repair circuit 200e and the sixth column repair circuit 200f may include a fifth latch array 210e and a sixth latch array 210f and a fifth comparison logic 220e and a sixth comparison logic 220f, respectively. The fifth latch array 210e and the sixth latch array 210f may include a plurality of latch groups 210e_0 to 210e_x and a plurality of latch groups 210f_0 to 210f_x, respectively. The plurality of latch groups 210e_0 to 210e_x correspond to the segments, and the number of the plurality of latch groups 210e_0 to 210e_x is equal to the number of segments. The plurality of latch groups 210f_0 to 210f_x correspond to the segments, and the number of the plurality of latch groups 210f_0 to 210f_x is equal to the number of segments. Each of the fifth latch array 210e and the sixth latch array 210f may receive a column address of a defective memory cell from the fuse array 180 .

[0063] Each of the plurality of latch groups 210f_0 to 210f_x of the sixth latch array 210f may include a plurality of latch elements L1 to L6. Unlike each of the plurality of latch groups 210f_0 to 210f_x of the sixth latch array 210f, each of the plurality of latch groups 210e_0 to 210e_x of the fifth latch array 210e may include not only a plurality of latch elements L1 to L6 but also a master latch (MST L) element.

[0064] Each of the plurality of latch groups 210e_0 to 210e_x of the fifth latch array 210e may receive not only the column address of the defective memory cell from the fuse array 180, but may also receive a master bit for determining whether to perform a repair operation from the fuse array 180. The master latch element of each of the plurality of latch groups 210e_0 to 210e_x of the fifth latch array 210e may receive the master bit as its input and latch the master bit. The remaining latch elements other than the master latch element of each of the plurality of latch groups 210e_0 to 210e_x of the fifth latch array 210e may receive the column address of the defective memory cell and may latch the column address.

[0065] Different from the fifth latch array 210e, each of the plurality of latch groups 210f_0 to 210f_x of the sixth latch array 210f may include a plurality of latch elements other than the main latch element. Different from the fifth latch array 210e, at least one of the plurality of latch elements of each of the plurality of latch groups of the sixth latch array 210f may invert the input and latch the inverted input. In other words, each of the plurality of latch groups 210f_0 to 210f_x of the sixth latch array 210f may invert at least one bit of the column address of the defective memory cell as its input and latch the input including at least one bit after inversion. The output of the main latch element among the plurality of latch elements included in each of the plurality of latch groups 210e_0 to 210e_x of the fifth latch array 210e may be the fifth enable signal. For example, the primary bit of a defective memory cell stored in the fuse array 180 may not be sent to the plurality of latch elements of the sixth latch array 210f.

[0066] The sixth comparison logic 220f may receive the output of each of the plurality of latch groups 210f_0 to 210f_x of the sixth latch array 210f as its input, may perform a NOR operation on the input, and may output a sixth enable signal based on the NOR operation result. The fifth comparison logic 220e may receive the output of each of the latch elements other than the main latch element of each of the plurality of latch groups 210e_0 to 210e_x of the fifth latch array 210e as its input, may compare the received output with the external column address, and may output a fifth address match signal based on the comparison result. The sixth comparison logic 220f can receive as its input the output of each of the multiple latch groups 210f_0 to 210f_x of the sixth latch array 210f in which at least one bit of the column address is inverted by at least one latch element, and can invert the output of at least one latch element included in its input, and can compare the input including the inversion result with the external column address, and can output a sixth address match signal based on the comparison result.

[0067] In the operation of the memory device according to some embodiments, there may be an error in the output of each of the multiple latch elements of any latch array. For example, the latch array may receive a default value of "000000" from the fuse array 180. However, an error occurs in the latch array that has received the default value, so that the latch array may output "001000". The cause of the error may be, for example, a defect in at least one fuse element in the fuse array. In addition, noise may occur when sending an address from the fuse array, resulting in an incorrect address being sent. When the external column address matches the output of the latch array, the non-defective memory cell can be repaired. Therefore, the memory device may fail.

[0068] like Fig.14 As shown in , each of the plurality of latch groups 210e_0 to 210e_x included in the fifth latch array 210e of the fifth column repair circuit 200e may also include a master latch element. Therefore, an error occurs in the output of the fifth latch array 210e, so that the fifth latch array 210e outputs "001000". However, in this case, the fifth column repair circuit 200e may not perform a repair operation. The column decoder 200 may include a sixth column repair circuit 200f that operates in a complementary manner to the fifth column repair circuit 200e. Therefore, although the space occupied by the repair circuit within the chip increases, a memory device with increased stability may be provided.

[0069] Fig.15 1 is a block diagram of a memory system according to some embodiments, and the memory system according to some embodiments may include a memory controller 10 and at least one memory device 100. The memory device 100 may be the memory device 100 according to some embodiments of the present disclosure. The memory controller 10 may generally control the operation of the memory device 100. For example, the memory controller 10 may control data exchange between the host 20 and the memory device 100. For example, the memory controller 10 may control the memory device 100 in response to a request from the host 20 so that data DQ may be written to the memory device or data DQ may be read from the memory device.

[0070] The host 20 may communicate with the memory system using an interface protocol such as Peripheral Component Interconnect Express (PCI-E), Advanced Technology Attachment (ATA), Serial ATA (SATA), Parallel ATA (PATA), Serial Attached SCSI (SAS), or Compute Express Link (CXL). In addition, the interface protocol between the host 20 and the memory system 1 is not limited to the examples described above, and may be one of other interface protocols such as USB (Universal Serial Bus), MMC (Multimedia Card), ESDI (Enhanced Small Disk Interface), or IDE (Integrated Drive Electronics).

[0071] The memory controller 10 and the memory device 100 may communicate with each other through a memory interface MEM I / F. The memory controller 10 may apply a command CMD for controlling the memory device 100 to the memory device 100 to control the operation of the memory device 100. In this regard, the memory device 100 may include a dynamic memory unit. For example, the memory device 100 may include a dynamic random access memory (DRAM), a double data rate 4 (DDR4) synchronous DRAM (SDRAM), a low power DDR4 (LPDDR4) SDRAM, or a low power DDR5 (LPDDR5) SDRAM. However, the embodiments according to the technical concept of the present disclosure are not limited thereto, and the memory device 100 may include a non-volatile memory device. However, in the present embodiment, an example in which the memory device 100 is implemented as a volatile memory device is described.

[0072] The memory controller 10 may send a clock signal CLK and a command CMD to the memory device 100. The memory controller 10 may provide data DQ to the memory device 100 and may receive the data DQ from the memory device 100. The memory controller 10 may provide an address ADDR of the data DQ to the memory device 100 so as to write data to the memory device 100 or read data from the memory device 100. The memory device 100 may include a control logic circuit 110, an address register 120 receiving the address ADDR, a data input / output buffer 195, a memory cell array 300 storing the data DQ therein, a column decoder 200, a row decoder 160, and the like.

[0073] Although the embodiments of the present disclosure have been described with reference to the accompanying drawings, the embodiments of the present disclosure are not limited to the above embodiments, but can be implemented in various different forms. It is understood by those skilled in the art that the present disclosure can be practiced in other specific forms without changing the technical spirit or essential features of the present disclosure. Therefore, it should be understood that the embodiments described above are not restrictive in all aspects, but illustrative.

Claims

1. A memory device, comprising: a memory cell array having a plurality of normal memory cells and a plurality of redundant memory cells in the memory cell array; a fuse array configured to: store the address and the primary bit of the defective first memory cell in the fuse array; as well as A column decoder configured to select among a plurality of column selection lines associated with normal memory cells and a plurality of spare column selection lines associated with redundant memory cells, the column decoder comprising: A first column repair circuit includes a first latch array and a first comparison logic, the first latch array having a plurality of first latch elements in the first latch array, the plurality of first latch elements being configured to store column addresses of defective first memory cells, the first comparison logic being configured to compare outputs of the plurality of first latch elements with an external column address, and generating a first enable signal indicating whether to repair the defective first memory cells in response to the comparison.

2. The memory device according to claim 1, wherein: The first comparison logic is configured to generate a first enable signal by performing a NOR operation on outputs of the plurality of first latch elements.

3. The memory device according to claim 1, wherein: The first comparison logic includes: a plurality of XNOR gates configured to: perform an XNOR operation on the outputs of the plurality of first latch elements of the first latch array and bits of an external column address; and The NOR gate is configured to perform a NOR operation on the outputs of the plurality of first latch elements.

4. The memory device according to claim 1, wherein: The master bit stored in the fuse array is not sent to the plurality of first latch elements of the first latch array.

5. The memory device according to claim 1, wherein: At least one of the plurality of first latch elements of the first latch array is configured to invert an input of the at least one of the plurality of first latch elements of the first latch array and output the inverted input.

6. The memory device according to claim 1, wherein: Each of the plurality of column selection lines and the plurality of spare column selection lines is divided into a plurality of segments; wherein the first latch array comprises a plurality of latch groups, and the number of the plurality of latch groups is equal to the number of the plurality of segments; and wherein each of the plurality of latch groups comprises the plurality of first latch elements.

7. The memory device according to claim 1, in, The fuse array is further configured to: store the address and the primary bit of the defective second memory cell in the fuse array; wherein the column decoder further comprises a second column repair circuit, the second column repair circuit comprises a second latch array and a second comparison logic, the second latch array comprises a plurality of second latch elements, the plurality of second latch elements are configured to store column addresses of defective second memory cells in the plurality of second latch elements, and the second comparison logic is configured to compare outputs of the plurality of second latch elements of the second latch array with an external column address; wherein the first column repair circuit and the second column repair circuit are different from each other; wherein the second comparison logic is configured to: generate a second enable signal based on outputs of the plurality of second latch elements of the second latch array; and The second enabling signal indicates whether to repair the defective second memory cell.

8. The memory device according to claim 7, wherein: The first comparison logic is configured to generate a first enable signal by performing an OR operation on the outputs of the plurality of first latch elements of the first latch array; and wherein the second comparison logic is configured to generate a second enable signal by performing an OR operation on the outputs of the plurality of second latch elements of the second latch array.

9. The memory device according to claim 7, wherein: The master bit of a defective first memory cell stored in the fuse array is not sent to the plurality of first latch elements of the first latch array; and wherein the master bit of a defective second memory cell stored in the fuse array is not sent to the plurality of second latch elements of the second latch array.

10. The memory device according to claim 7, wherein: Each of the plurality of column selection lines and the plurality of spare column selection lines is divided into a plurality of segments; wherein the first latch array includes a plurality of first latch groups, the second latch array includes a plurality of second latch groups, and the number of the plurality of first latch groups and the number of the plurality of second latch groups are each equal to the number of the plurality of segments; and wherein each of the plurality of first latch groups includes the plurality of first latch elements, and each of the plurality of second latch groups includes the plurality of second latch elements.

11. The memory device according to claim 7, wherein: The first comparison logic includes: a plurality of first XNOR gates configured to perform an XNOR operation on the outputs of the plurality of first latch elements of the first latch array and bits of an external column address; and a first NOR gate configured to perform a NOR operation on outputs of the plurality of first latch elements of the first latch array, and Wherein, the second comparison logic includes: a plurality of second XNOR gates configured to: perform an XNOR operation on the outputs of the plurality of second latch elements of the second latch array and the bits of the external column address; and The second NOR gate is configured to perform a NOR operation on the outputs of the plurality of second latch elements of the second latch array.

12. The memory device according to claim 7, wherein: At least one of the plurality of first latch elements of the first latch array is configured to invert an input of the at least one of the plurality of first latch elements of the first latch array and output the inverted input.

13. The memory device according to claim 1, in, The fuse array is configured to: also store the address and the primary bit of the defective second memory cell in the fuse array; wherein the column decoder further comprises a second column repair circuit, the second column repair circuit comprises a second latch array, a master latch element and a second comparison logic, the second latch array comprises a plurality of second latch elements, the plurality of second latch elements are configured to store the column address of the defective second memory cell in the plurality of second latch elements, the master latch element is configured to store the master bit of the defective second memory cell in the master latch element, and the second comparison logic is configured to compare the outputs of the plurality of second latch elements of the second latch array with the external column address; wherein the first column repair circuit and the second column repair circuit are different from each other; and The second comparison logic is configured to generate a second enable signal based on the output of the master latch element, and the second enable signal indicates whether to repair the defective second memory cell.

14. The memory device according to claim 13, wherein: The first comparison logic is configured to generate a first enable signal by performing a NOR operation on outputs of the plurality of first latch elements of the first latch array; and wherein the second comparison logic is configured to use the output of the master latch element as a second enable signal.

15. The memory device of claim 13, wherein: The primary bit of the defective first memory cell stored in the fuse array is not sent to the first latch array.

16. The memory device according to claim 13, in, Each of the plurality of column selection lines and the plurality of spare column selection lines is divided into a plurality of segments; wherein the first latch array includes a plurality of first latch groups, the second latch array includes a plurality of second latch groups, and each of the number of the plurality of first latch groups and the number of the plurality of second latch groups is equal to the number of the plurality of segments; wherein each of the plurality of first latch groups of the first latch array comprises the plurality of first latch elements; and Wherein, each of the plurality of second latch groups of the second latch array includes the plurality of second latch elements and a main latch element.

17. The memory device according to claim 13, in, The first comparison logic includes a plurality of first XNOR gates configured to perform an XNOR operation on outputs of the plurality of first latch elements of the first latch array and bits of an external column address; wherein the second comparison logic comprises a plurality of second XEN-OR gates configured to perform an XEN-OR operation on the outputs of the plurality of second latch elements of the second latch array and the bits of the external column address; and The first comparison logic includes a NOR gate, and the NOR gate is configured to perform a NOR operation on the outputs of the plurality of first latch elements of the first latch array.

18. The memory device of claim 13, wherein: At least one of the plurality of first latch elements of the first latch array is configured to invert an input of the at least one of the plurality of first latch elements of the first latch array and output the inverted input.

19. A method for operating a memory device, comprising: sending a column address of a defective first memory cell stored in the fuse array to a first latch array of a first column repair circuit; performing a first NOR operation on an output of the first latch array and outputting a first enable signal based on a result of the first NOR operation; comparing an output of the first latch array with an external column address and outputting a first address match signal based on the comparison result; as well as A second NOR operation is performed on the first enable signal and the first address match signal, and a first column repair signal is output based on a result of the second NOR operation.

20. A memory system comprising: a memory controller configured to: send an address of each of the read data and the write data to the memory device; as well as A memory device configured to repair a defective normal memory cell using a redundant memory cell, Wherein, the memory device comprises: A memory cell array, comprising a plurality of normal memory cells and a plurality of redundant memory cells, wherein the plurality of redundant memory cells are used to replace defective memory cells among the plurality of normal memory cells; a fuse array configured to: store the address and the primary bit of the defective first memory cell in the fuse array; an address register configured to: receive an address from a memory controller and transmit an external column address included in the received address to a column decoder; and A column decoder configured to: select among a plurality of column selection lines and a plurality of spare column selection lines; wherein the column decoder comprises a first column repair circuit, the first column repair circuit comprises a first latch array having a plurality of latch elements in the first latch array, the plurality of latch elements being configured to store column addresses of defective first memory cells in the plurality of latch elements, and a first comparison logic being configured to compare outputs of the plurality of latch elements with an external column address; and The first comparison logic is configured to generate a first enable signal based on outputs of the plurality of latch elements, and the first enable signal indicates whether to repair the defective first memory cell.

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