Semiconductor device and manufacturing method thereof

Abstract

According to the semiconductor device and the manufacturing method thereof provided by the invention, the thickness of the first oxide layer is increased, the first oxide layer is not completely removed when the first oxide layer is sacrificed subsequently, and silicon dioxide is not deposited as a dielectric layer after polycrystalline deposition is carried out in the groove, so that the production period can be shortened, and the cost can be reduced; in addition, after the lead window is etched, the polycrystalline morphology at the top end of the groove is basically flush with a silicon plane, so that the accuracy of lead photoetching line overlay is improved, the process difficulty is reduced, the yield of production lines is improved, voltage breakdown caused by thinning of an oxide layer during lead window etching is prevented, the over-electric stress limit parameter of a product is remarkably enhanced, and the yield of the product is improved. And the overall reliability is improved.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a semiconductor device and a method for manufacturing the same. Background Art

[0002] Currently, there is a problem in the process flow of trench Schottky products: after the lead hole is etched, the upper edge of the polysilicon in the trench will be too low below the silicon plane. This situation is caused by factors such as erosion during the lead drilling process, resulting in the large-groove gate oxide layer of the terminal being exposed to the external environment. In the subsequent lead etching, sputtering pretreatment, and pickling steps before front metallization, the gate oxide layer will be further thinned. Especially under reverse bias conditions, the area with thinner gate oxide layer is more likely to have local premature breakdown, increasing the risk of product failure due to excessive electrical stress during the reverse bias process. Summary of the invention

[0003] In order to at least overcome the above-mentioned deficiencies in the prior art, the object of the present application is to provide a semiconductor device and a method for manufacturing the same, the method comprising:

[0004] providing a substrate;

[0005] forming an epitaxial layer on the substrate;

[0006] forming a first oxide layer on a side of the epitaxial layer away from the substrate;

[0007] forming a groove on the epitaxial layer;

[0008] Partially etching the first oxide layer;

[0009] forming a second oxide layer in the groove; wherein the second oxide layer completely covers the inner wall of the groove;

[0010] Filling trench polysilicon in the trench; wherein the trench polysilicon is at least partially in contact with the first oxide layer;

[0011] Etching the first oxide layer to form a lead window; wherein the trench polysilicon and a portion of the epitaxial layer are exposed to the lead window;

[0012] Sputtering a barrier metal on a side of the lead window away from the epitaxial layer to form a barrier layer; wherein the barrier layer is at least partially in contact with the epitaxial layer and the trench polysilicon;

[0013] forming a first metal layer on a side of the barrier layer away from the first oxide layer;

[0014] A second metal layer is formed on a side of the substrate away from the epitaxial layer.

[0015] In a possible implementation manner, the step of forming a first oxide layer on a side of the epitaxial layer away from the substrate includes:

[0016] A low pressure chemical vapor deposition method is used to deposit a layer on one side of the epitaxial layer. Silicon dioxide is used as the first oxide layer.

[0017] In a possible implementation manner, the step of forming a groove on the epitaxial layer includes:

[0018] Performing photolithography on the first oxide layer to form a trench window;

[0019] The epitaxial layer is etched from the trench window to form a trench.

[0020] In a possible implementation manner, the angle between the sidewall of the groove and its bottom wall is not less than 90 degrees; and in the direction perpendicular to the substrate, the depth of the groove is greater than 1 um.

[0021] In a possible implementation manner, the step of partially corroding the first oxide layer includes:

[0022] The first oxide layer is immersed in an etchant and etched for 1 to 2 minutes, with an etching height of 0.1 to 0.3 um.

[0023] In a possible implementation manner, the step of filling the trench with trench polysilicon includes:

[0024] depositing polysilicon material into the trenches by chemical vapor deposition;

[0025] The trench polysilicon is etched back so that the trench polysilicon in the trench is lower than the first oxide layer and away from the surface of the epitaxial layer.

[0026] In a possible implementation manner, the step of performing barrier metal sputtering on a side of the lead window away from the epitaxial layer to form a barrier layer includes:

[0027] Inert gas is filled into the sputtering chamber and a high voltage electric field is applied to accelerate the plasma to bombard the metal target, sputtering metal atoms to deposit and form a thin film. The thickness and uniformity of the thin film are monitored during the sputtering process to form the barrier layer.

[0028] In a possible implementation, the materials of the first metal layer and the second metal layer include titanium, nickel, aluminum, or titanium, nickel, silver, or titanium, aluminum, titanium, nickel, silver in sequence in the direction away from the substrate.

[0029] The present application also provides a semiconductor device, which is manufactured using any of the semiconductor device manufacturing methods described above.

[0030] The present application also provides an electronic device, comprising the aforementioned semiconductor device.

[0031] Compared with the prior art, this application has the following beneficial effects:

[0032] The present application provides a semiconductor device and a manufacturing method thereof, which can reduce the production cycle and reduce the cost by increasing the thickness of the first oxide layer, not completely removing the first oxide layer when sacrificing the first oxide layer later, and not depositing silicon dioxide as a dielectric layer after polycrystalline deposition in the groove. In addition, after the lead window is etched, the polycrystalline morphology at the top of the groove is basically flush with the silicon plane, which is beneficial to improving the accuracy of lead photolithography line overlay, reducing the process difficulty, improving the production line qualification rate, preventing the oxide layer from becoming thinner during lead window etching to cause voltage breakdown, significantly enhancing the over-electrical stress limit parameters of the product, and thus improving the overall reliability. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required in the embodiments will be briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without creative work.

[0034] Figure 1 A schematic diagram of a process for manufacturing a semiconductor device provided in this embodiment;

[0035] Figure 2 One of the structural schematic diagrams of the semiconductor device provided in this embodiment;

[0036] Figure 3 The second structural schematic diagram of the semiconductor device provided in this embodiment;

[0037] Figure 4 The third structural schematic diagram of the semiconductor device provided in this embodiment;

[0038] Figure 5 The fourth structural schematic diagram of the semiconductor device provided in this embodiment;

[0039] Figure 6 The fifth structural schematic diagram of the semiconductor device provided in this embodiment;

[0040] Figure 7 The sixth structural schematic diagram of the semiconductor device provided in this embodiment;

[0041] Figure 8 The seventh structural schematic diagram of the semiconductor device provided in this embodiment;

[0042] Fig. 9 The eighth structural schematic diagram of the semiconductor device provided in this embodiment;

[0043] Fig.10 A ninth structural diagram of a semiconductor device provided in this embodiment;

[0044] Fig.11 The tenth structural diagram of the semiconductor device provided in this embodiment;

[0045] Fig.12 Schematic diagram of sub-steps of step S14 in this embodiment;

[0046] Fig.13 Schematic diagram of sub-steps of step S17 in this embodiment.

[0047] Marking description: substrate-100; epitaxial layer-200; first oxide layer-300; first oxide layer corrosion portion-310; groove-400; groove window-410; second oxide layer-500; groove polysilicon-600; lead window-710; barrier layer-800; first metal layer-910; second metal layer-920; D1-groove depth; D2-first oxide layer corrosion height. DETAILED DESCRIPTION

[0048] In order to make the purpose, technical solution and advantages of the embodiments of the present application clearer, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, rather than all the embodiments. The components of the embodiments of the present application described and shown in the drawings here can be arranged and designed in various different configurations.

[0049] Therefore, the following detailed description of the embodiments of the present application provided in the accompanying drawings is not intended to limit the scope of the present application for which protection is sought, but merely represents selected embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in the field without creative work are within the scope of protection of the present application.

[0050] It should be noted that similar reference numerals and letters denote similar items in the following drawings, and therefore, once an item is defined in one drawing, further definition and explanation thereof is not required in subsequent drawings.

[0051] In the description of this application, it should be noted that the terms "upper", "lower", etc. indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, or the orientation or positional relationship in which the product of the application is usually placed when in use, which is only for the convenience of describing this application and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on this application. In addition, the terms "first", "second", etc. are only used to distinguish the description, and cannot be understood as indicating or implying relative importance.

[0052] In addition, the terms "horizontal", "vertical", "overhanging" and the like do not mean that the components are required to be absolutely horizontal or overhanging, but can be slightly tilted. For example, "horizontal" only means that its direction is more horizontal than "vertical", and does not mean that the structure must be completely horizontal, but can be slightly tilted.

[0053] In the description of this application, it should also be noted that, unless otherwise clearly specified and limited, the terms "set", "install", "connect", and "connect" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, or it can be the internal communication of two elements. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0054] It should be noted that, in the absence of conflict, different features in the embodiments of the present application may be combined with each other.

[0055] The inventors have found that there is a problem in the existing process flow of trench semiconductor devices: after the lead hole is etched, the upper edge of the polysilicon in the trench will be too low below the silicon plane. This situation is caused by factors such as erosion during the lead drilling process, resulting in the second oxide layer of the large groove of the terminal being exposed to the external environment. In the subsequent lead etching, sputtering pretreatment, and pickling steps before front metallization, the second oxide layer will be further thinned. Under reverse bias conditions, areas with thinner second oxide layers are more likely to experience local premature breakdown, increasing the risk of product failure due to excessive electrical stress during the reverse bias process.

[0056] In view of this, the present application provides a semiconductor device and a method for manufacturing the same, please refer to Figure 1 , comprising the following steps.

[0057] Step S11, providing a substrate 100.

[0058] For example, N-type silicon with high resistivity is used as the substrate 100 to ensure good electrical performance and isolation effect.

[0059] Step S12 , forming an epitaxial layer 200 on the surface of the substrate 100 .

[0060] Specifically, a high-quality epitaxial layer 200 may be formed on the surface of the substrate 100 by using epitaxial growth techniques, such as chemical vapor deposition, molecular beam epitaxy, and the like.

[0061] For example, an N-type silicon epitaxial layer 200 is grown on an N-type silicon substrate 100 , and the doping concentration is slightly higher than that of the substrate 100 , so as to improve the conductivity of the device.

[0062] Step S13, please refer to Figure 2 A first oxide layer 300 is formed on a surface of the epitaxial layer 200 away from the substrate 100 .

[0063] Specifically, a first oxide layer 300 may be formed on the surface of the epitaxial layer 200 by thermal oxidation, chemical oxidation, physical vapor deposition, etc. The first oxide layer 300 may be used as a masking layer and a protective layer for subsequent processes.

[0064] Step S14, please refer to Figure 4 , a trench 400 is formed on the epitaxial layer 200 .

[0065] Specifically, first, according to the preset design requirements, the pattern of the required groove 400 is drawn on the epitaxial layer 200 using photolithography technology. Then, using a dry or wet etching process, the epitaxial layer 200 is selectively etched according to the photoresist pattern as a mask until a groove 400 structure with a predetermined depth and width is finally formed.

[0066] Step S15, please refer to Figure 5 , the first oxide layer 300 is partially corroded.

[0067] In order to ensure that silicon dioxide is not deposited as a dielectric layer in the subsequent step, in this embodiment, the first oxide layer 300 is partially etched. In order to enable the first oxide layer 300 to be used as a dielectric layer in subsequent steps after being partially etched, the first oxide layer 300 provided in this embodiment should have a considerable thickness compared to the prior art.

[0068] Step S16, please refer to Figure 6 , a second oxide layer 500 is formed in the groove 400 ; wherein the second oxide layer 500 completely covers the inner wall of the groove 400 .

[0069] In this embodiment, a second oxide layer 500 is grown on the inner wall of the trench 400 and the surface where the epitaxial layer 200 contacts the first oxide layer 300 through an oxidation process. The second oxide layer 500 can completely cover the inner wall of the trench 400 to isolate the trench polysilicon 600 structure generated in subsequent steps from the epitaxial layer 200 and other impurities or defects that may exist.

[0070] Step S17, please refer to Figure 7 , a trench polysilicon 600 is filled in the trench 400 ; wherein the trench polysilicon 600 is at least partially in contact with the first oxide layer 300 .

[0071] The reverse voltage of the trench Schottky product depends on the local location where the breakdown occurs in advance or the electric field strength is concentrated. In the manufacturing process, the second oxide layer 500 formed in step S16 will be covered by the polycrystalline material. The trench polysilicon 600 provided in this embodiment is at least partially in contact with the first oxide layer 300 to ensure that after the lead etching of the terminal large groove, the polysilicon morphology at the top of the trench is basically flush with the silicon plane, and the second oxide layer 500 is still located under the polycrystalline, thereby effectively preventing the direct exposure of the second oxide layer 500 in a series of processes such as lead etching, sputtering pretreatment, and pickling before front metallization, and avoiding the situation where it gradually becomes thinner due to exposure. This structural design significantly enhances the over-electrical stress limit parameters of the product, thereby improving the overall reliability.

[0072] Step S18, please refer to Figure 8 and Fig. 9 , etching the first oxide layer 300 to form a lead window 710 ; wherein the trench polysilicon 600 and a portion of the epitaxial layer 200 are exposed to the lead window 710 .

[0073] In this embodiment, after the lead window 710 is etched, the trench polysilicon 600 is basically flush with the silicon plane, which improves the accuracy of lead photolithography line overlay, reduces the process difficulty, improves the production line qualification rate, prevents the second oxide layer 500 from becoming thinner and causing voltage breakdown when the lead window 710 is etched, and enhances the over-electrical stress capability of the semiconductor device.

[0074] Step S19, please refer to Fig.10 , barrier metal sputtering is performed on a side of the lead window 710 away from the epitaxial layer 200 to form a barrier layer 800; wherein the barrier layer 800 is at least partially in contact with the epitaxial layer 200 and the trench polysilicon 600.

[0075] In this embodiment, a barrier metal is deposited on one side of the lead window 710 by a sputtering process to form a barrier layer 800 of the semiconductor device. For example, nickel is used as the barrier metal, and a nickel film is deposited on one side of the lead window 710 by an electron beam evaporation or magnetron sputtering process as the barrier layer 800.

[0076] Step S20, please refer to Fig.11 A first metal layer 910 is formed on a side of the barrier layer 800 away from the first oxide layer 300 .

[0077] Step S21, please refer to Fig.11 A second metal layer 920 is formed on a side of the substrate 100 away from the epitaxial layer 200 .

[0078] For example, in step S20 and step S21, one or more metal films are deposited as the anode first metal layer 910 by evaporation or sputtering. At the same time, the cathode second metal layer 920 is made by a similar process on the back of the substrate 100. Then, annealing is performed to improve the contact characteristics between the metal and the semiconductor. Finally, the semiconductor device in this embodiment is manufactured through process steps such as scribing and testing.

[0079] In a possible implementation manner, in step S13, a low pressure chemical vapor deposition method may be used to deposit a layer on one side of the epitaxial layer 200 to form The silicon dioxide is used as the first oxide layer 300.

[0080] In this embodiment, the atmospheric pressure chemical vapor deposition technology can accurately control the thickness and uniformity of the silicon dioxide film, and the silicon dioxide film obtained by this method also has good adhesion to the substrate 100. At the same time, since a part of the first oxide layer 300 needs to be retained after step S15 to ensure that silicon dioxide is not deposited as a dielectric layer after step S17, in this embodiment, the first oxide layer 300 is set to a thicker film layer.

[0081] Specifically, first, the substrate 100 is placed in a deposition chamber, and it is ensured that the required cleanliness and vacuum are achieved in the deposition chamber. At the same time, the precursor gas and carrier gas of silicon dioxide are prepared. Under normal pressure or near normal pressure, the precursor gas and carrier gas are introduced into the deposition chamber at a certain flow ratio. The precursor gas undergoes a chemical reaction at high temperature to generate silicon dioxide and deposit it on the surface of the substrate 100. By precisely controlling parameters such as reaction temperature, gas flow rate, deposition time, etc., deposition on the substrate 100 can be achieved. Thickness of silicon dioxide film.

[0082] In one possible implementation, please refer to Fig.12 , step S14 includes the following steps.

[0083] Step S141, please refer to Figure 3 , photolithography is performed on the first oxide layer 300 to form a groove window 410.

[0084] Specifically, first, a layer of photoresist needs to be coated on the first oxide layer 300. Then, a photolithography machine is used to expose the first oxide layer 300 coated with the photoresist. During exposure, a mask having a groove window 410 pattern is used to block part of the light so that only the photoresist corresponding to the transparent part on the mask is exposed to light. After exposure, through a development step, a groove window 410 corresponding to the mask pattern can be formed on the first oxide layer 300.

[0085] Step S142, please refer to Figure 4 , the epitaxial layer 200 is etched from the trench window 410 to form a trench 400 .

[0086] In this embodiment, the etching depth and sidewall morphology need to be controlled to ensure that the formed trench 400 meets the design requirements. After etching, the epitaxial layer 200 material under the trench window 410 is removed to form a trench 400 structure with a specific depth and width.

[0087] In a possible implementation manner, the angle between the side wall of the groove 400 and the bottom wall thereof is not less than 90 degrees; in a direction perpendicular to the substrate 100 , the depth D1 of the groove is greater than 1 um.

[0088] It is worth noting that, in the present embodiment, the bottom of the trench 400 is configured to be a smooth structure without sharp corners, so as to prevent the electric field concentration at the bottom corner from affecting the reverse voltage of the semiconductor device.

[0089] In a possible implementation, in step S19, the first oxide layer 300 may be immersed in an etchant for 1 to 2 minutes, and the first oxide layer etching height D2 is set to 0.1 to 0.3 um.

[0090] In this embodiment, by controlling the time for which the first oxide layer 300 is immersed in the etchant, a first oxide layer 300 of a certain thickness is retained on the surface of the epitaxial layer 200 as a dielectric layer before etching the lead window 710. This reduces the production cycle of semiconductor devices and reduces costs.

[0091] In one possible implementation, please refer to Fig.13 , step S17 includes the following steps.

[0092] Step S171 , depositing polysilicon material into the trench 400 by chemical vapor deposition technology.

[0093] Step S172 , etching back the trench polysilicon 600 , so that the trench polysilicon 600 in the trench 400 is lower than the first oxide layer 300 and away from the surface of the epitaxial layer 200 .

[0094] In this embodiment, the trench polysilicon 600 is etched back to remove excess deposited material to achieve a desired shape and size, thereby ensuring that subsequent processes can proceed smoothly and guaranteeing the electrical performance and reliability of the ultimately formed semiconductor device.

[0095] In a possible implementation, in step S19, an inert gas may be filled into the sputtering chamber and a high voltage electric field may be applied to accelerate the plasma to bombard the metal target, sputtering out metal atoms to form a thin film, and the thickness and uniformity of the thin film may be monitored during the sputtering process to form the barrier layer 800.

[0096] In this embodiment, the barrier layer 800 with the desired thickness can be obtained by using plasma acceleration to bombard the target material and monitoring the thickness and uniformity of the formed film during the sputtering process.

[0097] Specifically, first, an inert gas, such as argon, is filled into the sputtering chamber. The filling of the inert gas provides a stable and controllable environment for the subsequent sputtering process. Next, a high-voltage electric field is applied in the sputtering chamber to form a plasma. As the plasma is formed and accelerated by the high-voltage electric field, these high-speed ions then bombard the preset metal target. The high-speed impact of the ions will cause the atoms on the surface of the metal target to be sputtered out, and these sputtered metal atoms are then deposited on the substrate in the chamber under the action of the electric field or natural diffusion, gradually accumulating to form a uniform thin film.

[0098] During the sputtering process, a sensor or detection system can be used to ensure that the formed barrier layer 800 meets the design requirements, so that it has sufficient thickness to ensure its function and maintains a high degree of uniformity over the entire substrate.

[0099] In a possible implementation, the materials of the first metal layer 910 and the second metal layer 920 include titanium, nickel, aluminum, or titanium, nickel, silver, or titanium, aluminum, titanium, nickel, silver in the direction away from the substrate 100 .

[0100] In this embodiment, the process of depositing the first metal layer 910 and the second metal layer 920 needs to be monitored to ensure the uniformity and compactness of each layer of material and the good bonding between the layers. The titanium layer is often used as a bottom layer to enhance the bonding between the metal layer and the substrate 100 due to its excellent adhesion and barrier properties. The nickel layer provides protection for semiconductor devices due to its good corrosion resistance and mechanical strength. The design of this multi-layer metal structure not only improves the electrical performance of the chip, but also enhances its stability and reliability, providing a basis for subsequent packaging and testing steps.

[0101] Based on the same inventive concept, the present application also provides a semiconductor device manufactured using any of the aforementioned methods for manufacturing a semiconductor device.

[0102] The present application also provides an electronic device, comprising the aforementioned semiconductor device.

[0103] In summary, the present application provides a semiconductor device and a method for manufacturing the same, which can reduce the production cycle and reduce costs by increasing the thickness of the first oxide layer 300 and not completely removing the first oxide layer 300 when sacrificing the first oxide layer 300 later, and no longer depositing silicon dioxide as a dielectric layer after polycrystalline deposition in the groove 400; in addition, after the lead window 710 is etched, the polycrystalline morphology at the top of the groove 400 is basically flush with the silicon plane, which is beneficial to improving the accuracy of lead photolithography line overlay, reducing the process difficulty, and improving the production line qualification rate, preventing the oxide layer from becoming thinner during etching of the lead window 710, resulting in voltage breakdown, significantly enhancing the product's over-electrical stress limit parameters, and thereby improving the overall reliability.

[0104] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the existence of other identical elements in the process, method, article or device including the elements.

[0105] The above description is only the preferred embodiment of the present application and is not intended to limit the present application. For those skilled in the art, the present application may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A method for manufacturing a semiconductor device, characterized in that: The method comprises: providing a substrate; forming an epitaxial layer on the substrate; forming a first oxide layer on a side of the epitaxial layer away from the substrate; forming a groove on the epitaxial layer; Partially etching the first oxide layer; forming a second oxide layer in the groove; wherein the second oxide layer completely covers the inner wall of the groove; Filling trench polysilicon in the trench; wherein the trench polysilicon is at least partially in contact with the first oxide layer; Etching the first oxide layer to form a lead window; wherein the trench polysilicon and a portion of the epitaxial layer are exposed to the lead window; Sputtering a barrier metal on a side of the lead window away from the epitaxial layer to form a barrier layer; wherein the barrier layer is at least partially in contact with the epitaxial layer and the trench polysilicon; forming a first metal layer on a side of the barrier layer away from the first oxide layer; A second metal layer is formed on a side of the substrate away from the epitaxial layer.

2. The method for manufacturing a semiconductor device according to claim 1, wherein: The step of forming a first oxide layer on a side of the epitaxial layer away from the substrate comprises: A low pressure chemical vapor deposition method is used to deposit a layer on one side of the epitaxial layer. Silicon dioxide is used as the first oxide layer.

3. The method for manufacturing a semiconductor device according to claim 1, wherein: The step of making a groove on the epitaxial layer comprises: Performing photolithography on the first oxide layer to form a trench window; The epitaxial layer is etched from the trench window to form a trench.

4. The method for manufacturing a semiconductor device according to claim 1, wherein: The angle between the side wall of the groove and its bottom wall is not less than 90 degrees; in the direction perpendicular to the substrate, the depth of the groove is greater than 1um.

5. The method for manufacturing a semiconductor device according to claim 1, wherein: The step of partially corroding the first oxide layer comprises: The first oxide layer is immersed in an etchant and etched for 1 to 2 minutes, with an etching height of 0.1 to 0.3 um.

6. The method for manufacturing a semiconductor device according to claim 1, wherein: The step of filling the trench with trench polysilicon comprises: depositing polysilicon material into the trenches by chemical vapor deposition; The trench polysilicon is etched back so that the trench polysilicon in the trench is lower than the first oxide layer and away from the surface of the epitaxial layer.

7. The method for manufacturing a semiconductor device according to claim 1, wherein: The step of performing barrier metal sputtering on a side of the lead window away from the epitaxial layer to form a barrier layer comprises: Inert gas is filled into the sputtering chamber and a high voltage electric field is applied to accelerate the plasma to bombard the metal target, sputtering metal atoms to deposit and form a thin film. The thickness and uniformity of the thin film are monitored during the sputtering process to form the barrier layer.

8. The method for manufacturing a semiconductor device according to claim 1, wherein: The materials of the first metal layer and the second metal layer include titanium, nickel, aluminum, or titanium, nickel, silver, or titanium, aluminum, titanium, nickel, silver in sequence in the direction away from the substrate.

9. A semiconductor device, characterized in that: The semiconductor device is manufactured using the method for manufacturing a semiconductor device according to any one of claims 1 to 8.

10. An electronic device, characterized in that: A semiconductor device comprising the semiconductor device according to claim 9.

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