Preparation method of semiconductor structure and semiconductor structure

Abstract

The invention relates to a preparation method of a semiconductor structure and the semiconductor structure, and relates to the technical field of semiconductors, and the preparation method of the semiconductor structure comprises the steps: when a gate material layer is subjected to chemical mechanical polishing, a first load effect is formed, and then a first gate intermediate layer is subjected to preset dry etching to form a gate; the preset dry etching can generate a second load effect, the first load effect is the effect that the grinding rate is higher when the etching pattern density is larger, and the second load effect is the effect that the grinding rate is slower when the etching pattern density is larger, that is, the second load effect and the first load effect are reverse load effects, that is, the first load effect and the second load effect are mutually reverse load effects, that is, the first load effect and the second load effect are mutually reverse load effects. The second load effect has a reverse control effect on the first load effect generated by chemical mechanical polishing, and the first load effect generated by chemical mechanical polishing is improved. In addition, when atomic layer etching is carried out on the first dielectric material layer, due to the fact that atomic layer etching is a self-limiting chemical reaction, etching is more accurate, and defects are reduced.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a method for preparing a semiconductor structure and a semiconductor structure. Background Art

[0002] In the 28nm advanced process node, the gate last process is one of the mainstream methods for forming high-k metal gates, among which chemical mechanical polishing (CMP) plays an important role in the gate last process.

[0003] However, in the process of forming the gate, chemical mechanical polishing will have many problems. First, chemical mechanical polishing will produce a loading effect, resulting in an uneven surface of the formed gate. Second, when using chemical mechanical polishing to form the gate, excessive polishing will cause the gate height to be too low, and too little polishing will cause metal residue and lead to a short circuit. Third, because the gate is soft and active, it is easy to produce defects such as particle residue, scratches, and corrosion during polishing. Therefore, it is very important to improve the loading effect and polishing defects of the gate.

[0004] Based on this, how to improve the gate load effect and grinding defects has become a technical problem that technical personnel in this field need to solve urgently. Summary of the invention

[0005] Based on this, it is necessary to provide a method for preparing a semiconductor structure and a semiconductor structure in order to improve the loading effect and grinding defects of the gate.

[0006] In order to achieve the above object, on the one hand, the present invention provides a method for preparing a semiconductor structure, comprising:

[0007] providing a substrate having a plurality of grooves;

[0008] forming a first dielectric material layer on the upper surface of the substrate and the inner wall of the groove;

[0009] forming a gate material layer on a side of the first dielectric material layer away from the substrate, wherein the gate material layer fills the groove;

[0010] Using the first dielectric material layer as a stop layer, chemical mechanical polishing is performed on the gate material layer to form a first gate intermediate layer, wherein the chemical mechanical polishing has a first loading effect;

[0011] Performing atomic layer etching on the first dielectric material layer to form a first dielectric layer;

[0012] The first gate intermediate layer is subjected to a preset dry etching to form a gate, wherein the preset dry etching has a second load effect, and the second load effect and the first load effect are reverse load effects to each other.

[0013] In one embodiment, the step of performing atomic layer etching on the first gate intermediate layer and the first dielectric material layer to form the first dielectric layer and the gate includes:

[0014] Performing a first atomic layer etching on the first dielectric material layer to form the first dielectric layer.

[0015] In one of the embodiments, the first dielectric material layer includes at least two sub-dielectric material layers, and the first dielectric layer includes at least two sub-dielectric layers;

[0016] When performing the first atomic layer etching on the first dielectric material layer, different etching gases are used to etch each of the sub-dielectric material layers respectively, and the remaining part of each of the sub-dielectric material layers after etching forms the corresponding sub-dielectric layer.

[0017] In one embodiment, etching each of the sub-dielectric material layers separately includes:

[0018] Passing a first reaction gas to react and modify the sub-medium material layer;

[0019] A second reaction gas is introduced to react with the modified sub-dielectric material layer to generate a volatile gas.

[0020] In one embodiment, the step of performing a preset dry etching on the first gate intermediate layer to form a gate comprises:

[0021] Performing a preset dry etching on the first gate intermediate layer to form a second gate intermediate layer;

[0022] Performing a second atomic layer etching on the second gate intermediate layer to form the gate;

[0023] The step of performing a second atomic layer etching on the second gate intermediate layer to form the gate includes:

[0024] Passing a third reaction gas to react and modify the second gate intermediate layer;

[0025] A fourth reaction gas is introduced to react with the modified second grid intermediate layer to generate a volatile gas.

[0026] In one embodiment, the first dielectric material layer includes a first sub-dielectric material layer and a second sub-dielectric material layer sequentially arranged on one side of the substrate, the first sub-dielectric material layer is used to adjust the work function of the semiconductor structure, and the second sub-dielectric material layer is located on a side close to the gate.

[0027] In one embodiment, the step of using the first dielectric material layer as a stop layer and performing chemical mechanical polishing on the gate material layer to form a first gate intermediate layer includes:

[0028] The second sub-dielectric material layer is used as a stop layer, and the gate material layer is subjected to chemical mechanical polishing to form the first gate intermediate layer.

[0029] In one embodiment, before the step of forming a first dielectric material layer on the upper surface of the substrate and the inner wall of the groove, the method further includes:

[0030] A second dielectric layer is formed at the bottom of the groove.

[0031] In one embodiment, the gate material layer is made of aluminum metal.

[0032] On the other hand, the present invention further provides a semiconductor structure, which is prepared according to any of the above-mentioned methods for preparing the semiconductor structure.

[0033] Compared with the prior art, the above technical solution has the following unexpected technical effects:

[0034] The method for preparing the semiconductor structure first forms a first dielectric material layer and a gate material layer on a substrate, then uses the first dielectric material layer as a stop layer, first performs chemical mechanical polishing on the gate material layer to form a first gate intermediate layer, at which time a first load effect is formed, and then performs atomic layer etching on the first dielectric material layer to form a first dielectric layer. Since atomic layer etching is a self-limiting chemical reaction, etching is more precise, so the etching position can be well controlled during etching. Afterwards, a preset dry etching is performed on the first gate intermediate layer to form a gate, and the preset dry etching will produce a second load effect. Since the second load effect and the first load effect are mutually reverse load effects, that is, the second load effect has a reverse control effect on the first load effect generated by chemical mechanical polishing, thereby improving the first load effect generated by chemical mechanical polishing. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the conventional technology, the drawings required for use in the embodiments or the conventional technology descriptions are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0036] Figure 1 A schematic diagram of a semiconductor structure preparation process is provided for an embodiment of the present application;

[0037] Figure 2 A schematic structural diagram of a substrate of a semiconductor structure provided in an embodiment of the present application;

[0038] Figure 3 A schematic diagram of a structure after a first dielectric material layer is formed in a preparation process of a semiconductor structure provided in an embodiment of the present application;

[0039] Figure 4 A schematic diagram of a structure after a gate material layer is formed in a preparation process of a semiconductor structure provided in an embodiment of the present application;

[0040] Figure 5 for Figure 4 A schematic diagram of the enlarged structure in the dotted frame;

[0041] Figure 6 A schematic diagram of a structure after a first load effect is generated during the preparation process of a semiconductor structure provided in an embodiment of the present application;

[0042] Figure 7 A schematic diagram of a structure after a first gate intermediate layer is formed in a preparation process of a semiconductor structure provided in an embodiment of the present application;

[0043] Figure 8 A schematic diagram of a structure after a second gate intermediate layer is formed in a preparation process of a semiconductor structure provided in an embodiment of the present application;

[0044] Fig. 9 for Figure 8 A schematic diagram of the enlarged structure in the dotted frame;

[0045] Fig.10 A schematic diagram of a structure after a gate is formed in a preparation process of a semiconductor structure provided in an embodiment of the present application;

[0046] Fig.11 for Fig.10 Schematic diagram of the enlarged structure in the dotted box.

[0047] Explanation of the reference numerals: 01-substrate, 02-first dielectric material layer; 03-gate material layer; 04-first gate intermediate layer; 05-first dielectric layer; 06-gate; 07-second dielectric layer; 011-silicon substrate; 012-trench isolation structure; 013-gate oxide layer; 014-dielectric layer; 021-first sub-dielectric material layer; 022-second sub-dielectric material layer; 023-third sub-dielectric material layer; 051-first sub-dielectric layer; 052-second sub-dielectric layer; 053-third sub-dielectric layer; 041-second gate intermediate layer. DETAILED DESCRIPTION

[0048] In order to facilitate understanding of the present application, the present application will be described more fully below with reference to the relevant drawings. Embodiments of the present application are provided in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.

[0049] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0050] It should be understood that when a layer is referred to as being "on," "adjacent to," or "connected to" another layer, it can be directly on, adjacent to, or connected to the other layer, or intervening layers may be present. In contrast, when an element is referred to as being "directly on," "directly adjacent to," or "directly connected to" another layer, there are no intervening layers.

[0051] When used herein, the singular forms "a", "an", and "said / the" may also include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "include / comprise" or "have" etc. specify the presence of stated features, wholes, steps, operations, components, parts or combinations thereof, but do not exclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts or combinations thereof.

[0052] Based on the content in the background technology, in the existing method of preparing semiconductor structures, when preparing the gate, the gate material is usually polished by chemical mechanical polishing to form the gate, but this chemical mechanical polishing method is very easy to cause a loading effect caused by chemical mechanical polishing, and there will also be defects such as uneven gate height and structural residue. Therefore, in order to solve the CMP loading effect caused by chemical mechanical polishing, a method for preparing a semiconductor structure and a semiconductor structure are proposed.

[0053] The method for preparing the semiconductor structure first forms a first dielectric material layer and a gate material layer on a substrate, then uses the first dielectric material layer as a stop layer, first performs chemical mechanical polishing on the gate material layer to form a first gate intermediate layer, at which time a first load effect is formed, and then performs atomic layer etching on the first dielectric material layer to form the first dielectric layer. Since atomic layer etching is a self-limiting chemical reaction, etching is more precise, so the etching position can be well controlled during etching. Afterwards, the first gate intermediate layer is subjected to a preset dry etching to form a gate, and the preset dry etching will produce a second load effect. Since the first load effect is an effect that the grinding rate is faster when the etching pattern density is greater, and the second load effect is an effect that the grinding rate is slower when the etching pattern density is greater, that is, the second load effect and the first load effect are mutually reverse load effects, that is, the second load effect has a reverse control effect on the first load effect generated by chemical mechanical polishing, thereby improving the first load effect generated by chemical mechanical polishing.

[0054] In order to make the above-mentioned purposes, features and advantages of the present application more obvious and easy to understand, the present application is further described in detail below with reference to the accompanying drawings and specific implementation methods.

[0055] refer to Figure 1 , Figure 1 A schematic diagram of a semiconductor structure preparation process is provided for an embodiment of the present application; the semiconductor structure preparation method comprises:

[0056] S101: Provide a substrate 01, the substrate 01 having a plurality of grooves 015 (such as Figure 2 as shown).

[0057] S102: Form a first dielectric material layer 02 (such as Figure 3 as shown).

[0058] S103: forming a gate material layer 03 on the side of the first dielectric material layer 02 away from the substrate 01, and the gate material layer 03 fills the groove 015 (such as Figure 4 , Figure 5 as shown).

[0059] S104: using the first dielectric material layer 02 as a stop layer, chemical mechanical polishing is performed on the gate material layer 03 to form a first gate intermediate layer 04. The chemical mechanical polishing has a first load effect.

[0060] S105: Performing atomic layer etching on the first dielectric material layer 02 to form a first dielectric layer 05 (eg Figure 7 as shown).

[0061] S106: performing a preset dry etching on the first gate intermediate layer 04 to form a gate 06, wherein the preset dry etching has a second load effect, and the second load effect is an inverse load effect to the first load effect (such as Fig.10 as shown).

[0062] In the above-mentioned preparation method, a first dielectric material layer 02 and a gate material layer 03 are first formed on the substrate 01, and then the first dielectric material layer 02 is used as a stop layer, and the gate material layer 03 is first subjected to chemical mechanical polishing to form a first gate intermediate layer 04, at which a first load effect is formed, and then the first dielectric material layer 02 is subjected to atomic layer etching to form a first dielectric layer 05. Since atomic layer etching is a self-limiting chemical reaction, etching is more precise, so the etching position can be well controlled during etching. After that, the first gate intermediate layer 04 is subjected to a preset dry etching to form a gate 06, and the preset dry etching will produce a second load effect. Since the first load effect is the effect that the grinding rate is faster when the etching pattern density is greater, and the second load effect is the effect that the grinding rate is slower when the etching pattern density is greater, that is, the second load effect and the first load effect are mutually reverse load effects, that is, the second load effect has a reverse control effect on the first load effect generated by chemical mechanical polishing, thereby improving the first load effect generated by chemical mechanical polishing.

[0063] Specifically, in step S101, before preparing the semiconductor structure, a substrate 01 is first provided, and the substrate 01 has a plurality of grooves 015. The substrate 01 described herein is as follows: Figure 2 As shown, it includes a silicon substrate 011, a shallow trench isolation structure 012, a gate oxide layer 013 and a dielectric layer 014. Among them, the shallow trench isolation structure 012 is located in the silicon substrate 011, and is used to isolate the interference between different structures. The gate oxide layer 013 covers the silicon substrate 011 and the shallow trench isolation structure 012, and is used to lay the foundation for the subsequent structure preparation. The dielectric layer 014 is located on the side of the gate oxide layer 013 away from the silicon substrate 011, and serves as a zero-layer dielectric layer for isolating different components. The dielectric layer 014 is a graphic structure, that is, the dielectric layer 014 has a plurality of grooves, which are grooves 015 of the substrate 01. It should be noted that the substrate 01 provided above is only for illustration, and in actual application, it can be the substrate 01 specifically required by the semiconductor structure, and is not specifically limited here.

[0064] In step S102, Figure 3 As shown, a first dielectric material layer 02 is formed on one side of the substrate 01 , and the first dielectric material layer 02 covers the upper surface of the substrate 01 and the inner wall of the groove 015 . The first dielectric material layer 02 helps to improve the performance of the semiconductor structure.

[0065] In step S103, Figure 4As shown, a gate material layer 03 is formed on the side of the first dielectric material layer 02 facing away from the substrate 01, and the gate material layer 03 fills the groove 015. The gate material layer 03 is formed by deposition. Due to the presence of the groove, there is a height difference on the upper surface of the first dielectric material layer 02. When the gate material layer 03 is deposited, the surface of the gate material layer 03 will be concave and uneven.

[0066] In step S104, Figure 6 As shown, in order to increase the preparation speed, the first dielectric material layer 02 is used as a stop layer to perform chemical mechanical polishing on the gate material layer 03. At this time, the gate material layer 03 can be subjected to chemical mechanical polishing twice, for example, the first polishing thins the gate material layer 03, and then fine polishing is continued to form the first gate intermediate layer 04. However, during chemical mechanical polishing, for the gate material layer 03, the greater the gate pattern density, the faster the polishing rate, so a first load effect is generated, and the first load effect affects the performance of the semiconductor structure.

[0067] In step S105, the first dielectric material layer 02 is subjected to atomic layer etching to form the first dielectric layer 05. Compared with the existing CMP polishing, since the atomic layer etching is etched by a self-limiting chemical reaction, the etching position can be well controlled.

[0068] In step S106, if Fig.10 As shown, the first gate intermediate layer 04 is subjected to a preset dry etching. In the preset dry etching, the etching rate decreases due to the fast consumption of reactive ions in places where the gate pattern density is large, thereby generating a second load effect. The second load effect is an inverse load effect to the first load effect, and instead removes the first load effect generated by chemical mechanical polishing. Therefore, the use of dry etching is beneficial to reversely control the first load effect generated by chemical mechanical polishing, that is, to reduce the first load effect.

[0069] It should be noted that when the preset dry etching is adopted, the substrate 01 can be used as a stop layer, and the dry etching forms the gate 06. The main purpose of adopting the preset dry etching is to reversely control the unevenness of the surface of the gate material layer 03 by adjusting the etching gas, flow rate, time and other parameters, and to adjust the etching speed by switching the gas and flow rate parameters for the surface of different regions, that is, to further optimize the flatness of the structure surface through dry etching.

[0070] Optional, reference Figure 8 In another embodiment of the present application, before the step of forming the first dielectric material layer 02 on the upper surface of the substrate 01 and the inner wall of the groove 015, the method further includes:

[0071] A second dielectric layer 07 is formed at the bottom of the groove 015 .

[0072] Specifically, the dielectric layer 014 has a groove 015, and the groove 015 exposes the gate oxide layer 013. The second dielectric layer 07 is formed on the upper surface of the gate oxide layer 013 exposed by the dielectric layer 014, that is, at the bottom of the groove 015. Fig. 9 As shown, the second dielectric layer 07 includes a high-K layer 071 and a TiN layer 072 which are arranged in sequence, wherein the material of the high-K layer 071 is a dielectric material with a high dielectric constant. The high-K layer 071 is mainly used to increase the capacitance value of the transistor and reduce power consumption, while the TiN layer 072 is used to adjust the threshold voltage and improve the electrical characteristics of the device.

[0073] Optionally, in another embodiment of the present application, the material of the gate material layer 03 is aluminum metal material.

[0074] Specifically, the present application aims to improve the load effect of the gate electrode 06 made of aluminum metal material. It should be noted that the selection of the gate material layer 03 is only for example.

[0075] Optionally, in another embodiment of the present application, the step of performing atomic layer etching on the first dielectric material layer 02 to form the first dielectric layer 05 includes:

[0076] The first dielectric material layer 02 is subjected to a first atomic layer etching to form a first dielectric layer 05 .

[0077] Specifically, atomic layer etching is used for the first dielectric material layer 02. Compared with the existing CMP polishing, since atomic layer etching is etched through a self-limiting chemical reaction, the etching position can be well controlled, so that more precise etching can be achieved, thereby avoiding the generation of a load effect.

[0078] Optionally, in another embodiment of the present application, the first dielectric material layer 02 includes at least two sub-dielectric material layers (eg Figure 5 As shown, the first dielectric layer 05 includes at least two sub-dielectric layers (such as Fig. 9 as shown).

[0079] When the first dielectric material layer 02 is subjected to the first atomic layer etching, different etching gases are used to etch each sub-dielectric material layer respectively, and the remaining part of each sub-dielectric material layer after etching forms a corresponding sub-dielectric layer.

[0080] Specifically, the first dielectric layer 05 is formed by etching the first dielectric material layer 02 through the first atomic layer, so the first dielectric layer 05 has the same level as the first dielectric material layer 02. It should be noted that the materials of different sub-dielectric material layers are different, so the etching gases used are different. The remaining part after etching is the sub-dielectric layer. Different sub-dielectric layers together improve the overall performance of the semiconductor structure.

[0081] Optionally, in another embodiment of the present application, Figure 5 As shown, the first dielectric material layer 02 includes a first sub-dielectric material layer 021 and a second sub-dielectric material layer 022 sequentially arranged on one side of the substrate 01. The first sub-dielectric material layer 021 is used to adjust the work function of the semiconductor structure, and the second sub-dielectric material layer 022 is located on the side close to the gate.

[0082] Specifically, Figure 5 As shown, a third sub-dielectric material layer 023 is further included between the first sub-dielectric material layer 021 and the substrate 01. The third sub-dielectric material layer 023 may be a TaN layer, which can adjust the effective work function and improve the performance of the transistor. The first sub-dielectric material layer 021 may be a TiAl layer, which is used to finely control the work function of the gate to optimize the threshold voltage of the transistor. The second sub-dielectric material layer 022 may be a TTN layer, which is mainly used to increase the capacitance value of the transistor, thereby improving its ability to drive current.

[0083] Optionally, in another embodiment of the present application, the step of using the first dielectric material layer 02 as a stop layer and performing chemical mechanical polishing on the gate material layer 03 to form the first gate intermediate layer 04 includes:

[0084] The second sub-dielectric material layer 022 is used as a stop layer, and the gate material layer 03 is subjected to chemical mechanical polishing to form a first gate intermediate layer 04 (such as Figure 7 as shown).

[0085] Specifically, the second sub-dielectric material layer 022 may be a TTN layer, which may be used as a stop layer. The TTN layer includes Ti material and TiN material, and the grinding is stopped immediately when the Ti signal is captured. Thus, the gate material layer 03 is chemically mechanically polished to form the first gate intermediate layer 04.

[0086] Optionally, in another embodiment of the present application, etching each sub-dielectric material layer separately includes:

[0087] S201: introducing a first reaction gas to perform reaction modification on the sub-dielectric material layer.

[0088] S202: introducing a second reaction gas to react with the modified sub-dielectric material layer to generate a volatile gas.

[0089] Specifically, the process of etching three sub-dielectric material layers to form three sub-dielectric layers is taken as an example for description.

[0090] When etching the second sub-dielectric material layer 022, firstly perform step S01: introduce O3 or H2O2 to oxidize Ti and TiN into TiO2, then perform step S02: introduce HF to react with TiO2 to generate volatile TiF4, and repeat step S01 and step S02 for multiple times until the TTN material is completely removed.

[0091] When etching the first sub-dielectric material layer 021, firstly, step S11 is performed: the first sub-dielectric material layer 021 is oxidized, and TiO2 and Al2O3 are finally generated after oxidation; then step S12 is performed: HF is introduced to react to generate volatile TiF4, and then step S13 is performed: trimethylaluminum (TMA) reacts with AlF3 to generate volatile AlF(CH3)2; step S11, step S12 and step S13 are repeated for multiple times until the TiAl material is completely removed.

[0092] When etching the third sub-dielectric material layer 023, firstly perform step S21: introduce C4F8 and CO gas to react with TaN to generate TaF5 and fluorocarbon polymer; then perform step S22: introduce O2 to react with TaF5 / fluorocarbon polymer, and remove the product by using O2 gas flow; repeat step S21 and step S22 for multiple times until the TaN material is completely removed.

[0093] It should be noted that the second sub-dielectric material layer 022, the first sub-dielectric material layer 021 and the third sub-dielectric material layer 023 are subjected to reaction modification, and then the modified sub-dielectric material layers are reacted to generate volatile gases to form the second sub-dielectric layer 052, the first sub-dielectric layer 051 and the third sub-dielectric layer 053. The atomic layer etching method is adopted to avoid the CMP load effect, and because the etching is more precise, over-etching and under-etching are avoided, and the formation of defects is reduced.

[0094] Optionally, in another embodiment of the present application, the step of performing a preset dry etching on the first gate intermediate layer 04 to form the gate 06 includes:

[0095] The first gate intermediate layer 04 is subjected to a preset dry etching process to form a second gate intermediate layer 041 (eg Figure 8 shown);

[0096] Performing a second atomic layer etching on the second gate intermediate layer 041 to form a gate 06;

[0097] The step of performing a second atomic layer etching on the second gate intermediate layer 041 to form the gate 06 includes:

[0098] S301 : introducing a third reaction gas to perform reaction modification on the second gate intermediate layer 041 .

[0099] S302: introducing a fourth reaction gas to react with the modified second gate intermediate layer 041 to generate a volatile gas.

[0100] Specifically, refer to Figure 7 , the first gate intermediate layer 04 is subjected to a preset dry etching process to form a second gate intermediate layer 041. Figure 8 , Fig. 9 , Fig.10 as well as Fig.11 After the first gate intermediate layer 04 is dry-etched by a preset method, the first load effect is offset by the second load effect generated by the dry etching, forming a flat second gate intermediate layer 041. At this time, the second gate intermediate layer 041 may be partially higher than the second sub-dielectric layer 052, the first sub-dielectric layer 051 and the third sub-dielectric layer 053 (e.g. Figure 8 , Fig. 9 As shown in FIG. 1 ), in order to reduce the influence of the load effect on the formed gate 06, the second gate intermediate layer 041 can be further subjected to atomic layer etching. When etching the second gate intermediate layer 041, firstly, step S31 is performed: the second gate intermediate layer 041 is subjected to oxidation treatment, and the metal Al is oxidized to Al2O3 by O2; then step S32 is performed: HF and A are introduced. l2 O3 reacts to generate AlF3, and then step S33 is performed: trimethylaluminum (TMA) reacts with AlF3 to generate volatile AlF(CH3)2; steps S31, S32 and S33 are repeated many times until the surface of the gate 06 is flush with the first dielectric layer 05 (such as Fig.10 as shown).

[0101] The processes of the above atomic layer etching methods all use self-limiting chemical reactions, and only one layer of atoms is removed in each etching cycle, thereby avoiding over-etching and under-etching, so that a uniform and flat gate 06 can be obtained.

[0102] It should be noted that in some embodiments, the first load effect may cause the height of the first gate intermediate layer 04 to be lower than the height of the dielectric layer 014. At this time, the dielectric layer 014 may be etched while the second gate intermediate layer 041 is being etched, and there is no specific limitation.

[0103] Based on the preparation method of the above semiconductor structure, reference Fig.10 The present application also provides a semiconductor structure prepared by the above-mentioned semiconductor structure preparation method.

[0104] It should be noted that the semiconductor structure has all the above characteristics because it is made by the above preparation method. The semiconductor structure uses a second load effect to offset the first load effect generated by chemical mechanical polishing, making the load effect smaller. And because atomic layer etching is a self-limiting chemical reaction, etching is more precise, so over-etching and under-etching can be well avoided during etching, while improving the load effect and further reducing grinding defects.

[0105] In the description of this specification, the description with reference to the term "another embodiment" or the like means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic description of the above terms does not necessarily refer to the same embodiment or example.

[0106] The technical features of the above-mentioned embodiments can be combined arbitrarily. In order to make the description concise, not all possible combinations of the technical features of the above-mentioned embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0107] The above-described embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be construed as limiting the scope of the patent application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent application shall be subject to the attached claims.

Claims

1. A method for preparing a semiconductor structure, characterized in that: include: providing a substrate having a plurality of grooves; forming a first dielectric material layer on the upper surface of the substrate and the inner wall of the groove; forming a gate material layer on a side of the first dielectric material layer away from the substrate, wherein the gate material layer fills the groove; Using the first dielectric material layer as a stop layer, chemical mechanical polishing is performed on the gate material layer to form a first gate intermediate layer, wherein the chemical mechanical polishing has a first loading effect; Performing atomic layer etching on the first dielectric material layer to form a first dielectric layer; The first gate intermediate layer is subjected to a preset dry etching to form a gate, wherein the preset dry etching has a second load effect, and the second load effect and the first load effect are reverse load effects to each other.

2. The method for preparing a semiconductor structure according to claim 1, characterized in that: The step of performing atomic layer etching on the first dielectric material layer to form a first dielectric layer includes: Performing a first atomic layer etching on the first dielectric material layer to form the first dielectric layer.

3. The method for preparing a semiconductor structure according to claim 2, characterized in that: The first dielectric material layer includes at least two sub-dielectric material layers, and the first dielectric layer includes at least two sub-dielectric layers; When performing the first atomic layer etching on the first dielectric material layer, different etching gases are used to etch each of the sub-dielectric material layers respectively, and the remaining part of each of the sub-dielectric material layers after etching forms the corresponding sub-dielectric layer.

4. The method for preparing a semiconductor structure according to claim 3, characterized in that: When each of the sub-medium material layers is respectively etched, the steps include: Passing a first reaction gas to react and modify the sub-medium material layer; A second reaction gas is introduced to react with the modified sub-dielectric material layer to generate a volatile gas.

5. The method for preparing a semiconductor structure according to claim 1, characterized in that: The step of performing a preset dry etching on the first gate intermediate layer to form a gate comprises: Performing a preset dry etching on the first gate intermediate layer to form a second gate intermediate layer; Performing a second atomic layer etching on the second gate intermediate layer to form the gate; The step of performing a second atomic layer etching on the second gate intermediate layer to form the gate includes: Passing a third reaction gas to react and modify the second gate intermediate layer; A fourth reaction gas is introduced to react with the modified second grid intermediate layer to generate a volatile gas.

6. The method for preparing a semiconductor structure according to claim 1, characterized in that: The first dielectric material layer includes a first sub-dielectric material layer and a second sub-dielectric material layer sequentially arranged on one side of the substrate, the first sub-dielectric material layer is used to adjust the work function of the semiconductor structure, and the second sub-dielectric material layer is located on a side close to the gate.

7. The method for preparing a semiconductor structure according to claim 6, characterized in that: The step of using the first dielectric material layer as a stop layer and performing chemical mechanical polishing on the gate material layer to form a first gate intermediate layer comprises: The second sub-dielectric material layer is used as a stop layer, and the gate material layer is subjected to chemical mechanical polishing to form the first gate intermediate layer.

8. The method for preparing a semiconductor structure according to claim 1, characterized in that: Before the step of forming a first dielectric material layer on the upper surface of the substrate and the inner wall of the groove, the method further includes: A second dielectric layer is formed at the bottom of the groove.

9. The method for preparing a semiconductor structure according to claim 1, characterized in that: The gate material layer is made of aluminum metal.

10. A semiconductor structure, characterized in that: The semiconductor structure is prepared according to the method for preparing a semiconductor structure according to any one of claims 1 to 9.

Images