Formation method of semiconductor device

Abstract

A method for forming a semiconductor device comprises the following steps: providing a substrate on which a metal hard mask layer is formed; forming a patterned photoresist layer on the metal hard mask layer; performing plasma etching on the metal hard mask layer by taking the patterned photoresist layer as a mask so as to expose the substrate; performing plasma bombardment on the photoresist layer and the exposed substrate by adopting a plasma surface treatment process to obtain a bombarded photoresist layer and a bombarded substrate; and the photoresist layer after bombardment is removed, and the substrate after bombardment is etched. According to the invention, the problem of residual defects on the substrate can be improved, and the etching effect of substrate etching is improved.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor manufacturing, and in particular to a method for forming a semiconductor device. Background Art

[0002] In various semiconductor manufacturing technologies, it is necessary to etch the substrate, such as the Through Silicon Via (TSV) technology for forming interconnections between wafers, between chips, or between a chip and a substrate, and the Shallow Trench Isolation (STI) technology for forming shallow trench isolation regions between different semiconductor devices on a semiconductor substrate.

[0003] In some substrate etching processes, in order to improve the protection of the substrate, a metal hard mask layer needs to be used as an etching protection layer to improve the profile fineness of the etched groove.

[0004] However, in the existing metal hard mask layer etching process, high-energy ion bombardment is required to provide sufficient kinetic energy to destroy chemical bonds, resulting in the particles of the metal hard mask layer being easily sputtered onto the surface of the photoresist layer and affecting the removal of the photoresist in the subsequent step of removing the photoresist layer.

[0005] In the prior art, a wet etching process is subsequently used to remove the metal hard mask layer on the surface of the device. However, due to the presence of a residual photoresist layer, part of the metal hard mask layer cannot be removed by the wet etching process, resulting in defects.

[0006] There is an urgent need for a method for forming a semiconductor device that can reduce the impact of sputtered particles on the device during a metal hard mask layer etching process and improve wafer production quality. Summary of the invention

[0007] The technical problem solved by the present invention is to provide a method for forming a semiconductor device, which can improve the problem of residual defects on a substrate and enhance the etching effect of substrate etching.

[0008] To solve the above technical problems, an embodiment of the present invention provides a method for forming a semiconductor device, comprising: providing a substrate, on which a metal hard mask layer is formed; forming a patterned photoresist layer on the metal hard mask layer; using the patterned photoresist layer as a mask, plasma etching the metal hard mask layer to expose the substrate; using a plasma surface treatment process to plasma bombard the photoresist layer and the exposed substrate to obtain a bombarded photoresist layer and a bombarded substrate; removing the bombarded photoresist layer and etching the bombarded substrate.

[0009] Optionally, before plasma bombarding the photoresist layer and the exposed substrate, the method further includes: determining the bias power of the plasma bombardment process according to the bias power of the plasma etching; and adjusting the bias power of the etching chamber to the bias power of the plasma bombardment process.

[0010] Optionally, the bias power actually used in the step of performing plasma etching on the metal hard mask layer is less than the process specification lower limit of the standard bias power used to etch the metal hard mask layer; determining the bias power of the plasma bombardment process according to the bias power of the plasma etching, including: determining the power difference between the process specification lower limit of the standard bias power of the plasma etching and the bias power actually used for the plasma etching, recorded as a first power difference; determining a second power difference at least according to the first power difference, the second power difference being used to represent the difference between a preset standard bias power of the plasma bombardment process and the bias power actually to be used for the plasma bombardment process; using the difference between the preset standard bias power of the plasma bombardment process and the second power difference as the bias power of the plasma bombardment process; wherein, the larger the first power difference, the smaller the second power difference.

[0011] Optionally, a second power difference is determined at least based on the first power difference, including: determining the ratio of the first power difference to the lower limit of the process specification of the standard bias power of the plasma etching, and determining a first power influence factor based on a weighted calculation result of the ratio; determining the etching time to be adopted by the plasma bombardment process and the percentage it occupies in the process specification of its standard etching time, and determining the time influence factor based on the percentage and the standard bias power of the plasma bombardment process; determining the second power difference based on the first power influence factor and the time influence factor.

[0012] Optionally, the second power difference is determined by the following formula:

[0013]

[0014] Wherein, ΔP2 is used to represent the second power difference, ΔP1 is used to represent the first power difference, P l is used to represent the lower limit value of the process specification of the standard bias power of the plasma etching, w1 is used to represent the preset first weight, and 0≤w1≤1; T is used to represent the etching time to be adopted in the plasma bombardment process, T u The process specification upper limit value used to represent the standard etching time of the plasma bombardment process, T lThe lower limit value of the process specification for the standard etching time of the plasma bombardment process, P s It is used to represent the standard bias power of the plasma bombardment process, w2 is used to represent the preset second weight, and offset is used to represent the offset.

[0015] Optionally, one or more of the following is satisfied: a process specification lower limit value of a standard bias power for etching the metal hard mask layer is selected from: 180W to 220W; and the first power difference is selected from: 100W to 150W.

[0016] Optionally, the metal hard mask layer is a high-K value metal material layer; and the bombarded substrate is etched to obtain a through silicon via TSV.

[0017] Optionally, the etching gas used for plasma etching the metal hard mask layer contains argon, and the plasma surface treatment process is an argon plasma bombardment process.

[0018] Optionally, the material of the high-K value metal material layer is aluminum and its compounds; wherein the etching gas used for plasma etching the metal hard mask layer also contains BCl3 and Cl2.

[0019] Optionally, a patterned photoresist layer is formed on the metal hard mask layer, including: forming a dielectric layer on the metal hard mask layer, and then forming the patterned photoresist layer on the dielectric layer; removing the bombarded photoresist layer and etching the bombarded substrate, including: removing the bombarded photoresist layer to expose the dielectric layer; using the dielectric layer and the metal hard mask layer as patterned masks to etch the bombarded substrate.

[0020] Compared with the prior art, the technical solution of the embodiment of the present invention has the following beneficial effects:

[0021] In an embodiment of the present invention, after the metal hard mask layer is subjected to plasma etching, by adding a step of plasma bombarding the photoresist layer and the exposed substrate using a plasma surface treatment process, the metal hard mask layer particles retained on the photoresist layer can be effectively reduced, and the cleanliness of the device after the reaction can be improved, thereby effectively reducing the possibility of residual photoresist layer, which is helpful to improve the problem of residual defects on the substrate and improve the etching effect of substrate etching.

[0022] Furthermore, according to the bias power of the plasma etching, the bias power of the plasma bombardment process is determined, and the bias power of the etching chamber is adjusted to the bias power of the plasma bombardment process, so that the plasma bombardment process can be improved, and the selection of bias power is more suitable for the current environment and other predetermined parameters. Compared with relying on manual experience to determine the bias power, the accuracy and efficiency of bias power selection can be effectively improved, and a better balance can be achieved between improving the cleanliness of particle removal and protecting the substrate of the device.

[0023] Furthermore, the bias power actually used in the step of plasma etching the metal hard mask layer is less than the lower limit of the process specification of the standard bias power used to etch the metal hard mask layer, so that in the first round of bias power determination step, the reduced bias power can be used to effectively control the bias power within a certain low range, which helps to reduce the situation where the excessive bias power damages the device substrate. And, by determining the first power difference, at least according to the first power difference, the second power difference is determined; the difference between the preset standard bias power of the plasma bombardment process and the second power difference is used as the bias power of the plasma bombardment process, wherein the larger the first power difference, the smaller the second power difference, so that in the second round of bias power determination step, the available bias power can be determined by combining the preset lower limit of the process specification of the standard bias power of the plasma etching process and the standard bias power of the plasma bombardment process, so that it is more suitable for the current environment and other predetermined parameters, and the accuracy and efficiency of the standard bias selection are further improved.

[0024] Furthermore, in the second round of bias power determination step, the influence of the current bias power on the device can be determined by determining the first power influence factor, and then the influence of the etching time to be adopted in the current plasma bombardment process on the device can be determined by determining the time influence factor. Since excessive bias power and excessive etching time will reduce device quality, too small bias power and too short etching time will reduce the degree of particle removal, determining the second power difference in combination with the weighted results of the first power influence factor and the time influence factor will help to achieve a balance between bias power and etching time, thereby better protecting the device substrate while better improving the particle removal cleanliness.

[0025] Furthermore, one or more of the following is met: the lower limit value of the process specification of the standard bias power for etching the metal hard mask layer is selected from: 180W to 220W, the first power difference is selected from: 100W to 150W, and the first power difference can be used to reduce the bias power to a greater extent in the first round of bias power determination step, thereby protecting the substrate of the device to a greater extent.

[0026] Furthermore, one or more of the following conditions are met: the metal hard mask layer is a high-K value metal material layer; the through-silicon via TSV is obtained by etching the bombarded substrate. Since the formation of TSV has requirements such as better electrical performance, lower power consumption, wider bandwidth, higher density, and smaller dimensions, and in order to have a higher charge storage capacity, a metal hard mask layer material with a higher K value is used, which makes it more difficult to remove particles from the metal hard mask layer and increases the protection requirements for the substrate of the device. On this basis, by adopting the above scheme, the actual bias power used in the plasma bombardment process can be better determined, so that the cleanliness of particle removal can be improved and the substrate of the device can be effectively protected.

[0027] Furthermore, the etching gas used for plasma etching the metal hard mask layer contains argon, and the plasma surface treatment process is an argon plasma bombardment process. Therefore, the argon used in the previous process step can be used for the argon plasma bombardment process in the next step, effectively reducing the process cost and improving the process efficiency.

[0028] Furthermore, by forming a dielectric layer on the metal hard mask layer and then forming the patterned photoresist layer on the dielectric layer, in the process of removing the bombarded photoresist layer and etching the bombarded substrate, the bombarded photoresist layer can be first removed to expose the dielectric layer, and then the bombarded substrate is etched using the dielectric layer and the metal hard mask layer as patterned masks, thereby protecting the metal hard mask layer through the dielectric layer, which helps to further reduce the possibility of the metal hard mask layer being bombarded to generate particles and being adsorbed, thereby improving device quality. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figures 1 to 3 It is a schematic diagram of a device cross-sectional structure corresponding to each step in a method for forming a semiconductor device in the prior art;

[0030] Figure 4 is a flow chart of a method for forming a semiconductor device in an embodiment of the present invention;

[0031] Figures 5 to 9 It is a schematic diagram of a device cross-sectional structure corresponding to each step in a method for forming a semiconductor device in an embodiment of the present invention.

[0032] Description of reference numerals:

[0033] Substrate 100 , metal hard mask layer 110 , photoresist layer 130 , particles 141 , substrate 200 , metal hard mask layer 210 , dielectric layer 220 , photoresist layer 230 , polymer layer 240 , particles 241 . DETAILED DESCRIPTION

[0034] As mentioned above, in the existing partial substrate etching process, in order to improve the protection of the substrate, a metal hard mask layer needs to be used as an etching protection layer to improve the profile fineness of the etched groove.

[0035] However, in the metal hard mask layer etching process, high-energy ion bombardment is required to provide sufficient kinetic energy to destroy chemical bonds, resulting in the particles of the metal hard mask layer being easily sputtered onto the surface of the photoresist layer and affecting the removal of the photoresist in the subsequent step of removing the photoresist layer.

[0036] Next, in the process of removing the metal hard mask layer on the surface of the device by a wet etching process, due to the presence of the residual photoresist layer, part of the metal hard mask layer cannot be removed by the wet etching process, resulting in defects.

[0037] Figures 1 to 3 It is a schematic diagram of the device cross-sectional structure corresponding to each step in a method for forming a semiconductor device in the prior art.

[0038] Reference Figure 1 , providing a substrate 100, on which a metal hard mask layer 110 is formed, on which a patterned photoresist layer 130 is formed, and using the patterned photoresist layer 130 as a mask, etching the metal hard mask layer 110 to expose the substrate 100.

[0039] The high energy ion bombardment may cause the particles 141 of the metal hard mask layer 110 to be easily sputtered onto the surface of the photoresist layer 130 .

[0040] Reference Figure 2 , remove the photoresist layer 130.

[0041] In particular, due to the influence of the particles 141 of the metal hard mask layer 110 , the photoresist layer 130 under the particles 141 is difficult to be removed and remains.

[0042] Reference Figure 3 , using the metal hard mask layer 110 as a mask, etching the substrate 100, and then removing the metal hard mask layer 110.

[0043] Part of the metal hard mask layer 110 cannot be removed by the wet etching process due to the residual photoresist layer 130 , and remains on the substrate 100 to generate defects.

[0044] After research, it was found that in the prior art, since the process of removing the photoresist layer 130 and the process of etching the substrate 100 cannot remove the particles 141 of the metal hard mask layer 110, in the process of removing the metal hard mask layer 110, although the particles 141 can be removed, the residual photoresist layer 130 cannot be removed, resulting in residual defects on the substrate 100.

[0045] In an embodiment of the present invention, after the metal hard mask layer is subjected to plasma etching, by adding a step of plasma bombarding the photoresist layer and the exposed substrate using a plasma surface treatment process, the metal hard mask layer particles retained on the photoresist layer can be effectively reduced, and the cleanliness of the device after the reaction can be improved, thereby effectively reducing the possibility of residual photoresist layer, which is helpful to improve the problem of residual defects on the substrate and improve the etching effect of substrate etching.

[0046] In order to make the above-mentioned objects, features and beneficial effects of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0047] Reference Figure 4 , Figure 4 1 is a flow chart of a method for forming a semiconductor device in an embodiment of the present invention. The method for forming a semiconductor device may include steps S41 to S45:

[0048] Step S41: providing a substrate, on which a metal hard mask layer is formed;

[0049] Step S42: forming a patterned photoresist layer on the metal hard mask layer;

[0050] Step S43: using the patterned photoresist layer as a mask, performing plasma etching on the metal hard mask layer to expose the substrate;

[0051] Step S44: using a plasma surface treatment process to perform plasma bombardment on the photoresist layer and the exposed substrate to obtain a bombarded photoresist layer and a bombarded substrate;

[0052] Step S45: removing the bombarded photoresist layer and etching the bombarded substrate.

[0053] The above steps are described below.

[0054] Figures 5 to 9 It is a schematic diagram of a device cross-sectional structure corresponding to each step in a method for forming a semiconductor device in an embodiment of the present invention.

[0055] Reference Figure 5, providing a substrate 200 , on which a metal hard mask layer 210 is formed; and forming a patterned photoresist layer 230 on the metal hard mask layer 210 .

[0056] The substrate 200 may include a semiconductor substrate, and its material may include silicon, germanium, silicon germanium, silicon carbide, gallium arsenide or indium gallium. The substrate 200 may also include a structure located on the surface of the semiconductor substrate, such as a gate oxide layer, etc., and is not limited to the portion within the surface of the semiconductor substrate. Figure 5 The illustrated substrate 200 may be a semiconductor substrate and a dielectric layer 220 thereon, such as tetraethyl orthosilicate (TEOS).

[0057] The material of the metal hard mask layer 210 may be a high-K value (high dielectric constant) metal material layer, so that it may have a higher charge storage capability and be used to form a suitable structure, such as an interconnection structure.

[0058] Furthermore, the material of the high-K value metal material layer may be aluminum and its compounds, which helps to better meet the requirements of the semiconductor device for the ability to store charges.

[0059] Further, in Figure 5 In the semiconductor device shown, the step of forming the patterned photoresist layer 230 on the metal hard mask layer 210 may include: forming a dielectric layer 220 on the metal hard mask layer 210 , and then forming the patterned photoresist layer 230 on the dielectric layer 220 .

[0060] The dielectric layer 220 may be a silicon oxide layer, a silicon nitride layer, or a stacked structure of a silicon oxide layer and a silicon nitride layer. The silicon oxide may be, for example, SiO2, and the silicon nitride may be, for example, Si3N4.

[0061] It should be pointed out that, further, the step of forming the patterned photoresist layer 230 on the dielectric layer 220 may include: forming a photoresist layer 230 and a polymer layer 240 on the dielectric layer 220; patterning the photoresist layer 230 and the polymer layer 240 to obtain a patterned photoresist layer 230; and etching the dielectric layer 220 using the patterned photoresist layer 230 as a mask to obtain a stack of the patterned photoresist layer 230 and the dielectric layer 220.

[0062] In the embodiment of the present invention, by forming a dielectric layer 220 on the metal hard mask layer 210 and then the patterned photoresist layer 230, in the process of removing the bombarded photoresist layer 230 and etching the bombarded substrate 200, the bombarded photoresist layer 230 is first removed to expose the dielectric layer 220, and then the bombarded substrate 200 is etched using the dielectric layer 220 and the metal hard mask layer 210 as patterned masks, thereby protecting the metal hard mask layer 210 through the dielectric layer 220, which helps to further reduce the possibility of the metal hard mask layer 210 being bombarded to generate particles and being adsorbed, thereby improving the device quality.

[0063] In a specific embodiment, the polymer layer 240 can exist independently of the photoresist layer 230, and its material can be an olefin monomer that generates free radicals under the action of light and further initiates the polymerization of the monomers to generate a polymer, such as acrylic acid and methacrylic acid monomers through free radical polymerization.

[0064] In another specific implementation, the polymer layer 240 may also be a component constituting the photoresist layer 230 , and the performance of the photoresist layer 230 may be effectively improved by being integrated into the photoresist layer 230 .

[0065] In a specific implementation, by forming the polymer layer 240 , the protection of the photoresist layer 230 can be improved during the patterning process of the photoresist layer 230 , providing a better morphology basis for the subsequent etching of the dielectric layer 220 and the metal hard mask layer 210 .

[0066] Reference Figure 6 , using the patterned photoresist layer 230 as a mask, the metal hard mask layer 210 is plasma etched to expose the substrate 200 .

[0067] In the plasma etching process, high energy ion bombardment may cause the particles 241 of the metal hard mask layer 210 to be easily sputtered onto the surface of the photoresist layer 230 .

[0068] Furthermore, the material of the high-K value metal material layer is aluminum and its compounds; wherein the etching gas used for plasma etching the metal hard mask layer 210 may contain BCl3 and Cl2.

[0069] In a specific implementation, by additionally adding BCl3, chlorine (Cl) ions can be used to react with aluminum to remove aluminum. Further, chlorine (Cl) ions can also be used to react with aluminum byproducts.

[0070] Specifically, aluminum by-products may include Al2O3 compounds obtained by the reaction of aluminum with air and AlF3 compounds obtained by the reaction of aluminum with fluorine-containing gases. They fall on the wafer surface and are adsorbed on the side walls or top inner surfaces of the chamber, affecting the etching effect of the current wafer and subsequent wafers.

[0071] Among them, Al2O3 can be removed by reacting chlorine (Cl) ions with Al2O3 through the following chemical reaction formula:

[0072] Al2O3+Cl - →AlCl3↑

[0073] AlF3 can also be removed by reacting chlorine (Cl) ions with AlF3 through the following chemical reaction formula:

[0074]

[0075] In the embodiment of the present invention, by additionally adding BCl3, Cl ions can be used to react with it to remove aluminum and its aluminum by-products, thereby improving the problems caused by aluminum by-products.

[0076] Furthermore, the etching gas may also contain Cl 2. Compared with adding only BCl 3, the Cl ion concentration in the etching chamber can be increased, thereby increasing the speed of forming AlCl 3 by reaction, improving etching efficiency and wafer cleanliness.

[0077] Reference Figure 7 , a plasma surface treatment process is used to perform plasma bombardment on the photoresist layer 230 and the exposed substrate 200 to obtain a bombarded photoresist layer 230 and a bombarded substrate 200.

[0078] It should be pointed out that, in the embodiment of the present invention, the effect of plasma bombardment on the photoresist layer 230 and the exposed substrate 200 can be improved by specially adjusting the bias power of the plasma bombardment process.

[0079] Specifically, before plasma bombarding the photoresist layer 230 and the exposed substrate 200, the method may further include: determining the bias power of the plasma bombardment process according to the bias power of the plasma etching; and adjusting the bias power of the etching chamber to the bias power of the plasma bombardment process.

[0080] In an embodiment of the present invention, the bias power of the plasma bombardment process is determined according to the bias power of the plasma etching, and the bias power of the etching chamber is adjusted to the bias power of the plasma bombardment process, so that the plasma bombardment process can be improved, and the selection of the bias power is more suitable for the current environment and other predetermined parameters. Compared with relying on manual experience to determine the bias power, the accuracy and efficiency of the bias power selection can be effectively improved, and a better balance can be achieved between improving the cleanliness of particle removal and protecting the substrate 200 of the device.

[0081] Further, the bias power actually used in the step of plasma etching the metal hard mask layer 210 is less than the process specification lower limit of the standard bias power used to etch the metal hard mask layer 210; the step of determining the bias power of the plasma bombardment process according to the bias power of the plasma etching may include: determining the power difference between the process specification lower limit of the standard bias power of the plasma etching and the bias power actually used for the plasma etching, recorded as a first power difference; determining a second power difference at least according to the first power difference, the second power difference being used to represent the difference between the preset standard bias power of the plasma bombardment process and the bias power actually to be used for the plasma bombardment process; and using the difference between the preset standard bias power of the plasma bombardment process and the second power difference as the bias power of the plasma bombardment process; wherein, the larger the first power difference, the smaller the second power difference.

[0082] In an embodiment of the present invention, the bias power actually used in the step of plasma etching the metal hard mask layer 210 is less than the lower limit of the process specification of the standard bias power used to etch the metal hard mask layer 210, so that in the first round of bias power determination step, a reduced bias power can be used to effectively control the bias power within a certain low range, which helps to reduce the situation where excessive bias power damages the device substrate.

[0083] In addition, the first power difference is used to represent the power difference between the lower limit of the process specification of the standard bias power of plasma etching and the bias power actually used in the plasma etching. Since the actually used bias power is relatively small, the power difference is a positive rational number, and the larger the value of the first power difference is, the smaller the actually used bias power is.

[0084] The second power difference is used to represent the difference between the preset standard bias power of the plasma bombardment process and the bias power actually to be adopted in the plasma bombardment process, so that after determining the second power difference according to the first power difference by utilizing the correlation between the two offsets, the bias power of the plasma bombardment process actually used can be determined by calculating the difference between the preset standard bias power of the plasma bombardment process and the second power difference.

[0085] In an embodiment of the present invention, a second power difference is determined by determining a first power difference, at least based on the first power difference; and a difference between the preset standard bias power of the plasma bombardment process and the second power difference is used as the bias power of the plasma bombardment process.

[0086] Among them, the larger the first power difference is, the smaller the second power difference is. Therefore, in the second round of bias power determination step, the available bias power can be determined by combining the pre-set process specification lower limit of the standard bias power of the plasma etching process and the standard bias power of the plasma bombardment process, making it more suitable for the current environment and other predetermined parameters, further improving the accuracy and efficiency of the standard bias selection.

[0087] Furthermore, at least based on the first power difference, the step of determining the second power difference may include: determining the ratio of the first power difference to the lower limit of the process specification of the standard bias power of the plasma etching, and determining the first power influence factor based on the weighted operation result of the ratio; determining the etching time to be adopted by the plasma bombardment process and the percentage it occupies in the process specification of its standard etching time, and determining the time influence factor based on the percentage and the standard bias power of the plasma bombardment process; determining the second power difference based on the first power influence factor and the time influence factor.

[0088] Specifically, since the first power influence factor is determined by the ratio of the first power difference to the lower limit of the process specification of the standard bias power of the plasma etching, and is determined based on the weighted operation result of the ratio, the degree of influence of the current bias power on the device can be determined by determining the first power influence factor.

[0089] In addition, since excessive bias power and excessive etching time will reduce device quality, and excessive bias power and excessively short etching time will reduce the degree of particle removal, the second power difference is determined by combining the weighted results of the first power influence factor and the time influence factor. On this basis, the determined second power difference helps to achieve a balance between bias power and etching time.

[0090] In an embodiment of the present invention, in the second round of bias power determination step, the influence of the current bias power on the device can be determined by determining the first power influence factor, and then the influence of the etching time to be adopted in the current plasma bombardment process on the device can be determined by determining the time influence factor. Since excessive bias power and excessive etching time will reduce device quality, and excessive bias power and excessively short etching time will reduce the degree of particle removal, determining the second power difference in combination with the weighted results of the first power influence factor and the time influence factor is helpful to achieve a balance between bias power and etching time, thereby better protecting the substrate of the device while better improving the particle removal cleanliness.

[0091] Furthermore, the second power difference may be determined by using the following formula:

[0092]

[0093] Wherein, ΔP2 is used to represent the second power difference, ΔP1 is used to represent the first power difference, P l is used to represent the lower limit value of the process specification of the standard bias power of the plasma etching, w1 is used to represent the preset first weight, and 0≤w1≤1; T is used to represent the etching time to be adopted in the plasma bombardment process, T u The process specification upper limit value used to represent the standard etching time of the plasma bombardment process, T l The lower limit value of the process specification for the standard etching time of the plasma bombardment process, P s It is used to represent the standard bias power of the plasma bombardment process, w2 is used to represent the preset second weight, and offset is used to represent the offset.

[0094] The offset may be used to adjust the second power difference according to historical experience data or product data of other similar process platforms, and may also be set to zero.

[0095] In another specific implementation of the embodiment of the present invention, the following formula may be used to determine the second power difference at least according to the first power difference:

[0096]

[0097] Among them, the various parameters in the formula can be determined by referring to the previous text and will not be repeated here.

[0098] Further, the method satisfies one or more of the following conditions: a process specification lower limit value of a standard bias power for etching the metal hard mask layer 210 is selected from: 180W to 220W, and the first power difference value is selected from: 100W to 150W.

[0099] In an embodiment of the present invention, by setting a suitable process specification lower limit value of the standard bias power of the metal hard mask layer 210, the bias power can be reduced to a greater extent in the first round of bias power determination step through the first power difference, thereby protecting the substrate of the device to a greater extent.

[0100] exist Figure 7 In the illustrated method, after the bias power of the etching chamber is adjusted to the bias power of the plasma bombardment process, a plasma surface treatment process may be used to perform plasma bombardment on the photoresist layer 230 and the exposed substrate 200 .

[0101] Furthermore, the plasma surface treatment process can be selected from: an argon plasma bombardment process, a nitrogen plasma bombardment process, and other inert gas plasma bombardment processes except argon.

[0102] In a specific implementation, by using nitrogen, inert gas, etc. for plasma bombardment process, the impact on device performance can be reduced.

[0103] Furthermore, the etching gas used for plasma etching the metal hard mask layer 210 contains argon, and the plasma surface treatment process is an argon plasma bombardment process.

[0104] In the embodiment of the present invention, the argon gas used in the previous process step can be used to carry out the argon plasma bombardment process in the next step, thereby effectively reducing the process cost and improving the process efficiency.

[0105] Further, one or more of the following conditions may be satisfied: the metal hard mask layer 210 is a high-K value metal material layer; and the through silicon via TSV is obtained by etching the bombarded substrate 200 .

[0106] Since the formation of TSV has the requirements of better electrical performance, lower power consumption, wider bandwidth, higher density, smaller size, etc., and in order to have a higher charge storage capacity, a metal hard mask layer 210 material with a higher K value is used, which makes it more difficult to remove particles in the metal hard mask layer 210 and increases the protection demand for the device substrate 200.

[0107] In the embodiment of the present invention, the above solution is adopted to better determine the bias power actually used in the plasma bombardment process, so as to better improve the particle removal cleanliness and effectively protect the substrate 200 of the device.

[0108] Reference Figure 8 , removing the bombarded photoresist layer 230 and etching the bombarded substrate 200 .

[0109] As shown in the figure, after removing the photoresist layer 230 , the dielectric layer 220 may be exposed, and the bombarded substrate 200 may be etched using the dielectric layer 220 and the metal hard mask layer 210 as patterned masks.

[0110] In the embodiment of the present invention, by forming a dielectric layer 220 on the metal hard mask layer 210 and then the patterned photoresist layer 230, in the process of removing the bombarded photoresist layer 230 and etching the bombarded substrate 200, the bombarded photoresist layer 230 is first removed to expose the dielectric layer 220, and then the bombarded substrate 200 is etched using the dielectric layer 220 and the metal hard mask layer 210 as patterned masks, thereby protecting the metal hard mask layer 210 through the dielectric layer 220, which helps to further reduce the possibility of the metal hard mask layer 210 being bombarded to generate particles and being adsorbed, thereby improving the device quality.

[0111] Reference Fig. 9 , remove the dielectric layer 220 and the metal hard mask layer 210 to obtain the etched substrate 200.

[0112] In the embodiment of the present invention, after the metal hard mask layer 210 is subjected to plasma etching, the photoresist layer 230 (see Figure 6 ) and the exposed substrate 200 are subjected to plasma bombardment, which can effectively reduce the metal hard mask layer 200 particles 241 remaining on the photoresist layer 230 (refer to Figure 6 ), improve the cleanliness of the device after the reaction, thereby effectively reducing the possibility of residual photoresist layer 230, which is helpful to improve the residual defect problem on the substrate 200 and improve the etching effect of the substrate 200.

[0113] It should be understood that the term "and / or" in this article is only a description of the association relationship of the associated objects, indicating that there can be three relationships. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. In addition, the character " / " in this article indicates that the associated objects before and after are in an "or" relationship.

[0114] The "plurality" appearing in the embodiments of the present application refers to two or more.

[0115] The first, second, etc. descriptions appearing in the embodiments of the present application are only used for illustration and distinction of the description objects. There is no order, nor do they indicate any special limitation on the number of devices in the embodiments of the present application, and cannot constitute any limitation on the embodiments of the present application.

[0116] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A method for forming a semiconductor device, characterized in that: include: providing a substrate, wherein a metal hard mask layer is formed on the substrate; forming a patterned photoresist layer on the metal hard mask layer; Using the patterned photoresist layer as a mask, plasma-etching the metal hard mask layer to expose the substrate; Using a plasma surface treatment process, the photoresist layer and the exposed substrate are subjected to plasma bombardment to obtain a bombarded photoresist layer and a bombarded substrate; The bombarded photoresist layer is removed and the bombarded substrate is etched.

2. The method according to claim 1, characterized in that Before plasma bombarding the photoresist layer and the exposed substrate, the method further comprises: Determining the bias power of the plasma bombardment process according to the bias power of the plasma etching; The bias power of the etching chamber is adjusted to the bias power of the plasma bombardment process.

3. The method according to claim 2, characterized in that The bias power actually used in the step of performing plasma etching on the metal hard mask layer is less than the process specification lower limit value of the standard bias power used for etching the metal hard mask layer; Determining the bias power of the plasma bombardment process according to the bias power of the plasma etching includes: Determine a power difference between a process specification lower limit value of a standard bias power of the plasma etching and a bias power actually used in the plasma etching, and record it as a first power difference; Determining a second power difference value at least according to the first power difference value, wherein the second power difference value is used to represent a difference between a preset standard bias power of the plasma bombardment process and a bias power actually to be used in the plasma bombardment process; Using the difference between the preset standard bias power of the plasma bombardment process and the second power difference as the bias power of the plasma bombardment process; The larger the first power difference is, the smaller the second power difference is.

4. The method according to claim 3, characterized in that Determining a second power difference value at least according to the first power difference value includes: Determine a ratio of the first power difference to a lower limit of a process specification of a standard bias power of the plasma etching, and determine a first power influence factor based on a weighted calculation result of the ratio; Determine the etching time to be adopted by the plasma bombardment process and the percentage of the etching time in the process specification of the standard etching time, and determine the time influencing factor based on the percentage and the standard bias power of the plasma bombardment process; The second power difference is determined according to the first power impact factor and the duration impact factor.

5. The method according to claim 4, characterized in that The second power difference is determined by the following formula: Wherein, ΔP2 is used to represent the second power difference, ΔP1 is used to represent the first power difference, P l is used to represent the lower limit value of the process specification of the standard bias power of the plasma etching, w1 is used to represent a preset first weight, and 0≤w1≤1; T is used to represent the etching time to be adopted in the plasma bombardment process, T u The process specification upper limit value used to represent the standard etching time of the plasma bombardment process, T l The lower limit value of the process specification for the standard etching time of the plasma bombardment process, P s It is used to represent the standard bias power of the plasma bombardment process, w2 is used to represent the preset second weight, and offset is used to represent the offset.

6. The method according to any one of claims 3 to 5, characterized in that: Meet one or more of the following: The lower limit value of the process specification of the standard bias power for etching the metal hard mask layer is selected from: 180W to 220W; The first power difference is selected from: 100W to 150W.

7. The method according to claim 1, characterized in that Meet one or more of the following: The metal hard mask layer is a high-K value metal material layer; The bombarded substrate is etched to obtain a through silicon via TSV.

8. The method according to claim 7, characterized in that The etching gas used for plasma etching the metal hard mask layer contains argon gas, and the plasma surface treatment process is an argon plasma bombardment process.

9. The method according to claim 8, characterized in that The material of the high-K value metal material layer is aluminum and its compounds; Wherein, the etching gas used for plasma etching the metal hard mask layer also contains BCl3 and Cl2.

10. The method according to claim 1, characterized in that Forming a patterned photoresist layer on the metal hard mask layer, comprising: forming a dielectric layer on the metal hard mask layer, and then forming the patterned photoresist layer on the dielectric layer; Removing the bombarded photoresist layer and etching the bombarded substrate, comprising: removing the bombarded photoresist layer to expose the dielectric layer; The bombarded substrate is etched using the dielectric layer and the metal hard mask layer as patterned masks.

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