TGV substrate integrated packaging method and packaging structure

Abstract

The invention provides a TGV substrate integrated packaging method and packaging structure, and relates to the technical field of semiconductor packaging. The TGV substrate integrated packaging method comprises the following steps: a first substrate is a glass substrate; the first substrate comprises a first surface and a second surface which are oppositely arranged; a chip is mounted on the first surface, and a plastic package body wrapping the chip is formed on the first surface. And grinding and thinning the second surface. And forming a first through hole corresponding to the position of the electrode on the chip on the second surface. Forming a first groove in the second surface; and the first grooves are communicated with the first through holes in the corresponding different chips. Forming a second through hole in the second surface; the second through hole corresponds to the first through hole in position and is communicated with the first through hole; the second through hole extends at least in the axial direction relative to the first through hole so as to expose the electrode. Forming a first metal layer in the first through hole, the second through hole and the first groove; the first metal layer is electrically connected with the electrode. The method is beneficial for improving the packaging efficiency and quality and reducing the hidden crack risk of the glass substrate.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor packaging, and in particular to a TGV substrate integrated packaging method and packaging structure. Background Art

[0002] TGV is the abbreviation of "Through Glass Via", which means glass penetration. Due to the inherent characteristics of glass substrates that are easy to break, in order to reduce the risk of fragmentation, the thickness of existing TGV glass substrates is usually thicker, which affects the overall packaging thickness. In addition, due to the thicker thickness of the glass substrate, the perforations made on it are deeper, and the depth-to-diameter ratio of the holes is larger, which is easy to produce voids when filling with metal, affecting the packaging quality. Summary of the invention

[0003] The object of the present invention is to provide a TGV substrate integrated packaging method and packaging structure, which can reduce the packaging thickness of the glass substrate, reduce the risk of glass substrate cracking, and improve the packaging quality and reliability.

[0004] In a first aspect, the present invention provides a TGV substrate integrated packaging method, comprising: A first substrate is provided; the first substrate is a glass substrate; the first substrate comprises a first surface and a second surface which are arranged opposite to each other; a chip is mounted on the first surface, and a plastic package covering the chip is formed; Grinding and thinning the second surface of the first substrate; A first through hole is formed on the second surface; the position of the first through hole corresponds to the position of the electrode on the chip; A first groove is formed on the second surface; the first groove is connected to the first through holes on corresponding different chips; A second through hole is formed on the second surface; the second through hole corresponds to the position of the first through hole and is connected to the first through hole; the second through hole is extended from the first through hole at least in the axial direction to expose the electrode; A first metal layer is formed in the first through hole, the second through hole and the first groove; and the first metal layer is electrically connected to the electrode.

[0005] In an optional embodiment, the step of providing a first substrate includes: An adhesive layer is formed between the first substrate and the chip; wherein the chip has a functional area on one side where the electrode is provided, the adhesive layer covers the surface of the chip on one side where the electrode is provided, and has an opening at a position corresponding to the functional area.

[0006] In an optional embodiment, in the step of forming a first through hole on the second surface, the first through hole penetrates the first substrate; In the step of forming a second through hole on the second surface, the second through hole penetrates the adhesive layer.

[0007] In an optional embodiment, the step of forming a first through hole on the second surface includes: irradiating a first area of ​​the second surface with a first laser, wherein the first area corresponds to a position of the electrode; etching the first region to form the first through hole; The step of forming a first groove on the second surface comprises: irradiating a second area of ​​the second surface with a second laser, wherein the second area is used to connect the first through holes between the corresponding different chips; The second region is etched to form the first groove; the depth of the first groove is smaller than the depth of the first through hole.

[0008] In an optional embodiment, the step of irradiating a first area of ​​the second surface with a first laser; and corroding the first area to form the first through hole comprises: irradiating a first area of ​​the second surface with a first laser; etching the first area to form a prefabricated groove; irradiating the bottom of the prefabricated groove with a third laser; etching the bottom of the prefabricated groove to form a through groove penetrating the first substrate, wherein the diameter of the through groove is smaller than the diameter of the prefabricated groove; The through groove and the prefabricated groove together form the first through hole.

[0009] In an optional embodiment, the step of forming a second through hole on the second surface includes: The adhesive layer corresponding to the electrode is removed by dry etching to form a second through hole connected to the first through hole on the adhesive layer.

[0010] In an optional embodiment, the step of forming a first metal layer in the first through hole, the second through hole and the first groove includes: forming a first metal layer on the entire second surface, and filling the first through hole, the second through hole and the first groove with the first metal layer; The first metal layer is ground to expose the second surface of the first substrate; wherein the surfaces of the first metal layer in the first through hole, the second through hole and the first groove are flush with the second surface respectively.

[0011] In an optional embodiment, it also includes: Mounting a second substrate on the second surface; A third through hole and a second groove are formed on the second substrate; A second metal layer is filled in the third through hole and the second groove; and the second metal layer is electrically connected to the first metal layer.

[0012] In an optional embodiment, it also includes: forming a solder resist layer covering the second surface; and opening a first window on the solder resist layer; The first window is filled with a third metal layer to form a pad; the pad is electrically connected to the first metal layer; Bumps are formed on the pads.

[0013] In a second aspect, the present invention provides a packaging structure, which is prepared by the TGV substrate integrated packaging method as described in any one of the aforementioned embodiments.

[0014] The TGV substrate integrated packaging method and packaging structure provided by the embodiments of the present invention have the following beneficial effects: First, a plastic encapsulation body is formed on one side of the glass substrate, and then the glass substrate is ground. During the grinding process, the plastic encapsulation body can play a supporting and buffering role, and the overall grinding of the complete glass substrate can greatly reduce the risk of cracking. After the glass substrate is ground, the first through hole, the first groove and the second through hole are formed to reduce the risk of cracking, reduce the thickness of the glass substrate, and achieve ultra-thin packaging. The first through hole formed in this way has a smaller depth-to-diameter ratio, better metal filling performance, less prone to voids, and better bonding between the metal and the glass substrate. Secondly, by opening the first groove on the glass substrate, the metal in the first groove is used for wiring of the circuit layer to achieve chip interconnection. Opening the first groove is conducive to improving the bonding between the metal and the glass substrate, preventing structural stratification, and improving the packaging quality. In addition, metal filling can be completed in the first through hole, the first groove and the second through hole at one time, with higher process efficiency and better bonding, which is conducive to improving packaging efficiency and packaging quality. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] In order to more clearly illustrate the specific implementation methods of the present invention or the technical solutions in the prior art, the drawings required for use in the specific implementation methods or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some implementation methods of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0016] Figure 1 A schematic diagram of the structure of preparing an adhesive layer in the TGV substrate integrated packaging method provided in an embodiment of the present invention; Figure 2 A schematic diagram of the structure of separating a wafer into a single chip in the TGV substrate integrated packaging method provided by an embodiment of the present invention; Figure 3A schematic diagram of the structure of attaching a chip to a first substrate in a TGV substrate integrated packaging method provided by an embodiment of the present invention; Figure 4 A schematic diagram of the structure of a plastic package body formed in the TGV substrate integrated packaging method provided by an embodiment of the present invention; Figure 5 A schematic diagram of a structure for forming a buffer groove in a plastic package body in a TGV substrate integrated packaging method provided by an embodiment of the present invention; Figure 6 A schematic diagram of the structure of thinning the first substrate in the TGV substrate integrated packaging method provided by an embodiment of the present invention; Figure 7 A schematic diagram of a structure for forming a first through hole and a first groove in a TGV substrate integrated packaging method provided in an embodiment of the present invention; Figure 8 Another structural schematic diagram of forming a first through hole in the TGV substrate integrated packaging method provided by an embodiment of the present invention; Fig. 9 A schematic diagram of a structure for forming a second through hole in a TGV substrate integrated packaging method provided by an embodiment of the present invention; Fig.10 A schematic diagram of a structure for forming a first metal layer in a TGV substrate integrated packaging method provided by an embodiment of the present invention; Fig.11 Another schematic diagram of the structure of a chip in the TGV substrate integrated packaging method provided by an embodiment of the present invention; Fig.12 for Fig.11 A local enlarged schematic diagram of the middle A; Fig.13 A schematic diagram of the structure of forming a solder resist layer and bumps in the TGV substrate integrated packaging method provided by an embodiment of the present invention; Fig.14 A schematic diagram of a structure for forming multi-layer wiring in a TGV substrate integrated packaging method provided by an embodiment of the present invention; Fig.15 A schematic diagram of a double-sided mounting structure formed in a TGV substrate integrated packaging method provided in an embodiment of the present invention.

[0017] Icon: 110-first substrate; 111-first surface; 112-second surface; 113-first through hole; 114-prefabricated groove; 115-through groove; 116-first groove; 120-chip; 121-electrode; 1211-micro bump; 1213-metal bonding layer; 122-functional area; 130-adhesive layer; 131-opening; 133-second through hole; 140-wafer; 150-plastic package; 151-buffer groove; 152-buffer block; 160-first metal layer; 161-electrical connection column; 162-wiring layer; 170-solder mask; 171-pad; 172-bump; 180-second substrate; 181-second metal layer; 190-conductive column; 191-connecting pad. DETAILED DESCRIPTION

[0018] In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Generally, the components of the embodiments of the present invention described and shown in the drawings here can be arranged and designed in various different configurations.

[0019] Therefore, the following detailed description of the embodiments of the present invention provided in the accompanying drawings is not intended to limit the scope of the invention claimed for protection, but merely represents selected embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0020] It should be noted that similar reference numerals and letters denote similar items in the following drawings, and therefore, once an item is defined in one drawing, further definition and explanation thereof is not required in subsequent drawings.

[0021] In the description of the present invention, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inside", "outside", etc. indicate positions or positional relationships based on the positions or positional relationships shown in the accompanying drawings, or the positions or positional relationships in which the product of the invention is usually placed when in use. They are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific position, be constructed and operated in a specific position, and therefore cannot be understood as limiting the present invention. In addition, the terms "first", "second", "third", etc. are only used to distinguish the description, and cannot be understood as indicating or implying relative importance.

[0022] In addition, the terms "horizontal", "vertical", "overhanging" and the like do not mean that the components are required to be absolutely horizontal or overhanging, but can be slightly tilted. For example, "horizontal" only means that its direction is more horizontal than "vertical", and does not mean that the structure must be completely horizontal, but can be slightly tilted.

[0023] In the description of the present invention, it is also necessary to explain that, unless otherwise clearly specified and limited, the terms "set", "install", "connect", and "connect" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, or it can be the internal communication of two elements. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0024] Some embodiments of the present invention are described in detail below in conjunction with the accompanying drawings. In the absence of conflict, the following embodiments and features in the embodiments can be combined with each other.

[0025] The TGV substrate integrated packaging method and packaging structure proposed in the embodiments of the present invention can realize the packaging of ultra-thin glass substrates, reduce the risk of hidden cracks in the glass substrate, and help improve the packaging quality and packaging efficiency.

[0026] The TGV substrate integrated packaging method generally includes the following packaging processes: S1. Provide a first substrate 110, which is a glass substrate. The first substrate 110 includes a first surface 111 and a second surface 112 that are opposite to each other. A chip 120 is mounted on the first surface 111, and a plastic package 150 covering the chip 120 is formed.

[0027] S2, grinding and thinning the second surface 112 of the first substrate 110.

[0028] It can be understood that during the grinding process, the plastic encapsulation body 150 first formed in step S1 can play a supporting and buffering role, and the overall grinding of the complete glass substrate can greatly reduce the risk of cracking. After grinding and thinning, the packaging of ultra-thin glass substrates can be achieved, greatly reducing the packaging height. It is worth noting that if the glass substrate is perforated first and then ground, this method will greatly increase the risk of hidden cracks in the glass substrate. Since the local strength of the glass substrate is weakened after perforation, grinding the entire substrate will cause the glass substrate to break. Therefore, in this embodiment, the entire substrate is first ground and thinned before the subsequent perforation process. The overall grinding thickness can be flexibly set according to actual needs.

[0029] S3 , forming a first through hole 113 on the second surface 112 ; the position of the first through hole 113 corresponds to the position of the electrode 121 on the chip 120 .

[0030] S4, forming a first groove 116 on the second surface 112; the first groove 116 is connected to the first through hole 113 on the corresponding different chips 120. The first groove 116 is used to fill the first metal layer 160 as a wiring layer 162 to achieve electrical connection between different chips 120, that is, to achieve interconnection between the chips 120.

[0031] S5. Form a second through hole 133 on the second surface 112; the second through hole 133 corresponds to the position of the first through hole 113 and is connected; the second through hole 133 is extended at least in the axial direction to the first through hole 113 to expose the electrode 121. Optionally, the first through hole 113 and the second through hole 133 are coaxially arranged, and the first metal layer 160 is filled in the first through hole 113 and the second through hole 133 as an electrical connection column 161, one end of the electrical connection column 161 is electrically connected to the electrode 121, and the other end is electrically connected to the wiring layer 162. That is, the electrical connection column 161 is used to realize the electrical connection between the electrode 121 on the chip 120 and the wiring layer 162.

[0032] S6. Form a first metal layer 160 in the first through hole 113, the second through hole 133 and the first groove 116; the first metal layer 160 is electrically connected to the electrode 121. In this embodiment, the metal filling in the first through hole 113, the first groove 116 and the second through hole 133 can be completed at one time, that is, the electrical connection column 161 and the wiring layer 162 can be formed at one time, which improves the process efficiency and bonding strength, and the electrical connection is more reliable.

[0033] Furthermore, after the glass substrate is ground, the first through hole 113 and the second through hole 133 are formed. The first through hole 113 and the second through hole 133 have a smaller aspect ratio, which is beneficial to improving the density of subsequent metal filling and reducing the risk of forming voids due to insufficient filling, thereby improving the bonding strength between the first metal layer 160 and the first substrate 110.

[0034] S7, forming a solder resist layer 170 covering the second surface 112. The solder resist layer 170 protects the second surface 112 of the glass substrate and the wiring layer 162. A first window is opened on the solder resist layer 170, and the third metal layer is filled in the first window to form a pad 171. The pad 171 is electrically connected to the first metal layer 160. A bump 172 is formed on the pad 171. The packaging process is completed.

[0035] Optionally, in step S1, the step of providing the first substrate 110 includes: Combination Figure 1, an adhesive layer 130 is formed between the first substrate 110 and the chip 120; wherein, the chip 120 has a functional area 122 on one side where the electrode 121 is provided, and the adhesive layer 130 covers the surface of the chip 120 on one side where the electrode 121 is provided, and has an opening 131 at a position corresponding to the functional area 122. The chip 120 may be a radio frequency chip 120, a filter chip 120, or another type of chip 120, which is not specifically limited here.

[0036] Optionally, an adhesive layer 130 is coated on the wafer 140, and the adhesive layer 130 is made of a photosensitive material. An opening 131 that leaks out the functional area 122 is formed on the adhesive layer 130 by a photolithography process. It can be understood that the surface of one side of the chip 120 where the functional area 122 is provided is covered by the adhesive layer 130 except for the functional area 122, and the electrode 121 of the chip 120 is also covered by the adhesive layer 130.

[0037] Combination Figure 2 The wafer 140 is cut by metal blade cutting or laser cutting to separate the whole wafer 140 into individual chips 120. Each chip 120 is covered with an adhesive layer 130.

[0038] Combination Figure 3 , the side of the single chip 120 covered with the adhesive layer 130 is mounted on the first substrate 110. The adhesive layer 130 can fix the chip 120 on the first substrate 110, and the adhesive layer 130 can isolate and protect the adjacent electrodes 121. The adhesive layer 130 is made of insulating material. Chips 120 of different types, models, and sizes can be mounted on the same first substrate 110, and multiple chips 120 can be integrated and packaged together, making the packaged product more functional. Figure 3 3 different chips 120 are shown mounted on the first substrate 110 .

[0039] It should be noted that the process of coating the adhesive layer 130 on the surface of the wafer 140 is not only convenient for subsequent chip bonding, but also can improve the problem in the traditional technology that the bottom filler is poorly filled and difficult to enter between the electrodes 121 of the chip 120 due to the large size of the chip 120. The packaging process of this embodiment can omit the dispensing process of the bottom filler, the process is simpler, the structural reliability is better, and the packaging efficiency is higher.

[0040] In some other embodiments, the adhesive layer 130 may be first coated on the first substrate 110 and opened at positions corresponding to the functional areas 122 of the chip 120 , and then the chip 120 is mounted on the first substrate 110 , which is not specifically limited here.

[0041] Combination Figure 4A plastic package 150 is formed on the side of the first substrate 110 where the chip 120 is mounted. The plastic package 150 encapsulates all the chips 120 on the first substrate 110 to protect and reinforce the structure. In addition, the plastic package 150 plays a supporting and buffering role in the subsequent grinding process of the first substrate 110, reducing the risk of the first substrate 110 breaking.

[0042] Combination Figure 5 Optionally, a buffer groove 151 is provided on the side of the plastic package body 150 away from the first substrate 110, and a buffer block 152 can be filled in the buffer groove 151. The opening of the buffer groove 151 can release stress and alleviate the warping deformation of the structure caused by the plastic package stress. The provision of the buffer block 152 can improve the buffering performance and provide better buffering and support in the subsequent grinding process. The buffer block 152 can be made of one or more of metal, ceramic, silicon oxide, and epoxy resin. The number of buffer grooves 151 can be one or more, and the cross-sectional shape and distribution position of the buffer groove 151 can be flexibly set according to actual conditions. For example, the buffer groove 151 can be provided at a position corresponding to the first through hole 113 and the first groove 116, which is not specifically limited here.

[0043] Alternatively, the buffer groove 151 may not be filled with material, and an empty groove structure may be retained, which can also play a buffering role and improve the heat dissipation performance.

[0044] Combination Figure 6 In step S2, the first substrate 110 is ground and thinned. During the grinding process, the first substrate 110 is placed upward, and the plastic package 150 plays a supporting and buffering role, which can reduce the risk of cracking. The grinding thickness can be designed according to actual needs. In this embodiment, after grinding, the thickness of the first substrate 110 can reach less than 20um, preferably less than 10um, which greatly reduces the thickness of the first substrate 110 and the overall packaging height, and realizes ultra-thin packaging.

[0045] It should be noted that in this embodiment, the grinding process is advanced to before the perforation process. At this time, the glass substrate is a complete whole. Compared with the glass substrate that has been partially perforated, the risk of cracking can be greatly reduced.

[0046] Combination Figure 7 In step S3 , the first through hole 113 penetrates the first substrate 110 , and the first through hole 113 extends from the second surface 112 of the first substrate 110 to the adhesive layer 130 at the electrode 121 .

[0047] Optionally, a first laser is used to irradiate a first area of ​​the second surface 112; the first area corresponds to the position of the electrode 121. The first area on the first substrate 110 is induced to be modified by laser irradiation, and then the first area is etched to form a first through hole 113. The first substrate 110 is etched by a wet etching process, and the first area induced by the laser is etched faster than other areas that are not induced by the laser, so that the first through hole 113 can be quickly etched on the first substrate 110.

[0048] In this step, the adhesive layer 130 protects the electrode 121 , and the etching solution will not remove the adhesive layer 130 and cause damage to the electrode 121 .

[0049] Optionally, the first through hole 113 is a cylindrical straight hole, that is, on the axis of the first through hole 113, its diameter remains unchanged. During the subsequent metal filling, the flow resistance of the molten metal is lower, the filling performance is better, and the occurrence of voids and the like is effectively avoided. The bonding force between the metal layer and the glass substrate is better, and the conductivity is better. It is easy to understand that since the first substrate 110 has been thinned, the depth of the first through hole 113 is relatively small, the metal filling performance is better, the electrical connection path is shorter, the transmission signal loss is lower, and the transmission speed is faster.

[0050] Optionally, the first through hole 113 can be formed by etching once or by etching for multiple times. The cross-sectional shape of the first through hole 113 can be circular, or can be triangular, quadrilateral, elliptical, pentagonal, hexagonal or any other shape. The cross section of the first through hole 113 can be consistent in the axial direction or can be gradually changed. Or the first through hole 113 can be designed to have a large cross section at one end and a small cross section at the other end. The first through hole 113 can be a tapered hole, an X-shaped hole, an L-shaped hole, a wavy hole, a stepped hole, etc., which are not specifically limited here.

[0051] Optional, combined Figure 8 In some embodiments, a first laser is used to irradiate a first region of the second surface 112; the first region is etched to form a prefabricated groove 114. The depth of the prefabricated groove 114 is less than the thickness of the first substrate 110. A third laser is used to irradiate the bottom of the prefabricated groove 114; the bottom of the prefabricated groove 114 is etched to form a through groove 115 that penetrates the first substrate 110, and the diameter of the through groove 115 is less than or equal to the diameter of the prefabricated groove 114. The through groove 115 can be a straight hole or a tapered hole, etc., and the through groove 115 ends at the bonding layer 130 at the electrode 121, that is, the through groove 115 exposes the bonding layer 130. The through groove 115 and the prefabricated groove 114 together form a first through hole 113.

[0052] In the step of forming the through groove 115, the prefabricated groove 114 can be widened or deepened, or the prefabricated groove 114 can be widened and deepened at the same time. The design of the step hole is conducive to increasing the contact area between the metal layer and the glass substrate, thereby improving the bonding between the metal layer and the glass substrate, and the electrical performance is better. And the step-by-step multiple hole-forming process is adopted, which is conducive to controlling the hole opening accuracy, adjusting the alignment error with the electrode 121, and preventing the hole position deviation from reducing the conductivity or electrical connection failure. And by using multiple holes, the hole depth is smaller each time, and it is not easy to cause cracks. It should be noted that in the multiple hole-forming process, the roughness of the hole wall of the first through hole 113 is increased and the adhesion is enhanced, which is conducive to improving the bonding between the hole wall of the first through hole 113 and the metal layer.

[0053] The first laser and the third laser can be different lasers, and the etching solutions in the multiple hole forming processes can be the same or different, which is not specifically limited here.

[0054] It should be noted that if the prefabricated groove 114 is formed in advance, when the first groove 116 is opened, the first groove 116 and the prefabricated groove 114 are connected, so that when the first metal layer 160 is subsequently formed, the metal cross-sectional area at the corner where the electrical connection column 161 and the wiring layer 162 are connected is larger, and the electrical connection performance and bonding are better. Of course, in some embodiments, the prefabricated groove 114 and the first groove 116 can be carried out simultaneously and completed in one process step to improve process efficiency. Optionally, the depth of the prefabricated groove 114 is consistent with the depth of the first groove 116. In some other embodiments, the depth of the prefabricated groove 114 and the depth of the first groove 116 may also be different, and are not specifically limited here.

[0055] In step S4, a first groove 116 is formed. Optionally, a second laser is used to irradiate a second region of the second surface 112; the second region is used to connect the first through holes 113 between corresponding different chips 120. The second region is etched to form the first groove 116; the depth of the first groove 116 is less than the depth of the first through hole 113.

[0056] It can be understood that after the second laser irradiation, the second region of the first substrate 110 is induced to be modified, and then the second region is corroded by the etching liquid to form the first groove 116. The second laser and the first laser can be different, and the etching liquid used can also be different, but the principle of laser-induced modification and etching and removing the modified part by the etching liquid is similar, which will not be repeated here.

[0057] Since the first groove 116 is formed, the wiring layer 162 is arranged in the first groove 116, and the glass substrate can protect the wiring layer 162. In addition, the provision of the first groove 116 reduces the overall package thickness. Compared with directly forming the wiring layer 162 on the second surface 112, the solution in this embodiment increases the contact area between the wiring layer 162 and the glass substrate, which is conducive to improving the bonding between the wiring layer 162 and the glass substrate, and better protecting the wiring layer 162.

[0058] Optionally, after forming the first through hole 113 and the first groove 116 , the hole wall of the first through hole 113 and the groove wall of the first groove 116 may be roughened to increase the bonding force between the subsequent metal layer and the glass substrate and prevent structural delamination.

[0059] Combination Fig. 9 Optionally, step S5 of forming the second through hole 133 from the second surface 112 includes: The adhesive layer 130 corresponding to the electrode 121 is removed by dry etching to form a second through hole 133 connected to the first through hole 113 on the adhesive layer 130. Optionally, a plasma etching process can be used to dry-etch the product to etch away the adhesive layer 130 at the electrode 121 of the chip 120 to expose the electrode 121. After the plasma etching process, the second surface 112 of the glass substrate is cleaner, which can further increase the bonding strength between the glass substrate and the metal layer.

[0060] It is easy to understand that in the step of forming the second through hole 133 , the aperture of the first through hole 113 can be appropriately enlarged, and the hole wall of the first through hole 113 can be cleaned, which is beneficial to improving the bonding strength between the subsequent glass substrate and the metal layer.

[0061] Of course, the invention is not limited thereto, and the second through hole 133 may also be formed by laser drilling, wet etching or other process methods, which are not specifically limited here.

[0062] Combination Fig.10 In step S6, a first metal layer 160 is formed on the entire second surface 112, and the first metal layer 160 is filled into the first through hole 113, the second through hole 133 and the first groove 116. The first metal layer 160 is ground to expose the second surface 112 of the first substrate 110; wherein the surfaces of the first metal layer 160 in the first through hole 113, the second through hole 133 and the first groove 116 are flush with the second surface 112 respectively.

[0063] Optionally, a metal layer is sputtered on the entire surface by PVD, and then the entire surface is electroplated to fill the second through hole 133, the first through hole 113 and the first groove 116 with metal at one time. This process is highly efficient, and the first metal layer 160 is formed in one step, with better electrical connection performance and bonding. The metal layer on the second surface 112 is then thinned by a thinning process until all the metal outside the first groove 116 is removed, that is, the glass substrate is exposed. The thinning process includes but is not limited to grinding, etching, etc. It can be understood that after grinding, the metal in the first through hole 113, the second through hole 133 and the first groove 116 is left; and the metal surface in the second through hole 133 and the first groove 116 is flush with the second surface 112 of the first substrate 110. In this way, the production of the electrical connection column 161 and the wiring layer 162 is completed.

[0064] Combination Fig.11 and Fig.12 Optionally, micro-etching can be used to form a roughened surface on the electrode 121 of the chip 120. The roughened surface can be regarded as a micro-groove or micro-bump 1211 structure formed on the surface of the electrode 121. A metal bonding layer 1213 is formed on the roughened surface. The metal bonding layer 1213 can be made of metals such as titanium, tungsten, and nickel. This is beneficial to improving the electrical connection performance and bonding strength between the first metal layer 160 and the electrode 121 when the first metal layer 160 is subsequently electroplated.

[0065] Combination Fig.13 In step S7, a solder resist layer 170 is formed to cover the second surface 112; a first window is opened on the solder resist layer 170; a third metal layer is filled in the first window to form a pad 171; the pad 171 is electrically connected to the first metal layer 160; and a bump 172 is formed on the pad 171.

[0066] Optionally, a solder resist layer 170 is formed on the entire surface of the second surface 112 by using a photolithography process, and the solder resist layer 170 protects the first substrate 110 and the first metal layer 160 flush with the surface of the first substrate 110. The position of the bump 172 is defined on the solder resist layer 170, and then the pad 171 under the bump 172 is made by a chemical plating process, and then the bump 172 is formed on the pad 171 by a printing or ball planting process. In this way, the electrode 121 of the chip 120 is guided from the inside to the surface of the first substrate 110.

[0067] Optional, combined Fig.14 In some implementations, in order to increase the density of input and output pins and improve product integration performance, a multi-layer wiring layer 162 is provided to meet more line interconnections. For example, a first wiring layer 162 is formed on the first substrate 110, and a second wiring layer 162 is formed on the second substrate 180, and the second wiring layer 162 is electrically connected to the first wiring layer 162.

[0068] Optionally, after forming the solder resist layer 170 and the pad 171 under the bump 172, the second substrate 180 is mounted on the second surface 112 of the first substrate 110. The second substrate 180 can be made of glass, ceramic or silicon substrate, etc. The second substrate 180 takes a glass substrate as an example. The second substrate 180 is bonded or bonded to the first substrate 110. A third through hole and a second groove are opened on the second substrate 180. The manufacturing process of the third through hole is similar to that of the first through hole 113. After laser induced modification, the third through hole is formed by wet etching. The position of the third through hole corresponds to the position of the pad 171 on the first substrate 110. The preparation process of the second groove is similar to that of the first groove 116 mentioned above, which will not be repeated here.

[0069] The second metal layer 181 is filled in the third through hole and the second groove to form the second wiring layer 162; the second metal layer 181 is electrically connected to the first metal layer 160. The second metal layer 181 is formed by sputtering and electroplating, and its formation principle is similar to that of the first metal layer 160. The second metal layer 181 in the third through hole and the second groove can also be formed in one step to improve the packaging efficiency. A solder resist layer 170 is formed on the side of the second substrate 180 away from the first substrate 110, a pad 171 is formed on the solder resist layer 170, and a bump 172 is made on the pad 171.

[0070] Optionally, in some embodiments, combined with Fig.15 , the two structures formed by steps S1 to S7 can also be mounted together to form a structure similar to a double-sided package, thereby further improving the integration of the package structure. It should be noted that when the two above-mentioned package structures are stacked together, the bumps 172 on one of the first substrates 110 are bonded to the bumps 172 on the other first substrate 110. Of course, the preparation process of the bumps 172 on one of the first substrates 110 can also be omitted, and the bumps 172 on one of the first substrates 110 can be bonded to the pads 171 on the other first substrate 110.

[0071] Optionally, if it is necessary to electrically connect the two stacked package structures with other modules, a connection pad 191 may be reserved on at least one of the two first substrates 110 to achieve electrical connection with other external modules.

[0072] Alternatively, the connection pad 191 can also be led out from the plastic package 150 by slotting, such as slotting the plastic package 150 and forming a conductive column 190 by electroplating metal, and the conductive column 190 is connected to the first metal layer 160 on any side, or is electrically connected to the first metal layer 160 on both sides. A connection pad 191 electrically connected to the conductive column 190 is formed on the surface of the plastic package 150. The connection pad 191 can be provided on any side of the plastic package 150 on both sides, or the connection pad 191 can be provided on the surface of the plastic package 150 on both sides.

[0073] An embodiment of the present invention further provides a packaging structure, which is prepared by using the TGV substrate integrated packaging method as described in any one of the aforementioned embodiments.

[0074] In summary, the TGV substrate integrated packaging method and packaging structure provided by the embodiments of the present invention have the following beneficial effects, including: First, a plastic encapsulation body 150 is formed on one side of the glass substrate, and then the glass substrate is ground. During the grinding process, the plastic encapsulation body 150 can play a supporting and buffering role, and the whole glass substrate is ground, which can greatly reduce the risk of cracking. After the glass substrate is ground, the first through hole 113, the first groove 116 and the second through hole 133 are formed to reduce the risk of cracking, reduce the thickness of the glass substrate, and achieve ultra-thin packaging. The first through hole 113 formed in this way has a smaller depth-to-diameter ratio, better metal filling performance, less prone to voids, and better bonding between the metal and the glass substrate. Secondly, by opening the first groove 116 on the glass substrate, the metal in the first groove 116 is used for wiring of the circuit layer to realize the interconnection of the chip 120. The opening of the first groove 116 is conducive to improving the bonding between the metal and the glass substrate, preventing structural delamination, and improving the packaging quality. In addition, the metal filling can be completed in the first through hole 113, the first groove 116 and the second through hole 133 at one time, with higher process efficiency and better bonding, which is conducive to improving packaging efficiency and packaging quality. Furthermore, the packaging structure provided in this embodiment can integrate a variety of different chips 120 together, thereby increasing packaging integration, improving product performance, and enriching product functions.

[0075] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the above embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the above embodiments, or make equivalent replacements for some or all of the technical features therein. Any modifications, equivalent replacements, improvements, etc. made should be included in the protection scope of the present invention.

Claims

1. A TGV substrate integrated packaging method, characterized in that: include: A first substrate is provided; the first substrate is a glass substrate; the first substrate comprises a first surface and a second surface which are arranged opposite to each other; a chip is mounted on the first surface, and a plastic package covering the chip is formed; Grinding and thinning the second surface of the first substrate; A first through hole is formed on the second surface; the position of the first through hole corresponds to the position of the electrode on the chip; A first groove is formed on the second surface; the first groove is connected to the first through holes on corresponding different chips; A second through hole is formed on the second surface; the second through hole corresponds to the position of the first through hole and is connected to the first through hole; the second through hole is extended from the first through hole at least in the axial direction to expose the electrode; A first metal layer is formed in the first through hole, the second through hole and the first groove; and the first metal layer is electrically connected to the electrode.

2. The TGV substrate integrated packaging method according to claim 1, characterized in that: The step of providing a first substrate comprises: An adhesive layer is formed between the first substrate and the chip; wherein the chip has a functional area on one side where the electrode is provided, the adhesive layer covers the surface of the chip on one side where the electrode is provided, and has an opening at a position corresponding to the functional area.

3. The TGV substrate integrated packaging method according to claim 2, characterized in that: In the step of forming a first through hole on the second surface, the first through hole penetrates the first substrate; In the step of forming a second through hole on the second surface, the second through hole penetrates the adhesive layer.

4. The TGV substrate integrated packaging method according to claim 1, characterized in that: The step of forming a first through hole on the second surface comprises: irradiating a first area of ​​the second surface with a first laser, wherein the first area corresponds to a position of the electrode; etching the first region to form the first through hole; The step of forming a first groove on the second surface comprises: irradiating a second area of ​​the second surface with a second laser, wherein the second area is used to connect the first through holes between the corresponding different chips; The second region is etched to form the first groove; the depth of the first groove is smaller than the depth of the first through hole.

5. The TGV substrate integrated packaging method according to claim 4, characterized in that: The steps of irradiating a first area of ​​the second surface with a first laser and corroding the first area to form the first through hole include: irradiating a first area of ​​the second surface with a first laser; etching the first area to form a prefabricated groove; irradiating the bottom of the prefabricated groove with a third laser; etching the bottom of the prefabricated groove to form a through groove penetrating the first substrate, wherein the diameter of the through groove is smaller than the diameter of the prefabricated groove; The through groove and the prefabricated groove together form the first through hole.

6. The TGV substrate integrated packaging method according to claim 2, characterized in that: The step of forming a second through hole on the second surface comprises: The adhesive layer corresponding to the electrode is removed by dry etching to form a second through hole connected to the first through hole on the adhesive layer.

7. The TGV substrate integrated packaging method according to claim 1, characterized in that: The step of forming a first metal layer in the first through hole, the second through hole and the first groove comprises: forming a first metal layer on the entire second surface, and filling the first through hole, the second through hole and the first groove with the first metal layer; The first metal layer is ground to expose the second surface of the first substrate; wherein the surfaces of the first metal layer in the first through hole, the second through hole and the first groove are flush with the second surface respectively.

8. The TGV substrate integrated packaging method according to claim 1, characterized in that: Also includes: Mounting a second substrate on the second surface; A third through hole and a second groove are formed on the second substrate; A second metal layer is filled in the third through hole and the second groove; and the second metal layer is electrically connected to the first metal layer.

9. The TGV substrate integrated packaging method according to any one of claims 1 to 8, characterized in that: Also includes: forming a solder resist layer covering the second surface; Opening a first window on the solder resist layer; The first window is filled with a third metal layer to form a pad; the pad is electrically connected to the first metal layer; Bumps are formed on the pads.

10. A packaging structure, characterized in that: The TGV substrate is prepared by the TGV substrate integrated packaging method as described in any one of claims 1 to 9.

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