Chip packaging method, chip packaging structure and electronic equipment

Abstract

The invention relates to a chip packaging method, a chip packaging structure and electronic equipment, and the chip packaging method comprises the following steps: providing a chip to be packaged, forming a plurality of heat dissipation parts on the first surface of the chip, and forming a plurality of interconnection parts on the second surface of the chip; electrically connecting the interconnection piece with a first substrate; a second substrate is electrically connected with the first substrate through an electric connecting piece, the interconnection piece faces the first substrate, and the heat dissipation piece faces the second substrate; and a plastic package body wrapping the chip, the heat dissipation piece and the electric connecting piece is formed between the first substrate and the second substrate. According to the chip packaging method disclosed by the invention, the heat dissipation performance of the chip can be improved under the condition that the thickness of the chip packaging structure is not increased.

Description

Technical Field

[0001] The present disclosure relates to the field of chip technology, and in particular to a chip packaging method, a chip packaging structure and an electronic device. Background Art

[0002] With the rapid development of electronic devices, higher requirements are placed on the performance, bandwidth and power consumption of semiconductor chips. HBPOP (High bandwidth Package on Package) and FCCSP (Flip-Chip Chip Scale Package) have worse heat dissipation performance due to structural limitations, which affects the performance and power consumption of the chip. Therefore, how to improve the heat dissipation performance of the chip is a technical problem that needs to be solved urgently. Summary of the invention

[0003] The present disclosure provides a chip packaging method to improve the heat dissipation performance of the chip.

[0004] The chip packaging method disclosed in the present invention comprises the following steps:

[0005] Providing a chip to be packaged, wherein a first surface of the chip is formed with a plurality of heat sinks, and a second surface of the chip is formed with a plurality of interconnects;

[0006] electrically connecting the interconnect to the first substrate;

[0007] Electrically connecting the second substrate to the first substrate through an electrical connector, wherein the interconnector faces the first substrate and the heat sink faces the second substrate;

[0008] A plastic package encapsulating the chip, the heat sink and the electrical connector is formed between the first substrate and the second substrate.

[0009] Optionally, when the plastic packaging body is formed between the first substrate and the second substrate, the plastic packaging body fills a plastic packaging gap between two adjacent heat sinks.

[0010] Optionally, when the second substrate is electrically connected to the first substrate, the surface of the heat sink facing away from the first substrate is in contact with the surface of the second substrate facing toward the first substrate; or, when the second substrate is electrically connected to the first substrate, there is a heat dissipation gap between the surface of the heat sink facing away from the first substrate and the surface of the second substrate facing toward the first substrate, and the plastic package fills the heat dissipation gap.

[0011] Optionally, providing a chip to be packaged includes the following steps:

[0012] forming a first protective layer on the front side of the wafer, wherein the first protective layer covers the front side of the wafer;

[0013] forming a plurality of the heat sinks on the back side of the wafer;

[0014] forming a second protective layer on the back side of the wafer, wherein the second protective layer covers the back side of the wafer;

[0015] The first protective layer is removed, and the wafer is cut to form a plurality of chips, wherein the second surface of the chip has a plurality of interconnections.

[0016] Optionally, a plurality of heat sinks are formed on the back side of the wafer by laser etching or dry etching.

[0017] Optionally, the Young's modulus of the second protective layer is greater than or equal to a first preset value and less than or equal to a second preset value, and the viscosity of the second protective layer is greater than or equal to a preset viscosity to prevent the heat sink from shaking when the wafer is cut.

[0018] Optionally, connecting the chip to the first substrate and electrically connecting the second substrate to the first substrate comprises the following steps:

[0019] connecting the chip to the first substrate;

[0020] Controlling the position of the second substrate so that the minimum distance between the second substrate and the second substrate is a preset distance;

[0021] The second substrate is electrically connected to the first substrate.

[0022] Optionally, forming a plastic package encapsulating the chip between the first substrate and the second substrate comprises the following steps:

[0023] The plastic encapsulation body is formed by a plastic encapsulation mold, wherein the pressure applied to the heat sink during the process of forming the plastic encapsulation body by mold closing and injection molding is less than or equal to a preset pressure.

[0024] The present disclosure also provides a chip packaging structure.

[0025] The chip packaging structure disclosed in the present invention includes a chip, a first substrate, a second substrate and a plastic package body, wherein the first surface of the chip is provided with a plurality of heat sinks, and the second surface of the chip is provided with a plurality of interconnections; the chip is arranged between the first substrate and the second substrate, the second substrate is electrically connected to the first substrate through an electrical connector, the interconnections face the first substrate and are electrically connected to the first substrate, and the heat sink faces the second substrate; the plastic package body is arranged between the first substrate and the second substrate and wraps the chip, the heat sink and the electrical connector.

[0026] Optionally, the plastic packaging body fills a plastic packaging gap between two adjacent heat dissipating elements.

[0027] Optionally, the surface of the heat sink facing away from the first substrate contacts the surface of the second substrate facing the first substrate; or, a heat dissipation gap exists between the surface of the heat sink facing away from the first substrate and the surface of the second substrate facing the first substrate, and the plastic package fills the heat dissipation gap.

[0028] Optionally, the ratio of the height of the heat sink to the thickness of the chip is 0.3-0.5; and / or, the distance between two adjacent heat sinks is 70 μm-110 μm.

[0029] Optionally, the heat sink is cylindrical or rectangular; and / or the equivalent diameter of the heat sink is 30 μm to 90 μm.

[0030] Optionally, the heat sink and the chip are formed integrally.

[0031] The present disclosure also provides an electronic device.

[0032] The electronic device disclosed in the present invention includes the chip packaging structure described in any one of the above items.

[0033] The chip packaging method disclosed in the present invention forms a plurality of interconnecting members on the second surface of the chip, so that the interconnecting members can be used to realize the electrical connection between the chip and the first substrate, and the first substrate and the second substrate are electrically connected through the electrical connecting member to realize the electrical connection between the chip and the second substrate; a plastic package body is formed between the first substrate and the second substrate to wrap the chip, so that the chip is protected by the plastic package body; a plurality of heat sinks facing the second substrate are formed on the first surface of the chip, and the plastic package body wraps the heat sink, so that the space occupied by the heat sink is the plastic package space of the plastic package body, which not only avoids the heat sink from occupying other external spaces and reduces the thickness of the chip packaging structure, but also makes the heat sink closer to the second substrate, so that the heat generated by the chip during operation can be quickly transferred to the second substrate through the heat sink, and then transferred to the outside through the second substrate, thereby improving the heat dissipation performance of the chip. In this way, the heat dissipation performance of the chip can be improved without increasing the thickness of the chip packaging structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] Figure 1 It is a flowchart of a chip packaging method according to an embodiment of the present disclosure.

[0035] Figure 2 It is a manufacturing flow chart of a chip packaging method according to an embodiment of the present disclosure.

[0036] Figure 3It is a chip manufacturing flow chart of a chip packaging method according to an embodiment of the present disclosure.

[0037] Figure 4 It is a schematic structural diagram of a chip packaging structure according to an embodiment of the present disclosure.

[0038] Figure 5 It is a schematic structural diagram of a chip in a chip packaging structure according to an embodiment of the present disclosure.

[0039] Figure 6 It is a comparison diagram of the heat dissipation effect of a chip packaging structure according to an embodiment of the present disclosure and a chip packaging structure in related technologies.

[0040] Figure 7 It is a comparison chart of thermal evaluation in running scenarios of a chip packaging structure according to an embodiment of the present disclosure and a chip packaging structure in related technologies.

[0041] Figure 8 It is a thermal resistance comparison diagram of a chip packaging structure according to an embodiment of the present disclosure and a chip packaging structure in related art.

[0042] Reference numerals:

[0043] 100. Chip packaging structure;

[0044] 1. chip; 11. first surface; 12. second surface;

[0045] 2. Heat dissipation components;

[0046] 3. Interconnection parts;

[0047] 4. a first substrate;

[0048] 5. A second substrate;

[0049] 6. Plastic sealing body;

[0050] 7. Filling body;

[0051] 8. Electrical connectors;

[0052] 9. Solder balls;

[0053] 10. wafer; 101. front side; 102. back side;

[0054] 20. The first protective layer;

[0055] 30. The second protective layer. DETAILED DESCRIPTION

[0056] Embodiments of the present disclosure are described in detail below, and examples of the embodiments are shown in the accompanying drawings. The embodiments described below with reference to the accompanying drawings are exemplary and are intended to be used to explain the present disclosure, but should not be understood as limiting the present disclosure.

[0057] like Figures 1 to 5 As shown, the chip packaging method of the embodiment of the present disclosure includes the following steps:

[0058] S1, providing a chip 1 to be packaged, wherein a first surface 11 of the chip 1 is formed with a plurality of heat sinks 2, and a second surface 12 of the chip 1 is formed with a plurality of interconnectors 3;

[0059] Exemplarily, the heat sink wraps the heat sink column;

[0060] Exemplarily, the interconnection member includes an interconnection pillar or the like.

[0061] S2, electrically connecting the interconnection member 3 to the first substrate 4, and forming a filling body in the area where the interconnection member 3 is located;

[0062] S3, electrically connecting the second substrate 5 to the first substrate 4 through the electrical connector 8, wherein the interconnection member 3 faces the first substrate 4, and the heat sink 2 faces the second substrate 5;

[0063] S4, forming a plastic package 6 encapsulating the chip 1, the heat sink 2, the filler 7 and the electrical connector 8 between the first substrate 4 and the second substrate 5.

[0064] The chip packaging method of the embodiment of the present disclosure forms a plurality of interconnecting members 3 on the second surface 12 of the chip 1, and the interconnecting members 3 can be used to realize the electrical connection between the chip 1 and the first substrate 4, and the first substrate 4 and the second substrate 5 are electrically connected through the electrical connector 8 to realize the electrical connection between the chip 1 and the second substrate 5; a plastic package 6 is formed between the first substrate 4 and the second substrate 5 to wrap the chip 1, so that the chip 1 is protected by the plastic package 6; a plurality of heat sinks 2 facing the second substrate 5 are formed on the first surface 11 of the chip 1, and the plastic package 6 wraps the heat sink 2, so that the space occupied by the heat sink 2 is the plastic package space of the plastic package 6, which not only avoids the heat sink 2 from occupying other external spaces and reduces the thickness of the chip packaging structure 100, but also makes the heat sink 2 closer to the second substrate 5, so that the heat generated by the chip 1 during operation can be quickly transferred to the second substrate 5 through the heat sink 2, and then transferred to the outside through the second substrate 5, thereby improving the heat dissipation performance of the chip 1. Therefore, the heat dissipation performance of the chip 1 can be improved without increasing the thickness of the chip packaging structure 100.

[0065] In some embodiments, Figure 2 and Figure 4 As shown, the plastic packaging body 6 fills the plastic packaging gap between two adjacent heat sinks 2 .

[0066] When the chip 1 is specifically plastic-sealed, the plastic-sealing gap between two adjacent heat sinks 2 can be used for the plastic-sealing material to pass through, so that the plastic-sealing gap between two adjacent heat sinks 2 is filled with the plastic-sealing material, and the plastic-sealing body 6 is formed after the plastic-sealing material is solidified.

[0067] By filling the plastic sealing gap between two adjacent heat sinks 2 with the plastic sealing body 6, not only can the protection effect of the chip 1 be improved, but also the reliability of the chip packaging structure 100 can be improved; moreover, the heat generated by the chip 1 when working can also be transferred to the second substrate 5 through the plastic sealing body 6 filled in the plastic sealing gap, and transferred to the outside through the second substrate 5, thereby further improving the heat dissipation performance of the chip 1.

[0068] Alternatively, if Figure 2 As shown, when the second substrate 5 is electrically connected to the first substrate 4 , the surface of the heat sink 2 facing away from the first substrate 4 is in contact with the surface of the second substrate 5 facing the first substrate 4 .

[0069] By bringing the surface of the heat sink 2 facing away from the first substrate 4 into contact with the surface of the second substrate 5 facing the first substrate 4, the heat generated by the chip 1 during operation can be directly conducted to the second substrate 5 through the heat sink 2 and transferred to the outside through the second substrate 5, thereby further improving the heat dissipation performance of the chip 1.

[0070] In some embodiments, when the second substrate 5 is electrically connected to the first substrate 4 , a heat dissipation gap is provided between the surface of the heat dissipation element 2 facing away from the first substrate 4 and the surface of the second substrate 5 facing the first substrate 4 , and the plastic package 6 fills the heat dissipation gap.

[0071] By filling the heat dissipation gap with the plastic package 6, the heat generated by the chip 1 during operation can be first directly thermally conducted to the plastic package 6 located in the heat dissipation gap through the heat sink 2, and then thermally conducted to the second substrate 5 through the plastic package 6 located in the heat dissipation gap, and then transferred to the outside through the second substrate 5, thereby further improving the heat dissipation performance of the chip 1.

[0072] In order to make the technical solution of the present disclosure easier to understand, the following takes the arrangement direction of the first substrate 4 and the second substrate 5 being consistent with the up-down direction as an example to further describe the technical solution of the present disclosure. Figures 3 to 5 shown.

[0073] For example, Figure 4 As shown, the first surface 11 is located on the upper side of the second surface 12, the heat sink 2 is arranged upward, and the interconnection member 3 is arranged downward. The first substrate 4 is located on the lower side of the second substrate 5. The upper surface of the heat sink 2 contacts the lower surface of the second substrate 5. The heat generated by the chip 1 during operation can be transferred upward to the second substrate 5 through the heat sink 2, and then transferred to the outside through the upper surface and side surface of the second substrate 5.

[0074] Alternatively, if Figure 3 As shown, providing a chip 1 to be packaged includes the following steps:

[0075] Forming a first protective layer 20 on the front side 101 of the wafer 10 , wherein the first protective layer 20 covers the front side 101 of the wafer 10 ;

[0076] A plurality of heat sinks 2 are formed on the back side 102 of the wafer 10;

[0077] forming a second protective layer 30 on the back side 102 of the wafer 10 , wherein the second protective layer 30 covers the back side 102 of the wafer 10 ;

[0078] The first protection layer 20 is removed, and the wafer 10 is cut to form a plurality of chips 1 , wherein a plurality of interconnecting members 3 are formed on the second surface 12 of the chip 1 .

[0079] For example, Figure 3 As shown, first, the front side 101 of the wafer 10 is placed upward and the back side 102 is placed downward, and a first protective layer 20 is formed on the front side 101; then, the back side 102 of the wafer 10 is placed upward and the front side 101 is placed downward, and the back side 102 is ground; then, a plurality of heat sinks 2 are formed on the back side 102 of the wafer 10; then, a second protective layer 30 is formed on the back side 102 of the wafer 10; then, the front side 101 of the wafer 10 is placed upward and the back side 102 is placed downward, and the first protective layer 20 is removed; then, the wafer 10 is cut, so that the wafer 10 forms a plurality of chips 1. The first protective layer 20 and the second protective layer 30 are both elastic layers, for example, the first protective layer 20 and the second protective layer 30 are both adhesive tapes, the first protective layer 20 is attached to the front side 101 of the wafer 10, and the second protective layer 30 is attached to the back side 102 of the wafer 10.

[0080] By forming the first protective layer 20 on the front side 101 of the wafer 10, the first protective layer 20 can be used to protect the front side 101 of the wafer 10, thereby preventing the front side 102 of the wafer 10 from being worn when processing the back side 102 of the wafer 10; by forming the second protective layer 30 on the back side 102 of the wafer 10, the second protective layer 30 can be used to protect the heat sink 2, thereby preventing the heat sink 2 from being damaged when cutting the wafer 10 and forming the interconnection 3 on the second surface 12 of the chip 1. Thus, the yield and quality of the chip 1 are improved.

[0081] Optionally, the Young's modulus of the second protective layer 30 is greater than or equal to the first preset value and less than or equal to the second preset value, and the viscosity of the second protective layer 30 is greater than or equal to the preset viscosity to prevent the heat sink 2 from shaking when the wafer 10 is cut.

[0082] It is understandable that when the wafer 10 is cut and the copper pillars 3 are formed on the second surface 12 of the chip 1 , the heat sink 2 is prone to shake, causing damage to the chip 1 .

[0083] For example, at 23° C., the Young's modulus of the second protective layer 30 is 2500 MPa to 6000 MPa, and the ratio of the thickness of the second protective layer 30 to the height of the heat sink 2 is greater than 2. The second protective layer 30 may be UV glue to ensure the stickiness when the wafer 10 is cut. For example, when the wafer 10 is cut, the stickiness of the second protective layer 30 is greater than or equal to 400 mN / 25 mm; after the wafer 10 is cut, the stickiness of the second protective layer 30 is less than or equal to 100 mN / 25 mm.

[0084] By setting the second protective layer 30 to have a suitable Young's modulus and suitable viscosity, it is possible to avoid the heat sink 2 shaking when cutting the wafer 10 to cause damage to the chip 1 and improve the yield of the chip packaging structure 100 .

[0085] Optionally, a plurality of heat sinks 2 are formed on the back side 102 of the wafer 10 by laser grooving or dry etching.

[0086] Thus, the chip 1 and the heat sink 2 are an integrated structure, for example, the heat sink 2 is a silicon column. The process of the heat sink 2 is simple, which reduces stress accumulation. At the same time, since the chip 1 and the heat sink 2 are integrated, there is no interface problem between the chip 1 and the heat sink 2, so that the heat transfer effect between the chip 1 and the heat sink 2 can be improved, and the heat dissipation performance of the chip 1 can be further improved.

[0087] In some embodiments, connecting the chip 1 to the first substrate 4 and electrically connecting the second substrate 5 to the first substrate 4 include the following steps:

[0088] Connecting the chip 1 to the first substrate 4;

[0089] Controlling the position of the second substrate 5 so that the minimum distance between the second substrate 5 and the first substrate 4 is a preset distance;

[0090] The second substrate 5 is connected to the first substrate 4 .

[0091] The preset spacing is determined according to the overall thickness of the chip 1 , the heat sink 2 and the interconnection 3 . For example, the preset spacing is equal to the overall thickness of the chip 1 , the heat sink 2 and the interconnection 3 .

[0092] By controlling the position of the second substrate 5 so that the minimum distance between the second substrate 5 and the first substrate 4 is a preset distance, the second substrate 5 can be prevented from touching the heat sink 2 and causing damage to the heat sink 2, thereby improving the yield of the chip packaging structure 100.

[0093] In some embodiments, forming a plastic package 6 between the first substrate 4 and the second substrate 5 includes the following steps:

[0094] The plastic encapsulation body 6 is formed by the plastic encapsulation mold, and the pressure applied to the heat sink 2 during the process of forming the plastic encapsulation body 6 by mold closing and injection molding is less than or equal to the preset pressure.

[0095] For example, by controlling the height of the plastic packaging module, the pressure applied to the heat sink 2 during the process of closing the mold and injection molding to form the plastic packaging body 6 is controlled to be less than or equal to a preset pressure.

[0096] By controlling the pressure applied by the plastic molding die to the heat sink 2 to be less than or equal to a preset pressure, it is possible to avoid excessive pressure on the heat sink 2 caused by the plastic molding die, thereby damaging the heat sink 2 and improving the yield of the chip packaging structure 100 .

[0097] The chip packaging structure 100 of the embodiment of the present disclosure includes a chip 1, a first substrate 4, a second substrate 5, a filling body 7 and a plastic package 6. The chip 1 is arranged between the first substrate 4 and the second substrate 5. The second substrate 5 is electrically connected to the first substrate 4 through an electrical connector 8. The plastic package 6 is arranged between the first substrate 4 and the second substrate 5 and wraps the chip 1, the heat sink 2, the copper column 3 and the electrical connector 8 connecting the first substrate 4 and the second substrate 5. A plurality of heat sinks 2 are arranged on the first surface 11 of the chip 1, a plurality of interconnects 3 are arranged on the second surface 12 of the chip 1, the interconnects 3 face the first substrate 4 and are electrically connected to the first substrate 4, the heat sink 2 faces the second substrate 5, and the plastic package 6 wraps the side of the heat sink 2.

[0098] like Figure 2 As shown, the chip packaging method of the embodiment of the present disclosure is specifically as follows:

[0099] First, the electrical connector 8 is fixed on one surface of the second substrate 5;

[0100] Then, the interconnection member 3 of the chip 1 to be packaged is electrically connected to the first substrate 4;

[0101] Afterwards, a filling body 7 is formed at the position of the interconnection member 3 to protect the interconnection member 3;

[0102] Next, the second substrate 5 is electrically connected to the first substrate 4 via an electrical connector 8, wherein the electrical connector may be a copper column, a copper core ball or a pure tin ball;

[0103] Next, a plastic package 6 is formed between the first substrate 4 and the second substrate 5 to encapsulate the chip 1, the heat sink 2, the interconnection 3 and the electrical connection 8;

[0104] Finally, solder balls 9 are implanted on the surface of the first substrate 4 facing away from the chip 1 , wherein the chip packaging structure 100 is connected to an external device through the solder balls 9 .

[0105] The chip packaging structure 100 of the embodiment of the present disclosure can realize the electrical connection between the chip 1 and the first substrate 4 by arranging a plurality of interconnecting members 3 on the second surface 12 of the chip 1, and realize the electrical connection between the chip 1 and the second substrate 5 by arranging the first substrate 4 and the second substrate 5 electrically; by arranging a plastic package 6 that wraps the chip 1, the heat sink 2, the interconnecting members 3 and the electrical connector 8 between the first substrate 4 and the second substrate 5, the chip 1 can be protected by the plastic package 6; by arranging a plurality of heat sinks 2 facing the second substrate 5 on the first surface 11 of the chip 1, and the plastic package 6 wraps the heat sink 2, so that the space occupied by the heat sink 2 is the plastic package space of the plastic package 6, which not only avoids the heat sink 2 from occupying other external spaces and reduces the thickness of the chip packaging structure 100, but also makes the heat sink 2 closer to the second substrate 5, so that the heat generated by the chip 1 during operation can be quickly transferred to the second substrate 5 through the heat sink 2, and then transferred to the outside through the second substrate 5, thereby improving the heat dissipation performance of the chip 1. Therefore, the heat dissipation performance of the chip 1 can be improved without increasing the thickness of the chip packaging structure 100.

[0106] Optionally, the heat sink 2 and the chip 1 are formed integrally.

[0107] The heat sink 2 and the chip 1 are integrally formed, so that there is no interface problem between the chip 1 and the heat sink 2 , thereby improving the heat transfer effect between the chip 1 and the heat sink 2 and further improving the heat dissipation performance of the chip 1 .

[0108] Optionally, the plastic package body 6 fills the gap between two adjacent heat sinks 2 .

[0109] By filling the plastic sealing gap between two adjacent heat sinks 2 with the plastic sealing body 6, not only can the protection effect of the chip 1 be improved, but also the reliability of the chip packaging structure 100 can be improved; moreover, the heat generated by the chip 1 when working can also be transferred to the second substrate 5 through the plastic sealing body 6 filled in the plastic sealing gap, and transferred to the outside through the second substrate 5, thereby further improving the heat dissipation performance of the chip 1.

[0110] Optionally, a surface of the heat sink 2 facing away from the first substrate 4 is in contact with a surface of the second substrate 5 facing the first substrate 4 .

[0111] By bringing the surface of the heat sink 2 facing away from the first substrate 4 into contact with the surface of the second substrate 5 facing the first substrate 4, the heat generated by the chip 1 during operation can be directly conducted to the second substrate 5 through the heat sink 2 and transferred to the outside through the second substrate 5, thereby further improving the heat dissipation performance of the chip 1.

[0112] Optionally, a heat dissipation gap is provided between a surface of the heat dissipation element 2 facing away from the first substrate 4 and a surface of the second substrate 5 facing the first substrate 4 , and the plastic package 6 fills the heat dissipation gap.

[0113] By filling the heat dissipation gap with the plastic package 6, the heat generated by the chip 1 during operation can be first directly thermally conducted to the plastic package 6 located in the heat dissipation gap through the heat sink 2, and then thermally conducted to the second substrate 5 through the plastic package 6 located in the heat dissipation gap, and then transferred to the outside through the second substrate 5, thereby further improving the heat dissipation performance of the chip 1.

[0114] Optionally, the ratio of the height of the heat sink 2 to the thickness of the chip 1 is 0.3-0.5.

[0115] For example, Figure 5 As shown, the height of the heat sink 2 is H1, the thickness of the chip 1 is H2, and the ratio of H1 to H2 is 0.3 to 0.5. Specifically, the height of the heat sink 2 can be 45 μm, and the thickness of the chip 1 can be 120 μm.

[0116] It can be understood that, when the thickness of the chip 1 is constant, the greater the ratio of the height of the heat sink 2 to the thickness of the chip 1, the greater the height of the heat sink 2, and the greater the thickness of the chip packaging structure 100; when the thickness of the chip 1 is constant, the smaller the ratio of the height of the heat sink 2 to the thickness of the chip 1, the smaller the height of the heat sink 2, the smaller the heat dissipation area of ​​the heat sink 2, and the worse the heat dissipation effect of the heat sink 2.

[0117] By setting the ratio of the height of the heat sink 2 to the thickness of the chip 1 to 0.3-0.5, when the thickness of the chip packaging structure 100 is relatively small, the heat dissipation effect of the heat sink 2 can be better, that is, when the thickness of the chip packaging structure 100 is relatively small, the heat dissipation performance of the chip packaging structure 100 is guaranteed.

[0118] In specific implementation, the height of the heat sink 2 can be adjusted according to the thickness of the chip 1 and the distance between the surface of the chip 1 facing the second substrate 5 and the surface of the plastic package body 1 facing the second substrate 5 .

[0119] Optionally, the distance between two adjacent heat sinks 2 is 70 μm to 110 μm.

[0120] For example, Figure 5 As shown, the distance D between two adjacent heat sinks 2 is 90 μm.

[0121] It can be understood that the larger the distance D between two adjacent heat sinks 2 is, the easier it is for the plastic encapsulation material to flow through the gap between two adjacent heat sinks 2 when the chip 1 is encapsulated with the plastic encapsulation material, thereby avoiding the formation of pores in the plastic encapsulation body 6 between the two adjacent heat sinks 2, thereby improving the reliability of the chip packaging structure 100. However, the fewer the number of heat sinks 2 is, the more unfavorable it is to improve the heat dissipation performance of the chip 1; the smaller the distance D between two adjacent heat sinks 2 is, the more the number of heat sinks 2 is, which is beneficial to improving the heat dissipation performance of the chip 1. However, when the chip 1 is encapsulated with the plastic encapsulation material, it is not easy to flow through the gap between two adjacent heat sinks 2, and the plastic encapsulation body 6 between the two adjacent heat sinks 2 is prone to form pores, thereby reducing the reliability of the chip packaging structure 100.

[0122] By setting the spacing between two adjacent heat sinks 2 to 70 μm to 110 μm, the number of heat sinks 2 can be increased while avoiding the generation of pores in the plastic package 6 between two adjacent heat sinks 2, thereby improving the heat dissipation performance of the chip 1 while ensuring good reliability of the chip packaging structure 100.

[0123] Optionally, the heat sink 2 is cylindrical or rectangular.

[0124] The heat sink 2 is configured to be cylindrical or rectangular, which facilitates the processing and manufacturing of the heat sink 2 , thereby facilitating the reduction of the manufacturing cost of the chip packaging structure 100 .

[0125] Of course, in other embodiments, the heat sink 2 may also be configured in other shapes such as a triangular prism, a hexagonal prism, etc.

[0126] Optionally, the equivalent diameter of the heat sink 2 is 30 μm to 100 μm.

[0127] It can be understood that the larger the equivalent diameter of the heat sink 2, the better the structural strength of the heat sink 2, but the fewer the number of heat sinks 2 on the chip 1, which is not conducive to improving the heat dissipation uniformity of the chip 1; the smaller the equivalent diameter of the heat sink 2, the more the number of heat sinks 2 on the chip 1, which is more conducive to improving the heat dissipation uniformity of the chip 1, but the structural strength of the heat sink 2 is worse.

[0128] By setting the equivalent diameter of the heat sink 2 to 30 μm to 100 μm, the uniformity of heat dissipation of the chip 1 can be ensured while the structural strength of the heat sink 2 is ensured.

[0129] The chip packaging structure 100 of the disclosed embodiment can be used in HBPOP products. By providing multiple heat sinks 2, the flow of the plastic packaging material will not be blocked, and the performance of the chip packaging structure 100 is guaranteed; by forming the heat sink 2 and the chip 1 as one piece, the process of the chip packaging structure 100 is simple, and there is no need to add subsequent complex hole making and hole filling processes, which reduces stress accumulation, and there is no interface problem between the heat sink 2 and the chip 1, and the heat transfer effect of the heat sink 2 is better.

[0130] The chip packaging structure 100 of the embodiment of the present disclosure is subjected to thermal simulation experiments with the chip packaging structure in the related art. Given that the heat source area has the same power consumption of 5.66W, the temperature simulation of chip 1 is performed based on a mobile phone product at room temperature. Among them, the chip 1 in the chip packaging structure 100 of the embodiment of the present disclosure is a rectangle with a length of 10.7mm, a width of 10.4mm, and a thickness of 120μm. The heat sink 2 is a cube with a length of 70μm, a width of 70μm, and a height of 45μm. The distance between the surface of the chip 1 facing the second substrate 5 and the surface of the plastic package 1 facing the second substrate 5 is 200μm. In the chip packaging structure in the related art, the chip is a rectangle with a length of 10.7mm, a width of 10.4mm, and a thickness of 120μm. The PKG size of the chip packaging structure is 14*14.9. Figure 6 As shown, a comparison diagram of the heat dissipation effects of the chip packaging structure 100 of the embodiment of the present disclosure and the chip packaging structure in the related art shows that at room temperature, the maximum temperature of the heat source zone of the chip in the chip packaging structure in the related art is 95.3°C, while the maximum temperature of the heat source zone of chip 1 in the chip packaging structure 100 of the embodiment of the present disclosure is 91.4°C, and the maximum temperature is reduced by 4.1%, that is, the heat dissipation effect of chip 1 in the chip packaging structure 100 of the embodiment of the present disclosure is better.

[0131] like Figure 7 As shown, in the chip benchmark scenario, the chip junction temperature is evaluated to be 95°C, and the corresponding SOC and CPU power consumption. Under the same other conditions, the chip packaging structure 100 of the embodiment of the present disclosure improves the SOC and CPU power consumption of the chip benchmark scenario by 0.34w, which has obvious benefits, such as Figure 8 As shown, in comparison of chip thermal resistance, under the same other conditions, the chip thermal resistance of the chip packaging structure 100 of the embodiment of the present disclosure is reduced by 1.5K / W, and the thermal resistance improvement reaches 13.6%.

[0132] The electronic device of the embodiment of the present disclosure includes the chip packaging structure 100 described in any of the above embodiments. The electronic device may be a mobile phone, a tablet computer, a smart wearable device, a smart home device, etc.

[0133] For example, the solder ball 9 is soldered to a circuit board of an electronic device to achieve electrical connection between the chip 1 and the circuit board.

[0134] Although the embodiments of the present disclosure have been shown and described above, it is to be understood that the above embodiments are illustrative and cannot be construed as limitations on the present disclosure. Changes, modifications, substitutions and variations of the above embodiments by those of ordinary skill in the art are all within the scope of protection of the present disclosure.

Claims

1. A chip packaging method, characterized in that: The following steps are involved: Providing a chip to be packaged, wherein a first surface of the chip is formed with a plurality of heat sinks, and a second surface of the chip is formed with a plurality of interconnects; electrically connecting the interconnect to the first substrate; Electrically connecting the second substrate to the first substrate through an electrical connector, wherein the interconnector faces the first substrate and the heat sink faces the second substrate; A plastic package encapsulating the chip, the heat sink and the electrical connector is formed between the first substrate and the second substrate.

2. The chip packaging method according to claim 1, characterized in that: When the plastic packaging body is formed between the first substrate and the second substrate, the plastic packaging body fills the plastic packaging gap between two adjacent heat sinks.

3. The chip packaging method according to claim 2, characterized in that: When the second substrate is electrically connected to the first substrate, the surface of the heat sink facing away from the first substrate is in contact with the surface of the second substrate facing the first substrate; or When the second substrate is electrically connected to the first substrate, a heat dissipation gap is provided between the surface of the heat dissipation element facing away from the first substrate and the surface of the second substrate facing the first substrate, and the plastic package fills the heat dissipation gap.

4. The chip packaging method according to claim 1, characterized in that: Providing a chip to be packaged includes the following steps: forming a first protective layer on the front side of the wafer, wherein the first protective layer covers the front side of the wafer; forming a plurality of the heat sinks on the back side of the wafer; forming a second protective layer on the back side of the wafer, wherein the second protective layer covers the back side of the wafer; The first protective layer is removed, and the wafer is cut to form a plurality of chips, wherein the second surface of the chip has a plurality of interconnections.

5. The chip packaging method according to claim 4, characterized in that: A plurality of heat sinks are formed on the back side of the wafer by laser etching or dry etching.

6. The chip packaging method according to claim 4, characterized in that: The Young's modulus of the second protective layer is greater than or equal to a first preset value and less than or equal to a second preset value, and the viscosity of the second protective layer is greater than or equal to a preset viscosity to prevent the heat sink from shaking when the wafer is cut.

7. The chip packaging method according to any one of claims 1 to 6, characterized in that: Connecting the chip to the first substrate and electrically connecting the second substrate to the first substrate comprises the following steps: connecting the chip to the first substrate; Controlling the position of the second substrate so that the minimum distance between the second substrate and the first substrate is a preset distance; The second substrate is electrically connected to the first substrate.

8. The chip packaging method according to any one of claims 1 to 6, characterized in that: Forming a plastic package encapsulating the chip between the first substrate and the second substrate includes the following steps: The plastic encapsulation body is formed by a plastic encapsulation mold, wherein the pressure applied to the heat sink during the process of forming the plastic encapsulation body by mold closing and injection molding is less than or equal to a preset pressure.

9. A chip packaging structure, characterized in that: include: A chip, wherein a first surface of the chip is provided with a plurality of heat sinks, and a second surface of the chip is provided with a plurality of interconnects; a first substrate and a second substrate, the chip is arranged between the first substrate and the second substrate, the second substrate is electrically connected to the first substrate through an electrical connector, the interconnection member faces the first substrate and is electrically connected to the first substrate, and the heat sink faces the second substrate; A plastic package is disposed between the first substrate and the second substrate and wraps the chip, the heat sink and the electrical connector.

10. The chip packaging structure according to claim 9, characterized in that: The plastic sealing body fills the plastic sealing gap between two adjacent heat sinks.

11. The chip packaging structure according to claim 9, characterized in that: The surface of the heat sink facing away from the first substrate is in contact with the surface of the second substrate facing the first substrate; or A heat dissipation gap is formed between a surface of the heat dissipation element facing away from the first substrate and a surface of the second substrate facing the first substrate, and the plastic package fills the heat dissipation gap.

12. The chip packaging structure according to claim 9, characterized in that: The ratio of the height of the heat sink to the thickness of the chip is 0.3 to 0.5; and / or The distance between two adjacent heat sinks is 70 μm to 110 μm.

13. The chip packaging structure according to claim 9, characterized in that: The heat sink is cylindrical or rectangular; and / or The equivalent diameter of the heat sink is 30 μm to 90 μm.

14. The chip packaging structure according to claim 9, characterized in that: The heat sink and the chip are integrally formed.

15. An electronic device, characterized in that: A chip packaging structure comprising any one of claims 9 to 14.

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