Semiconductor device and manufacturing method thereof
By providing a nitride layer, a photoresist layer and an insulating medium in the semiconductor device, forming shallow trenches in the substrate layer, and setting step layers and thickened parts, the problem of aluminum diffusion in the semiconductor storage area is solved, and the reliability and performance of the device are improved.
Patent Information
- Application Number
- CN202311507864.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-11-10
- Publication Date
- 2025-05-13
AI Technical Summary
In the semiconductor 28nmHK process flow, the semiconductor memory area is prone to aluminum diffusion problems, resulting in device performance degradation or failure.
By providing a nitride layer, a photoresist layer and an insulating medium in the semiconductor device, and forming shallow trenches in the substrate layer, step layers and thickened portions are provided to prevent aluminum from diffusion.
It effectively prevents aluminum diffusion in the storage area, avoids the problem of degradation or failure of semiconductor devices, and improves the reliability and performance of the device.
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Figure CN119993899A_ABST
Abstract
Description
Technical Field
[0001] The present disclosure relates to the field of semiconductor technology, and in particular, to a semiconductor device and a method for manufacturing the same. Background Art
[0002] Shallow trench isolation (STI) originated in the 1980s. This process is a completely flat, completely bird-beak-free new isolation technology. This technology completely avoids high-temperature processes, strictly guarantees the area of the device active area, and the silicon substrate surface and the isolation medium surface are completely on the same plane, improving the minimum isolation interval and junction capacitance. At the same time, low-temperature processes can also potentially increase production and reduce costs.
[0003] In the related art, especially in the semiconductor 28nmHK process flow, the semiconductor gate is made of metal material, such as aluminum. However, aluminum diffusion is prone to occur in the semiconductor storage area, which may lead to performance degradation or failure of the semiconductor device. Summary of the invention
[0004] The purpose of the present disclosure is to provide a semiconductor device and a method for manufacturing the same, so as to solve the technical problems existing in the related art.
[0005] In order to achieve the above object, the present disclosure provides a semiconductor device, the semiconductor device comprising a substrate layer, a first pad oxide layer, a nitride layer and a photoresist layer, the first pad oxide layer being arranged on the substrate layer, the nitride layer being arranged on the first pad oxide layer, the nitride layer comprising a first region and a second region, the photoresist layer being arranged on the first region;
[0006] The second region is etched recessed toward the substrate layer and recessed into the substrate layer to form a shallow trench, wherein an insulating medium is disposed in the shallow trench;
[0007] The shallow trench comprises a first groove body portion located in the substrate layer, the insulating medium comprises a base layer and a step layer connected to each other, the base layer is arranged in the first groove body portion, and the step layer is arranged protruding from the first groove body portion;
[0008] The step layer comprises a step base and a thickened portion which are connected to each other, the step base is connected to the base layer, and the thickened portion is arranged on a side of the step base away from the base layer.
[0009] Optionally, the semiconductor device further includes a second pad oxide layer and a third pad oxide layer;
[0010] The first groove body portion includes a groove side wall and a groove bottom wall connected to each other, the second pad oxide layer covers the surface of the groove side wall, and one side of the second pad oxide layer is connected to the first pad oxide layer, and the third pad oxide layer covers the surface of the groove bottom wall, and the third pad oxide layer is connected to the other side of the second pad oxide layer;
[0011] The base layer is connected to a surface of the second pad oxide layer away from the side wall of the groove, and the base layer is connected to a surface of the third pad oxide layer away from the bottom wall of the groove.
[0012] Optionally, the thickened portion is configured as a layer of uniform thickness, and the thickness of the thickened portion is between 90A and 110A.
[0013] The present disclosure also provides a method for manufacturing a semiconductor device, the method comprising:
[0014] Disposing a first pad oxide layer on the surface of the substrate layer;
[0015] Depositing nitride on the surface of the first pad oxide layer to form a nitride layer;
[0016] Performing photolithography masking on a portion of the surface of the nitride layer to form a photoresist layer;
[0017] Etching the nitride layer, the first pad oxide layer and a portion of the substrate layer that are not protected by the photoresist layer to form a shallow trench;
[0018] Filling the shallow trench with an insulating medium;
[0019] Planarizing and grinding the surface of the insulating medium, with the nitride layer serving as a grinding stop layer;
[0020] Etching the insulating medium by etching back and reducing the etching time to a first time, so that the insulating medium protrudes from the step base of the substrate layer to provide a thickened portion;
[0021] The nitride layer is removed.
[0022] Optionally, before filling the shallow trench with an insulating medium,
[0023] A second pad oxide layer is provided on the side wall of the shallow trench located in the first groove body portion of the substrate layer, and the second pad oxide layer is connected to the first pad oxide layer; and
[0024] A third pad oxide layer is disposed on the bottom wall of the shallow trench located in the first groove body portion of the substrate layer, and the third pad oxide layer is connected to the second pad oxide layer.
[0025] Optionally, the planarizing and grinding the surface of the insulating medium, with the nitride layer serving as a grinding stop layer, comprises: planarizing and grinding the surface of the insulating medium using a chemical mechanical polishing process.
[0026] Optionally, etching the nitride layer, the first pad oxide layer, and a portion of the substrate layer that are not protected by the photoresist layer to form a shallow trench includes:
[0027] The nitride layer, the first pad oxide layer and a portion of the substrate layer that are not protected by the photoresist layer are etched by chemical vapor etching or physical etching.
[0028] Optionally, the filling the shallow trench with an insulating medium includes:
[0029] The shallow trench is filled with polysilicon or high-density silicon oxide, and after the filling is completed, the polysilicon or high-density silicon oxide is annealed.
[0030] Optionally, the shallow trench includes a first groove body portion located in the substrate layer, and a cross-section of the first groove body portion is trapezoidal;
[0031] The first groove body portion includes a groove side wall and a groove bottom wall connected to each other, and the groove side wall is inclined at an angle between 77 degrees and 83 degrees.
[0032] Optionally, the thickness of the thickened portion is between 90A and 110A.
[0033] In the above technical scheme, the first pad oxide layer acts as an isolation layer to protect the active area from chemical contamination during the process of removing the nitride layer; the nitride layer, on the one hand, acts as a solid mask material to help protect the active area, and on the other hand, can act as a barrier material; the photoresist layer uses a photolithography machine to directly engrave the pattern of a specific mask on the coated semiconductor device, and the engraved pattern of the photoresist layer is used to protect those areas of the semiconductor device that do not need to be etched; by filling the insulating medium into the shallow trench, the isolation effect between transistors can be enhanced, and by setting a step layer and setting a thickened portion on the step layer, the height of the step layer can be effectively increased, effectively blocking the problem of aluminum diffusion in the storage area, avoiding the problem of performance degradation or failure of the semiconductor device, and ensuring the high integration and high performance of the semiconductor device, while improving the reliability and performance of the semiconductor device.
[0034] Other features and advantages of the present disclosure will be described in detail in the following detailed description. BRIEF DESCRIPTION OF THE DRAWINGS
[0035] The accompanying drawings are used to provide a further understanding of the present disclosure and constitute a part of the specification. Together with the following specific embodiments, they are used to explain the present disclosure but do not constitute a limitation of the present disclosure. In the accompanying drawings:
[0036] Figure 1 It is a schematic diagram of the cross-sectional structure of a semiconductor device according to an embodiment of the present disclosure, and the insulating medium is not shown in the figure.
[0037] Figure 2 It is a schematic diagram of the cross-sectional structure of a semiconductor device according to an embodiment of the present disclosure, and the figure schematically shows an insulating medium filled in a shallow trench, and the insulating medium is planarized and polished to be flush with the nitride layer.
[0038] Figure 3 1 is a schematic diagram of the cross-sectional structure of a semiconductor device according to an embodiment of the present disclosure, in which the nitride layer is removed.
[0039] Figure 4 It is a schematic flow chart of a method for manufacturing a semiconductor device according to an embodiment of the present disclosure.
[0040] Description of Reference Numerals
[0041] 1 Substrate layer 2 First pad oxide layer
[0042] 3 Nitride layer 31 First region
[0043] 32 second region 4 photoresist layer
[0044] 5 Second pad oxide layer 6 Third pad oxide layer
[0045] 10 shallow groove 101 first groove part
[0046] 1011 groove side wall 1012 groove bottom wall
[0047] 100 Insulation medium 1001 Base layer
[0048] 1002 step layer 1003 step base
[0049] 1004 Thickening DETAILED DESCRIPTION
[0050] The specific implementation of the present disclosure is described in detail below in conjunction with the accompanying drawings. It should be understood that the specific implementation described herein is only used to illustrate and explain the present disclosure, and is not used to limit the present disclosure.
[0051] Reference Figures 1 to 3As shown, the present disclosure provides a semiconductor device, which includes a substrate layer 1, a first pad oxide layer 2, a nitride layer 3 and a photoresist layer 4, wherein the first pad oxide layer 2 is arranged on the substrate layer 1, the nitride layer 3 is arranged on the first pad oxide layer 2, the nitride layer 3 includes a first region 31 and a second region 32, and the photoresist layer 4 is arranged on the first region 31. The second region 32 is etched and recessed toward the substrate layer 1 and recessed into the substrate layer 1 to form a shallow trench 10, in which an insulating medium 100 is arranged. The shallow trench 10 includes a first groove body portion 101 located in the substrate layer 1, and the insulating medium 100 includes a base layer 1001 and a step layer 1002 connected to each other, the base layer 1001 is arranged in the first groove body portion 101, and the step layer 1002 is arranged protruding from the first groove body portion 101. The step layer 1002 includes a step base 1003 and a thickened portion 1004 which are connected to each other. The step base 1003 is connected to the base layer 1001 , and the thickened portion 1004 is arranged on a side of the step base 1003 away from the base layer 1001 .
[0052] In the above technical scheme, the first pad oxide layer 2 is used as an isolation layer to protect the active area from chemical contamination during the process of removing the nitride layer 3; the nitride layer 3 is used as a solid mask material on the one hand, which helps to protect the active area, and can be used as a blocking material on the other hand; the photoresist layer 4 uses a photolithography machine to directly engrave the pattern of a specific mask on the coated semiconductor device, and the engraved pattern of the photoresist layer 4 is used to protect those areas of the semiconductor device that do not need to be etched; by filling the insulating medium 100 into the shallow trench 10, the isolation effect between transistors can be enhanced, and by setting the step layer 1002 and setting the thickened portion 1004 on the step layer 1002, the height of the step layer 1002 can be effectively increased, effectively blocking the problem of aluminum diffusion in the storage area, avoiding the problem of performance degradation or failure of the semiconductor device, and ensuring the high integration and high performance of the semiconductor device, while improving the reliability and performance of the semiconductor device.
[0053] In one embodiment, referring to Figures 1 to 3As shown, the semiconductor device further includes a second pad oxide layer 5 and a third pad oxide layer 6; the first groove body portion 101 includes a groove sidewall 1011 and a groove bottom wall 1012 connected to each other, the second pad oxide layer 5 covers the surface of the groove sidewall 1011, and one side of the second pad oxide layer 5 is connected to the first pad oxide layer 2, the third pad oxide layer 6 covers the surface of the groove bottom wall 1012, and the third pad oxide layer 6 is connected to the other side of the second pad oxide layer 5, the base layer 1001 is connected to the surface of the second pad oxide layer 5 away from the groove sidewall 1011, and the base layer 1001 is connected to the surface of the third pad oxide layer 6 away from the groove bottom wall 1012. By arranging the second pad oxide layer 5 and the third pad oxide layer 6 on the groove wall of the first groove body portion 101, the insulation performance can be further improved to prevent current leakage. In addition, the first pad oxide layer 2, the second pad oxide layer 5 and the third pad oxide layer 6 can also play a role in stress buffering.
[0054] Optionally, the thickened portion 1004 is configured as a uniform thickness layer, and the thickness of the thickened portion 1004 is between 90A and 110A. For example, the thickness of the thickened portion 1004 can be set to 90A, 100A, or 110A, and the present disclosure does not limit this. In addition, the thickness of the step base 1003 can be set to 210A, but the present disclosure does not limit the thickness of the step base 1003.
[0055] In addition, the above-mentioned substrate layer 1 can be manufactured and processed using silicon material, the first pad oxide layer 2, the second pad oxide layer 5 and the third pad oxide layer 6 can all be constructed as silicon oxide, the nitride layer 3 can be constructed as silicon nitride, and the insulating medium 100 can be made of polycrystalline silicon or high-density silicon oxide, but the present disclosure does not limit the above-mentioned materials.
[0056] The present disclosure also provides a method for manufacturing a semiconductor device, the method comprising:
[0057] S11, providing a first pad oxide layer 2 on the surface of the substrate layer 1;
[0058] S12, depositing nitride on the surface of the first pad oxide layer 2 to form a nitride layer 3;
[0059] S13, performing photolithography masking on a portion of the surface of the nitride layer 3 to form a photoresist layer 4;
[0060] S14, etching the nitride layer 3, the first pad oxide layer 2 and a portion of the substrate layer 1 which are not protected by the photoresist layer 4, to form a shallow trench 10;
[0061] S15, filling the shallow trench 10 with an insulating medium 100;
[0062] S16, planarizing and grinding the surface of the insulating medium 100, and using the nitride layer 3 as a grinding stop layer;
[0063] S17, etching the insulating medium 100 by etching back and reducing the etching time to the first time, so that the insulating medium 100 protrudes from the step base 1003 of the substrate layer to add a thickened portion 1004;
[0064] S18, removing the nitride layer 3.
[0065] In the above technical scheme, the first pad oxide layer 2 is used as an isolation layer to protect the active area from chemical contamination during the process of removing the nitride layer 3; the nitride layer 3 is used as a solid mask material on the one hand, which helps to protect the active area, and can be used as a blocking material on the other hand; the photoresist layer 4 uses a photolithography machine to directly print the pattern of a specific mask on the coated semiconductor device, and the printed pattern of the photoresist layer 4 is used to protect those areas of the semiconductor device that do not need to be etched; by filling the insulating medium 100 into the shallow trench 10, the isolation effect between transistors can be enhanced, and the insulating medium 100 is etched by back etching and the etching time is reduced to the first time, so that the insulating medium 100 protrudes from the step base 1003 of the substrate layer. The thickened portion 1004 is added, which can effectively increase the height of the step layer 1002, effectively prevent the problem of aluminum diffusion in the storage area, avoid the problem of performance degradation or failure of the semiconductor device, and improve the reliability and performance of the semiconductor device while ensuring the high integration and high performance of the semiconductor device.
[0066] In addition, the first time mentioned above can be set according to the required thickness of the thickened portion 1004, and the present disclosure does not limit this.
[0067] Optionally, before the shallow trench 10 is filled with the insulating medium 100,
[0068] A second pad oxide layer 5 is disposed on the groove sidewall 1011 of the first groove body portion 101 of the shallow groove 10 located on the substrate layer 1, and the second pad oxide layer 5 is connected to the first pad oxide layer 2; and,
[0069] A third pad oxide layer 6 is disposed on the bottom wall 1012 of the first groove body portion 101 of the shallow groove 10 located on the substrate layer 1 , and the third pad oxide layer 6 is connected to the second pad oxide layer 5 .
[0070] By providing a second pad oxide layer 5 and a third pad oxide layer 6 on the groove wall of the first groove body portion 101, the insulation performance can be further improved to prevent current leakage. In addition, the first pad oxide layer 2, the second pad oxide layer 5 and the third pad oxide layer 6 can also play a role in stress buffering.
[0071] In one embodiment, the surface of the insulating medium 100 is planarized and ground, and the nitride layer 3 is used as a stop layer for grinding, including: using a chemical mechanical polishing process to planarize and grind the surface of the insulating medium 100.
[0072] The chemical mechanical polishing process is also called the CMP (Chemical-Mechanical Polishing) process. This process mainly removes the excess insulating dielectric 100 on the surface after the insulating dielectric 100 fills the shallow trench 10 to achieve complete surface flatness. When the CMP rate of the insulating dielectric 100 is equivalent to the CMP rate of the nitride layer 3, the surface of the nitride layer 3 after CMP is approximately on the same plane as the insulating dielectric 10 filled in the shallow trench 10. Since there will be a little oxide film loss in the cleaning after CMP, the thickness of the nitride layer 3 will determine the step height between the active area surface and the insulating dielectric surface. The insulating dielectric 100 can avoid the generation of parasitic corner transistor effects. Within this limit, the residual thickness of the nitride layer 3 after CMP is optimized to obtain accurate field area graphics. The insulating dielectric 100 on the active area must be polished off to expose the nitride layer 3 underneath and be on the same plane as the surface of the insulating dielectric 100 in the shallow trench 10. In fact, the grinding rate on isolated, narrow graphic structures is faster than that on densely arranged or wide-area graphic structures. When grinding the uneven wafer surface, the pressure on the protrusions is much higher than that on the concave parts, so the protrusions are ground faster. However, due to the softness of the grinding disc, a butterfly-shaped depression will appear in the center of the wide area.
[0073] In some embodiments, the nitride layer 3, the first pad oxide layer 2 and a portion of the substrate layer 1 which are not protected by the photoresist layer 4 are etched to form a shallow trench 10, including:
[0074] The nitride layer 3 , the first pad oxide layer 2 , and a portion of the substrate layer 1 that are not protected by the photoresist layer 4 are etched by chemical vapor etching or physical etching, but the present disclosure does not limit the etching method.
[0075] For example, an etcher can be used for etching. The etcher uses high-power radio frequency energy to ionize fluorine-based or chlorine-based gases in a vacuum reaction chamber. The radio frequency energy decomposes molecules and ionizes atoms, filling the reaction chamber with a variety of plasma components. These plasma components remove the silicon located as isolation areas on the silicon wafer through physical etching and chemical etching. After each step of the etching process is completed, the silicon wafer must be debonded and cleaned in a series of chemical reagents.
[0076] In other embodiments, the shallow trench 10 is filled with the insulating medium 100, including:
[0077] The shallow trench 10 is filled with polysilicon or high-density silicon oxide, and after the filling is completed, the polysilicon or high-density silicon oxide is annealed to improve the density and flatness of the insulating medium 100, but the present disclosure does not limit the specific material of the insulating medium 100.
[0078] Optionally, the shallow trench 10 includes a first trench body portion 101 located in the substrate layer 1, and the cross-section of the first trench body portion 101 is a trapezoid; the first trench body portion 101 includes a trench sidewall 1011 and a trench bottom wall 1012 connected to each other, and the trench sidewall 1011 is inclined at an angle between 77 degrees and 83 degrees. A method commonly used to control the shape of the shallow trench 10 is to use etching gases such as CL2, HBr and O2, which can produce polymer products when used for silicon etching, and these products can form a positive trapezoid when the shallow trench 10 is etched.
[0079] Optionally, the thickness of the thickened portion 1004 is between 90A and 110A. For example, the thickness of the thickened portion 1004 can be set to 90A, 100A, or 110A, and the present disclosure does not limit this. In addition, the thickness of the step base 1003 can be set to 210A, but the present disclosure does not limit the thickness of the step base 1003.
[0080] The preferred embodiments of the present disclosure are described in detail above in conjunction with the accompanying drawings; however, the present disclosure is not limited to the specific details in the above embodiments. Within the technical concept of the present disclosure, a variety of simple modifications can be made to the technical solution of the present disclosure, and these simple modifications all fall within the protection scope of the present disclosure.
[0081] It should also be noted that the various specific technical features described in the above specific embodiments can be combined in any suitable manner without contradiction. In order to avoid unnecessary repetition, the present disclosure will not further describe various possible combinations.
[0082] In addition, various embodiments of the present disclosure may be arbitrarily combined, and as long as they do not violate the concept of the present disclosure, they should also be regarded as the contents disclosed by the present disclosure.
Claims
1. A semiconductor device, characterized in that: The semiconductor device comprises a substrate layer, a first pad oxide layer, a nitride layer and a photoresist layer, wherein the first pad oxide layer is arranged on the substrate layer, the nitride layer is arranged on the first pad oxide layer, the nitride layer comprises a first region and a second region, and the photoresist layer is arranged on the first region; The second region is etched recessed toward the substrate layer and recessed into the substrate layer to form a shallow trench, wherein an insulating medium is disposed in the shallow trench; The shallow trench comprises a first groove body portion located in the substrate layer, the insulating medium comprises a base layer and a step layer connected to each other, the base layer is arranged in the first groove body portion, and the step layer is arranged protruding from the first groove body portion; The step layer comprises a step base and a thickened portion which are connected to each other, the step base is connected to the base layer, and the thickened portion is arranged on a side of the step base away from the base layer.
2. The semiconductor device according to claim 1, wherein: The semiconductor device further includes a second pad oxide layer and a third pad oxide layer; The first groove body portion includes a groove side wall and a groove bottom wall connected to each other, the second pad oxide layer covers the surface of the groove side wall, and one side of the second pad oxide layer is connected to the first pad oxide layer, and the third pad oxide layer covers the surface of the groove bottom wall, and the third pad oxide layer is connected to the other side of the second pad oxide layer; The base layer is connected to a surface of the second pad oxide layer away from the groove sidewall, and the base layer is connected to a surface of the third pad oxide layer away from the groove bottom wall.
3. The semiconductor device according to claim 1 or 2, characterized in that: The thickened portion is configured as a uniform thickness layer, and the thickness of the thickened portion is between 90A and 110A.
4. A method for manufacturing a semiconductor device, characterized in that: The manufacturing method comprises: Disposing a first pad oxide layer on the surface of the substrate layer; Depositing nitride on the surface of the first pad oxide layer to form a nitride layer; Performing photolithography masking on a portion of the surface of the nitride layer to form a photoresist layer; Etching the nitride layer, the first pad oxide layer and a portion of the substrate layer that are not protected by the photoresist layer to form a shallow trench; Filling the shallow trench with an insulating medium; Planarizing and grinding the surface of the insulating medium, with the nitride layer serving as a grinding stop layer; Etching the insulating medium by etching back and reducing the etching time to a first time, so that the insulating medium protrudes from the step base of the substrate layer to provide a thickened portion; The nitride layer is removed.
5. The method for manufacturing a semiconductor device according to claim 4, wherein: Before filling the shallow trench with an insulating medium, Disposing a second pad oxide layer on the sidewall of the shallow trench located in the first groove body portion of the substrate layer, and the second pad oxide layer is connected to the first pad oxide layer; and, A third pad oxide layer is disposed on the bottom wall of the shallow trench located in the first groove body portion of the substrate layer, and the third pad oxide layer is connected to the second pad oxide layer.
6. The method for manufacturing a semiconductor device according to claim 4, wherein: The planarizing and grinding the surface of the insulating medium, with the nitride layer serving as a grinding stop layer, includes: planarizing and grinding the surface of the insulating medium using a chemical mechanical polishing process.
7. The method for manufacturing a semiconductor device according to claim 4, wherein: The etching of the nitride layer, the first pad oxide layer, and a portion of the substrate layer that are not protected by the photoresist layer to form a shallow trench includes: The nitride layer, the first pad oxide layer and a portion of the substrate layer that are not protected by the photoresist layer are etched by chemical vapor etching or physical etching.
8. The method for manufacturing a semiconductor device according to claim 4, wherein: The step of filling the shallow trench with an insulating medium comprises: The shallow trench is filled with polysilicon or high-density silicon oxide, and after the filling is completed, the polysilicon or high-density silicon oxide is annealed.
9. The method for manufacturing a semiconductor device according to claim 4, wherein: The shallow trench comprises a first groove body portion located in the substrate layer, and the cross-section of the first groove body portion is a trapezoid; The first groove body portion includes a groove side wall and a groove bottom wall connected to each other, and the groove side wall is inclined at an angle between 77 degrees and 83 degrees.
10. The method for manufacturing a semiconductor device according to claim 4, wherein: The thickness of the thickened portion is between 90A and 110A.