Semiconductor device and manufacturing method thereof

Abstract

The invention relates to a semiconductor device and a manufacturing method thereof, and the method comprises the steps: providing a substrate which comprises a preset region used for forming an isolation groove, and the top corner of one side, close to the preset region, of the substrate is a right angle; non-crystallization ion implantation is carried out on the preset area so that a non-crystallization ion implantation area can be formed on the side, close to the surface of the substrate, in the preset area, the non-crystallization ion implantation area extends into the portions, on the two sides of the preset area, of the substrate, and the top corners are made to be smooth; oxidizing the non-crystallized ion implantation region and forming a first oxide layer; the portion, located above the preset area, of the first oxide layer is removed, the portion, in the preset area, of the substrate is removed to form the isolation groove, the top corners are located on the two sides of a top opening of the isolation groove, and the remaining first oxide layer covers the top corners. According to the invention, the probability of forming a recess defect in the shallow trench isolation structure is reduced or avoided.

Description

Technical Field

[0001] The present application relates to the field of semiconductor manufacturing technology, and in particular to a semiconductor device and a manufacturing method thereof. Background Art

[0002] In general semiconductor manufacturing processes, an etching process is usually performed immediately after an oxide layer and a silicon nitride layer are deposited on a silicon substrate to form a shallow trench isolation (STI) structure on the silicon substrate. Next, an insulating oxide layer is first filled in the shallow trench isolation structure, and then the silicon nitride layer on the silicon substrate is removed, so that the portion of the insulating oxide layer located in the top corner area of ​​the shallow trench isolation structure is exposed.

[0003] However, when the portion of the insulating oxide layer located in the top corner region of the shallow trench isolation structure is exposed, during the subsequent wet etching process (Wet), hydrofluoric acid (HF) will consume the insulating oxide layer (the material of the insulating oxide layer is, for example, SiO2) at the top corner region, and cause a depression (Divot) to form in the top corner region of the shallow trench isolation structure. When there is a depression in the top corner region of the shallow trench isolation structure, it is easy to generate a polysilicon residue (Poly Residue) defect in the depression in the subsequent polysilicon (Poly) process, or cause other side effects (Side Effect), thereby seriously affecting the yield and stability of the semiconductor device. Summary of the invention

[0004] Based on this, it is necessary to provide a semiconductor device and a manufacturing method thereof, which can reduce or avoid the probability of depression defects in the shallow trench isolation structure and improve the yield and stability of the semiconductor device.

[0005] The present application provides a method for manufacturing a semiconductor device, comprising:

[0006] Providing a substrate, wherein the substrate includes a preset area for forming an isolation trench, and a top corner of the substrate close to the preset area is at a right angle;

[0007] Performing amorphization ion implantation into the preset region to form an amorphization ion implantation region on one side of the preset region close to the substrate surface, wherein the amorphization ion implantation region extends into the substrate on both sides of the preset region and rounds the top corner;

[0008] Oxidizing the amorphized ion implanted region to form a first oxide layer;

[0009] The portion of the first oxide layer located above the preset area is removed, and the substrate in the preset area is removed to form the isolation trench, wherein the top corner is located on both sides of the top opening of the isolation trench, and the remaining first oxide layer covers the top corner.

[0010] In one embodiment, the process of performing amorphization ion implantation into the preset region to form an amorphization ion implantation region on a side of the preset region close to the substrate surface includes:

[0011] Performing a first ion implantation process with a first implantation angle in the predetermined area to form a first ion implantation region;

[0012] Performing a second ion implantation process with a second implantation angle in the preset area to form a second ion implantation region, wherein the amorphization ion implantation region includes the first ion implantation region and the second ion implantation region;

[0013] The inclination direction of the first implantation angle is the same as that of the second implantation angle and is opposite in direction, and the first ion implantation region and the second ion implantation region at least partially overlap.

[0014] In one of the embodiments, along a direction perpendicular to the surface of the substrate and penetrating into the substrate, a cross-sectional width of the first ion implantation region and a cross-sectional width of the second ion implantation region gradually decrease.

[0015] In one embodiment, the amorphization ions implanted during the amorphization ion implantation process include germanium ions.

[0016] In one embodiment, the amorphized ion implanted region is oxidized to form the first oxide layer by a furnace oxidation process;

[0017] In the process of oxidizing the amorphized ion implanted region to form the first oxide layer, a portion located on the surface side of the substrate is oxidized together and forms a portion of the first oxide layer.

[0018] In one of the embodiments, along a direction perpendicular to the surface of the substrate, a cross-sectional shape of the top corner is arc-shaped.

[0019] In one of the embodiments, after forming the isolation trench, the method for manufacturing the semiconductor device further includes:

[0020] Filling the isolation trench with a second oxide layer to form a shallow trench isolation structure including the isolation trench and an oxide layer, wherein the oxide layer includes the second oxide layer and a portion of the first oxide layer located above the top corner;

[0021] A portion of the oxide layer away from one side of the isolation trench is removed to expose the substrate at a side of the top corner away from the isolation trench, and the remaining oxide layer fills the isolation trench.

[0022] In one embodiment, after forming the first oxide layer and before forming the isolation trench, the method for manufacturing the semiconductor device further includes:

[0023] forming a hard mask layer on the first oxide layer;

[0024] The process of removing the portion of the first oxide layer located above the preset area further includes: removing the portion of the hard mask layer located above the preset area so that the isolation trench penetrates the hard mask layer;

[0025] After the isolation trench is filled with a second oxide layer and before a portion of the oxide layer away from a side of the isolation trench is removed, the method for manufacturing a semiconductor device further includes:

[0026] The hard mask layer is removed.

[0027] Accordingly, the present application also provides a semiconductor device, comprising:

[0028] substrate;

[0029] An isolation trench is located in the substrate, and the substrate on both sides of the isolation trench is provided with rounded top corners;

[0030] The first oxide layer is located on the substrate, and the first oxide layer covers the top corner.

[0031] In one embodiment, the semiconductor device further includes:

[0032] The second oxide layer is located in the isolation trench, and the surface of the second oxide layer is higher than the surface of the first oxide layer, or the surface of the second oxide layer is flush with the surface of the first oxide layer.

[0033] The unexpected effect of the present application is: by forming an amorphized ion implantation region in a preset area of ​​the substrate, the top corners of the substrate near the preset area are rounded; by oxidizing the amorphized ion implantation region to form a first oxide layer, and forming an isolation trench in the preset area, the top corners on both sides of the isolation trench are rounded and covered by the first oxide layer, reducing or avoiding the risk of recessed defects in the subsequently formed shallow trench isolation structure, thereby helping to improve the performance and stability of semiconductor devices. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the conventional technology, the drawings required for use in the embodiments or the conventional technology descriptions are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0035] Figure 1 The schematic diagram is a structural diagram corresponding to the step of providing a semiconductor substrate in a method for manufacturing an STI structure in the related art.

[0036] Figure 2 It is a structural schematic diagram corresponding to the step of forming a trench in a method for manufacturing an STI structure in the related art.

[0037] Figure 3 It is a structural schematic diagram corresponding to the step of filling an isolation layer in a trench in a method for manufacturing an STI structure in the related art.

[0038] Figure 4 It is a structural schematic diagram corresponding to the step of removing the silicon nitride layer in a method for manufacturing an STI structure in the related art.

[0039] Figure 5 The present invention is a structural schematic diagram corresponding to the step of etching an oxide layer and an isolation layer to form an STI structure in a method for manufacturing an STI structure in the related art.

[0040] Figure 6 A flow chart of a method for manufacturing a semiconductor device provided in one of the embodiments of the present application.

[0041] Figure 7 A structural schematic diagram corresponding to the step of providing a substrate in a method for manufacturing a semiconductor device provided in one of the embodiments of the present application.

[0042] Figure 8 A structural schematic diagram corresponding to a process of amorphizing ion implantation in a method for manufacturing a semiconductor device provided in one of the embodiments of the present application.

[0043] Fig. 9 A schematic structural diagram corresponding to the step of forming an amorphous ion implantation region in a method for manufacturing a semiconductor device provided in one of the embodiments of the present application.

[0044] Fig.10 A schematic structural diagram corresponding to the step of growing a first oxide layer on an amorphized ion implantation region and a substrate in a method for manufacturing a semiconductor device provided in one of the embodiments of the present application.

[0045] Fig.11A schematic structural diagram corresponding to the step of forming a hard mask layer on a first oxide layer in a method for manufacturing a semiconductor device according to one embodiment of the present application.

[0046] Fig.12 A structural schematic diagram corresponding to the step of forming an isolation trench in a method for manufacturing a semiconductor device provided in one of the embodiments of the present application.

[0047] Fig.13 A schematic structural diagram corresponding to the step of filling and forming a second oxide layer in an isolation trench in a method for manufacturing a semiconductor device according to one embodiment of the present application.

[0048] Fig.14 A schematic structural diagram corresponding to the step of removing a hard mask layer in a method for manufacturing a semiconductor device provided in one of the embodiments of the present application.

[0049] Fig.15 A structural schematic diagram corresponding to the step of etching the first oxide layer and the second oxide layer and forming a shallow trench isolation structure in a method for manufacturing a semiconductor device provided in one of the embodiments of the present application.

[0050] Among them, the figure marks include: 100-semiconductor substrate; 110-oxide layer; 120-silicon nitride layer; 130-photoresist layer; 131-anti-reflective layer; 140-groove; 150-isolation layer; 151-depression defect; X1-STI structure; 200-substrate; 200a-preset area; 201-amorphized ion implantation area; 201a-first ion implantation area; 201b-second ion implantation area; 210-mask layer; 220-first oxide layer; 230-hard mask layer; 240-isolation trench; 250-second oxide layer; X2-shallow trench isolation structure; B-top corner. DETAILED DESCRIPTION

[0051] In order to facilitate understanding of the present application, the present application will be described more fully below with reference to the relevant drawings. Embodiments of the present application are provided in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.

[0052] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0053] It should be understood that when an element or layer is referred to as "on ...", "adjacent to ...", "connected to" or "coupled to" other elements or layers, it can be directly on, adjacent to, connected to or coupled to other elements or layers, or there can be intervening elements or layers. On the contrary, when an element is referred to as "directly on ...", "directly adjacent to ...", "directly connected to" or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. can be used to describe various elements, components, regions, layers, doping types and / or parts, these elements, components, regions, layers, doping types and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type or part from another element, component, region, layer, doping type or part. Therefore, without departing from the teachings of the present invention, the first element, component, region, layer, doping type or portion discussed below may be represented as a second element, component, region, layer or portion; for example, the first doping type may be referred to as the second doping type, and similarly, the second doping type may be referred to as the first doping type; the first doping type and the second doping type are different doping types, for example, the first doping type may be P-type and the second doping type may be N-type, or the first doping type may be N-type and the second doping type may be P-type.

[0054] Spatially relative terms such as "under," "beneath," "below," "under," "above," "above," and the like may be used herein to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that, in addition to the orientations shown in the figures, spatially relative terms also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is flipped, an element or feature described as "under other elements" or "under it" or "under it" will be oriented as being "above" the other elements or features. Thus, the exemplary terms "under" and "under" may include both upper and lower orientations. In addition, the device may also include additional orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptors used herein are interpreted accordingly.

[0055] When used herein, the singular forms "a", "an" and " / the" may also include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "include / comprise" or "have" and the like specify the presence of stated features, wholes, steps, operations, components, parts or combinations thereof, but do not exclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts or combinations thereof. At the same time, in this specification, the term "and / or" includes any and all combinations of the relevant listed items.

[0056] In a general semiconductor device manufacturing method, a concave defect is easily formed at the top corner region of the STI structure, which has a negative impact on the performance of the semiconductor device. For example, the formation process of the concave defect can refer to Figures 1 to 5 The manufacturing process of the semiconductor device.

[0057] First, see Figure 1 A semiconductor substrate 100 is provided, the semiconductor substrate 100 is covered with an oxide layer 110 and a silicon nitride layer 120, and a patterned photoresist layer 130 is formed on the silicon nitride layer 120. Optionally, other semiconductor structures are formed between the silicon nitride layer 120 and the patterned photoresist layer 130, for example, an anti-reflection layer 131 can be formed between the silicon nitride layer 120 and the patterned photoresist layer 130 to reduce reflection of light.

[0058] Next, see Figure 2 The silicon nitride layer 120 , the oxide layer 110 and the semiconductor substrate 100 are etched using the patterned photoresist layer 130 as a mask to form a trench 140 penetrating the silicon nitride layer 120 and the oxide layer 110 and extending into the semiconductor substrate 100 , and then the patterned photoresist layer 130 is removed.

[0059] Then, see Figure 3 , an isolation layer 150 is filled in the trench 140, and the isolation layer 150 extends to cover the silicon nitride layer 120 on both sides of the trench 140. Optionally, the material of the isolation layer 150 includes silicon oxide or other oxide materials.

[0060] Next, see Figure 4 , etching and removing the silicon nitride layer 120, a portion of the oxide layer 110, and a portion of the isolation layer 150 located on the silicon nitride layer 120; see Figure 5 The remaining oxide layer 110 and part of the isolation layer 150 are removed by a wet etching process to expose the semiconductor substrate 100 on both sides of the trench 140 and form an STI structure X1, wherein the STI structure X1 includes the trench 140 and the isolation layer 150.

[0061] However, after the silicon nitride layer 120, part of the oxide layer 110 and part of the isolation layer 150 are removed by etching, since the thickness of the remaining oxide layer 110 is less than the thickness of the surface portion of the isolation layer 150 that is higher than the semiconductor substrate 100, in the subsequent wet etching process, the oxide layer 110 will be removed before the isolation layer 150, and the top corner of the trench 140 will be exposed. In the subsequent wet etching process, the top and sidewall of the portion of the isolation layer 150 that is higher than the semiconductor substrate 100 are etched, thereby forming a concave defect 151 at the top corner. If the depth of the concave defect 151 is too deep, the problem of polysilicon residue (Poly residue) is likely to occur in the subsequent polysilicon (Poly) process, and other side effects may also occur, which may even affect the performance stability of the semiconductor device in severe cases.

[0062] In order to solve the above problems, the present application provides a semiconductor device and a manufacturing method thereof, which helps to reduce or avoid the probability of depressions occurring at the top corners of the shallow trench isolation structure, thereby improving the yield and stability of the semiconductor device.

[0063] Figure 6 A flowchart of a method for manufacturing a semiconductor device provided in one embodiment of the present application. Figure 6 One embodiment of the present application provides a method for manufacturing a semiconductor device, including the following steps S01 to S04.

[0064] Step S01: providing a substrate, wherein the substrate includes a preset area for forming an isolation trench, and a top corner of the substrate close to the preset area is a right angle.

[0065] Step S02: performing amorphization ion implantation into the preset region to form an amorphization ion implantation region on one side of the preset region close to the substrate surface, wherein the amorphization ion implantation region extends into the substrate on both sides of the preset region and rounds the top corner.

[0066] Step S03: oxidizing the amorphized ion implanted region to form a first oxide layer.

[0067] It should be noted that, since an amorphized ion implantation region is formed on one side of the preset area close to the substrate surface in step S02, and the amorphized ion implantation region extends into the substrate on both sides of the preset area and the top corner is rounded, the portion of the amorphized ion implantation region extending into the substrate covers the top corner, and accordingly, the first oxide layer formed by oxidation of the amorphized ion implantation region also covers the above-mentioned top corner.

[0068] Step S04: removing the portion of the first oxide layer located above the preset area, and removing the substrate in the preset area to form the isolation trench, wherein the top corners are located on both sides of the top opening of the isolation trench, and the remaining first oxide layer covers the top corners. It should be noted that when the first oxide layer covers the top corners, the first oxide layer can play a protective role in the subsequent process of the shallow trench isolation structure, thereby reducing or avoiding the generation of recessed defects in the oxide layer of the shallow trench isolation structure.

[0069] The manufacturing method of the semiconductor device as described above forms an amorphized ion implantation region in a preset region of the substrate, so that the top corners of the substrate near the preset region are rounded; the amorphized ion implantation region is oxidized to form a first oxide layer, and an isolation trench is formed in the preset region, so that the top corners on both sides of the isolation trench are rounded and covered by the first oxide layer, thereby reducing or avoiding the risk of generating a recessed defect in a subsequently formed shallow trench isolation structure, thereby helping to improve the performance and stability of the semiconductor device.

[0070] See also Figure 7 In one embodiment, a substrate 200 is provided, wherein the substrate 200 includes a predetermined region 200a for forming an isolation trench, and a top corner B of the substrate 200 close to the predetermined region 200a is a right angle. Optionally, the substrate 200 is a silicon substrate.

[0071] See also Figure 8 In one embodiment, amorphizing ion implantation is performed into a preset region 200a of a substrate 200 to form an amorphizing ion implantation region 201 on one side of the preset region 200a close to the surface of the substrate 200. The amorphizing ion implantation region 201 extends into the substrate 200 on both sides of the preset region 200a and rounds the top corner B.

[0072] For example, see Figure 8 and Fig. 9 The process of forming an amorphized ion implantation region 201 in a predetermined region 200a of a substrate 200 includes: forming a patterned mask layer 210 on the substrate, wherein the patterned mask layer 210 exposes the predetermined region 200a in the substrate 200; performing a first ion implantation process (i.e., implanting an amorphized ion implantation region 201 at a first implantation angle) in the predetermined region 200a using the mask layer 210 as a mask; Figure 8 The process indicated by the solid arrow in the middle) is used to form a first ion implantation region 201a; a second ion implantation process with a second implantation angle is performed in the predetermined region 201a (ie Figure 8The process is represented by the dotted arrow in the figure) to form the second ion implantation area 201b, the amorphized ion implantation area 201 includes the first ion implantation area 201a and the second ion implantation area 201b; and the mask layer 210 is removed. Optionally, the inclination direction of the first implantation angle is opposite to the inclination direction of the second implantation angle, the first implantation angle is the same as the second implantation angle, and the first ion implantation area 201a and the second ion implantation area 201b partially overlap.

[0073] Continue reading Figure 8 and Fig. 9 In one embodiment, along the direction of vertical injection into the surface of the substrate 200, the cross-sectional width of the first ion implantation region 201a and the cross-sectional width of the second ion implantation region 201b gradually decrease, and the cross-sectional morphology of the first ion implantation region 201a and the second ion implantation region 201b is a cone with the tip pointing downward.

[0074] In other embodiments of the present application, the relative position and morphology of the first ion implantation region and the second ion implantation region can be adjusted according to actual needs. For example, the first ion implantation region and the second ion implantation region can completely overlap, and the relevant parameters of the first ion implantation process and the second ion implantation process can be adjusted according to actual needs. It is only necessary to ensure that "the amorphized ion implantation region can extend into the substrate on both sides of the preset area and make the top corners in the substrate rounded". The present application does not impose any restrictions on this.

[0075] In other embodiments of the present application, the amorphized ion implantation region can be formed through several ion implantation processes, and the specific morphology of the amorphized ion implantation region can be adjusted by adjusting the process parameters of each ion implantation process to form an amorphized ion implantation region that meets the process requirements.

[0076] In one of the embodiments, amorphizing ions are ions that can be implanted into the substrate to form an amorphizing ion implantation region. Amorphizing ions include germanium (Ge) ions, arsenic (As) ions, boron (B) ions, phosphorus (P) ions, etc. Those skilled in the art can select suitable amorphizing ions for ion implantation process according to actual process requirements to form an amorphizing ion implantation region.

[0077] See also Fig.10In one embodiment, the amorphized ion implanted region 201 is oxidized to form a first oxide layer 220. Optionally, the first oxide layer 220 is formed by a furnace tube oxidation process. Optionally, in the process of oxidizing the amorphized ion implanted region 201 to form the first oxide layer 220 by a furnace tube oxidation process, a portion of the substrate 200 located on one side of the surface of the substrate 200 is oxidized together and forms a portion of the first oxide layer 220. That is, the first oxide layer 220 is formed in the amorphized ion implanted region 201 and extends to cover the surface of the substrate 200.

[0078] It should be noted that, since the thickness of the first oxide layer 220 formed by growth is positively correlated with the implantation depth and implantation concentration of the amorphized ion implantation region 201 in the substrate 200, the thickness of the portion of the first oxide layer 220 formed in the amorphized ion implantation region 201 is greater than the thickness of the portion formed on the substrate 200. At the same time, since the amorphized ion implantation region covers the top corners B on both sides of the preset region 200a, the portion of the first oxide layer 220 located above the top corner B is also thicker than the portion of the first oxide layer 220 located on the surface of the substrate 200, which is conducive to using the first oxide layer to protect other structures in the isolation trench from damage during the subsequent etching process.

[0079] See also Fig.11 In one embodiment, after forming the first oxide layer 220, the method for manufacturing a semiconductor device further includes forming a hard mask layer 230 on the first oxide layer 220. Optionally, the material of the hard mask layer 230 includes silicon nitride.

[0080] Continue reading Fig.11 In one embodiment, a chemical vapor deposition process is used to form a hard mask layer 230 on the first oxide layer 220. It should be noted that since the hard mask layer 230 is formed by a deposition process, the top surface morphology of the hard mask layer 230 inherits the top surface morphology of the first oxide layer 220.

[0081] See also Fig.12 In one embodiment, a portion of the first oxide layer 220 located above the predetermined region 200a is removed, and the substrate 200 in the predetermined region 200a is removed to form an isolation trench 240. At this time, the top corner B is located on both sides of the top opening of the isolation trench 240, and the remaining first oxide layer 220 covers the top corner B. Optionally, along a direction perpendicular to the surface of the substrate 200, the cross-sectional shape of the top corner B is arc-shaped.

[0082] It should be noted that, during the formation of the isolation trench, the portion of the first oxide layer located above the preset area is removed, so that a portion of the remaining first oxide layer is located above the top corner and the other portion covers the substrate surface. At the same time, since the portion of the first oxide layer located above the top corner is thicker than the portion of the first oxide layer located on the substrate surface, the first oxide layer can play a protective role in subsequent process steps, thereby helping to reduce or avoid the formation of recess defects in the subsequently formed shallow trench isolation structure.

[0083] Continuing to refer to 12, in one embodiment, a dry etching process is used to remove a portion of the first oxide layer 220 and the substrate 200 in the predetermined area 200a to form the isolation trench 240. At the same time, in the case where the hard mask layer 230 is formed on the first oxide layer 220, the dry etching process will also remove the portion of the hard mask layer 230 located above the predetermined area, thereby preventing the portions of the first oxide layer 220 located on both sides of the predetermined area from being removed during the formation of the isolation trench 240, so as to facilitate the subsequent process.

[0084] See also Fig.13 In one embodiment, a second oxide layer 250 is filled in the isolation trench 240 to form a shallow trench isolation structure X2 including the isolation trench 240 and the oxide layer, wherein the oxide layer includes the second oxide layer 250 and a portion of the first oxide layer 220 located above the top corner B (i.e., the oxide layer includes Fig.13 The second oxide layer 250 and the portion of the first oxide layer 220 within the dotted line frame). Optionally, the material of the second oxide layer 250 includes silicon oxide.

[0085] Continue reading Fig.13 In one embodiment, the process of forming the second oxide layer 250 includes: filling the isolation trench 240 with an oxide material (not shown in the figure), and the oxide material extends to cover other semiconductor structures on both sides of the isolation trench 240, and planarizing the oxide material to form the second oxide layer 250 that fills the isolation trench 240. Optionally, the oxide material is filled by a chemical vapor deposition process (Chemical Vapor Deposition, CVD); and the planarization process is performed by a chemical mechanical polishing process (Chemical Mechanical Polishing, CMP).

[0086] It should be noted that when a hard mask layer 230 is formed on the first oxide layer 220, the hard mask layer 230 can protect the first oxide layer 220 during the planarization process of the second oxide layer 250 to ensure that the first oxide layer 220 has sufficient thickness to protect the shallow trench isolation structure from damage during the subsequent wet etching process.

[0087] See also Fig.13 and Fig.14 In the case where a hard mask layer 230 is formed on the first oxide layer 220 , after forming the second oxide layer 250 , the method for manufacturing a semiconductor device further includes: removing the hard mask layer 230 .

[0088] See also Fig.14 and Fig.15 In one embodiment, a portion of the oxide layer away from the isolation trench 240 is removed to expose the substrate 200 on the side of the top corner B away from the isolation trench 240, and the remaining oxide layer (including the second oxide layer 250 and the first oxide layer 220) fills the isolation trench 240. Optionally, a wet etching process (Wet Etch) is used to remove a portion of the oxide layer away from the isolation trench 240 to expose the substrate 200 on both sides of the shallow trench isolation structure X2.

[0089] It should be noted that during the above-mentioned wet etching process, the overall thickness of the first oxide layer 220 and the thickness of the second oxide layer 250 are both reduced, and the first oxide layer 220 always covers the top corner B and the side of the side wall of the second oxide layer 250 close to the top corner B during the above-mentioned wet etching process, so as to reduce or avoid the risk of recessed defects in the portion of the oxide layer located in the isolation trench 240.

[0090] Continue reading Fig.15 In one of the embodiments, along the direction of vertical injection into the surface of the substrate 200, the cross-sectional width of the oxide layer (i.e., the combined structure of the first oxide layer 220 and the second oxide layer 250) shows a trend of first increasing and then decreasing, and the portion of the oxide layer located above the top corner area B has the largest cross-sectional width, and the portion of the oxide layer located above the top corner B (i.e., the first oxide layer 220) can protect the second oxide layer 250 from damage during the etching process related to the shallow trench isolation structure X2.

[0091] Accordingly, the present application also provides a semiconductor device. Fig.15 In one embodiment, the semiconductor device includes a substrate 200, an isolation trench 240 and a first oxide layer 220, wherein the isolation trench 240 is located in the substrate 200, and the substrate 200 on both sides of the isolation trench 240 is provided with a rounded top corner B, the first oxide layer 220 is located on the substrate 200, and the first oxide layer 220 covers the top corner B.

[0092] It should be noted that by providing rounded top corners on the substrate on both sides of the isolation trench, leakage of semiconductor devices can be reduced or avoided. On this basis, by providing a first oxide layer covering the top corners, the first oxide layer can be used to protect the related structures of the isolation trench from damage in subsequent processes, thereby reducing or avoiding the risk of recessed defects in the subsequently formed shallow trench isolation structure, thereby effectively improving the performance and stability of semiconductor devices.

[0093] Continue reading Fig.15 In one embodiment, the semiconductor device further includes a second oxide layer 250 located in the isolation trench 240, and the second oxide layer 250 at least fills the isolation trench 240. Optionally, the surface of the second oxide layer 250 is higher than the surface of the first oxide layer 220, or the surface of the second oxide layer 250 is flush with the surface of the first oxide layer 220. At this time, the isolation trench 240, the first oxide layer 220 and the second oxide layer 250 are combined to form a shallow trench isolation structure X2 of the semiconductor device.

[0094] In one embodiment, the material of the substrate 200 includes silicon material; the materials of the first oxide layer 220 and the second oxide layer 250 both include silicon oxide.

[0095] contrast Figure 5 and Fig.15 It can be seen that in general semiconductor devices, the oxide layer 110 in the STI structure X1 will be removed before the isolation layer 150 and cause the top corner of the trench 140 to be exposed, so that the top and side walls of the portion of the isolation layer 150 that is higher than the semiconductor substrate 100 are damaged in the subsequent etching process, thereby forming a recess defect 151 at the top corner; while in the semiconductor device provided in the present application, a rounded top corner B is set and a first oxide layer 220 is set on the top corner B, so that during the etching process related to the shallow trench isolation structure X2, the first oxide layer 220 is used to protect the second oxide layer 250 from damage, thereby effectively reducing or avoiding the risk of recess defects in the shallow trench isolation structure X2.

[0096] In one embodiment, the semiconductor device described above is manufactured using the semiconductor device manufacturing method provided in the present application. In other embodiments of the present application, the semiconductor device can also be manufactured using other methods according to actual needs, and the semiconductor device manufacturing method can also be used to manufacture other semiconductor structures with the same or similar structures to improve the performance and stability of the semiconductor device.

[0097] The unexpected effect of the present application is: by forming an amorphized ion implantation region in a preset area of ​​the substrate, the top corners of the substrate near the preset area are rounded; by oxidizing the amorphized ion implantation region to form a first oxide layer, and forming an isolation trench in the preset area, the top corners on both sides of the isolation trench are rounded and covered by the first oxide layer, reducing or avoiding the risk of recessed defects in the subsequently formed shallow trench isolation structure, thereby helping to improve the performance and stability of semiconductor devices.

[0098] In the description of this specification, the description with reference to the terms "some embodiments", "other embodiments", "ideal embodiments", etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic descriptions of the above terms do not necessarily refer to the same embodiment or example.

[0099] The technical features of the above-mentioned embodiments can be combined arbitrarily. In order to make the description concise, not all possible combinations of the technical features of the above-mentioned embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0100] The above-described embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be construed as limiting the scope of the patent application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent application shall be subject to the attached claims.

Claims

1. A method for manufacturing a semiconductor device, characterized in that: include: Providing a substrate, wherein the substrate includes a preset area for forming an isolation trench, and a top corner of the substrate close to the preset area is at a right angle; Performing amorphization ion implantation into the preset region to form an amorphization ion implantation region on one side of the preset region close to the substrate surface, wherein the amorphization ion implantation region extends into the substrate on both sides of the preset region and rounds the top corner; Oxidizing the amorphized ion implanted region to form a first oxide layer; The portion of the first oxide layer located above the preset area is removed, and the substrate in the preset area is removed to form the isolation trench, wherein the top corner is located on both sides of the top opening of the isolation trench, and the remaining first oxide layer covers the top corner.

2. The method for manufacturing a semiconductor device according to claim 1, wherein: The process of performing amorphization ion implantation into the preset region to form an amorphization ion implantation region on a side of the preset region close to the substrate surface includes: Performing a first ion implantation process with a first implantation angle in the predetermined area to form a first ion implantation region; Performing a second ion implantation process with a second implantation angle in the preset area to form a second ion implantation region, wherein the amorphization ion implantation region includes the first ion implantation region and the second ion implantation region; The inclination direction of the first implantation angle is the same as that of the second implantation angle and is opposite in direction, and the first ion implantation region and the second ion implantation region at least partially overlap.

3. The method for manufacturing a semiconductor device according to claim 2, wherein: Along a direction perpendicular to the surface of the substrate, a cross-sectional width of the first ion implantation region and a cross-sectional width of the second ion implantation region gradually decrease.

4. The method for manufacturing a semiconductor device according to claim 1, wherein: The amorphization ions implanted during the amorphization ion implantation process include germanium ions.

5. The method for manufacturing a semiconductor device according to claim 1, wherein: Oxidizing the amorphized ion implanted region to form the first oxide layer by using a furnace tube oxidation process; In the process of oxidizing the amorphized ion implanted region to form the first oxide layer, a portion located on the surface side of the substrate is oxidized together and forms a portion of the first oxide layer.

6. The method for manufacturing a semiconductor device according to claim 1, wherein: Along a direction perpendicular to the surface of the substrate, a cross-sectional shape of the top corner is arc-shaped.

7. The method for manufacturing a semiconductor device according to claim 1, wherein: After forming the isolation trench, the method for manufacturing the semiconductor device further includes: Filling the isolation trench with a second oxide layer to form a shallow trench isolation structure including the isolation trench and an oxide layer, wherein the oxide layer includes the second oxide layer and a portion of the first oxide layer located above the top corner; A portion of the oxide layer away from one side of the isolation trench is removed to expose the substrate at a side of the top corner away from the isolation trench, and the remaining oxide layer fills the isolation trench.

8. The method for manufacturing a semiconductor device according to claim 7, wherein: After forming the first oxide layer and before forming the isolation trench, the method for manufacturing the semiconductor device further includes: forming a hard mask layer on the first oxide layer; The process of removing the portion of the first oxide layer located above the preset area further includes: removing the portion of the hard mask layer located above the preset area so that the isolation trench penetrates the hard mask layer; After the isolation trench is filled with a second oxide layer and before a portion of the oxide layer away from a side of the isolation trench is removed, the method for manufacturing a semiconductor device further includes: The hard mask layer is removed.

9. A semiconductor device, characterized in that: include: substrate; An isolation trench is located in the substrate, and the substrate on both sides of the isolation trench is provided with rounded top corners; The first oxide layer is located on the substrate, and the first oxide layer covers the top corner.

10. The semiconductor device according to claim 9, characterized in that The semiconductor device further comprises: The second oxide layer is located in the isolation trench, and the surface of the second oxide layer is higher than the surface of the first oxide layer, or the surface of the second oxide layer is flush with the surface of the first oxide layer.

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