Semiconductor device structure and manufacturing method thereof

Abstract

In accordance with some embodiments of the present disclosure, a method of manufacturing a semiconductor device structure and a semiconductor device structure are disclosed. The method includes forming a backside connection structure by sequentially forming heat transfer layers stacked on each other and a backside metallization structure sandwiched between the heat transfer layers. The formation of the at least one heat transfer layer includes performing an annealing process to convert the layer of insulating material into a layer of insulating nanostructured material having nanocrystallines and dopants distributed along the grain boundaries of the nanocrystallines.

Description

Technical Field

[0001] The invention relates to a semiconductor component structure and a manufacturing method thereof. Background Art

[0002] Technological advances in the semiconductor integrated circuit (IC) industry have resulted in smaller sizes and more complex designs in IC structures. Summary of the invention

[0003] According to some embodiments of the present disclosure, a semiconductor component structure is disclosed. The structure includes a semiconductor substrate having a first surface and a second surface opposite to the first surface, and a component layer disposed on the first surface of the semiconductor substrate. The component layer includes a plurality of transistors. The structure includes a backside connection structure disposed on the second surface of the semiconductor substrate and electrically connected to the plurality of transistors. The backside connection structure includes a backside metallization structure and at least one insulating nanostructure material having nanocrystals and dopants distributed along the grain boundaries of the nanocrystals.

[0004] According to some embodiments of the present disclosure, a method for manufacturing a semiconductor component structure is disclosed. A component layer is formed on a first surface of a semiconductor substrate, and the component layer is formed by a plurality of transistors. A thinning process is performed on the semiconductor substrate, and the semiconductor substrate is thinned starting from a second surface of the semiconductor substrate relative to the first surface. A material layer containing a dopant is formed on the second surface of the thinned semiconductor substrate. The material layer is formed by first nanocrystals of a first grain size. A cap layer is formed on the material layer to cover the material layer. An annealing process is performed on the cap layer and the material layer to transform the material layer into a nanostructured material layer. The nanostructured material layer is formed by second nanocrystals having a second grain size, and the second grain size is larger than the first grain size grains. A metallization structure is formed in the nanostructured material layer.

[0005] According to some embodiments of the present disclosure, a method for manufacturing a semiconductor device structure is disclosed. A semiconductor substrate is provided, having a through hole embedded therein; a device layer is formed on a first side of the semiconductor substrate. The device layer is formed by a plurality of transistors. A first material layer is formed on a second side of the semiconductor substrate relative to the first side, and the first material layer is doped. The first material layer is formed by first nanocrystals of a first grain size and contains a first dopant. A first cap layer is formed on the first material layer, covering the first material layer. A first nanostructured material layer is formed below the first cap layer by performing a first laser annealing process. The first nanostructured material layer is formed by second nanocrystals of a second grain size greater than the first grain size, and the first dopant is distributed along the grain boundaries of the second nanocrystals. A first metallization structure is formed in the first nanostructured material layer. A second material layer is formed above the first material layer, and the second material layer is doped. The second material layer is formed by third nanocrystals of a third grain size and contains a second dopant. A second cap layer is formed on the second material layer, covering the second material layer. A second nanostructured material layer is formed below the second cap layer by performing a second laser annealing process. The second material layer is formed by fourth nanocrystals having a fourth grain size greater than the third grain size. The second dopant is distributed along the grain boundaries of the fourth nanocrystals. A second metallization structure is formed in the second nanostructured material layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Figures 1 to 5 Schematic cross-sectional views of various stages in a method for manufacturing a semiconductor device structure according to some embodiments of the present disclosure are shown.

[0007] Figure 6 and Figure 7 According to some embodiments of the present disclosure, Figure 4 and Figure 5 A schematic enlarged view of a portion of a material layer within a semiconductor component is shown.

[0008] Figure 8 is a schematic top view of an exemplary structure of a semiconductor device structure according to some embodiments of the present disclosure, depicted taking into account a scanning direction of multiple die units.

[0009] Fig. 9 is a graph showing the relationship between thermal conductivity and grain size of a material layer.

[0010] Fig.10 illustrative process diagrams showing process steps of a method for manufacturing a semiconductor device structure according to some embodiments of the present disclosure.

[0011] Figures 11 to 13is a schematic cross-sectional view of an example structure of a semiconductor device structure according to some embodiments of the present disclosure.

[0012] Description of Reference Numerals

[0013] 10:Semiconductor component structure

[0014] 10B: back surface

[0015] 10F: Front surface

[0016] 100:Semiconductor substrate

[0017] 100T:Surface

[0018] 101: Quarantine

[0019] 102:Piercing

[0020] 103: Component layer

[0021] 1032: Transistor

[0022] 1033:Nanosheet

[0023] 1034: Dielectric Materials

[0024] 1035: Gate

[0025] 105: Connection layer

[0026] 1052: Contact

[0027] 1052A: Perforation

[0028] 1052B: Plug

[0029] 1072: Interlayer dielectric layer

[0030] 1074:Metalized structure

[0031] 1074A: Top metallization layer

[0032] 1074B: Bottom metallization layer

[0033] 200: Material layer

[0034] 201: nanostructured material layer, first heat transfer layer

[0035] 210: First top cover layer

[0036] 220: first backside metallization structure

[0037] 222, 322, 422, 522: pad pattern

[0038] 224, 324, 424, 524: Metal matrix pattern

[0039] 301: Second heat transfer layer

[0040] 310: Second top cover layer

[0041] 320: Second backside metallization structure

[0042] 401: The third heat transfer layer

[0043] 410: The third top cover layer

[0044] 420: Third backside metallization structure

[0045] 501: The fourth heat transfer layer

[0046] 520: fourth backside metallization structure

[0047] A: Area

[0048] BL1: First backside layer

[0049] BL2: Second backside layer

[0050] BL3: The third back layer

[0051] BL4: The fourth back layer

[0052] C1: Carrier structure

[0053] CG1: Micro-nano-grains

[0054] CG2: Giant Nanograins

[0055] DD1: Double inlay opening

[0056] DP: Dopant

[0057] DU1: Grain Unit

[0058] GB: Grain Boundary

[0059] S10, S12, S14, S16, S18, S20, S22: Steps DETAILED DESCRIPTION

[0060] The present disclosure provides many different embodiments or examples for implementing the different features of the present disclosure. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are only examples and are not intended to be limiting. For example, the following description of forming a first feature on or on a second feature may include an embodiment in which the first feature and the second feature are formed to be in direct contact, and may also include an embodiment in which an additional feature may be formed between the first feature and the second feature so that the first feature and the second feature may not be in direct contact. In addition, the present disclosure may reuse reference numbers and / or letters in various examples. This repetition is for the purpose of brevity and clarity, rather than representing the relationship between the various embodiments and / or configurations discussed.

[0061] In addition, for ease of description, spatially relative terms such as "beneath," "below," "lower," "above," "upper," and the like may be used herein to describe the relationship of one component or feature illustrated in the figures to another (other) component or feature. The spatially relative terms are intended to encompass different orientations of a component in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein should be interpreted accordingly.

[0062] In addition, when a number or a range of numbers is described as "about," "approximate," etc., the term is intended to encompass numbers within a reasonable range taking into account variations that inherently occur during manufacturing as understood by those of ordinary skill in the art. For example, based on known manufacturing errors associated with manufacturing features having properties associated with the number, the number or range of numbers encompasses a reasonable range including the number, such as within + / - 10% of the number. For example, a material layer having a thickness of "about 5 nanometers" may encompass a range of sizes from 4.25 nanometers to 5.75 nanometers, where the manufacturing tolerance associated with the deposited material layer is known to those of ordinary skill in the art to be + / - 15%. Further, the present disclosure may repeat figure numerals and / or letters in various examples. Such repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and / or configurations discussed.

[0063] Some embodiments described herein provide a semiconductor component including a backside heat transfer structure having at least one or more layers of insulating material (electrical insulator) with high thermal conductivity, the thermal conductivity being used to assist heat transfer and heat dissipation of a backside power rail or other backside power distribution line or transmission network. By laser annealing and in-situ doping, a high-quality insulating layer with large grain size and high thermal conductivity can be formed on the backside portion of the semiconductor component. By such a formation process, the high heat transfer insulating layer is formed as part of the backside heat transfer structure to provide satisfactory effective thermal conductivity for the backside power rail and reduce the maximum temperature of the backside power scheme, thereby bringing improved heat transfer efficiency and good component performance to the semiconductor component. In addition, the formation of the high thermal conductivity dielectric layer is compatible with the back-end-of-line (BOEL) process and / or the manufacturing process of the backside structure. Thus, an efficient heat dissipation system for semiconductor components is achieved through straightforward processes that are compatible with currently available manufacturing processes.

[0064] from Figures 1 to 5 , which is a schematic cross-sectional view of a portion of a semiconductor device structure at a sequential intermediate stage of a manufacturing method according to some embodiments of the present disclosure. Figure 6 and Figure 7 According to some embodiments of the present disclosure, Figure 4 and Figure 5 An enlarged schematic diagram of a portion of a material layer within a semiconductor device structure is shown. Fig.10 An exemplary flow chart of process steps of a method for manufacturing a semiconductor device structure according to some embodiments of the present disclosure is shown.

[0065] refer to Figure 1 In some embodiments, a semiconductor component structure 10 is provided. In some embodiments, the semiconductor component structure 10 includes a semiconductor wafer. For example, the semiconductor wafer is a silicon wafer, or a bulk wafer made of other semiconductor materials such as III-V semiconductor materials (e.g., gallium nitride (GaN) or gallium arsenide (GaAs)). In some embodiments, the semiconductor component structure 10 can be considered to have multiple die units or semiconductor dies before dicing or singulation. Figure 1 In FIG. 1 , only a portion of the semiconductor device structure 10 including at least one die unit is shown. Figure 8 , depicted as a schematic top view of a semiconductor device structure 10 having a plurality of die units DU1. It should be understood that the number of die units or semiconductor dies is only exemplary. In some embodiments, the die units DU1 are or include different die types with different functions. In some embodiments, the die units DU1 are or include dies of the same die type or the same function.

[0066] According to an embodiment, in Figure 1 In the embodiment, the semiconductor component structure 10 includes a semiconductor substrate 100 having an isolation region 101 formed therein and a through hole 102 penetrating into the semiconductor substrate 100. The semiconductor component structure also includes at least one component layer 103 formed on the front side surface 10F of the semiconductor substrate 100, above the isolation region 101 and above the semiconductor substrate 100. In some embodiments, the semiconductor substrate 100 may be a monocrystalline semiconductor substrate, such as a silicon substrate, a silicon-on-insulator (SOI) substrate, a germanium substrate, or a germanium-on-insulator (GOI) substrate. In some embodiments, the semiconductor substrate 100 includes an elemental semiconductor, such as germanium; a suitable compound semiconductor, such as gallium arsenide (GaAs), silicon carbide (SiC), indium arsenide (InAs) or indium phosphide (InP), or a suitable alloy semiconductor, such as silicon germanium (SiGe), gallium arsenide phosphide (GaAsP), or gallium indium phosphide (GaInP). In some embodiments, the substrate 100 includes an oxide semiconductor material, such as indium tin oxide (ITO). In some embodiments, the isolation region 101 includes a shallow trench isolation (STI) structure. In some embodiments, the through-hole 102 buried and penetrating into the semiconductor substrate 100 includes a through semiconductor via (TSV).

[0067] In some embodiments, reference Figure 1, forming a component layer 103 to include a plurality of transistors 1032 covered by a dielectric material 1034. In some embodiments, the component layer 103 includes a semiconductor transistor 1032 formed in or on the semiconductor substrate 100 by a front-end-of-line process. In some embodiments, the transistor 1032 includes one or more types of transistors, such as field effect transistors (FETs), including fin-type FETs, nanosheet FETs, nanowire FETs, gate-all-around FETs, fork-sheet FETs, or complementary FETs, and the configuration of the transistor structure may vary according to design requirements. In some embodiments, the component layer 103 may also include other active components and / or passive components, such as capacitors, resistors, diodes, photodiodes, sensors, inductors, or fuses. In one embodiment, the transistor 1032 is depicted as a nanosheet field effect transistor as an exemplary structure, and the nanosheet field effect transistor includes at least a nanosheet 1033 as a channel and a gate 1035 surrounding the nanosheet 1033. Figure 1 For the purpose of illustration, two transistors (and dots indicating the omission of multiple transistors or components) are depicted to represent multiple transistors, but the number of transistors is not limited by the drawings. It should also be understood that the type or configuration of transistors included in transistor 1032 is not limited by the embodiments or drawings shown herein. In some embodiments, these through-holes 102 buried in semiconductor substrate 100 are considered to be back-side through-holes electrically connected to transistor 1032. That is, the through-holes 102 located on the back side of transistor 1032 serve as part of the back-side electrical connection structure of transistor 1032 (or component layer 103).

[0068] In some embodiments, reference Figure 1, a connection layer 105 is formed on the component layer 103 above the semiconductor substrate 100. The connection layer 105 is formed to have more than one or more contacts 1052 configured as through-holes 1052A and plugs 1052B. Although not explicitly shown in the figure, it should be understood that some or all of the contacts 1052 of the connection layer 105 are electrically connected to the transistors 1032 in the component layer 103, and the transistors 1032 are electrically connected to each other through the connection layer 105. In some embodiments, the contact 1052 is a metal contact, and the material of the contact includes tungsten (W), tungsten alloy, titanium (Ti), tantalum (Ta), cobalt (Co), nickel (Ni), nitrides thereof, or combinations thereof.

[0069] refer to Figure 2 In some embodiments, after forming the connection layer 105, an interconnection line layer 107 is formed on the connection layer 105 above the component layer 103. In some embodiments, the interconnection line layer 107 includes an interlayer dielectric layer 1072 and a metallization structure 1074 formed between the interlayer dielectric layers 1072. In an exemplary embodiment, the metallization structures 1074 are interconnected, some transistors 1032 are electrically connected to the metallization structures 1074, and some transistors 1032 or semiconductor components are interconnected with each other through the contacts 1052 and the metallization structures 1074.

[0070] like Figure 2 As shown, in some embodiments, the metallization structure 1074 is embedded in the interlayer dielectric layer 1072 and sandwiched between the interlayer dielectric 1072 above the connection layer 105. In some embodiments, the metallization structure 1074 includes a metallization layer of an interconnect line structure, including interconnected metal lines, perforations, and contact pads. In some embodiments, the metallization structure 1074 includes at least an electrically interconnected top metallization layer 1074A and a bottom metallization layer 1074B, and the metallization structure 1074 is electrically connected to the connection layer 105 and the component layer 103. In some embodiments, the top metallization layer 1074A includes a top metal line and a perforation, and the bottom metallization layer 1074B includes a bottom metal line and a trace. The metallization structure 1074 shown herein is for illustrative purposes only, and the metallization structure 1074 may include other configurations and may include one or more perforations and / or inlay structures. The present disclosure does not limit the number of metallization layers and the number of sublayers included in the interlayer dielectric layer 1072, and the number of layers or sublayers shown in the drawings is only exemplary. Additional layers such as barrier layers, etch stop layers, etc. may also be formed between multiple layers or sub-layers thereof.

[0071] In some embodiments, the material of the metallization structure 1074 includes aluminum (Al), aluminum alloy, copper (Cu), copper alloy, titanium (Ti), tantalum (Ta), cobalt (Co), nickel (Ni), tungsten (W), nitrides thereof, or combinations thereof. In some embodiments, the metallization structure 1074 including the top metallization layer 1074A and the bottom metallization layer 1074B and the portion formed therebetween is formed by the same metallization process and is made of the same metal material. In some embodiments, the metallization structure 1074 is made of copper or a copper alloy. In some embodiments, the material of the interlayer dielectric layer 1072 includes silicon oxide, a spin-on dielectric material, a low dielectric material, or a combination thereof. In some embodiments, the insulating interlayer dielectric layer 1072 includes a low dielectric layer. Examples include borophosporosilicate glass (BPSG), phosporosilicate glass (PSG), amorphous fluorinated carbon, parylen, bisbenzocyclobutene (BCB), polyimide, fluorinated poly(aryl ethers), FLARE, Xerogel, Aerogel, hydrogen silsesquioxane (HSQ), fluorinated silicon oxide (SiOF), or a combination thereof.

[0072] In some embodiments, the connection layer 105 and the interconnection line layer 107 are formed by a middle of the line (MEOL) process and a back end of the line (BEOL) process.

[0073] refer to Figure 3 In some embodiments, the semiconductor device structure 10 is turned upside down (flipped) and placed on the carrier structure C1, so that the interconnect layer 107 faces the carrier structure C1. In some embodiments, the carrier structure C1 is a carrier wafer or a sacrificial semiconductor wafer. Figure 3As shown, the top metallization layer 1074A of the interconnect layer 107 is in direct contact with the carrier structure C1. Optionally, a fusion bonding film may be formed between the semiconductor component structure 10 and the carrier structure C1, and the semiconductor component structure 10 is attached to the carrier structure C1 by fusion bonding. After flipping the semiconductor component structure 10, the semiconductor substrate 100 including the conductive through-via 102 is located above the connection layer 105 and the interconnect layer 107, and the back side surface 10B of the semiconductor substrate 100 faces upward and is exposed. Then, a back side thinning process is performed on the exposed surface 10B (back side) of the semiconductor substrate 100 of the semiconductor component structure 10, and the semiconductor substrate 100 is partially removed (thinned), but the conductive through-via 102 is still embedded in the semiconductor substrate 100, rather than being exposed to the processed (thinned) surface 100T of the semiconductor substrate 100, as shown in FIG. Figure 3 In some embodiments, the thinning process includes a polishing process, an etching process, or a combination thereof. Alternatively, the thinning process may partially remove (thin) the semiconductor substrate 100 to expose the conductive through-via 102 .

[0074] refer to Figure 4 In some embodiments, the material layer 200 is formed on the surface 100T above the semiconductor substrate 100. In some embodiments, the material layer 200 is formed of an insulating material and is formed by performing a low temperature deposition process and a doping process sequentially or simultaneously. In some embodiments, the material layer 200 is formed by in-situ doping deposition. In some embodiments, the material layer 200 can be manufactured to an appropriate thickness by a deposition process, such as chemical vapor deposition (CVD) (e.g., plasma-enhanced CVD, PECVD, low-pressure CVD, LPCVD, sub-atmosphere CVD, SACVD) or physical vapor deposition (e.g., sputtering, e-beam evaporation) or other suitable methods. In some embodiments, the deposition process for forming the material layer 200 is a low temperature deposition process performed at a reaction temperature below 400 degrees Celsius or below about 425 degrees Celsius, which is compatible with back-end-of-line (BEOL) processes.

[0075] In some embodiments, the insulating material of the material layer 200 includes diamond, crystalline (polycrystalline or single crystal) aluminum nitride (AlN), crystalline silicon carbide (SiC), and crystalline boron nitride (BN). In some embodiments, the dopant used in the doping process is or includes transition metal elements, including one or more selected from titanium (Ti), zirconium (Zr), niobium (Nb), yttrium (Y), chromium (Cr), nickel (Ni), manganese (Mn), molybdenum (Mo), ruthenium (Ru), strontium (Sr), cobalt (Co), and iron (Fe). In some embodiments, the dopant used in the doping process is or includes boron (B), silicon (Si), or aluminum (Al). In some embodiments, the material layer 200 includes diamond, which is formed by chemical vapor deposition using in-situ doping with dopants containing Al, Si, Nb, Mn, and / or B. In some embodiments, the material layer 200 includes polycrystalline AlN formed by physical vapor deposition of dopants added by co-sputtering, and the dopants include Ti, Zr, Nb, Y, Cr, Ni, Si, Mn and / or Ru. The formation of the material layer 200 involves performing a deposition process with a reaction temperature below 425 degrees Celsius or below 400 degrees Celsius to be compatible with BEOL processes, and doping or implantation to add dopants into the material layer 200.

[0076] In some embodiments, the material layer 200 is formed as a crystalline material layer having crystals (grains). In one embodiment, the material layer 200 is formed as a polycrystalline material layer having nano-sized grains (nano-grains). In a polycrystalline form, grain boundaries occur where different crystalline orientations face each other, and the grain boundaries extend through the structure of the material layer.

[0077] Figure 6 A portion of a material layer 200 in the semiconductor device structure 10 is shown (shown by Figure 4 The dotted line encloses the area A). Figure 4 and Figure 6 In some embodiments, the material layer 200 is a grained insulating material layer formed by nano-grains CG1, and the dopant Dp is mainly distributed along the grain boundaries GB of the nano-grains CG1. Figure 4 In the embodiment, the dopant Dp is present in the material layer 200, but for simplicity, a relatively small amount of the dopant Dp is present in the material layer 200. Figure 4In some embodiments, the material layer 200 forms nano-grains CG1 having a grain size (average grain size) of less than 50 nanometers. In one embodiment, the material layer 200 forms nano-grains CG1 having a grain size ranging from about 20 nanometers to about 30 nanometers. Since the dopant Dp may include transition metal elements or heavy metal atoms, due to the large volume and local dangling bonds of the metal elements, the dopant Dp tends to be distributed at or along the grain boundaries GB, such as Figure 6 shown.

[0078] refer to Figure 5 , after forming the material layer 200, a cap layer 210 is formed on the material layer 200. In some embodiments, the material of the cap layer 210 includes titanium nitride (TiN), tantalum nitride (TaN), aluminum oxide (e.g., Al2O3), silicon carbonitride (SiCN), silicon carbide (SiC) or silicon nitride (e.g., Si3N4). In some embodiments, the material of the material layer 200 is different from the material of the cap layer 210. The cap layer 210 is formed on the entire top surface of the material layer 200 to protect the material layer 200 from the influence of subsequent processes. In one embodiment, the cap layer 210 is formed to have a thickness of about 5 nanometers to about 10 nanometers. In some embodiments, the cap layer 210 is formed by vapor deposition such as plasma enhanced vapor deposition.

[0079] refer to Figure 5 In some embodiments, after forming the cap layer 210, an annealing process is performed on the semiconductor device structure 10. In some embodiments, the annealing process includes performing a laser annealing process to heat and anneal the material layer 200 under the protection of the cap layer 210. Figure 4 In some embodiments, the laser annealing process includes applying a laser beam (by Figure 5 The pointed cone shown is directly applied to the top cap layer 210 of the semiconductor device structure 10, heating the underlying material layer 200 to form a nanostructured material layer 201. Compared with tunnel thermal annealing, the laser annealing process is significantly faster and saves time.

[0080] refer to Figure 5 , a laser annealing process is performed on the semiconductor component structure 10 along the scanning path, and the scanning path of the laser beam (by Figure 8The curved arrow shown in the figure shows that the laser scanning path sequentially passes through the plurality of tube core units DU1 of the wafer-form semiconductor device structure 10. In some embodiments, the width of the laser scanning path ranges from tens to hundreds of microns, and the span of the laser scanning path is designed to completely cover the span of the material layer 200. In an embodiment, the laser annealing process is performed using a pulsed mode laser. In an embodiment, a continuous wave laser is used to perform the laser annealing process. The lasers that may be used include a carbon dioxide laser (CO2 laser), a fiber laser, a semiconductor laser or a solid-state laser (e.g., a neodymium-doped yttrium aluminum garnet (Nd-YAG) laser, an erbium-doped YAG (Er-YAG) laser), an excimer laser (e.g., a KrF laser), and the wavelength of the laser can be in the range of about 248 nanometers to about 10 microns.

[0081] In the laser annealing process, the material layer 200 is fully heated and annealed to form the nanostructured material layer 201, and the dopant (e.g., transition metal element) in the material layer 200 promotes atypical and abnormal grain growth when heated by the heat generated by the laser annealing process, and causes giant grains to be formed in the nanostructured material layer 201. That is, in the presence of the dopant and by using the annealing process (the heat generated), the material layer 200 having micro-nano grains CG1 becomes a nanostructured material layer 201 formed of giant grains CG2. The cap layer 210 is used as a passivation layer to prevent the surface of the material layer 200 from being burned during the laser treatment. Moreover, due to the presence of the cap layer 210, under the heating of the laser annealing process, the defects in the material layer 200 will gather toward the cap layer 210, so that the nanostructured material layer 201 is formed in a manner with reduced surface roughness and fewer defects.

[0082] In some embodiments, the nanostructured material layer 201 is formed of nanograins CG2 having a grain size (average grain size) greater than 50 nanometers. In some embodiments, the nanostructured material layer 201 is formed of giant nanograins CG2, whose grain size before annealing is at least about twice or more than twice the grain size of the nanograins CG1 of the material layer 200. In an embodiment, the nanostructured material layer 201 is formed of giant nanograins CG2 having a lateral grain size greater than 50 nanometers and a vertical grain size greater than about 80 nanometers. After the laser annealing process, the dopant Dp tends to be distributed at or along the grain boundaries GB of the giant nanograins CG2, such as Figure 7shown.

[0083] Fig. 9 It is a graph showing the relationship between the thermal conductivity of a material layer and its grain size. The thermal conductivity of a material is an indicator of its heat transfer ability, usually expressed as a k value or kappa value, with the unit of W / m·K. Fig. 9 As shown, there is a linear relationship between the thermal conductivity (kappa value, unit W / m·K) and the grain size (unit angstrom (A°)) of the material layer. As previously mentioned, the nanostructured material layer 201 obtained after the laser annealing process has nano-grains CG2, whose grain size is at least about twice or more than twice the grain size of the nano-grains CG1 of the material layer 200 before annealing. Through the reaction of the extremely fast annealing process, the micro-grain insulating material layer 200 becomes a giant grain insulating material layer 201, which has high thermal conductivity and acts as a heat transfer layer.

[0084] Based on extrapolation and simulation results, the thermal conductivity (or kappa value) of the nanostructured material layer 201 is at least two times higher than the thermal conductivity (or kappa value) of the unannealed material layer 200, or even higher. The thermal conductivity of the material layer film is measured as an in-plane kappa value and an out-of-plane kappa value in the directions parallel and perpendicular to the film surface, respectively. For example, a deposited layer of aluminum nitride (AlN) is formed with a dopant as described in the previous paragraph, and the aluminum nitride layer formed before annealing has a lateral grain size of about 20 nanometers and an in-plane kappa value of about 20 nanometers to 40 nanometers, and after annealing, the aluminum nitride layer has a lateral grain size greater than 50 nanometers, an in-plane kappa value greater than 80 W / m·K, a vertical grain size of about equal to or greater than 80 nanometers, and an out-of-plane kappa value ranging from about 100 to 300 W / m·K. Compared to low dielectric materials with low thermal conductivity of about 0.3 W / m·K, the nanostructured material layer 201 has a very high thermal conductivity, about 100 to 500 times higher, which results in a nanostructured material layer 201 with much lower thermal conductivity, better heat transfer effect and heat dissipation performance. Compared to the nanostructured material layer 201 of the untreated material layer 200 (unannealed), the grain size of the nanostructured material layer 201 is at least twice or more, and the thermal resistance is reduced by at least 50% through the laser annealing process. In some embodiments, the nanostructured material layer 201 has a grain size greater than 50 nanometers, and the increased thermal conductivity is at least four times higher than the untreated material layer 200. For the nanostructured material layer 201 with giant grains, the volume of the grain boundaries is lower, resulting in better time-dependent dielectric breakdown (TDDB) or breakdown voltage (VBD) of the nanostructured material layer 201, which is attributed to lower leakage current characteristics and better device performance.

[0085] refer to Fig.10 , in step S10 and referring to Figure 1 The semiconductor device structure 10 including the device layer 103 is formed by a front-end-of-line (FEOL) process of wafer manufacturing. Subsequently, in step 12, and with reference to Figure 1 and Figure 2 In step S14, the connection layer 105 is formed on the semiconductor device structure 10 through a middle-end-of-line (MEOL) process, and in step S15, the interconnection layer 107 is formed on the connection layer 105 above the semiconductor device structure 10 through a back-end-of-line (BEOL) process. Figure 3, a backside thinning process is performed on the semiconductor device structure 10. In step S18 and referring to Figure 4 A material layer 200 including a dopant Dp is formed on the back side of the semiconductor device structure 10. In step S20 and referring to Figure 5 , the top cover layer 210 is formed on the material layer 200 and covers the material layer 200. In step S22 and referring to Figure 5 , perform an annealing process to form a nanostructured material layer 201 (heat transfer layer). Figure 4 ) is subjected to an annealing process, and the material layer 200 becomes a nanostructured material layer 201.

[0086] Figures 11 to 13 is a schematic cross-sectional view of an example structure of a semiconductor device structure according to some embodiments of the present disclosure.

[0087] like Figure 4 and Figure 5 As shown, after forming the material layer 200 and the nanostructured material layer 201, the semiconductor device structure 10 is formed with a heat transfer layer 201 (the aforementioned nanostructured material layer 201) and a cap layer 210 remaining on the heat transfer layer 201 formed on the semiconductor substrate 100. Fig.11 In some embodiments, a first backside metallization structure 220 is formed in the heat transfer layer 201 in the semiconductor device structure 10. By means of a dual damascene process, the formation of the first backside metallization structure 220 involves forming a damascene opening DD1 penetrating the top cover layer 210, passing through the heat transfer layer 201 and extending into the semiconductor substrate 100 to expose the conductive via 102, and forming a liner pattern 222 and a metal base pattern 224 in the dual damascene opening DD1, and filling the dual damascene opening DD1.

[0088] like Fig.11As shown, the dual damascene opening DD1 extends from the top surface of the top cap layer 210 to the top surface of the through-hole 102, so that the through-hole 102 is exposed by forming the dual damascene opening DD1. In some embodiments, the formation of the dual damascene opening DD1 includes forming a mask pattern (not shown) on the top cap layer 210 and the heat transfer layer 201, and sequentially etching the top cap layer 210 and the heat transfer layer 201 to form a trench opening (trench opening) and a via opening (via opening) of the dual damascene opening DD1. In some embodiments, the formation of the dual damascene opening DD1 involves one or more etching processes, and the etching process may include a dry etching process, a wet etching process, a reactive ion etching process (Reactive-Ion Etching, RIE), other suitable methods or combinations thereof. In some embodiments, the etching process includes multiple etching steps using different etching chemicals to design etching selectivity to form an opening with a desired profile. It should be understood that the dual damascene process described herein is merely exemplary and that the openings and bonding structures formed within the openings may be formed by a suitable formation process for forming trenches, damascenes, via openings, or other openings of other suitable configurations.

[0089] refer to Fig.11 In some embodiments, the formation of the pad pattern 222 and the metal matrix pattern 224 includes forming a pad / barrier layer (not shown) above the heat transfer layer 201 and conformally covering the dual damascene opening DD1, forming a metal material layer (not shown) above the pad / barrier layer filled in the dual damascene opening DD1 (filling the dual damascene opening DD1), and performing a removal process, which partially removes the pad / barrier layer outside the dual damascene opening DD1 to form the pad pattern 222, and partially removes the metal material layer to form the metal matrix pattern 224 in the dual damascene opening DD1. In some embodiments, the removal process includes performing an etch-back process, or a chemical mechanical polishing (CMP) process, or a combination thereof, to remove the additional pad layer and the additional metal material layer outside the dual damascene opening DD1. As shown in FIG. 11, in some embodiments, after performing the removal process, the cap layer 210 may be partially removed and partially remain but does not expose the underlying heat transfer layer 201.

[0090] In some embodiments, Fig.11 In the embodiment, a first backside metallization structure 220 including a pad pattern 222 and a metal matrix pattern 224 is formed in the dual damascene opening DD1. When the pad / barrier layer and the metal material layer outside the dual damascene opening DD1 or above the top surface of the heat transfer layer 201 are removed, the top of the metal matrix pattern 224 and the top of the pad pattern 1063 are aligned with each other. Figure 2The top surface of the heat transfer layer 201 in the embodiment of the present invention is substantially flush. Herein, the first backside metallization structure or feature may include other configurations and may include one or more perforations and / or damascene structures.

[0091] In some embodiments, Fig.11 As shown, the first backside metallization structure 220 formed in the dual damascene opening DD1 is in direct contact with the conductive through-via 102 and is physically and electrically connected to the conductive through-via 102. In some embodiments, because the through-via 102 buried in the semiconductor substrate 100 is considered as a backside through-via electrically connected to the transistor 1032, the first backside metallization structure 220 is electrically connected to the transistor 1032 through the through-via 102 and serves as part of the backside electrical connection structure of the transistor 1032 (or the component layer 103).

[0092] Here, the first backside metallization structure 220 , the remaining cap layer 210 and the heat transfer layer 201 form a first backside layer BL1 .

[0093] In some embodiments, the material of the pad liner / barrier layer or pad liner pattern 222 includes titanium (Ti), tantalum (Ta), manganese (Mn), niobium (Nb), vanadium (V), yttrium (Y) or its nitride or a combination thereof. In some embodiments, the pad liner / barrier layer is formed to a thickness ranging from about 10 angstroms to about 100 angstroms. In some embodiments, the pad liner pattern 222 includes a titanium / titanium nitride (Ti / TiN) composite layer or a tantalum / tantalum nitride (Ta / TaN) composite layer. In some embodiments, the material of the metal material layer or metal matrix pattern 224 includes one or more metals of W, Cu, Co, Ni, Al, Rh, Ir, Ru, Mo, Os, Ag, and Au; or one or more metal alloys of aluminum copper alloy (AlCu), nickel aluminum alloy (NiAl), ruthenium aluminum alloy (RuAl), vanadium nickel alloy (VNi), vanadium platinum alloy (VPt), aluminum scandium alloy (AlSc) or a combination thereof. The formation of the metal material layer involves electrochemical plating (ECP), electroless deposition (ELD), deposition including chemical vapor deposition, physical vapor deposition, ion beam deposition (IBD), atomic layer deposition or other suitable processes such as molecular beam epitaxy (MBE).

[0094] refer to Fig.12 The second backside layer is formed on the first backside layer BL1, following similar manufacturing process steps, methods and using similar or identical materials as those described for the first backside layer BL1. Fig.12In some embodiments, the formation of the second backside layer BL2 involves forming a second heat transfer layer 301 and forming a second backside metallization structure 320 in the second heat transfer layer 301. The second heat transfer layer 301 is a nanostructured insulating material layer with giant-sized nanocrystals and high thermal conductivity. Similarly, the second heat transfer layer 301 is formed by the same or similar process steps S18 to S22 as the first heat transfer layer 201. In some embodiments, the second heat transfer layer 301 is formed by forming a second material layer with a dopant (not shown) on the top cover layer 210 and the first back metallization structure 220, forming the second top cover layer 310 on the second material layer, and then performing an annealing process to transform the second material layer containing the dopant into the second heat transfer layer 301 (nanostructured material layer). In some embodiments, the second material layer is formed with a dopant by performing a deposition process and a doping process sequentially or simultaneously. In some embodiments, the second heat transfer layer 301 comprises an insulating material, formed of large or giant grains (nano-grains) and having dopants distributed along the grain boundaries of the nano-grains. In an embodiment, the second heat transfer layer 301 is formed of giant nano-grains having a lateral grain size greater than about 50 nanometers. In an embodiment, the second heat transfer layer 301 is formed of giant nano-grains having a lateral grain size greater than about 50 nanometers and a vertical grain size greater than about 80 nanometers. Similarly, the second heat transfer layer 301 is formed according to the same or similar materials and methods as described in the previous paragraph with the first heat transfer layer 201. In some embodiments, the second backside metallization structure 320 includes a pad pattern 322 and a metal matrix pattern 324, and the second backside metallization structure 320 can be formed by the same or similar process steps used to form the first backside metallization structure 220.

[0095] In some embodiments, the insulating material of the second heat transfer layer 301 includes diamond, crystalline (polycrystalline or single crystal) aluminum nitride (AlN), crystalline silicon carbide (SiC) and crystalline boron nitride (BN). In some embodiments, the materials of the first heat transfer layer 201 and the second heat transfer layer 301 are substantially the same. In some embodiments, the material of the second heat transfer layer 301 is different from the material of the first heat transfer layer 201. Depending on the insulating material of the first heat transfer layer 201 or the second heat transfer layer 301, different dopants can be used to assist in the formation of giant nanograins in the nanostructure material layer during the laser annealing process. In some embodiments, the materials of the first top cap layer 210 and the second top cap layer 310 are the same. In some embodiments, the materials of the first top cap layer 210 and the second top cap layer 310 are different. In some embodiments, the second backside metallization structure 320 is formed using the same or similar materials and methods as those used by the first backside metallization structure 220.

[0096] In some embodiments, Fig.12As shown, the second backside metallization structure 320 is physically and electrically connected to the first backside metallization structure 220. In some embodiments, the second backside metallization structure 320 is electrically connected to the transistor 1032 through the first backside metallization structure 220 and the through-hole 102 buried in the semiconductor substrate 100, and serves as part of the backside electrical connection structure of the transistor 1032 (or the component layer 103). Here, the second backside metallization structure or feature may include other configurations and may include one or more connection lines, traces, through-holes and / or damascene structures.

[0097] refer to Fig.13 , the third back side layer BL3 and the fourth back side layer BL4 are sequentially formed on the second back side layer BL2 and the first back side layer BL1. The first and second back side layers BL1 to BL2 close to the semiconductor substrate 100 may be referred to as low back side layers, and the third and fourth back side layers BL3 to BL4 away from the semiconductor substrate 100 may be referred to as high back side layers. It should be understood that the third back side layer BL3 and the fourth back side layer BL4 are formed according to similar manufacturing process steps, methods and using similar or identical materials as those described for the previously formed back side layer BL1 or BL2. Fig.13 In some embodiments, the third backside layer BL3 includes a third heat transfer layer 401 and a third cap layer 410 covering the third heat transfer layer 401, and a third backside metallization structure 420 including a pad pattern 422 and a metal matrix pattern 424 embedded in the heat transfer layer 401. Fig.13 In some embodiments, the fourth backside layer BL4 includes a fourth heat transfer layer 501 and a fourth top cover layer 510 covering the fourth heat transfer layer 501, and a fourth backside metallization structure 520 including a pad pattern 522 and a metal matrix pattern 524 embedded in the heat transfer layer 501. In some embodiments, the heat transfer layers 401 and 501 are independently and respectively nanostructured insulating material layers with giant-sized nanograins and high thermal conductivity. Similarly, the heat transfer layer 401 or 501 is formed by the same or similar process steps S18 to S22 as described above, and this formation involves performing a deposition process and a doping process sequentially or simultaneously. In some embodiments, the heat transfer layer 401 or 501 includes an insulating material formed of large or giant grains (nanograins) and having dopants distributed along the grain boundaries of the nanograins. In an embodiment, the third heat transfer layer 401 is formed of giant nanograins having a lateral grain size greater than about 50 nanometers. In an embodiment, the fourth heat transfer layer 501 is formed of giant nano-grains having a lateral grain size greater than about 50 nanometers and optionally a vertical grain size greater than about 80 nanometers.

[0098] In some embodiments, the insulating material of the heat transfer layer 401 or 501 includes diamond, crystalline (polycrystalline or single crystal) aluminum nitride (AlN), crystalline silicon carbide (SiC) and crystalline boron nitride (BN). In some embodiments, the materials of the heat transfer layers 401 and 501 are substantially the same. In some embodiments, the material of the heat transfer layer 401 is different from the material of the heat transfer layer 501. In some embodiments, the material of the heat transfer layer 401 and 501 is different from the material of the heat transfer layer 301 or 201. The heat transfer layers 401 and 501 may include a dopant different from the dopant included in the first heat transfer layer 201 or the second heat transfer layer 301, resulting in a different average grain size of the nanocrystals in the nanostructured insulating material of the heat transfer layer 401 or 501. In some embodiments, the materials of the top cap layers 410 and 510 are the same. In some embodiments, the materials of the top cap layers 410 and 510 are different. In some embodiments, the third backside metallization structure 420 is formed using the same or similar materials and methods as the lower backside metallization structure, but the fourth backside metallization structure 520 is formed using the same or similar materials and methods as used for the lower backside metallization structure.

[0099] In some embodiments, Fig.13 As shown, the third backside metallization structure 420 is physically and electrically connected to the second backside metallization structure 320, and the fourth backside metallization structure 520 is physically and electrically connected to the third backside metallization structure 420. In some embodiments, the third backside metallization structure 420 includes a power delivery network having a configuration such as a through-hole, a connecting line, a trace, and / or a damascene structure. In some embodiments, the fourth backside metallization structure 520 includes a backside power rail (BPR) having a configuration such as a track, a trace, and / or a damascene structure. In some embodiments, the third backside metallization structure 420 and the fourth backside metallization structure 520 work together to deliver power to the underlying component layer 103 through the low backside metallization structure 220, 320 and the through-hole 102 buried in the semiconductor substrate 100, and the third backside metallization structure 420 and the fourth backside metallization structure 520 electrically connected to the transistor 1032 also serve as part of the backside electrical connection structure.

[0100] refer to Fig.13, the backside layers BL1, BL2, BL3 and BL4 form a backside connection structure to provide electrical connection and deliver power to the underlying component layer 103. In addition, the backside connection structure also includes heat transfer layers 201, 301, 401, 501 as backside heat transfer structures for assisting the heat dissipation of the backside connection structure, in particular for effectively dissipating the heat of the backside power rail or other power transmission network. It should be understood that the number of backside layers or heat transfer layers is only exemplary. The backside layers or heat transfer layers are not limited to the four layers shown in the context, but may include more or fewer layers to form a backside connection structure or a backside heat transfer structure.

[0101] In some embodiments, heat transfer layer 401 has a lateral grain size greater than 50 nanometers and a kappa value greater than 80 W / m·K. In some embodiments, heat transfer layer 501 has a lateral grain size greater than 50 nanometers and a kappa value greater than 80 W / m·K. In an embodiment, heat transfer layer 501 has a grain size of about or greater than 80 nanometers, and a kappa value ranging from about 100 W / m·K to 300 W / m·K.

[0102] In some embodiments, the material of heat transfer layer 401 and 501 is different from the material of heat transfer layer 301 or 201. In some embodiments, the formation of heat transfer layer 401 or 501 includes in-situ doping by chemical vapor deposition, using dopants containing Al, Si, Nb, Mn and / or B to form a diamond layer, and then performing a laser annealing process to promote giant grain growth in the diamond layer. In some embodiments, the formation of heat transfer layer 301 or 201 includes forming a crystalline AlN layer by physical vapor deposition, and adding dopants containing Ti, Zr, Nb, Y, Cr, Ni, Si, Mn, and / or Ru by co-sputtering, and then performing a laser annealing process to promote giant grain growth in the AlN layer.

[0103] In some embodiments, heat transfer layers 401 and 501 are formed of the same or similar material as that forming heat transfer layer 301 or 201, but heat transfer layer 401 or 501 is formed of nanocrystals having a grain size greater than that of the nanocrystals of heat transfer layer 301 or 201, and the thermal conductivity of heat transfer layer 401 or 501 is higher than that of heat transfer layer 301 or 201.

[0104] In some embodiments, heat transfer layer 401 or 501 has a higher thermal conductivity than heat transfer layer 301 or 201 , further facilitating heat transfer from hot spots (eg, power rails or power delivery networks) to other locations within the component structure.

[0105] By incorporating a high thermal conductivity heat transfer layer in the backside connection structure, especially a nanostructured dielectric material layer with large grain size and high thermal conductivity near the backside power rail, an efficient heat dissipation system is established. According to simulation results, the expected maximum temperature (maximum temperature, Tmax) of the hot spot near the backside power rail is reduced by about 40%. By avoiding the degradation that may be caused by high Tmax, the reliability and performance of the semiconductor component structure are significantly improved.

[0106] Furthermore, through an ultrafast laser annealing process for forming a nanostructured dielectric material layer with a large grain size and high thermal conductivity, a high-quality nanostructured material layer with high thermal conductivity can be formed at a back-end process compatible temperature (e.g., 400 degrees Celsius), and such a process can be easily integrated into the manufacturing process of the back-side connection structure including the back-side power rail.

[0107] According to some embodiments of the present disclosure, a semiconductor component structure is disclosed. The structure includes a semiconductor substrate having a first surface and a second surface opposite to the first surface, and a component layer disposed on the first surface of the semiconductor substrate. The component layer includes a plurality of transistors. The structure includes a backside connection structure disposed on the second surface of the semiconductor substrate and electrically connected to the transistors. The backside connection structure includes a backside metallization structure and at least one insulating nanostructure material having nanocrystals and dopants distributed along the grain boundaries of the nanocrystals.

[0108] According to some embodiments of the present disclosure, a method for manufacturing a semiconductor component structure is disclosed. A component layer is formed on a first surface of a semiconductor substrate, and the component layer is formed by a plurality of transistors. A thinning process is performed on the semiconductor substrate, and the semiconductor substrate is thinned starting from a second surface of the semiconductor substrate relative to the first surface. A material layer containing a dopant is formed on the second surface of the thinned semiconductor substrate. The material layer is formed by first nanocrystals of a first grain size. A cap layer is formed on the material layer to cover the material layer. An annealing process is performed on the cap layer and the material layer to transform the material layer into a nanostructured material layer. The nanostructured material layer is formed by second nanocrystals having a second grain size, and the second grain size is larger than the first grain size grains. A metallization structure is formed in the nanostructured material layer.

[0109] According to some embodiments of the present disclosure, a method for manufacturing a semiconductor device structure is disclosed. A semiconductor substrate is provided, having a through hole embedded therein; a device layer is formed on a first side of the semiconductor substrate. The device layer is formed by a plurality of transistors. A first material layer is formed on a second side of the semiconductor substrate relative to the first side, and the first material layer is doped. The first material layer is formed by first nanocrystals of a first grain size and contains a first dopant. A first cap layer is formed on the first material layer, covering the first material layer. A first nanostructured material layer is formed below the first cap layer by performing a first laser annealing process. The first nanostructured material layer is formed by second nanocrystals of a second grain size greater than the first grain size, and the first dopant is distributed along the grain boundaries of the second nanocrystals. A first metallization structure is formed in the first nanostructured material layer. A second material layer is formed above the first material layer, and the second material layer is doped. The second material layer is formed by third nanocrystals of a third grain size and contains a second dopant. A second cap layer is formed on the second material layer, covering the second material layer. A second nanostructured material layer is formed below the second cap layer by performing a second laser annealing process. The second material layer is formed by fourth nanocrystals having a fourth grain size greater than the third grain size. The second dopant is distributed along the grain boundaries of the fourth nanocrystals. A second metallization structure is formed in the second nanostructured material layer.

[0110] The above overview of features and embodiments is intended to enable those of ordinary skill in the art to better understand aspects of the present invention. Those of ordinary skill in the art will appreciate that they can easily use this disclosure as a basis for designing or modifying other processes and structures to achieve the same purpose and / or achieve the same advantages as the embodiments described herein. Those of ordinary skill in the art will also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that they can make various changes, substitutions, and modifications herein without departing from the spirit and scope of this disclosure.

Claims

1. A method for manufacturing a semiconductor component structure, characterized in that: include: forming a device layer on a first surface of a semiconductor substrate, wherein the device layer is formed of a plurality of transistors; Performing a thinning process on the semiconductor substrate, thinning the semiconductor substrate starting from a second surface of the semiconductor substrate opposite to the first surface; forming a material layer containing dopants on the second surface of the thinned semiconductor substrate, wherein the material layer is formed of first nanocrystal grains of a first grain size; forming a top cover layer on the material layer to cover the material layer; Performing an annealing process on the cap layer and the material layer to transform the material layer into a nanostructured material layer, wherein the nanostructured material layer is formed by second nanocrystal grains having a second grain size, and the second grain size is larger than the first grain size grains; as well as A metallization structure is formed in the nanostructured material layer.

2. The method according to claim 1, characterized in that The forming of the material layer containing the dopant includes performing a deposition process and performing in-situ doping of the dopant.

3. The method according to claim 2, characterized in that The forming of the material layer includes depositing an insulating material layer selected from diamond, crystalline aluminum nitride (AlN), crystalline silicon carbide (SiC) or crystalline boron nitride (BN).

4. The method according to claim 1, characterized in that: The forming of the material layer containing dopants includes forming a diamond layer by performing a chemical vapor deposition process with in-situ doping.

5. The method according to claim 1, characterized in that The forming of the material layer containing the dopant includes forming a crystalline aluminum nitride (AlN) layer by performing a physical vapor deposition process and co-sputtering the dopant.

6. The method according to claim 1, characterized in that The forming of a metallization structure in the nanostructured material layer includes forming a metal power rail in the nanostructured material layer.

7. A method for manufacturing a semiconductor component structure, characterized in that: include: providing a semiconductor substrate having a through hole embedded therein; forming a component layer on the first side of the semiconductor substrate, wherein the component layer is formed by a plurality of transistors; Forming a first material layer on a second side of the semiconductor substrate opposite to the first side, and performing doping on the first material layer, wherein the first material layer is formed of first nanocrystal grains of a first grain size and contains a first dopant; forming a first cap layer on the first material layer to cover the first material layer; Forming a first nanostructured material layer below the first cap layer by performing a first laser annealing process, wherein the first nanostructured material layer is formed of second nanocrystals having a second grain size greater than the first grain size, and the first dopant is distributed along grain boundaries of the second nanocrystals; forming a first metallization structure in the first nanostructured material layer; forming a second material layer above the first material layer, and performing doping on the second material layer, wherein the second material layer is formed of third nanocrystal grains of a third grain size and contains a second dopant; forming a second cap layer on the second material layer to cover the second material layer; A second nanostructured material layer is formed below the second cap layer by performing a second laser annealing process, wherein the second material layer is formed of fourth nanocrystals having a fourth grain size greater than the third grain size. The second dopant is distributed along the grain boundary of the fourth nano-grain; and A second metallization structure is formed in the second nanostructured material layer.

8. The method according to claim 7, characterized in that The forming of a first metallization structure in the first nanostructure material layer includes forming a connection pattern in the first nanostructure material layer, wherein the connection pattern is connected to the through-hole and to the plurality of transistors.

9. A semiconductor component structure, characterized in that: include: A semiconductor substrate having a first surface and a second surface opposite to the first surface; a component layer disposed on the first surface of the semiconductor substrate, wherein the component layer includes a plurality of transistors; as well as a backside connection structure, disposed on the second surface of the semiconductor substrate and electrically connected to the plurality of transistors, The backside connection structure comprises a backside metallization structure and at least one insulating nanostructured material having nanocrystal grains and dopants distributed along grain boundaries of the nanocrystal grains.

10. The structure according to claim 9, characterized in that The backside metallization structure includes a metal backside power rail.

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