Chip packaging method, chip structure and electronic equipment

Abstract

The invention relates to a chip packaging method, a chip structure and electronic equipment, and relates to the technical field of integrated circuits. The chip packaging method comprises the following steps: providing a substrate and a first chip, wherein the first chip is arranged on the substrate; forming a first filling layer around the side wall of the first chip; forming a wire embedding layer on the first filling layer, wherein the wire embedding layer comprises a contact wire; a second chip is placed on the wire embedding layer, so that a second drain electrode of the second chip is electrically connected with the first source electrode through a contact wire; forming a third filling layer to wrap the second chip, and exposing the terminals of the second source electrode and the second grid electrode; the third filling layer further comprises a plurality of contact lines which are respectively connected with the contact lines of the wire embedding layer so as to expose the wiring end of the first source electrode and the wiring end of the first grid electrode at the top. According to the chip packaging method provided by the invention, filling is carried out in sequence through the plurality of filling layers, so that electric connection between the first chip and the second chip can be realized, and the mechanical strength of a packaged product is improved.

Description

Technical Field

[0001] The present application relates to the field of integrated circuit technology, and in particular to a chip packaging method, a chip structure and an electronic device. Background Art

[0002] In traditional power device packaging, single chip packaging is the main method, and multiple chips are used in parallel. However, with the needs of the market and applications, the space and volume requirements are further compressed, and multi-chip packaging or stacking is needed.

[0003] There are many technical difficulties and bottlenecks in chip stacking, especially in the field of power devices. Due to the particularity of its product structure, its back contains a large area of ​​metal as a drain or conduction electrode and cannot be simply stacked. Summary of the invention

[0004] Based on this, it is necessary to provide a chip packaging method, a chip structure and an electronic device to address the problem that power devices in the prior art are difficult to stack.

[0005] In a first aspect, the present application provides a chip packaging method, the chip packaging method comprising the following steps: Providing a substrate and a first chip, and configuring the first chip on the substrate; the first chip includes a first body region, a first source and a first gate of the first chip are located on the top of the first body region, and a first back gold layer is provided at the bottom of the first body region as a first drain; forming a first filling layer around the sidewall of the first chip; forming a buried wire layer on the first filling layer, wherein the buried wire layer includes a contact wire; A second chip is placed on the buried wire layer, so that the second drain of the second chip is electrically connected to the first source through the contact wire; the second chip includes a second body region, the second source and the second gate of the second chip are located on the top of the second body region, and the bottom of the second body region has a second back gold layer as a second drain; A third filling layer is formed to cover the second chip and expose the connection terminals of the second source and the second gate; the third filling layer also includes a plurality of contact wires respectively connected to the contact wires of the buried wire layer to expose the connection terminals of the first source and the first gate at the top.

[0006] In one embodiment, forming a buried wire layer on the first filling layer, wherein the buried wire layer includes a contact wire, comprises: A first source horizontal contact line and a first gate horizontal contact line are formed on the first chip; the first source horizontal contact line is electrically connected to the first source, and the first gate horizontal contact line is electrically connected to the first gate; forming a second filling layer, wherein the second filling layer covers the first source horizontal contact line and the first gate horizontal contact line; A plurality of holes are formed by laser drilling the second filling layer, and a conductive material is filled in the holes to respectively form a first vertical contact line, a second vertical contact line and a third vertical contact line; the first vertical contact line and the second vertical contact line are both electrically connected to the first source horizontal contact line, and the third vertical contact line is electrically connected to the first gate horizontal contact line.

[0007] In one embodiment, before placing the second chip on the buried wire layer, the method further includes: forming a first pad surface on the first vertical contact line, forming a second pad surface on the third vertical contact line, and forming a second drain horizontal contact line on the second vertical contact line, so that the second chip is electrically connected to the first source through the second drain horizontal contact line; The step of forming a third filling layer to cover the second chip and expose the connection terminals of the second source and the second gate includes: forming the third filling layer to cover the second chip; A plurality of holes are formed by laser drilling the third filling layer, and conductive material is filled in the holes to respectively form a fourth vertical contact line and a fifth vertical contact line, wherein the fourth vertical contact line is electrically connected to the first pad surface, and the fifth vertical contact line is electrically connected to the second pad surface.

[0008] In one embodiment, providing a substrate, providing a first chip, and configuring the first chip on the substrate comprises: Providing a substrate, and forming a first drain horizontal contact line on the substrate; Disposing a first chip on the substrate, and electrically connecting a first drain of the first chip to the first drain horizontal contact line; After forming the third filling layer to cover the second chip and expose the connection terminals of the second source and the second gate, the method further includes: removing the substrate, forming a fourth filling layer at the bottom of the first chip, and covering the first drain horizontal contact line with the fourth filling layer; When the second filling layer is laser-drilled to form a hole, a hole is also formed above the first drain horizontal contact line, and the first drain horizontal contact line is exposed, and the hole is filled to form a sixth vertical contact line, and the sixth vertical contact line is electrically connected to the first drain horizontal contact line; The third filling layer further includes an eighth vertical contact line, and the eighth vertical contact line is electrically connected to the sixth vertical contact line to expose a connection terminal of the first drain electrode on a surface of the third filling layer.

[0009] In one embodiment, the chip packaging method further includes: A fifth filling layer is formed on the third filling layer, and the fifth filling layer includes a plurality of contact lines, which are electrically connected to the contact lines on the third filling layer respectively, so as to expose the connection terminals of the first source, the second source, the first gate and the second gate respectively on the top of the fifth filling layer.

[0010] In one embodiment, the buried wire layer includes a connection member, the connection member is electrically connected to the first source electrode, and the second drain electrode is connected to the first source electrode through the connection member.

[0011] In one of the embodiments, at the top position of the third filling layer, the terminal of the first source is located between the terminal of the second source and the terminal of the second gate.

[0012] In one embodiment, the chip packaging method further includes: A connection port is formed on the connection terminal of the first source electrode, the connection terminal of the first gate electrode, the connection terminal of the second source electrode, and the connection terminal of the second gate electrode by chemical plating or electroplating.

[0013] In a second aspect, the present application further provides a chip structure, which is packaged by any one of the chip packaging methods described above.

[0014] In a third aspect, the present application also provides an electronic device, wherein the electronic device includes the chip structure.

[0015] In the chip packaging method, chip structure and electronic device provided by the present invention, the first chip and the second chip both include a source, a drain and a gate, wherein the source and the gate are located on the same side, and a back gold layer is formed on the other side as a drain. The packaging method provided by the present application first fills the side wall of the first chip to obtain a first filling layer, and then forms a buried wire layer on the first filling layer, wherein the buried wire layer has a contact wire, and the contact wire is electrically connected to the source and gate of the first chip respectively. After that, the second chip is placed on the buried wire layer, so that the second drain of the second chip is electrically connected to the first source of the first chip through the contact wire. After that, a third filling layer is formed to cover the second chip, and the second source and the second gate of the second chip are exposed as wiring terminals. By filling in a plurality of filling layers in sequence, the electrical connection between the first chip and the second chip can be realized, and the mechanical strength of the packaged product can be improved. In addition, by packaging two or more chips together, the conduction path between the chips is reduced, which can reduce the response time on the one hand, reduce the connection impedance (Rsson) on the other hand, reduce heat dissipation, and improve power density. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the conventional technology, the drawings required for use in the embodiments or the conventional technology descriptions are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0017] Figure 1 is a flow chart of a packaging method provided in an embodiment; Figure 2 is a schematic diagram of forming a first filling layer in one embodiment; Figure 3 is a schematic diagram of forming a horizontal contact line in one embodiment; Figure 4 A schematic diagram of forming a second filling layer and forming a vertical contact line in one embodiment; Figure 5 is a schematic diagram of placing a second chip in one embodiment; Figure 6 is a schematic diagram of forming a third filling layer in one embodiment; Figure 7 is a schematic diagram of forming a fourth filling layer and a fifth filling layer in one embodiment; Figure 8a is a schematic diagram of a chip structure in another embodiment; Figure 8b A schematic diagram of a chip structure in yet another embodiment; Figure 8c FIG. 4 is a schematic diagram of a chip structure in another embodiment.

[0018] Description of reference numerals: 10. First chip; 11. First source; 12. First gate; 13. First body region; 14. First drain; 20. Second chip; 21. Second source; 22. Second gate; 23. Second body region; 24. Second drain; 30. First filling layer; 40. Second filling layer; 41. First source horizontal contact line; 42. First gate horizontal contact line; 43. First vertical contact line; 44. Second vertical contact line; 45. Third vertical contact line; 46. Connector; 50. Third filling layer; 51. Fourth vertical contact line; 52. Fifth vertical contact line; 60. Fourth filling layer; 61. First drain horizontal contact line; 62. Sixth vertical contact line; 63. Seventh vertical contact line; 64. Eighth vertical contact line; 65. Second drain horizontal contact line; 66. Substrate; 70. Fifth filling layer; 80. Connection port. DETAILED DESCRIPTION

[0019] In order to facilitate understanding of the present application, the present application will be described more fully below with reference to the relevant drawings. The preferred embodiments of the present application are given in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.

[0020] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0021] It should be understood that when an element or layer is referred to as "on ... ", "adjacent to ... ", "connected to" or "coupled to" other elements or layers, it can be directly on other elements or layers, adjacent to, connected to or coupled to other elements or layers, or there can be intervening elements or layers. On the contrary, when an element is referred to as "directly on ... ", "directly adjacent to ... ", "directly connected to" or "directly coupled to" other elements or layers, there is no intervening element or layer. It should be understood that although the terms first, second, third, etc. can be used to describe various elements, components, regions, layers, doping types and / or parts, these elements, components, regions, layers, doping types and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type or part from another element, component, region, layer, doping type or part. Therefore, without departing from the teachings of the present invention, the first element, component, region, layer, doping type or part discussed below can be represented as a second element, component, region, layer or part.

[0022] Spatial relationship terms such as "under", "below", "below", "under", "above", "above", etc., may be used here to describe the relationship between an element or feature shown in the figure and other elements or features. It should be understood that in addition to the orientations shown in the figures, spatial relationship terms also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is turned over, the element or feature described as "under other elements" or "under it" or "under it" will be oriented as "on" other elements or features. Therefore, the exemplary terms "under" and "under" may include both upper and lower orientations. In addition, the device may also include additional orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptors used herein are interpreted accordingly.

[0023] When used herein, the singular forms "a", "an", and "said / the" may also include plural forms, unless the context clearly indicates otherwise. It should also be understood that when the terms "consisting of" and / or "comprising" are used in this specification, the presence of the features, integers, steps, operations, elements and / or parts can be determined, but the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups is not excluded. At the same time, when used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0024] The relevant structures of the embodiments of the present invention should not be limited to the specific shapes shown in the drawings of the specification, but include shape deviations due to, for example, manufacturing technology. The shapes shown in the drawings are schematic in nature and do not limit the scope of the present invention.

[0025] In some embodiments, see Figure 1 , a chip packaging method is provided, and the chip packaging method includes the following steps S11~S15.

[0026] S11, see Figure 2 , provide a substrate 66, provide a first chip 10, and configure the first chip 10 on the substrate 66; the first chip 10 includes a first body region 13, the first source 11 and the first gate 12 of the first chip 10 are located on the top of the first body region 13, and the bottom of the first body region 13 has a first back gold layer as a first drain 14.

[0027] Exemplarily, the first chip 10 is a power chip, and the first chip 10 may be configured on a substrate 66. The first body region 13 may be a substrate.

[0028] S12, please continue to read Figure 2 A first filling layer 30 is formed around the sidewall of the first chip 10 .

[0029] Exemplarily, four side walls surrounding the first chip 10 are all formed with filling materials, and the filling materials form the first filling layer 30 .

[0030] In some embodiments, when the first filling layer 30 is formed around the side wall of the first chip 10, it is easy to form a partial filling material on the first chip 10, resulting in blocking the first source 11 or the first gate 12 on the top of the first chip 10. At this time, drilling is performed through a punching process to expose the first source 11 and the first gate 12 of the first chip.

[0031] S13, see Figure 3 and Figure 4 , a buried wire layer is formed on the first filling layer 30, wherein the buried wire layer includes a contact wire.

[0032] Exemplarily, the contact wire may be a metal lead or other conductive material. Optionally, the contact wire may be any one or more combinations of Ti, W, Cu or Au.

[0033] S14, see Figure 5 , a second chip 20 is placed on the buried wire layer, so that the second drain 24 of the second chip 20 is electrically connected to the first source 11 through the contact wire; the second chip 20 includes a second body region 23, the second source 21 and the second gate 22 of the second chip 20 are located on the top of the second body region 23, and the bottom of the second body region 23 has a second back gold layer as the second drain 24.

[0034] Exemplarily, the second chip 20 is also a power device, and has the same structure as the first chip 10 .

[0035] S15, see Figure 5 , forming a third filling layer 50 to cover the second chip 20 and expose the wiring terminals of the second source 21 and the second gate 22; the third filling layer 50 also includes a plurality of contact wires respectively connected to the contact wires of the buried wire layer to expose the wiring terminals of the first source 11 and the first gate 12 at the top.

[0036] In the above chip packaging method, the first chip 10 and the second chip 20 both include a source, a drain and a gate, wherein the source and the gate are located on the same side, and a back gold layer is formed on the other side as a drain. The packaging method provided in the present application first fills the side wall of the first chip 10 to obtain a first filling layer 30, and then forms a buried wire layer on the first filling layer 30, wherein the buried wire layer has a contact wire, and the contact wire is electrically connected to the source and gate of the first chip 10 respectively. Then, the second chip 20 is placed on the buried wire layer, so that the second drain 24 of the second chip 20 is electrically connected to the first source 11 of the first chip 10 through the contact wire. Then, a third filling layer 50 is formed to cover the second chip 20, and the second source 21 and the second gate 22 of the second chip 20 are exposed as wiring terminals. By filling multiple filling layers in sequence, the electrical connection between the first chip 10 and the second chip 20 can be achieved, and the mechanical strength of the packaged product can be improved.

[0037] In some embodiments, step S13 forms a buried wire layer on the first filling layer 30, and the buried wire layer includes a contact wire, including: Figure 3, a first source horizontal contact line 41 and a first gate horizontal contact line 42 are formed on the first chip 10; the first source horizontal contact line 41 is electrically connected to the first source 11, and the first gate horizontal contact line 42 is electrically connected to the first gate 12; a second filling layer 40 is formed, and the second filling layer 40 covers the first source horizontal contact line 41 and the first gate horizontal contact line 42; a plurality of holes are formed by laser drilling the second filling layer 40, and a conductive material is filled in the holes to form a first vertical contact line 43, a second vertical contact line 44 and a third vertical contact line 45 respectively; the first vertical contact line 43 and the second vertical contact line 44 are both electrically connected to the first source horizontal contact line 41, and the third vertical contact line 45 is electrically connected to the first gate horizontal contact line 42.

[0038] It can be understood that the first gate horizontal contact line 42 or the first source horizontal contact line 41 can be an RDL rewiring.

[0039] Exemplarily, the first source horizontal contact line 41 and the first gate horizontal contact line 42 extend along a first direction, which is a direction parallel to the upper surface of the first chip 10, such as a horizontal direction. The first vertical contact line 43, the second vertical contact line 44 and the third vertical contact line 45 extend along a second direction, which is a direction perpendicular to the upper surface of the first chip 10, such as a vertical direction.

[0040] Exemplarily, the buried wire layer includes contact wires and filling materials, and the electrodes of the first chip 10 are extended by the contact wires to form lead terminals or to be electrically connected to the second chip 20. The contact wires are then packaged and limited by the filling materials to improve the sealing effect.

[0041] In this embodiment, a horizontal contact line is first formed on the first filling layer 30, and then a second filling layer 40 is formed by filling material, and a conductive metal material is injected after opening the second filling layer 40 to form a vertical contact line. On the one hand, by forming the horizontal contact line first, it can ensure that there is a good electrical connection between the various parts of the chip, and the conductive path can be freely planned. For the solution of forming the filling layer first, the conductive path is limited by the groove opening process; on the other hand, the layered filling method can effectively avoid the contact or short circuit problem between different layers.

[0042] In some embodiments, see Figure 5In step S14, before placing the second chip 20 on the buried wire layer, the packaging method also includes: forming a first pad surface on the first vertical contact line 43, forming a second pad surface on the third vertical contact line 45, and forming a second drain horizontal contact line 65 on the second vertical contact line 44, so that the second chip 20 is electrically connected to the first source 11 through the second drain horizontal contact line 65; forming a third filling layer 50 to cover the second chip 20, and exposing the connection terminals of the second source 21 and the second gate 22, including: forming a third filling layer 50 to cover the second chip 20; forming a plurality of holes by laser drilling the third filling layer 50, and filling the holes with conductive material to form a fourth vertical contact line 51 and a fifth vertical contact line 52 respectively, the fourth vertical contact line 51 is electrically connected to the first pad surface, and the fifth vertical contact line 52 is electrically connected to the second pad surface.

[0043] In the above steps, the buried wire layer includes a second chip 20, a contact wire and a third filling layer 50. The design of the longitudinal contact wire can optimize the circuit layout inside the chip, reduce parasitic capacitance and resistance during signal transmission, and further improve the packaging density and interconnection performance of the chip, optimize the connection between each layer in the chip, make the multi-layer interconnection process more compact and stable, and avoid unnecessary connection failures and performance degradation.

[0044] Continue to see Figure 2 and Figure 3 In order to form a terminal at the bottom of the first gate 12, in some embodiments, in step S11, a substrate 66 is provided, a first chip 10 is provided, and the first chip 10 is configured on the substrate 66, including: providing the substrate 66, forming a first drain horizontal contact line 61 on the substrate 66; configuring the first chip 10 on the substrate 66, and electrically connecting the first drain 14 of the first chip 10 to the first drain horizontal contact line 61; forming a third filling layer 50 to cover the second chip 20 and expose the second source 21 and the second gate 22. After that, the method further includes: removing the substrate 66, A fourth filling layer 60 is formed at the bottom of the sheet 10, and the first drain transverse contact line 61 is covered by the fourth filling layer 60; when the second filling layer 40 is laser-drilled to form a hole, a hole located above the first drain transverse contact line 61 is also formed, and the first drain transverse contact line 61 is exposed, and the hole is filled to form a sixth vertical contact line 62, and the sixth vertical contact line 62 is electrically connected to the first drain transverse contact line 61; the third filling layer 50 also includes an eighth vertical contact line 64, and the eighth vertical contact line 64 is electrically connected to the sixth vertical contact line 62, so as to expose the connection terminal of the first drain 14 on the surface of the third filling layer 50. It can be understood that the eighth vertical contact line 64 and the sixth vertical contact line 62 can also be connected through the seventh vertical contact line 63 in the second filling layer 40.

[0045] In this way, the drain of the first chip 10 can also be connected to the top of the third filling layer 50 through a contact line, with the top of the third filling layer 50 as the wiring terminal, so that the first source 11, the first gate 12, the first drain 14 of the first chip 10 and the second source 21, the second gate 22 of the second chip 20 can all be led out from the top of the third filling layer 50.

[0046] See also Figure 7 In order to facilitate the lead-out of the second source 21 and the second gate 22 on the second chip 20, in some embodiments, the chip packaging method also includes: forming a fifth filling layer 70 on the third filling layer 50, the fifth filling layer 70 including a plurality of contact lines, which are respectively electrically connected to the contact lines on the third filling layer 50, so as to expose the connection terminals of the first source 11, the second source 21, the first gate 12 and the second gate 22 at the top of the fifth filling layer 70.

[0047] By forming contact lines on the fifth filling layer 70 , the second source 21 and the second gate 22 on the second chip 20 can be more clearly and reliably led out of the chip package, avoiding direct exposure of the second gate 22 and the second source 21 on the third filling layer 50 .

[0048] See also Figure 8a In some embodiments, the buried wire layer includes a connector 46, the connector 46 is electrically connected to the first source 11, and the second drain 24 is connected to the first source 11 through the connector 46. The design of the connector 46 can play a key role in electrical connection during the packaging process, and it can be a pad, a lead or other similar structure. Through this design, the drain of the second chip 20 is directly welded to the first source 11 of the first chip 10 through the connector 46, thereby achieving electrical connection between the two. In this way, the connection between the second drain 24 and the first source 11 becomes tighter, avoiding a complex multi-layer interconnection structure, and further reducing the overall volume of the chip package.

[0049] By designing the connector 46 as a pad, the connector 46 can effectively guide the current from the drain of the second chip 20 to the source of the first chip 10, reducing the impedance in the current transmission path. The use of pads simplifies the formation of contact points, improves the controllability of the packaging process, and helps to improve the reliability of the connection. In addition, since the space required for additional lines and electrical connections is reduced, the packaging design can be optimized in physical size, making the packaged chip volume more compact. This compact structural design can not only reduce the packaging space, but also optimize the heat dissipation effect while improving the integration, which helps to improve the performance of the chip.

[0050] In some embodiments, at the top of the third filling layer 50, the terminal of the first source 11 is located between the terminal of the second source 21 and the terminal of the second gate 22. This arrangement can effectively optimize the electrical connection layout, reduce signal interference, and improve the stability of the overall circuit. Specifically, by placing the terminal of the first source 11 between the terminal of the second source 21 and the terminal of the second gate 22, a more compact circuit structure can be achieved, thereby shortening the current transmission path and reducing the resistance and inductance in the circuit. This can not only improve the signal transmission speed, but also reduce energy loss and improve the efficiency of the circuit.

[0051] In some embodiments, the chip packaging method further includes: forming a connection port 80 by chemical plating or electroplating the connection terminal of the first source 11, the connection terminal of the first gate 12, the connection terminal of the second source 21, and the connection terminal of the second gate 22. In this way, the packaged chip can be easily applied in the circuit structure.

[0052] The present application also provides a chip structure, which is obtained by packaging the chip packaging method of any embodiment. The obtained chip structure can be as follows: Figure 7 as well as Figure 8a , Figure 8b and Figure 8c Any of the structures shown.

[0053] In a third aspect, the present application also provides an electronic device, which includes a chip structure. The electronic device includes, for example, data storage devices, copiers, network devices, household appliances, instruments, mobile phones, computers and other devices with data storage functions. The electronic device may include a housing and a circuit board arranged in the housing, a memory or a data read-write circuit integrated on the circuit board. The structure of the memory can refer to the relevant description in some of the above embodiments. The electronic device may also include other necessary elements or components, which are not limited in the embodiments of the present disclosure.

[0054] The technical features of the above-mentioned embodiments can be combined arbitrarily. In order to make the description concise, not all possible combinations of the technical features of the above-mentioned embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0055] The above-described embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be construed as limiting the scope of the patent application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent application shall be subject to the attached claims.

Claims

1. A chip packaging method, characterized in that: The chip packaging method comprises the following steps: Providing a substrate and a first chip, and configuring the first chip on the substrate; the first chip includes a first body region, a first source and a first gate of the first chip are located on the top of the first body region, and a first back gold layer is provided at the bottom of the first body region as a first drain; forming a first filling layer around the sidewall of the first chip; forming a buried wire layer on the first filling layer, wherein the buried wire layer includes a contact wire; A second chip is placed on the buried wire layer, so that the second drain of the second chip is electrically connected to the first source through the contact wire; the second chip includes a second body region, the second source and the second gate of the second chip are located on the top of the second body region, and the bottom of the second body region has a second back gold layer as a second drain; A third filling layer is formed to cover the second chip and expose the connection terminals of the second source and the second gate; the third filling layer also includes a plurality of contact wires respectively connected to the contact wires of the buried wire layer to expose the connection terminals of the first source and the first gate at the top.

2. The chip packaging method according to claim 1, characterized in that: The step of forming a buried wire layer on the first filling layer, wherein the buried wire layer includes a contact wire, comprises: A first source horizontal contact line and a first gate horizontal contact line are formed on the first chip; the first source horizontal contact line is electrically connected to the first source, and the first gate horizontal contact line is electrically connected to the first gate; forming a second filling layer, wherein the second filling layer covers the first source horizontal contact line and the first gate horizontal contact line; A plurality of holes are formed by laser drilling the second filling layer, and a conductive material is filled in the holes to respectively form a first vertical contact line, a second vertical contact line and a third vertical contact line; the first vertical contact line and the second vertical contact line are both electrically connected to the first source horizontal contact line, and the third vertical contact line is electrically connected to the first gate horizontal contact line.

3. The chip packaging method according to claim 2, characterized in that: Before placing the second chip on the buried wire layer, the method further includes: forming a first pad surface on the first vertical contact line, forming a second pad surface on the third vertical contact line, and forming a second drain horizontal contact line on the second vertical contact line, so that the second chip is electrically connected to the first source through the second drain horizontal contact line; The step of forming a third filling layer to cover the second chip and expose the connection terminals of the second source and the second gate includes: forming the third filling layer to cover the second chip; A plurality of holes are formed by laser drilling the third filling layer, and conductive material is filled in the holes to respectively form a fourth vertical contact line and a fifth vertical contact line, wherein the fourth vertical contact line is electrically connected to the first pad surface, and the fifth vertical contact line is electrically connected to the second pad surface.

4. The chip packaging method according to claim 2, characterized in that: The providing of a substrate, providing a first chip, and configuring the first chip on the substrate comprises: Providing a substrate, and forming a first drain horizontal contact line on the substrate; Disposing a first chip on the substrate, and electrically connecting a first drain of the first chip to the first drain horizontal contact line; After forming the third filling layer to cover the second chip and expose the connection terminals of the second source and the second gate, the method further includes: removing the substrate, forming a fourth filling layer at the bottom of the first chip, and covering the first drain horizontal contact line with the fourth filling layer; When the second filling layer is laser-drilled to form a hole, a hole is also formed above the first drain horizontal contact line, and the first drain horizontal contact line is exposed, and the hole is filled to form a sixth vertical contact line, and the sixth vertical contact line is electrically connected to the first drain horizontal contact line; The third filling layer further includes an eighth vertical contact line, and the eighth vertical contact line is electrically connected to the sixth vertical contact line to expose a connection terminal of the first drain electrode on a surface of the third filling layer.

5. The chip packaging method according to claim 1, characterized in that: The chip packaging method further comprises: A fifth filling layer is formed on the third filling layer, and the fifth filling layer includes a plurality of contact lines, which are electrically connected to the contact lines on the third filling layer respectively, so as to expose the connection terminals of the first source, the second source, the first gate and the second gate respectively on the top of the fifth filling layer.

6. The chip packaging method according to claim 1, characterized in that: The buried wire layer includes a connection member, the connection member is electrically connected to the first source electrode, and the second drain electrode is connected to the first source electrode through the connection member.

7. The chip packaging method according to claim 6, characterized in that: At the top position of the third filling layer, the terminal of the first source is located between the terminal of the second source and the terminal of the second gate.

8. The chip packaging method according to claim 1, characterized in that: The chip packaging method further comprises: A connection port is formed on the connection terminal of the first source electrode, the connection terminal of the first gate electrode, the connection terminal of the second source electrode, and the connection terminal of the second gate electrode by chemical plating or electroplating.

9. A chip structure, characterized in that: The chip structure is packaged by the chip packaging method according to any one of claims 1 to 8.

10. An electronic device, characterized in that: The electronic device comprises the chip structure according to claim 9.

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