A linear charging circuit integrated with a communication interface and its control method

Abstract

The present invention discloses a linear charging circuit integrated with a communication interface and a control method thereof, which includes a linear charging module, a communication link module, an overvoltage protection module REG, a power supply selection module CMP1, and a general circuit module. The input end of the linear charging module, the input end of the communication link module, and the input end of the overvoltage protection module REG are connected to an input signal VIN. The output end of the linear charging module is connected to a battery terminal BAT and a first input end of the power supply selection module CMP1. The output end of the overvoltage protection module REG is connected to a second input end of the power supply selection module CMP1 and generates a signal VIN_REG. The output end of the power supply selection module CMP1 is connected to the general circuit module to provide a power supply AVCC for the general circuit module. The present invention effectively solves the problems of leakage, logic dead zone, and oscillation existing in the traditional dual-power circuit system, and improves the stability and reliability of the system.

Description

Technical Field

[0001] The present invention relates to a linear charging circuit and its control method, in particular to a linear charging circuit integrated with a communication interface and its control method, belonging to the technical field of semiconductor integrated circuits. Background Art

[0002] The linear charging circuit is a circuit design widely used in battery charging management. It adjusts the output voltage and current by regulating the conduction degree (impedance) of internal transistors, thereby achieving safe and stable constant voltage / constant current charging for the battery. It has the advantages of simple structure, low cost, and easy control. At present, the linear charging circuit has been relatively mature in technology. In the application field, allowing data exchange with external devices, such as status reports, fault diagnosis, etc., and real-time detection of the battery status and timely adjustment of charging parameters through the MCU host have gradually become the customer application trend. Therefore, it is necessary to design a linear charging circuit integrated with a communication interface. Summary of the Invention

[0003] The technical problem to be solved by the present invention is to provide a linear charging circuit integrated with a communication interface and its control method, which realizes the dual functions of charging and communication of the circuit under different voltage conditions.

[0004] To solve the above technical problem, the technical solution adopted by the present invention is:

[0005] A linear charging circuit integrated with a communication interface includes a linear charging module, a communication link module, an overvoltage protection module REG, a power supply selection module CMP1, and a general circuit module. The input end of the linear charging module, the input end of the communication link module, and the input end of the overvoltage protection module REG are connected to the input signal VIN. The output end of the linear charging module is connected to the battery terminal BAT and the first input end of the power supply selection module CMP1. The output end of the overvoltage protection module REG is connected to the second input end of the power supply selection module CMP1 and generates the signal VIN_REG. The output end of the power supply selection module CMP1 is connected to the general circuit module to provide the power supply AVCC for the general circuit module.

[0006] Further, the linear charging module includes a high-voltage-resistant NMOS transistor M1 and a high-voltage-resistant NMOS transistor M2. The drain of the high-voltage-resistant NMOS transistor M1 serves as the input end of the linear charging module. The source of the high-voltage-resistant NMOS transistor M1 is connected to the drain of the high-voltage-resistant NMOS transistor M2. The source of the high-voltage-resistant NMOS transistor M2 serves as the output end of the linear charging module. The gates of the high-voltage-resistant NMOS transistor M1 and the high-voltage-resistant NMOS transistor M2 are connected to the control signal ctl1.

[0007] Further, the communication link module includes a high-voltage-resistant NMOS transistor M3. The drain of the high-voltage-resistant NMOS transistor M3 serves as the input end of the communication link module, the source of the high-voltage-resistant NMOS transistor M3 serves as the output end of the communication link module, and the gate of the high-voltage-resistant NMOS transistor M3 is connected to a control signal ctl2. The control signal ctl1 and the control signal ctl2 are reverse signals.

[0008] Further, the control signals ctl1 and ctl2 are generated by a first control signal circuit. The first control signal circuit includes a comparator CMP2 and an inverter INV1. The first input end of the comparator CMP2 is connected to an input signal VIN, the second input end of the comparator CMP2 is connected to a reference voltage REF1, the output end of the comparator CMP2 is connected to the input end of the inverter INV1 and generates the control signal ctl1, and the output end of the inverter INV1 generates the control signal ctl2.

[0009] Further, the overvoltage protection module REG includes a resistor R1, a resistor R2, a resistor R3, a resistor R4, a resistor R5, an NMOS transistor M4, a PMOS transistor M5, an NMOS transistor M6, an NMOS transistor M7, and a reverse-biased PN junction D1. One end of the resistor R1, one end of the resistor R2, the source of the PMOS transistor M6, and one end of the resistor R3 are connected to an input signal VIN as the input end of the overvoltage protection module REG. The other end of the resistor R1 is connected to the cathode of the reverse-biased PN junction D1 and the gate of the NMOS transistor M4. The other end of the resistor R2 is connected to the drain of the NMOS transistor M4. The source of the NMOS transistor M4 is connected to one end of the resistor R4 and the drain of the PMOS transistor M5 and serves as the output end of the overvoltage protection module REG to generate a signal VIN_REG. The other end of the resistor R4 is connected to the drain and the gate of the NMOS transistor M6 and generates a bias voltage BIAS. The other end of the resistor R3 is connected to the gate of the PMOS transistor M5 and one end of the resistor R5. The other end of the resistor R5 is connected to one end of the NMOS transistor M7. The gate of the NMOS transistor M7 is connected to a control signal OVP. The anode of the reverse-biased PN junction D1, the source of the NMOS transistor M6, and the source of the NMOS transistor M7 are grounded.

[0010] Further, the control signal OVP is generated by a second control signal circuit. The second control signal circuit includes a comparator CMP3 and an inverter INV4. The first input end of the comparator CMP3 is connected to an input signal VIN, the second input end of the comparator CMP3 is connected to a reference voltage REF2, the output end of the comparator CMP3 is connected to the input end of the inverter INV4, and the output end of the inverter INV4 generates the control signal OVP.

[0011] Further, the power supply selection module CMP1 includes a PMOS transistor M8, a PMOS transistor M9, an NMOS transistor M10, an NMOS transistor M11, an NMOS transistor M12, an NMOS transistor M13, an NMOS transistor M14, a PMOS transistor M5, a Schmitt trigger SMIT1, an inverter INV2, and an inverter INV3. The source of the PMOS transistor M8 is connected to the signal VIN_REG, the source of the MOS transistor M9 is connected to the battery terminal BAT, the gate of the PMOS transistor M8 is connected to the drain of the PMOS transistor M8, the drain of the NMOS transistor M10, and the gate of the PMOS transistor M9. The gates of the NMOS transistor M10, the NMOS transistor M11, and the NMOS transistor M13 are connected to the bias voltage BIAS. The sources of the NMOS transistor M10, the NMOS transistor M11, and the NMOS transistor M13 are grounded. The source of the PMOS transistor M9 is connected to the power supply terminal BAT. The drain of the PMOS transistor M9 is connected to the drain of the NMOS transistor M11, the drain of the NMOS transistor M12, and the input terminal of the Schmitt trigger SMIT1. The output terminal of the Schmitt trigger SMIT1 is connected to the input terminal of the inverter INV2 and the gate of the NMOS transistor M12. The source of the NMOS transistor M12 is connected to the drain of the NMOS transistor M13. The output terminal of the inverter INV2 is connected to the input terminal of the inverter INV3 and the gate of the PMOS transistor M15. The output terminal of the inverter INV3 is connected to the gate of the NMOS transistor M14. The drain of the NMOS transistor M14 is connected to the battery terminal BAT. The source of the NMOS transistor M14 is connected to the source of the PMOS transistor M15 and serves as the output terminal of the power supply selection module CMP1 to generate the power supply AVCC. The drain of the PMOS transistor M15 is connected to the signal VIN_REG.

[0012] A control method for a linear charging circuit with an integrated communication interface includes the following steps:

[0013] The reference voltage REF1 is equal to the voltage of the battery terminal BAT;

[0014] When the voltage of the input signal VIN is less than the reference voltage REF1, the output of the comparator CMP2 in the first control signal circuit is at a low level. At this time, the control signal ctl1 is at a low level, and the control signal ctl2 is at a high level. Then the linear charging module is turned off, and the communication link module is turned on. At this time, the linear charging circuit can exchange data with an external device or a main control unit through the communication link module. At the same time, the control signal OVP in the second control signal circuit is at a high level. Then the NMOS transistor M7 in the overvoltage protection module REG is turned on, the gate of the PMOS transistor M5 is at a low level, the PMOS transistor M5 is turned on, and the voltage of the signal VIN_REG is equal to the input signal VIN. At this time, the voltage of the signal VIN_REG is lower than the voltage of the battery terminal BAT, and the power supply AVCC at the output terminal of the power supply selection module CMP1 is equal to the voltage of the battery terminal BAT;

[0015] When the voltage of the input signal VIN is greater than the reference voltage REF1 and less than the reference voltage REF2, the comparator CMP2 in the first control signal circuit outputs a high level. At this time, the control signal ctl1 is at a high level and the control signal ctl2 is at a low level. Then the linear charging module is turned on and the communication link module is turned off. At the same time, the control signal OVP in the second control signal circuit is at a high level, so the NMOS transistor M7 in the overvoltage protection module REG is turned on, the gate of the PMOS transistor M5 is at a low level, the PMOS transistor M5 is turned on, and the voltage of the signal VIN_REG is equal to the input signal VIN. At this time, the voltage of the signal VIN_REG is higher than or equal to the voltage of the battery terminal BAT, and the power supply AVCC at the output end of the power supply selection module CMP1 is equal to the voltage of the input signal VIN;

[0016] When the voltage of the input signal VIN is greater than the reference voltage REF2, the control signal OVP in the second control signal circuit is at a low level. Then the NMOS transistor M7 in the overvoltage protection module REG is turned off, the gate of the PMOS transistor M5 is at a high level, the PMOS transistor M5 is turned off, and the voltage of the signal VIN_REG is equal to 0. At this time, the reverse-biased PN junction D1 in the overvoltage protection module REG conducts, the gate of the NMOS transistor M4 is at a low level, the NMOS transistor M4 is turned off, so the bias voltage BIAS is 0, and the power supply selection module CMP1 does not work.

[0017] Compared with the prior art, the present invention has the following advantages and effects: The present invention provides an integrated communication interface linear charging circuit and its control method, which effectively solves the problems of leakage, logic dead zone and oscillation existing in the traditional dual-power circuit system, and improves the stability and reliability of the system; at the same time, the design of multiplexing the VIN port further simplifies the circuit structure and improves the overall integration level and efficiency. Brief Description of the Drawings

[0018] Figure 1 It is a schematic diagram of an integrated communication interface linear charging circuit of the present invention.

[0019] Figure 2 It is a schematic diagram of the overvoltage protection module REG of the present invention.

[0020] Figure 3 It is a schematic diagram of the power supply selection module CMP1 of the present invention.

[0021] Figure 4 It is a schematic diagram of the first control signal circuit of the present invention.

[0022] Figure 5 It is a schematic diagram of the second control signal circuit of the present invention. Detailed Embodiment

[0023] In order to elaborate in detail on the technical solutions adopted by the present invention to achieve the predetermined technical objectives, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only partial embodiments of the present invention, rather than all embodiments. Moreover, without creative efforts, the technical means or technical features in the embodiments of the present invention can be replaced. The present invention will be described in detail below with reference to the drawings and in conjunction with the embodiments.

[0024] As Figure 1 shown, a linear charging circuit with an integrated communication interface according to the present invention includes a linear charging module, a communication link module, an overvoltage protection module REG, a power supply selection module CMP1, and a general circuit module. The input end of the linear charging module, the input end of the communication link module, and the input end of the overvoltage protection module REG are connected to the input signal VIN. The output end of the linear charging module is connected to the battery terminal BAT and the first input end of the power supply selection module CMP1. The output end of the overvoltage protection module REG is connected to the second input end of the power supply selection module CMP1 and generates the signal VIN_REG. The output end of the power supply selection module CMP1 is connected to the general circuit module to provide the power supply AVCC for the general circuit module.

[0025] The linear charging module includes a high-voltage-resistant NMOS transistor M1 and a high-voltage-resistant NMOS transistor M2. The drain of the high-voltage-resistant NMOS transistor M1 serves as the input end of the linear charging module. The source of the high-voltage-resistant NMOS transistor M1 is connected to the drain of the high-voltage-resistant NMOS transistor M2. The source of the high-voltage-resistant NMOS transistor M2 serves as the output end of the linear charging module. The gates of the high-voltage-resistant NMOS transistor M1 and the high-voltage-resistant NMOS transistor M2 are connected to the control signal ctl1.

[0026] The communication link module includes a high-voltage-resistant NMOS transistor M3. The drain of the high-voltage-resistant NMOS transistor M3 serves as the input end of the communication link module. The source of the high-voltage-resistant NMOS transistor M3 serves as the output end of the communication link module. The gate of the high-voltage-resistant NMOS transistor M3 is connected to the control signal ctl2, and the control signal ctl1 and the control signal ctl2 are reverse signals.

[0027] As Figure 4 shown, the control signal ctl1 and the control signal ctl2 are generated by a first control signal circuit. The first control signal circuit includes a comparator CMP2 and an inverter INV1. The first input end of the comparator CMP2 is connected to the input signal VIN. The second input end of the comparator CMP2 is connected to the reference voltage REF1. The output end of the comparator CMP2 is connected to the input end of the inverter INV1 and generates the control signal ctl1. The output end of the inverter INV1 generates the control signal ctl2.

[0028] As Figure 2As shown in the figure, the overvoltage protection module REG includes resistor R1, resistor R2, resistor R3, resistor R4, resistor R5, NMOS transistor M4, PMOS transistor M5, NMOS transistor M6, NMOS transistor M7, and reverse-biased PN junction D1. One end of resistor R1, one end of resistor R2, the source of PMOS transistor M6, and one end of resistor R3 are connected to the input signal VIN as the input terminal of the overvoltage protection module REG. The other end of resistor R1 is connected to the cathode of reverse-biased PN junction D1 and the gate of NMOS transistor M4. The other end of resistor R2 is connected to the drain of NMOS transistor M4. The source of NMOS transistor M4 is connected to one end of resistor R4 and the drain of PMOS transistor M5 and serves as the output terminal of the overvoltage protection module REG to generate the signal VIN_REG. The other end of resistor R4 is connected to the drain and gate of NMOS transistor M6 to generate the bias voltage BIAS. The other end of resistor R3 is connected to the gate of PMOS transistor M5 and one end of resistor R5. The other end of resistor R5 is connected to one end of NMOS transistor M7. The gate of NMOS transistor M7 is connected to the control signal OVP. The anode of reverse-biased PN junction D1, the source of NMOS transistor M6, and the source of NMOS transistor M7 are grounded. The resistance values of resistors R2 and R4 are relatively large. When NMOS transistor M4 is in the on state, the maximum current passing through NMOS transistor M6 is (VIN - GND) / (R2 + R4), which is ensured to be less than 1 μA during design. This current always remains in the on state and provides the bias voltage BIAS. The maximum bias current of the comparator is set to a 1 μA constant current source to ensure that even when a suitable power supply is not selected, the comparator can maintain the basic working state and avoid logic dead zones and oscillation problems.

[0029] As Figure 5 shown in the figure, the control signal OVP is generated by the second control signal circuit. The second control signal circuit includes comparator CMP3 and inverter INV4. The first input terminal of comparator CMP3 is connected to the input signal VIN. The second input terminal of comparator CMP3 is connected to the reference voltage REF2. The output terminal of comparator CMP3 is connected to the input terminal of inverter INV4. The output terminal of inverter INV4 generates the control signal OVP.

[0030] As Figure 3As shown in the figure, the power supply selection module CMP1 includes PMOS transistor M8, PMOS transistor M9, NMOS transistor M10, NMOS transistor M11, NMOS transistor M12, NMOS transistor M13, NMOS transistor M14, PMOS transistor M5, Schmitt trigger SMIT1, inverter INV2 and inverter INV3. The source of PMOS transistor M8 is connected to signal VIN_REG, the source of MOS transistor M9 is connected to battery terminal BAT. The gate of PMOS transistor M8 is connected to the drain of PMOS transistor M8, the drain of NMOS transistor M10 and the gate of PMOS transistor M9. The gates of NMOS transistor M10, NMOS transistor M11 and NMOS transistor M13 are connected to bias voltage BIAS. The sources of NMOS transistor M10, NMOS transistor M11 and NMOS transistor M13 are grounded. The source of PMOS transistor M9 is connected to power supply terminal BAT. The drain of PMOS transistor M9 is connected to the drain of NMOS transistor M11, the drain of NMOS transistor M12 and the input terminal of Schmitt trigger SMIT1. The output terminal of Schmitt trigger SMIT1 is connected to the input terminal of inverter INV2 and the gate of NMOS transistor M12. The source of NMOS transistor M12 is connected to the drain of NMOS transistor M13. The output terminal of inverter INV2 is connected to the input terminal of inverter INV3 and the gate of PMOS transistor M15. The output terminal of inverter INV3 is connected to the gate of NMOS transistor M14. The drain of NMOS transistor M14 is connected to battery terminal BAT. The source of NMOS transistor M14 is connected to the source of PMOS transistor M15 and serves as the output terminal of power supply selection module CMP1 to generate power supply AVCC. The drain of PMOS transistor M15 is connected to signal VIN_REG. The present invention adopts power supply selection module CMP1 to avoid the leakage problem caused by the high impedance state of the power supply when the system is not enabled. NMOS transistor M12, NMOS transistor M13 and Schmitt trigger SMIT1 jointly form a voltage hysteresis function to prevent the comparator from generating oscillating output when the input voltage is close. The logic signal after Schmitt trigger SMIT1 is cascaded with inverters to enhance the driving ability to turn on NMOS transistor M14 or PMOS transistor M15, thus realizing the function of selecting a higher voltage. This design ensures the stability and reliability of the power supply selection and avoids unnecessary repeated switching caused by input voltage fluctuations.

[0031] A linear charging circuit with an integrated communication interface reduces the required number of ports, improves the overall integration and efficiency of the chip, and solves the common leakage problem in traditional dual-power circuit systems through the design of multiplexing the VIN port. In traditional dual-power circuits, a comparator is usually required to select a suitable power supply. However, the comparator itself also needs current to provide bias. When the appropriate power supply is not selected, the comparator may not work properly, easily forming a logic dead zone or generating an oscillating output. In contrast, the power supply comparison and selection module in the present invention can ensure that the power supply does not enter the high-impedance state when the system is not enabled, thus avoiding the leakage problem caused thereby. A current-mode comparator is used to distinguish the voltage levels of the VIN_REG and BAT terminals, and a Schmitt trigger is used to form a voltage hysteresis function to prevent oscillating output when the input voltages are close. The driving ability of the logic signal is enhanced by cascading inverters to turn on M14 or M15, ensuring that the higher voltage can be correctly selected as the power supply.

[0032] A control method for a linear charging circuit with an integrated communication interface includes the following steps:

[0033] The reference voltage REF1 is equal to the voltage of the battery terminal BAT.

[0034] When the voltage of the input signal VIN is less than the reference voltage REF1, the output of the comparator CMP2 in the first control signal circuit is at a low level. At this time, the control signal ctl1 is at a low level and the control signal ctl2 is at a high level. Then the linear charging module is turned off and the communication link module is turned on. At this time, the linear charging circuit can exchange data with external devices or the main control unit through the communication link module. At the same time, the control signal OVP in the second control signal circuit is at a high level, then the NMOS transistor M7 in the overvoltage protection module REG is turned on, the gate of the PMOS transistor M5 is at a low level, the PMOS transistor M5 is turned on, and the voltage of the signal VIN_REG is equal to the input signal VIN. At this time, the voltage of the signal VIN_REG is lower than the voltage of the battery terminal BAT, and the power supply AVCC at the output end of the power supply selection module CMP1 is equal to the voltage of the battery terminal BAT.

[0035] When the voltage of the input signal VIN is greater than the reference voltage REF1 and less than the reference voltage REF2, the comparator CMP2 in the first control signal circuit outputs a high level. At this time, the control signal ctl1 is at a high level and the control signal ctl2 is at a low level. Then the linear charging module is turned on and the communication link module is turned off. At the same time, the control signal OVP in the second control signal circuit is at a high level, so the NMOS transistor M7 in the overvoltage protection module REG is turned on, the gate of the PMOS transistor M5 is at a low level, the PMOS transistor M5 is turned on, and the voltage of the signal VIN_REG is equal to the input signal VIN. At this time, the voltage of the signal VIN_REG is higher than or equal to the voltage of the battery terminal BAT, and the power supply AVCC at the output terminal of the power supply selection module CMP1 is equal to the voltage of the input signal VIN.

[0036] When the voltage of the input signal VIN is greater than the reference voltage REF2, the control signal OVP in the second control signal circuit is at a low level, so the NMOS transistor M7 in the overvoltage protection module REG is turned off, the gate of the PMOS transistor M5 is at a high level, the PMOS transistor M5 is turned off, and the voltage of the signal VIN_REG is equal to 0. At this time, the reverse-biased PN junction D1 in the overvoltage protection module REG conducts, the gate of the NMOS transistor M4 is at a low level, and the NMOS transistor M4 is turned off, so the bias voltage BIAS is 0, the power supply selection module CMP1 does not work, and the bias voltage BIAS also provides a bias voltage for the comparators in the first control signal circuit and the second control signal circuit. In this state, the two control signal circuits do not work either, and the two loops of the corresponding linear charging module and communication link module do not work.

[0037] The present invention provides an integrated communication interface linear charging circuit and its control method, which effectively solves the problems of leakage, logic dead zone and oscillation existing in the traditional dual-power circuit system, and improves the stability and reliability of the system; at the same time, the design of multiplexing the VIN port further simplifies the circuit structure and improves the overall integration and efficiency.

[0038] The above are only the preferred embodiments of the present invention, and do not impose any form of limitation on the present invention. Although the present invention has been disclosed above with the preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make some changes or modifications to the above-disclosed technical content to make equivalent embodiments with equivalent changes within the scope of the technical solution of the present invention. However, as long as it does not depart from the content of the technical solution of the present invention, any simple modification, equivalent replacement and improvement made to the above embodiments according to the technical essence of the present invention within the spirit and principle of the present invention still fall within the protection scope of the technical solution of the present invention.

Claims

1. A linear charging circuit with an integrated communication interface, characterized in that: It includes a linear charging module, a communication link module, an overvoltage protection module REG, a power supply selection module CMP1 and a general circuit module. The input end of the linear charging module, the input end of the communication link module and the input end of the overvoltage protection module REG are connected to the input signal VIN. The output end of the linear charging module is connected to the battery end BAT and the first input end of the power supply selection module CMP1. The output end of the overvoltage protection module REG is connected to the second input end of the power supply selection module CMP1 and generates a signal VIN_REG. The output end of the power supply selection module CMP1 is connected to the general circuit module to provide power AVCC for the general circuit module. The linear charging module comprises a high-voltage resistant NMOS tube M1 and a high-voltage resistant NMOS tube M2, the drain of the high-voltage resistant NMOS tube M1 serves as the input end of the linear charging module, the source of the high-voltage resistant NMOS tube M1 is connected to the drain of the high-voltage resistant NMOS tube M2, the source of the high-voltage resistant NMOS tube M2 serves as the output end of the linear charging module, and the gate of the high-voltage resistant NMOS tube M1 and the gate of the high-voltage resistant NMOS tube M2 are connected to the control signal ctl1; the communication link module comprises a high-voltage resistant NMOS tube M3, the drain of the high-voltage resistant NMOS tube M3 serves as the input end of the communication link module, and the high-voltage resistant NMOS tube M3 The source of is used as the output end of the communication link module, the gate of the high-voltage NMOS tube M3 is connected to the control signal ctl2, and the control signal ctl1 and the control signal ctl2 are inverse signals; the control signal ctl1 and the control signal ctl2 are generated by a first control signal circuit, and the first control signal circuit includes a comparator CMP2 and an inverter INV1, a first input end of the comparator CMP2 is connected to the input signal VIN, a second input end of the comparator CMP2 is connected to the reference voltage REF1, an output end of the comparator CMP2 is connected to the input end of the inverter INV1 and generates the control signal ctl1, and the inverter IN The output end of V1 generates a control signal ctl2; the overvoltage protection module REG includes a resistor R1, a resistor R2, a resistor R3, a resistor R4, a resistor R5, an NMOS tube M4, a PMOS tube M5, an NMOS tube M6, an NMOS tube M7 and a reverse biased PN junction D1, one end of the resistor R1 and one end of the resistor R2, the source of the PMOS tube M5 and one end of the resistor R3 are connected to the input signal VIN as the input end of the overvoltage protection module REG, the other end of the resistor R1 is connected to the cathode of the reverse biased PN junction D1 and the gate of the NMOS tube M4, and the other end of the resistor R2 is connected to the drain of the NMOS tube M4. The source of the NMOS tube M4 is connected to one end of the resistor R4 and the drain of the PMOS tube M5 and serves as the output end of the overvoltage protection module REG to generate a signal VIN_REG. The other end of the resistor R4 is connected to the drain of the NMOS tube M6 and the gate of the NMOS tube M6 to generate a bias voltage BIAS. The other end of the resistor R3 is connected to the gate of the PMOS tube M5 and one end of the resistor R5. The other end of the resistor R5 is connected to one end of the NMOS tube M7. The gate of the NMOS tube M7 is connected to the control signal OVP. The anode of the reverse biased PN junction D1, the source of the NMOS tube M6 and the source of the NMOS tube M7 are grounded. The power supply selection module CMP1 includes a PMOS tube M8, a PMOS tube M9, an NMOS tube M10, an NMOS tube M11, an NMOS tube M12, an NMOS tube M13, an NMOS tube M14, a PMOS tube M5, a Schmitt trigger SMIT1, an inverter INV2 and an inverter INV3, the source of the PMOS tube M8 is connected to the signal VIN_REG, the source of the MOS tube M9 is connected to the battery terminal BAT, the gate of the PMOS tube M8 is connected to the drain of the PMOS tube M8, the drain of the NMOS tube M10 and the gate of the PMOS tube M9, the gate of the NMOS tube M10, the gate of the NMOS tube M11 and the gate of the NMOS tube M13 are connected to the bias voltage BIAS, the source of the NMOS tube M10, the source of the NMOS tube M11 and the source of the NMOS tube M13 are grounded, and the The source is connected to the power supply terminal BAT, the drain of the PMOS tube M9 is connected to the drain of the NMOS tube M11, the drain of the NMOS tube M12 and the input terminal of the Schmitt trigger SMIT1, the output terminal of the Schmitt trigger SMIT1 is connected to the input terminal of the inverter INV2 and the gate of the NMOS tube M12, the source of the NMOS tube M12 is connected to the drain of the NMOS tube M13, the output terminal of the inverter INV2 is connected to the input terminal of the inverter INV3 and the gate of the PMOS tube M15, the output terminal of the inverter INV3 is connected to the gate of the NMOS tube M14, the drain of the NMOS tube M14 is connected to the battery terminal BAT, the source of the NMOS tube M14 is connected to the source of the PMOS tube M15 and serves as the output terminal of the power supply selection module CMP1 to generate the power supply AVCC, and the drain of the PMOS tube M15 is connected to the signal VIN_REG.

2. The linear charging circuit with integrated communication interface according to claim 1, characterized in that: The control signal OVP is generated by a second control signal circuit, which includes a comparator CMP3 and an inverter INV4. The first input terminal of the comparator CMP3 is connected to the input signal VIN, the second input terminal of the comparator CMP3 is connected to the reference voltage REF2, the output terminal of the comparator CMP3 is connected to the input terminal of the inverter INV4, and the output terminal of the inverter INV4 generates the control signal OVP.

3. A control method for a linear charging circuit with an integrated communication interface according to any one of claims 1 to 2, characterized in that The following steps are involved: The reference voltage REF1 is equal to the battery terminal BAT voltage; When the voltage of the input signal VIN is less than the reference voltage REF1, the output of the comparator CMP2 in the first control signal circuit is low level, at this time the control signal ctl1 is low level, the control signal ctl2 is high level, then the linear charging module is turned off, the communication link module is turned on, and at this time the linear charging circuit can exchange data with the external device or the main control unit through the communication link module; at the same time, the control signal OVP in the second control signal circuit is high level, then the NMOS tube M7 in the overvoltage protection module REG is turned on, the gate of the PMOS tube M5 is low level, the PMOS tube M5 is turned on, the signal VIN_REG voltage is equal to the input signal VIN, at this time the signal VIN_REG voltage is lower than the battery terminal BAT voltage, and the power supply AVCC at the output end of the power supply selection module CMP1 is equal to the battery terminal BAT voltage; When the voltage of the input signal VIN is greater than the reference voltage REF1 and less than the reference voltage REF2, the output of the comparator CMP2 in the first control signal circuit is high level, at this time the control signal ctl1 is high level, the control signal ctl2 is low level, then the linear charging module is turned on, the communication link module is turned off, and at the same time the control signal OVP in the second control signal circuit is high level, then the NMOS tube M7 in the overvoltage protection module REG is turned on, the gate of the PMOS tube M5 is low level, the PMOS tube M5 is turned on, the signal VIN_REG voltage is equal to the input signal VIN, at this time the signal VIN_REG voltage is higher than or equal to the battery terminal BAT voltage, the power supply AVCC at the output end of the power supply selection module CMP1 is equal to the input signal VIN voltage; When the voltage of the input signal VIN is greater than the reference voltage REF2, the control signal OVP in the second control signal circuit is at a low level, the NMOS tube M7 in the overvoltage protection module REG is turned off, the gate of the PMOS tube M5 is at a high level, the PMOS tube M5 is turned off, and the voltage of the signal VIN_REG is equal to 0. At this time, the reverse biased PN junction D1 in the overvoltage protection module REG is turned on, the gate of the NMOS tube M4 is at a low level, the NMOS tube M4 is turned off, the bias voltage BIAS is 0, and the power supply selection module CMP1 does not work.

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