An anti-series bidirectional constant current source clamping circuit, an AC SSPC and a control method

Abstract

The present invention discloses an anti-series bidirectional constant current source clamping circuit, an AC SSPC and a control method. The clamping circuit adopts a symmetrical structure and includes an upper power transistor, a lower power transistor, a first negative feedback resistor and a second negative feedback resistor. The drain of the upper power transistor is connected to the power output terminal of the AC solid state power controller. The source of the upper power transistor is connected to one end of the first negative feedback resistor. The drain of the lower power transistor is connected to the power ground of the AC solid state power controller. The source of the lower power transistor is connected to one end of the second negative feedback resistor. The other ends of the first negative feedback resistor and the second negative feedback resistor are connected to each other and then connected to the same analog ground. The gates of the upper power transistor and the lower power transistor are connected to each other and then connected to the same control command. The clamping circuit of the present invention not only provides a path for the leakage current, but also greatly reduces the equivalent resistance on the load side, and realizes the constant current discharge of the capacitive load while reducing the voltage on the load side.

Description

Technical Field

[0001] The present invention relates to an anti-series bidirectional constant current source clamping circuit, an AC SSPC and a control method, belonging to the technical fields of power electronics and electrical engineering. Background Art

[0002] A solid state power controller (SSPC) uses power semiconductor devices as switches, integrating the switch control function of a relay and the protection function of a circuit breaker. It has advantages such as fast response, no arc, no mechanical contacts, low conduction power consumption, strong load adaptability, and high reliability, and is the key core of an advanced solid state power distribution system.

[0003] In an aerospace solid state power distribution system, in the no-load condition of an AC SSPC, due to the equivalent resistance on the load side being much larger than the equivalent resistance in the off state of the AC SSPC, the existence of leakage current will cause a "virtual voltage" phenomenon close to the power supply voltage on the load side. In addition, when an AC SSPC is connected to a capacitive load, in the off state, the leakage current will continuously charge the load side, resulting in continuous accumulation of the load side voltage. With the increase of the system voltage level, the above problems will be further aggravated, posing a serious threat to the normal operation of the system and personnel safety. Therefore, in-depth research on the clamping circuit of the AC SSPC has important theoretical significance and engineering value.

[0004] The conventional solution is to connect a discharging resistor in parallel on the load side. When the AC SSPC is turned off, the discharging resistor is incorporated into the load side to work, and the energy of the load capacitor is consumed on the discharging resistor. In terms of discharge safety and stability, there is a current spike at the initial discharge of this scheme, and then the discharge current decays exponentially, with relatively low safety and stability during the discharge process; in terms of the magnitude of the clamping voltage, the parallel discharging resistor scheme will finally clamp the load side voltage below 3V, and the clamping voltage is relatively high; in terms of the discharge time, the discharge time of the parallel discharging resistor is above 100ms, and the discharge time is relatively long; in terms of volume and weight, since the energy is consumed on the discharging resistor, the volume of this resistor is relatively large, resulting in a relatively large overall volume and weight of the power device.

[0005] In order to further reduce the clamping voltage and discharge time and improve the safety during the discharge process, it is necessary to further optimize the clamping circuit of the AC SSPC. Summary of the Invention

[0006] The technical problem to be solved by the present invention is, aiming at the defects and deficiencies in the foregoing background, to provide an anti-series bidirectional constant current source clamping circuit, an AC SSPC and a control method, which can not only clamp the load voltage below 1V, but also provide an energy release channel for the load capacitor, and achieve controllable energy release time, and the discharge time can be controlled within 10ms.

[0007] To solve the above technical problems, an embodiment of the present application first provides an anti-series bidirectional constant current source clamping circuit, which is applied to an AC solid-state power controller. The clamping circuit is characterized in that it is connected in parallel between the power output terminal and the power ground of the AC solid-state power controller. The clamping circuit adopts a symmetric structure and includes an upper power transistor, a lower power transistor, a first negative feedback resistor, and a second negative feedback resistor. The drain of the upper power transistor is connected to the power output terminal of the AC solid-state power controller. The source of the upper power transistor is connected to one end of the first negative feedback resistor. The drain of the lower power transistor is connected to the power ground of the AC solid-state power controller. The source of the lower power transistor is connected to one end of the second negative feedback resistor. The other ends of the first negative feedback resistor and the second negative feedback resistor are connected to the same analog ground after being connected to each other. The gates of the upper power transistor and the lower power transistor are connected to the same control instruction after being connected to each other.

[0008] An embodiment of the present application also provides an AC solid-state power controller, which includes a main power circuit, a clamping circuit, and a clamping circuit control logic circuit. The clamping circuit is characterized in that it is connected in parallel between the power output terminal and the power ground of the AC solid-state power controller. The clamping circuit adopts a symmetric structure and includes an upper power transistor, a lower power transistor, a first negative feedback resistor, and a second negative feedback resistor. The source of the upper power transistor is connected to one end of the first negative feedback resistor. The source of the lower power transistor is connected to one end of the second negative feedback resistor. The other ends of the first negative feedback resistor and the second negative feedback resistor are connected to the same analog ground after being connected to each other. The gates of the upper power transistor and the lower power transistor are connected to the same control instruction output by the clamping circuit control logic circuit after being connected to each other.

[0009] Preferably, the main power circuit includes a first power transistor and a second power transistor connected in anti-series. The drain of the first power transistor is connected to an AC power supply as the power input terminal of the AC solid-state power controller. The drain of the second power transistor is connected to the clamping circuit and the load as the power output terminal of the AC solid-state power controller. The gate of the first power transistor and the source of the second power transistor are connected to the same analog ground. The gates of the first power transistor and the second power transistor are connected to different switching instructions.

[0010] Preferably, the clamping circuit control logic circuit includes a NOR gate, an OR gate, and an RS flip-flop. The two input terminals of the NOR gate are respectively connected to the switching instructions of the first power transistor and the second power transistor. The four input terminals of the OR gate are respectively connected to the switching instructions of the first power transistor and the second power transistor, and the positive and negative logic signals of the load current direction. The output terminal of the NOR gate is connected to the terminal of the RS flip-flop. The output terminal of the OR gate is connected to the terminal of the RS flip-flop. The Output the control instruction at the end.

[0011] The embodiment of the present application also provides a control method for the above-mentioned AC solid-state power controller, which is characterized by including:

[0012] When the AC solid-state power controller is turned on: in the positive half-cycle of the AC power supply voltage, first turn on the second power transistor, and then turn on the first power transistor after the voltage passes through the zero point, and turn off the upper power transistor and the lower power transistor; in the negative half-cycle of the AC power supply voltage, first turn on the first power transistor, and then turn on the second power transistor after the voltage passes through the zero point, and turn off the upper power transistor and the lower power transistor;

[0013] When the AC solid-state power controller is turned off: in the positive half-cycle of the load current, first turn off the second power transistor, and then turn off the first power transistor after the current passes through the zero point, and turn on the upper power transistor and the lower power transistor; in the negative half-cycle of the load current, first turn off the first power transistor, and then turn off the second power transistor after the current passes through the zero point, and turn on the upper power transistor and the lower power transistor.

[0014] The present invention has the following beneficial effects:

[0015] 1. The clamping circuit of the present invention can clamp the load terminal voltage of the AC solid-state power controller when it is no-load to within 1V;

[0016] 2. The clamping circuit of the present invention provides an energy release path for capacitive loads, preventing the continuous accumulation of the load-side voltage caused by the existence of leakage current. The capacitive load energy discharge current is stable, without current spikes, and the discharge current and discharge time are controllable. The discharge time is reduced to within 10ms, effectively improving the safety of the AC solid-state power controller;

[0017] 3. In the clamping circuit of the present invention, two MOSFETs share the same turn-on signal, and the control is simple;

[0018] 4. The clamping circuit of the present invention only requires two enhancement-type MOSFETs, and the overall volume of the power devices is small. Description of the Drawings

[0019] Figure 1 is the circuit diagram of the AC SSPC based on the anti-series bidirectional constant-current source clamping circuit;

[0020] Figure 2 is the working mode diagram of the anti-series bidirectional constant-current source clamping circuit;

[0021] Figure 3 is the overall control timing diagram of the AC SSPC based on the anti-series bidirectional constant-current source clamping circuit;

[0022] Figure 4It is the working timing diagram of the anti - series bidirectional constant - current source clamping circuit;

[0023] Figure 5 It is the working circuit diagram under the condition that the load is no - load and the SSPC is in the steady - state off state;

[0024] Figure 6 It is the working circuit diagram under the condition that the load is capacitive and the SSPC is in the steady - state off state;

[0025] Figure 7 It is the control logic circuit diagram of the clamping circuit. Specific implementation mode

[0026] To make the purpose, technical solution and advantages of the present invention clearer, the present invention will be further described in detail below with reference to the drawings and embodiments.

[0027] Embodiment 1

[0028] This embodiment provides an anti - series bidirectional constant - current source clamping circuit, and provides an AC solid - state power controller based on the anti - series bidirectional constant - current source clamping circuit.

[0029] As Figure 1 shown, the anti - series bidirectional constant - current source clamping circuit of this embodiment is connected in parallel between the power output terminal Powerout and the power ground PGND of the AC solid - state power controller. The clamping circuit adopts a symmetrical structure, including the upper power transistor S aux1 , the lower power transistor S aux2 , the first negative - feedback resistor R 1, the second negative - feedback resistor R 2. The drain of the upper power transistor S aux1 is connected to the power output terminal of the AC solid - state power controller Powerout, The source of the upper power transistor S aux1 is connected to one end of the first negative - feedback resistor R 1. The drain of the lower power transistor S aux2 is connected to the power ground of the AC solid - state power controller PGND, The source of the lower power transistor S aux2 is connected to one end of the second negative - feedback resistor R 2. The other end of the first negative - feedback resistor R is connected to the other end of the second negative - feedback resistor R and then connected to the same analog ground AGND 2. The gates of the upper power transistor S aux1 , the lower power transistor S aux2 are connected together and then connected to the same control instruction CMD aux . Among them, the upper power transistor S aux1 , the lower power transistor S aux2All are enhancement-mode MOSFETs.

[0030] As Figure 1 shown, the AC SSPC of the anti-series bidirectional constant-current source clamping circuit in this embodiment consists of an AC power supply V S , an AC SSPC power circuit, and a load. Among them, the AC power supply is a 115V AC source, and the load is composed of a resistor and a capacitor in parallel. The AC SSPC power circuit includes a main power circuit, the above-mentioned anti-series bidirectional constant-current source clamping circuit, and Figure 7 the clamping circuit control logic circuit shown.

[0031] The main power circuit of the AC SSPC is composed of two identical N-channel enhancement-mode Si MOSFETs, the first power transistor S upp and the second power transistor S low , connected in anti-series. The drain of the first power transistor S upp is used as the power input terminal of the AC solid-state power controller to connect to the AC power supply, and the drain of the second power transistor S low is used as the power output terminal of the AC solid-state power controller to connect to the clamping circuit and the load. The gate of the first power transistor S upp , and the source of the second power transistor S low are connected to the same analog ground AGND1. The gate of the first power transistor S upp is connected to the first switch command CMD upp , and the gate of the second power transistor S low is connected to the second switch command CMD low .

[0032] As Figure 7 shown, the clamping circuit control logic circuit of this embodiment includes an OR-NOT gate OR1, an OR gate OR2, and an RS flip-flop composed of two NAND gates. The two input terminals of the OR-NOT gate OR1 are respectively connected to the first switch command CMD upp , the second switch command CMD low . The four input terminals of the OR gate OR2 are respectively connected to the first switch command CMD upp , the second switch command CMD low , and the positive and negative logic signals I + and I - of the load current direction. I +, I - are respectively logic signals representing the load current direction, and the high level indicates validity. I + indicates that the current direction is from the power input terminal Powerin of the AC SSPC to the power output terminal Powerout . I - indicates the opposite current direction. The output terminal of the OR-NOT gate OR1 is connected to the terminal, the output terminal of OR gate OR2 is connected to the terminal of the RS flip-flop, and the terminal of the RS flip-flop outputs the control instruction CMD of the clamping circuit aux .

[0033] Table 1 Function Table of Clamping Circuit Control Logic Circuit

[0034]

[0035] Figure 2 is the working mode diagram of the anti-series bidirectional constant current source clamping circuit. During the capacitive load energy release stage, according to the direction of the load discharge current, its working mode is divided into two categories: forward constant current discharge and reverse constant current discharge.

[0036] Mode Ⅰ: Forward constant current discharge

[0037] Assume that at the moment when the AC SSPC main power circuit is turned off, the load voltage V load is positive, that is, the power output terminal of the AC solid state power controller Powerout has a higher potential than the power ground PGND , the control instruction CMD of the clamping circuit aux jumps from low level to high level. At this time, the same drive voltage V drv (constantly 14V) is applied between the gates of the upper / lower power transistors and the analog ground AGND 2. When the actual gate-source voltage of the power transistor V GS is greater than the threshold voltage V TH , the discharge current in the circuit gradually increases from zero. Due to the existence of the first negative feedback resistor R 1, as the discharge current increases, the voltage division across the resistor V R1 also increases linearly, and the gate-source voltage aux1 of the upper power transistor S V GS1 decreases, thereby controlling the drain-source current I D1 of the power transistor to decrease. After a certain time, the circuit current reaches a constant value I CCS+ , at this time the upper power transistor S aux1 works in the saturation region and forms a forward constant current source with the first negative feedback resistor R 1; at the same time, due to the existence of the second negative feedback resistor R 2, the gate-source voltage aux2 of the lower power transistor S V GS2 increases, and at this time the lower power transistor Saux2 It is in a fully - conducting state and operates in the variable - resistance region.

[0038] The upper power transistor S aux1 and the first negative - feedback resistor R 1 form a constant - current source I CCS+ , which can be expressed as:

[0039]

[0040] Among them, μ 0 is the electron mobility, C ox is the gate - oxide capacitance per unit area, W is the channel width, L is the effective channel length. When the enhancement - mode MOSFET device is determined, the forward constant current I CCS+ is uniquely determined by the first negative - feedback resistor R 1.

[0041] Mode Ⅱ: Reverse constant - current discharge

[0042] Assume that at the moment when the AC SSPC main - power circuit is turned off, the load voltage V load is negative, that is, the potential of the power - output terminal of the AC solid - state power controller Powerout is lower than the power ground PGND , and the control instruction CMD aux jumps from a low level to a high level. At this time, the same driving voltage V drv (constantly 14 V) is applied between the gates of the upper / lower power transistors and the analog ground AGND 2. The gate - source voltage V GS of the power transistor rises to the threshold voltage V TH . The discharge current in the circuit gradually increases from zero. Due to the existence of the second negative - feedback resistor R 2, the voltage V R2 across the resistor increases linearly with the increase of the discharge current, resulting in the decrease of the gate - source voltage aux2 of the lower power transistor S V GS2 , and then controlling the drain - source current I D2 of the power transistor to decrease. After a certain time, the circuit current reaches a constant value I CCS- . At this time, the lower power transistor S aux2 operates in the saturation region, together with the second negative - feedback resistor R2 forms a reverse constant current source; meanwhile, the voltage division on the first negative feedback resistor R 1 causes the gate-source voltage of the upper power transistor S aux1 to increase. At this time, the upper power transistor S V GS1 is in a fully conducting state and operates in the variable resistance region. aux1

[0043] The constant current source composed of the lower power transistor and the second negative feedback resistor R 2 can be expressed as: I CCS-

[0044]

[0045] Similarly, when the enhancement-mode MOSFET device is determined, the reverse constant current I CCS- is uniquely determined by the second negative feedback resistor R 2. On the premise that the characteristics of the upper / lower power transistors in the clamping circuit are the same, in order to ensure that the magnitudes of the positive / negative discharge currents are basically the same, the resistances of the first and second negative feedback resistors in series should be equal during selection, that is:

[0046] R 1 =R 2 =R (3)

[0047] I CCS+ =I CCS- =I CCS (4)

[0048] Then there is:

[0049]

[0050] Define the gate transconductance g m of the MOSFET as:

[0051]

[0052] Among them, μ 0 is the electron mobility, C ox is the gate oxide capacitance per unit area, W is the channel width, L is the effective channel length, V GS is the gate-source voltage of the power transistor, V TH is the threshold voltage of the power transistor. ​​

[0053] Substituting Equation (6) into Equation (5), we get:

[0054]

[0055] After determining that the upper power transistor and the lower power transistor adopt the same type of enhancement-mode MOSFET, g m 、 V drv 、 V TH The values are fixed. According to Equation (7), the discharge current of this branch I CCS can be uniquely determined by the resistor R alone.

[0056] Assume that the absolute value of the initial voltage of the load is V 0, and the discharge current in the auxiliary branch is a constant value I CCS . Ignoring the parasitic resistance of the load-side circuit, the load discharge time T discharge can be expressed as:

[0057]

[0058] From Equation (8), it can be seen that the larger the discharge current I CCS , the shorter the discharge time T discharge . Therefore, when the discharge resistor R is determined, there is a definite corresponding relationship between the discharge current I CCS and the discharge time T discharge , which makes the energy discharge process of the capacitive load completely controllable, including the magnitude of the discharge current and the discharge time can be precisely regulated.

[0059] Figure 3 Figure 56 is the overall control timing diagram of the AC SSPC based on the anti-series bidirectional constant-current source clamping circuit. This control timing diagram corresponds to the power supply voltage V S turning on the AC SSPC when it is in the negative half-cycle, and the load current I load turning off the AC SSPC when it is in the positive half-cycle. Among them, t 0~ t 2 corresponds to the turn-on process of the AC SSPC, t 3~ t 5 corresponds to the turn-off process of the AC SSPC, t and the clamping circuit works after 5.

[0060] t 0: The total switch command CMD of the AC SSPC goes high, and the AC SSPC turns on. Since the power supply voltage V S is in the negative half-cycle, the first power transistor S of the main power circuit is turned on first upp , but since the second power transistor S of the main power circuit low has not been turned on yet, the main power circuit is still in the reverse cut-off state;

[0061] t 1: When the power supply voltage V S enters the positive half-cycle, the body diode of the second power transistor S of the main power circuit and the low channel of the already turned-on first power transistor S of the main power circuit upp form a forward path, and the load current starts to change from zero;

[0062] t 2: Turn on the second power transistor S of the main power circuit low , and the AC SSPC enters the steady-state conduction state;

[0063] t 3: The total switch command CMD of the AC SSPC goes low, and the AC SSPC turns off. The load current I load is in the positive half-cycle. First, turn off the second power transistor S of the main power circuit low . The current of the second power transistor S of the main power circuit low switches from the MOSFET channel to the body diode, and the load current continues;

[0064] t 4: When the load current I load enters the negative half-cycle, the AC SSPC is in the negative cut-off state, and the current is naturally turned off when it crosses zero;

[0065] t 5: Turn off the first power transistor S of the main power circuit upp . The AC SSPC enters the stable off state with bidirectional cut-off. The control command CMD of the clamping circuit aux goes high, and the upper power transistor S aux1 , the lower power transistor S aux2 turn on, and the loop current flows through the clamping circuit, and the load voltage gradually decreases accordingly.

[0066] Table 2 Zero-Crossing Switching Control Logic of AC SSPC

[0067]

[0068] Figure 4It is the working timing diagram of the anti - series bidirectional constant - current source clamping circuit. When the upper power transistor S aux1 and the lower power transistor S aux2 are turned on, if the voltage at the power output terminal Powerout of the AC solid - state power controller is higher than the voltage at the power ground PGND of the AC solid - state power controller, the working timing of the clamping circuit is as shown in (a); conversely, if when the upper power transistor S aux1 and the lower power transistor S aux2 are turned on, the voltage at the power output terminal Powerout of the AC solid - state power controller is lower than the voltage at the power ground PGND of the AC solid - state power controller, then the working timing of the clamping circuit is as shown in (b).

[0069] t 0: The total - switch command CMD of the AC SSPC is set low, and the AC SSPC is turned off.

[0070] t 1: The control command CMD aux of the clamping circuit is set to high level, the upper power transistor S aux1 and the lower power transistor S aux2 are turned on. If at this time the voltage at the power output terminal Powerout of the AC solid - state power controller is higher than the voltage at the power ground PGND of the AC solid - state power controller, the current I CSS + passes through the upper power transistor S aux1 , the first negative - feedback resistor R 1, the lower power transistor S aux2 , the second negative - feedback resistor R 2 to clamp the voltage on the load side to V C ; if at this time the voltage at the power output terminal Powerout of the AC solid - state power controller is lower than the voltage at the power ground PGND of the AC solid - state power controller, the current I CSS - passes through the lower power transistor S aux2 , the second negative - feedback resistor R , the upper power transistor S aux1 , the first negative - feedback circuit R 1 to clamp the voltage on the load side to V C .

[0071] For the AC solid - state power controller based on the anti - series bidirectional constant - current source clamping circuit of the present invention, when the AC solid - state power controller is turned on, the upper and lower power transistors S aux1 and S aux2When it is turned off, the clamping circuit does not work; when the AC solid-state power controller is turned off, the upper and lower power transistors S aux1 and S aux2 are turned on, the clamping circuit is connected in series with the load, and the energy stored in the load capacitor ( C load ) is consumed on the load resistor ( R load ). And because the equivalent resistance of this clamping circuit is much smaller than the equivalent resistance when the AC solid-state power controller is turned off, the voltage division value on the load side caused by the leakage current after turning off the AC solid-state power controller can be controlled within 1V.

[0072] Figure 5 Fig. is the working circuit diagram under the condition that the load is no-load and the SSPC is in the steady-state off state. Since the main power topology of the single-phase AC SSPC is composed of two identical N-channel enhancement-mode MOSFETs in anti-series, according to the circuit equivalence principle, the equivalent two-terminal network model of the SSPC with the resistor R SSPC in parallel with the capacitor C SSPC can be established. Among them, the equivalent resistance R SSPC of the SSPC in the steady-state conduction state is in the order of milliohms, and in the steady-state off state, it is in the order of megohms.

[0073] If this clamping circuit is not added, in the SSPC control circuit, due to the existence of the load voltage sampling and conditioning circuit, that is, the differential amplifier circuit composed of the load and the operational amplifier is in parallel, and the differential-mode input impedance Z diff of the operational amplifier is generally 100MΩ, so the no-load is approximately equivalent to a resistive load of 100 megohms. Assuming that the equivalent resistance when the main power circuit of the SSPC is turned off is 10MΩ, when the load is no-load and the SSPC is in the steady-state off state, the voltage on the load side is:

[0074]

[0075] After adding the clamping circuit, because the equivalent resistance of this clamping circuit is much smaller than the equivalent resistance when the SSPC is turned off R SSPC , the voltage division generated by the leakage current on the load side is much lower than the power supply voltage. The specific no-load clamping voltage V C is as follows:

[0076] V C = 2( V DS +R auxi leak ) (10)

[0077] In the above formula V DS is the drain-source on-state voltage drop of the enhancement-mode MOSFET, R aux are the resistances of the two resistors connected in series in the clamping circuit, i leak is the leakage current. Under the same conditions, after adding this clamping circuit, the voltage on the load side is much lower than that without the clamping circuit, greatly improving the safety of the system.

[0078] Figure 6 is the working circuit diagram of the capacitive load and the SSPC under the steady-state off condition. Among them, (a) is the circuit without the clamping circuit. For solid-state switches such as MOSFETs or IGBTs, even in the off state, there is still a very small leakage current (in the order of μA) in these devices. When the SSPC is turned off, this leakage current will slowly charge the capacitive load:

[0079]

[0080] Although the off-state leakage current of the SSPC is small, the continuous charging of the capacitive load will cause the voltage to rise linearly with time, and this voltage may pose a hazard to personnel or equipment and needs to be suppressed through circuit design or protection measures.

[0081] Figure 6 In (b) is the circuit after adding the clamping circuit. Ignoring the current of the capacitive load, almost all of the leakage current flows through the clamping circuit. At this time, the voltage on the load side is:

[0082] V load = 2( V DS +R aux i leak ) (12)

[0083] When the power MOSFET is turned on, its drain-source voltage usually remains at the millivolt level; while in the off state, the leakage current is only in the order of microamps. By introducing a clamping circuit and setting a negative feedback resistor of several tens of ohms, the voltage on the load side can be effectively limited within a few volts. Compared with the situation without adding the clamping circuit, after adding the clamping circuit, the voltage on the load side can remain basically stable, avoiding the continuous accumulation of "virtual voltage" caused by the leakage current. This design not only ensures the reliability of the system but also eliminates potential safety hazards, effectively protecting the safety of personnel and equipment.

[0084] The above embodiments are only used to illustrate the technical idea of the present invention, and the protection scope of the present invention cannot be limited thereby. Any modification made on the basis of the technical solution according to the technical idea proposed by the present invention falls within the protection scope of the present invention.

Claims

1. An anti-series bidirectional constant current source clamping circuit, applied to an AC solid-state power controller, characterized in that: The clamp circuit is connected in parallel between the power output end and the power ground of the AC solid-state power controller. The clamp circuit adopts a symmetrical structure and includes an upper power tube, a lower power tube, a first negative feedback resistor, and a second negative feedback resistor. The drain of the upper power tube is connected to the power output end of the AC solid-state power controller, the source of the upper power tube is connected to one end of the first negative feedback resistor, the drain of the lower power tube is connected to the power ground of the AC solid-state power controller, the source of the lower power tube is connected to one end of the second negative feedback resistor, the other end of the first negative feedback resistor is connected to the other end of the second negative feedback resistor and then connected to the same analog ground, the gates of the upper power tube and the lower power tube are connected and then connected to the same control instruction output by the clamp circuit control logic circuit; the clamp circuit control logic circuit includes an NOR gate, an OR gate and an RS trigger, the two input ends of the NOR gate are respectively connected to the switch instructions of the first power tube and the second power tube, the four input ends of the OR gate are respectively connected to the switch instructions of the first power tube and the second power tube, and the positive and negative logic signals of the load current direction; the output end of the NOR gate is connected to the RS trigger The output of the OR gate is connected to the RS flip-flop end, the RS flip-flop The terminal outputs the control instruction.

2. The anti-series bidirectional constant current source clamping circuit as claimed in claim 1, characterized in that: The upper power tube and the lower power tube are both enhancement type MOSFETs.

3. The anti-series bidirectional constant current source clamping circuit as claimed in claim 1, characterized in that: The upper power tube and the lower power tube have the same characteristics, and the first negative feedback resistor and the second negative feedback resistor have the same resistance values.

4. An AC solid-state power controller, comprising a main power circuit, a clamping circuit and a clamping circuit control logic circuit, characterized in that: The clamp circuit is connected in parallel between the power output terminal and the power ground of the AC solid-state power controller. The clamp circuit adopts a symmetrical structure, including an upper power tube, a lower power tube, a first negative feedback resistor, and a second negative feedback resistor. The source of the upper power tube is connected to one end of the first negative feedback resistor, the source of the lower power tube is connected to one end of the second negative feedback resistor, the other end of the first negative feedback resistor is connected to the other end of the second negative feedback resistor and then connected to the same analog ground. The gates of the upper power tube and the lower power tube are connected and then connected to the same control instruction output by the clamp circuit control logic circuit; the clamp circuit control logic circuit includes an NOR gate, an OR gate and an RS trigger. The two input ends of the NOR gate are respectively connected to the switch instructions of the first power tube and the second power tube, and the four input ends of the OR gate are respectively connected to the switch instructions of the first power tube and the second power tube, as well as the positive and negative logic signals of the load current direction; the output end of the NOR gate is connected to the RS trigger. The output of the OR gate is connected to the RS flip-flop end, the RS flip-flop The terminal outputs the control instruction.

5. The AC solid-state power controller according to claim 4, characterized in that: The upper power tube and the lower power tube are both enhancement type MOSFETs.

6. The AC solid-state power controller according to claim 4, characterized in that: The upper power tube and the lower power tube have the same characteristics, and the first negative feedback resistor and the second negative feedback resistor have the same resistance values.

7. The AC solid-state power controller according to any one of claims 4 to 6, characterized in that: The main power circuit includes a first power tube and a second power tube connected in anti-series, the drain of the first power tube being connected to an AC power supply as a power input end of an AC solid-state power controller, the drain of the second power tube being connected to a clamping circuit and a load as a power output end of the AC solid-state power controller, the gate of the first power tube and the source of the second power tube being connected to the same analog ground, and the gate of the first power tube and the gate of the second power tube being connected to different switching instructions.

8. The control method of the AC solid-state power controller according to claim 7, characterized in that: include: When the AC solid-state power controller is turned on: in the positive half cycle of the AC power supply voltage, the second power tube is turned on first, and the first power tube is turned on after the voltage passes through zero, and the upper power tube and the lower power tube are turned off; In the negative half cycle of the AC power supply voltage, the first power tube is turned on first, and the second power tube is turned on after the voltage passes through zero, and the upper power tube and the lower power tube are turned off; When the AC solid-state power controller is turned off: in the positive half cycle of the load current, the second power tube is turned off first, and the first power tube is turned off after the current passes through zero, and the upper power tube and the lower power tube are turned on; in the negative half cycle of the load current, the first power tube is turned off first, and the second power tube is turned off after the current passes through zero, and the upper power tube and the lower power tube are turned on.

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