Power converter suitable for generator special for FADEC system and control method of power converter

Abstract

The invention relates to a power converter suitable for a generator special for an FADEC system and a control method of the power converter, and relates to the field of aero-engine power conversion. According to the power converter suitable for the generator special for the FADEC system and the control method of the power converter provided by the technical scheme, the MOS transistor can be in a conducting state when current flows through the MOS transistor in a closed-loop control state, power consumption generated by a parasitic diode of the MOS transistor is effectively reduced, power supply safety of the FADEC system is ensured, and the service life of the FADEC system is prolonged. The problem that alternating current generated by a special generator has the characteristics of wide voltage, wide frequency, rapid change and the like and is difficult to convert and utilize is solved.

Description

Technical Field

[0001] The present invention relates to the technical field of aircraft engine power conversion, and in particular to a power converter suitable for a dedicated generator of a FADEC system and a control method thereof. Background Art

[0002] In modern aviation technology, the Full Authority Digital Engine Control (FADEC) system is a key component in the management and control of aircraft engines. The FADEC system integrates electronic controllers, sensors, and actuators to achieve real-time monitoring and precise control of the engine. It not only optimizes engine performance and improves fuel efficiency, but also enhances flight safety. The Federal Aviation Administration (FAA) of the United States is aware of the importance of the independence and reliability of the FADEC system to aviation safety, and has therefore formulated new regulatory requirements that the FADEC system should have a dedicated power supply independent of the aircraft's main power system. This regulation is intended to ensure that even if the aircraft's main power supply fails, the FADEC system can still maintain normal operation, thereby ensuring the continued stable operation of the engine, which is critical to flight safety in emergency situations.

[0003] In the design of a certain type of domestic aircraft, engineers chose an innovative approach to meet the new FAA regulations, that is, equipped with an AC generator designed specifically for the FADEC system. This generator is directly driven by the aircraft engine to rotate, and its working principle is to convert the mechanical energy of the engine into electrical energy to provide the necessary power support for the FADEC system. However, due to the wide range of speed changes of aircraft engines, the AC output of the dedicated generator has the characteristics of wide voltage, wide frequency and rapid changes. These characteristics bring significant technical challenges to the conversion and utilization of power. Specifically, the speed fluctuations of aircraft engines under different working conditions will cause the output voltage of the generator to be unstable, and the frequency will also change accordingly, which puts high demands on traditional power converters. In order to ensure the power supply quality of the FADEC system, a power converter that can adapt to this special input characteristic must be developed. This type of converter needs to be able to work efficiently over a wide range of voltage and frequency while maintaining output stability and reliability, which is essential to ensuring the performance of the FADEC system and the safety of the aircraft.

[0004] In addition, considering the weight restrictions and space constraints in aviation applications, the power converter also needs to be as compact and lightweight as possible without sacrificing its performance or reliability. Therefore, the development of a power converter for a dedicated generator for the FADEC system is not only a matter of solving technical problems, but also a major engineering design challenge. Summary of the invention

[0005] The object of the present invention is to provide a power converter suitable for a dedicated generator of a FADEC system and a control method thereof, so as to solve the problems existing in the above-mentioned prior art.

[0006] To achieve the above object, the technical solution adopted by the present invention is: In a first aspect, the present invention provides a power converter suitable for a dedicated generator of a FADEC system, comprising: A main power circuit, which is connected to the three-phase AC output terminal of the generator dedicated to the FADEC system and converts the three-phase AC into a DC voltage through power conversion; An input current collection circuit is connected to the three-phase alternating current output terminal of the FADEC system dedicated generator and is used to collect current value information of the three-phase alternating current; an output voltage collection circuit, connected to the DC voltage output terminal of the main power circuit, and used to collect output voltage information of the main power circuit; and An FPGA circuit, which is connected to the input current acquisition circuit and the output voltage acquisition circuit, and is used to receive the current value information collected by the input current acquisition circuit and the output voltage information collected by the output voltage acquisition circuit, and generate a drive signal to transmit to the drive circuit; The driving circuit is connected to the MOS tube in the main power circuit and is used to control the on and off of the MOS tube in the main power circuit to achieve AC / DC power conversion.

[0007] In a possible implementation, the FADEC system dedicated generator is a permanent magnet synchronous three-phase AC generator, which is driven by the aircraft engine to rotate and generate electricity during operation, and its three-phase AC output terminal is allowed to be short-circuited for a long time; The equivalent circuit of the FADEC system dedicated generator is a variable frequency constant current three-phase current source, the output three-phase current of which is a sine wave, the effective value is a constant, the frequency is directly proportional to the aircraft engine speed, and the phase difference is 120° electrical angle.

[0008] In a possible implementation, the main power circuit is a three-phase full-bridge circuit, including MOS tube V1, MOS tube V2, MOS tube V3, MOS tube V4, MOS tube V5, MOS tube V6 and an output capacitor C1, the source of the MOS tube V1 is connected to the drain of the MOS tube V2, and is connected to the output end of the A-phase winding of the FADEC system dedicated generator; The source of the MOS tube V3 is connected to the drain of the MOS tube V4, and is connected to the output end of the B-phase winding of the generator dedicated to the FADEC system; The source of the MOS tube V5 is connected to the drain of the MOS tube V6 and is connected to the output end of the C-phase winding of the generator dedicated to the FADEC system; The drains of the MOS transistors V1, V3 and V5 are connected to each other as a positive output terminal, and the sources of the MOS transistors V2, V4 and V6 are connected to each other as a negative output terminal; Wherein, two ends of the capacitor C1 are connected to the positive output end and the negative output end respectively.

[0009] In a possible implementation, the drive signal Q1, the drive signal Q2, the drive signal Q3, the drive signal Q4, the drive signal Q5, and the drive signal Q6 of the drive circuit are respectively connected to the gates of the MOS transistor V1, the MOS transistor V2, the MOS transistor V3, the MOS transistor V4, the MOS transistor V5, and the MOS transistor V6 to control the corresponding MOS transistors to be turned on and off, thereby realizing AC / DC power conversion.

[0010] In a possible implementation, the input current acquisition circuit includes a Hall current sensor, a first operational amplifier, and a first A / D conversion chip, wherein the Hall current sensor is connected in series to the three-phase AC output terminal of the FADEC system dedicated generator to collect the three-phase line current and convert it into a voltage signal; The first operational amplifier amplifies the voltage signal output by the Hall current sensor and transmits the amplified voltage signal to the first A / D conversion chip; The first A / D conversion chip realizes the conversion from analog quantity to digital quantity and transmits the conversion result to the FPGA circuit.

[0011] In a possible implementation, the output voltage acquisition circuit includes a voltage-dividing resistor, a second operational amplifier, and a second A / D conversion chip, wherein the voltage-dividing resistor is connected to the positive output terminal of the main power circuit, and is used to divide the voltage of the positive output terminal and transmit it to the second operational amplifier; The second operational amplifier amplifies the received signal and transmits it to the second A / D conversion chip; The second A / D conversion chip realizes the conversion from analog quantity to digital quantity and transmits the conversion result to the FPGA circuit.

[0012] In a second aspect, the present invention provides a control method for a power converter applicable to a dedicated generator of a FADEC system, the method being applied to the power converter applicable to the dedicated generator of the FADEC system as described above, the method comprising: S1, the power converter starts to work. When it is detected that the input current frequency increases continuously until it is greater than the set value, it is determined that the FADEC system dedicated generator starts to operate. The power converter will enter the soft start state and the output voltage will increase slowly by controlling the duty cycle of MOS tubes V2, MOS tubes V4 and MOS tubes V6; S2. When it is detected that the output voltage is close to the set value, the power converter will enter a closed-loop control state, and the output voltage is maintained at the set value by controlling the duty cycle of the MOS tube V2, the MOS tube V4 and the MOS tube V6; S3. When it is detected that the input current frequency decreases continuously until it is less than the set value, it is determined that the FADEC system dedicated generator stops running and the power converter stops working.

[0013] In a possible implementation, in step S1: The duty ratios of the MOS transistor V2, MOS transistor V4 and MOS transistor V6 are equal and gradually decrease from 1; The drive signals Q1, Q3 and Q5 corresponding to the MOS transistors V1, V3 and V5 are always zero; When the drive signals Q2, Q4, and Q6 corresponding to the MOS transistors V2, V4, and V6 are zero, the main power circuit is in an uncontrolled rectification state, and the power is transmitted to the equivalent load R through the parasitic body diodes of the MOS transistors V1 to V6; When the drive signals Q2, Q4, and Q6 corresponding to the MOS transistors V2, V4, and V6 are not zero, the MOS transistors V2, V4, and V6 are turned on at the same time, the output end of the FADEC system dedicated generator is short-circuited, power cannot be transmitted, and the capacitor C1 supplies power to the equivalent load R.

[0014] In a possible implementation, in step S2: When the A-phase current of the FADEC system dedicated generator is in the positive direction, it is closed-loop PI control at this time. If the closed-loop PI makes the drive signal Q2 of the MOS tube V2 zero, the MOS tube V1 and the MOS tube V2 are respectively in the on and off states, and the A-phase power is transmitted to the equivalent load R through the MOS tube V1; if the closed-loop PI makes the drive signal Q2 of the MOS tube V2 not zero, the MOS tube V1 and the MOS tube V2 are respectively in the off and on states, and the A-phase power flows back to the FADEC system dedicated generator through the MOS tube V2, the MOS tube V4 and the MOS tube V6, and the equivalent load R is powered by the capacitor C1; when the A-phase current of the FADEC system dedicated generator is in the negative direction, it is closed-loop high-efficiency control at this time, the MOS tube V2 is always on, and the MOS tube V1 is always off until the A-phase current is in the positive direction and then controlled by the closed-loop PI; When the B-phase current of the FADEC system dedicated generator is in the positive direction, it is closed-loop PI control at this time. If the closed-loop PI makes the drive signal Q4 of the MOS tube V4 zero, the MOS tube V3 and the MOS tube V4 are respectively in the on and off states, and the B-phase power is transmitted to the equivalent load R through the MOS tube V3; if the closed-loop PI makes the drive signal Q4 of the MOS tube V4 not zero, the MOS tube V3 and the MOS tube V4 are respectively in the off and on states, and the B-phase power flows back to the FADEC system dedicated generator through the MOS tube V2, the MOS tube V4 and the MOS tube V6, and the equivalent load R is powered by the capacitor C1; when the B-phase current of the FADEC system dedicated generator is in the negative direction, it is closed-loop high-efficiency control at this time, the MOS tube V4 is always on, and the MOS tube V3 is always off until the B-phase current is in the positive direction and then controlled by the closed-loop PI; When the C-phase current of the FADEC system dedicated generator is in the positive direction, it is closed-loop PI control at this time. If the closed-loop PI makes the drive signal Q6 of the MOS tube V6 zero, the MOS tube V5 and the MOS tube V6 are respectively in the on and off states, and the C-phase power is transmitted to the equivalent load R through the MOS tube V5; if the closed-loop PI makes the drive signal Q6 of the MOS tube V6 not zero, the MOS tube V5 and the MOS tube V6 are respectively in the off and on states, and the C-phase power flows back to the FADEC system dedicated generator through the MOS tube V2, the MOS tube V4 and the MOS tube V6, and the equivalent load R is powered by the capacitor C1; when the C-phase current of the FADEC system dedicated generator is in the negative direction, it is closed-loop high-efficiency control at this time, the MOS tube V6 is always on, and the MOS tube V5 is always off until the C-phase current is in the positive direction and then controlled by the closed-loop PI.

[0015] In a possible implementation, in step S2: The FPGA circuit compares the collected output voltage with the set value to obtain an error signal, performs PI calculation on the error signal to obtain a duty cycle, and controls the time when the MOS tubes V2, V4 and V6 are simultaneously turned on through the drive signal Q2, the drive signal Q4 and the drive signal Q6.

[0016] The beneficial effects brought about by the technical solution provided by the present invention include at least: The technical solution provides a power converter and a control method for a dedicated generator for a FADEC system, which can keep the MOS tube in a conducting state when current flows through the MOS tube under closed-loop control, effectively reduce the power consumption generated by the parasitic body diode of the MOS tube, ensure the power supply safety of the FADEC system, and solve the problem that the AC power generated by the dedicated generator is difficult to convert and utilize due to its wide voltage, wide frequency and rapid changes. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The accompanying drawings are used to provide further understanding of the present invention and constitute a part of the specification. They are used to explain the present invention together with the embodiments of the present invention and do not constitute a limitation of the present invention.

[0018] Figure 1 A structural block diagram of a power converter suitable for a generator dedicated to a FADEC system provided by an exemplary embodiment of the present invention is shown.

[0019] Figure 2 A logic block diagram of a control method for a power converter of a dedicated generator of a FADEC system provided by an exemplary embodiment of the present invention is shown.

[0020] Figure 3 A working mode diagram of a power converter applicable to a dedicated generator of a FADEC system provided by an exemplary embodiment of the present invention when in a soft start state is shown.

[0021] Figure 4 A working mode diagram of a power converter applicable to a dedicated generator of a FADEC system provided by an exemplary embodiment of the present invention when in a closed-loop control state is shown.

[0022] Figure 5 A working mode diagram of a power converter applicable to a dedicated generator of a FADEC system provided by an exemplary embodiment of the present invention is shown when the A-phase current is in a negative direction and the power converter is in a closed-loop control state. DETAILED DESCRIPTION

[0023] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0024] The present invention will be further described below in conjunction with the accompanying drawings and embodiments.

[0025] Figure 1 The structure block diagram of a power converter for a dedicated generator of a FADEC system provided by an exemplary embodiment of the present invention is shown. The power converter for a dedicated generator of a FADEC system includes: a main power circuit 2, an input current acquisition circuit 3, an output voltage acquisition circuit 4, an FPGA circuit 5, and a drive circuit 6. The main power circuit 2 is connected to the three-phase AC output terminal of the dedicated generator 1 of the FADEC system, and converts the three-phase AC into a DC voltage through electric energy conversion; the input current acquisition circuit 3 is connected to the three-phase AC output terminal of the dedicated generator 1 of the FADEC system, and is used to acquire the output voltage of the output current ... voltage; the input current acquisition circuit 3 is connected to the three-phase AC output terminal of the dedicated generator 1 of the FADEC system, and is used to acquire the output voltage of The current value information of the three-phase alternating current; the output voltage acquisition circuit 4 is connected to the DC voltage output end of the main power circuit 2, and is used to acquire the output voltage information of the main power circuit 2; the FPGA circuit 5 is connected to the input current acquisition circuit 3 and the output voltage acquisition circuit 4, and is used to receive the current value information acquired by the input current acquisition circuit 3 and the output voltage information acquired by the output voltage acquisition circuit 4, and generate a driving signal to transmit to the driving circuit 6; wherein the driving circuit 6 is connected to the MOS tube in the main power circuit 2, and is used to control the conduction and shutdown of the MOS tube in the main power circuit 2 to realize AC / DC power conversion.

[0026] In the embodiment of the present application, the main power circuit 2 is connected to the three-phase AC output terminal of the dedicated generator 1 of the FADEC system, and is responsible for performing the core AC / DC conversion task, that is, converting the three-phase AC into a DC voltage. The input current acquisition circuit 3 is also connected to the dedicated generator 1 of the FADEC system, and is responsible for monitoring the current value information of the three-phase AC flowing into the main power circuit 2. This function is essential for real-time understanding of the working status of the generator, and helps to achieve accurate control and protection of the entire FADEC system. The output voltage acquisition circuit 4 is connected after the main power circuit 2 to monitor the converted DC voltage level to ensure that it meets the expected requirements. The FPGA (field programmable gate array) circuit 5, as the core component of the FADEC system, receives data feedback from the input current acquisition circuit 3 and the output voltage acquisition circuit 4, adjusts its own algorithm logic according to this information, and then generates an appropriate drive signal to control the drive circuit 6. In this way, the FPGA can dynamically respond to changes in load and other external conditions to maintain the stability of the output voltage. Finally, the drive circuit 6 is directly connected to the MOS tube in the main power circuit 2, and controls the switching action of the MOS tube according to the instructions issued by the FPGA, thereby completing an efficient AC / DC power conversion process. Such an architecture not only improves conversion efficiency, but also enhances the reliability and flexibility of the FADEC system.

[0027] Specifically, the generator 1 dedicated to the FADEC system is a permanent magnet synchronous three-phase AC generator, which is driven by the aircraft engine to rotate and generate electricity during operation, and its three-phase AC output terminal is allowed to be short-circuited for a long time; the equivalent circuit of the generator 1 dedicated to the FADEC system is a variable frequency constant current three-phase current source, and its output three-phase current is a sinusoidal wave, the effective value is a constant, the frequency is directly proportional to the aircraft engine speed, and the phase difference is 120° electrical angle.

[0028] In the embodiment of the present application, the equivalent circuit model of the dedicated generator of the FADEC system is a variable frequency constant current three-phase current source, which means that it can adjust the output frequency according to the different speeds of the aircraft engine while keeping the effective value of the output current constant. Such characteristics ensure that the generator can provide stable and predictable power to each component in the FADEC system regardless of the operating conditions of the engine. In addition, the output three-phase current is a sinusoidal waveform, and the phase difference between each phase is 120° electrical angle, which ensures the quality and symmetry of the power, which is crucial to maintaining the normal operation of the electronic equipment inside the FADEC system. Specifically, since the output frequency of the generator is directly proportional to the speed of the aircraft engine, this means that as the engine speed changes, the frequency of the AC power output by the generator will also change linearly accordingly. This feature is critical to achieving precise engine control because it allows the FADEC system to dynamically adjust the control strategy based on the real-time monitored engine status, thereby optimizing performance, improving efficiency and enhancing reliability.

[0029] In detail, the main power circuit 2 is a three-phase full-bridge circuit, including a MOS tube V1, a MOS tube V2, a MOS tube V3, a MOS tube V4, a MOS tube V5, a MOS tube V6 and an output capacitor C1. The source of the MOS tube V1 is connected to the drain of the MOS tube V2, and is connected to the output end of the A-phase winding of the FADEC system dedicated generator 1; the source of the MOS tube V3 is connected to the drain of the MOS tube V4, and is connected to the output end of the B-phase winding of the FADEC system dedicated generator 1; the source of the MOS tube V5 is connected to the drain of the MOS tube V6, and is connected to the output end of the C-phase winding of the FADEC system dedicated generator 1; the drains of the MOS tube V1, the MOS tube V3 and the MOS tube V5 are connected to each other as a positive output end output, and the sources of the MOS tube V2, the MOS tube V4 and the MOS tube V6 are connected to each other as a negative output end output; wherein, the two ends of the capacitor C1 are respectively connected to the positive output end and the negative output end. The drive signals Q1, Q2, Q3, Q4, Q5 and Q6 of the drive circuit 6 are respectively connected to the gates of the MOS transistors V1, V2, V3, V4, V5 and V6 to control the corresponding MOS transistors to be turned on and off, thereby realizing AC / DC power conversion.

[0030] In the embodiment of the present application, the drive circuit 6 generates drive signals Q1 to Q6 and applies them to the gates of MOS tubes V1 to V6 respectively to control the on and off states of these MOS tubes. This precise switch control realizes efficient conversion from three-phase AC to DC. When the MOS tubes are alternately turned on according to a specific timing, they convert the AC input from the generator into a pulsating DC output, and then after filtering by capacitor C1, a relatively stable DC voltage is finally obtained. Such a setting can not only effectively realize AC / DC power conversion, but also ensure the stability and efficiency of the FADEC system.

[0031] Furthermore, the input current acquisition circuit 3 includes a Hall current sensor, a first operational amplifier and a first A / D conversion chip. The Hall current sensor is connected in series to the three-phase AC output terminal of the FADEC system dedicated generator 1, and is used to collect the three-phase line current and convert it into a voltage signal; the first operational amplifier amplifies the voltage signal output by the Hall current sensor and transmits it to the first A / D conversion chip; the first A / D conversion chip realizes the conversion from analog to digital and transmits the conversion result to the FPGA circuit 5. The output voltage acquisition circuit 4 includes a voltage divider resistor, a second operational amplifier and a second A / D conversion chip. The voltage divider resistor is connected to the positive output terminal of the main power circuit 2, and is used to divide the voltage of the positive output terminal and transmit it to the second operational amplifier; the second operational amplifier amplifies the received signal and transmits it to the second A / D conversion chip; the second A / D conversion chip realizes the conversion from analog to digital and transmits the conversion result to the FPGA circuit 5.

[0032] In the embodiment of the present application, the non-contact measurement method of the input current acquisition circuit 3 not only reduces the impact on the original circuit, but also improves the safety and reliability of the system; the voltage signal generated by the Hall current sensor is usually small, so it needs to be appropriately amplified by the first operational amplifier to ensure that the signal strength is sufficient to drive the subsequent A / D conversion process; the amplified voltage signal is then sent to the first A / D conversion chip, where the conversion from analog quantity to digital quantity is completed, and the digital signal finally converted will be transmitted to the FPGA circuit 5. The voltage divider resistor of the output voltage acquisition circuit 4 is connected to the positive output end of the main power circuit 2, and its function is to proportionally reduce the higher DC output voltage to a lower voltage level suitable for the input range of the A / D converter; this can protect the A / D conversion chip from damage by excessive voltage while ensuring the acquisition accuracy; the voltage signal after the voltage division process will then be transmitted to the second operational amplifier, where necessary signal conditioning (such as gain adjustment or offset correction) is performed again, and then transmitted to the second A / D conversion chip to realize analog-to-digital conversion, and finally the converted digital signal will also be sent to the FPGA circuit 5 for monitoring and feedback control.

[0033] In one example, the generator dedicated to the FADEC system is a permanent magnet synchronous three-phase AC generator. The output three-phase current is a sine wave with a phase difference of 120°. The frequency varies with the speed of the aircraft engine within 300~3000Hz, and the maximum effective value of the current is about 10A. The main power circuit is a three-phase full-bridge circuit, which consists of MOS tubes V1~V6 and output capacitor C1. MOS tubes V1~V6 use (G)C100N60T4, and C1 is a 400uF electrolytic capacitor. The input current acquisition circuit consists of a Hall current sensor, an operational amplifier, and an A / D conversion chip. The Hall current sensor uses ACS724LLCTR-20AB-T, the operational amplifier uses OPA2192QDGKRQ1, and the A / D conversion chip uses HWD7274EAA. The output voltage acquisition circuit consists of a voltage divider resistor, an operational amplifier, and an A / D conversion chip. The output voltage is divided by 18K resistor and 1K resistor, the operational amplifier is OPA2192QDGKRQ1, the A / D conversion chip is HWD7274EAA. The FPGA is A3P1000-FG144M. The MOS tubes V1~V6 are driven by bootstrap drive, and the drive circuit uses FW2103 drive chip to produce drive signals Q1~Q6.

[0034] Figure 2 A logic block diagram of a control method for a power converter for a dedicated generator of a FADEC system provided by an exemplary embodiment of the present invention is shown. The method is applied to the power converter for a dedicated generator of a FADEC system as described above. The method comprises the following steps: Step S1, the power converter starts working. When it is detected that the input current frequency continues to increase until it is greater than the set value, it is determined that the FADEC system dedicated generator starts to operate, and the power converter will enter the soft start state. By controlling the duty cycle of MOS tubes V2, MOS tubes V4 and MOS tubes V6, the output voltage is slowly increased.

[0035] Specifically, Figure 3 FIG. 1 shows an operating mode diagram of a power converter for a dedicated generator of a FADEC system provided by an exemplary embodiment of the present invention when in a soft start state, wherein Figure 3 (a) - The driving signals Q2, Q4 and Q6 of MOS tubes V2, V4 and V6 are zero. Figure 3(b) - The drive signals Q2, Q4 and Q6 of MOS tubes V2, V4 and V6 are not zero. The duty ratios of MOS tubes V2, V4 and V6 are equal and gradually decrease from 1; the drive signals Q1, Q3 and Q5 corresponding to MOS tubes V1, V3 and V5 are always zero; when the drive signals Q2, Q4 and Q6 corresponding to MOS tubes V2, V4 and V6 are zero, the main power circuit is in an uncontrolled rectification state, and the power is transmitted to the equivalent load R through the parasitic body diodes of MOS tubes V1 to V6; when the drive signals Q2, Q4 and Q6 corresponding to MOS tubes V2, V4 and V6 are not zero, MOS tubes V2, V4 and V6 are turned on at the same time, the output end of the dedicated generator of the FADEC system is short-circuited, the power cannot be transmitted, and the equivalent load R is powered by capacitor C1.

[0036] In the embodiment of the present application, in order to avoid voltage overshoot during startup, the present application adopts soft start technology to control the duty cycle of MOS tubes V2, V4 and V6. Different from the duty cycle of the traditional power converter gradually increasing from 0 during soft start, the duty cycle of MOS tubes V2, MOS tubes V4 and MOS tubes V6 of the present application is equal and gradually decreases from 1. This is because considering that the equivalent circuit of the dedicated generator of the FADEC system is a variable frequency constant current three-phase current source, the present application controls the power transmission by controlling the MOS tubes V2, V4 and V6 in the main power circuit to be turned on and off at the same time. The key to this step is that it can not only prevent the large current impact at the moment of startup, but also ensure that the output voltage gradually increases in a controlled manner, thereby protecting the downstream equipment from potential damage. In addition, since MOS tubes V1, V3 and V5 remain closed during the entire soft start period (the corresponding drive signals Q1, Q3 and Q5 are always zero), this can further reduce unnecessary energy loss and maintain the stability of the entire system.

[0037] Step S2: When it is detected that the output voltage is close to the set value, the power converter will enter a closed-loop control state, and the output voltage is maintained at the set value by controlling the duty cycle of the MOS tube V2, the MOS tube V4 and the MOS tube V6.

[0038] Specifically, Figure 4 FIG. 1 shows an operating mode diagram of a power converter for a dedicated generator of a FADEC system provided by an exemplary embodiment of the present invention when it is in a closed-loop control state, wherein Figure 4 (a) - The driving signal Q2 of MOS tube V2 is zero. Figure 4(b) - The drive signal Q2 of MOS tube V2 is not zero. When the A-phase current of the FADEC system dedicated generator is in the positive direction (the direction of the current flowing into the main power circuit is the positive direction, and vice versa is the negative direction), it is closed-loop PI control. If the closed-loop PI makes the drive signal Q2 of MOS tube V2 zero, MOS tube V1 and MOS tube V2 are in the on and off states respectively, and the A-phase power is transmitted to the equivalent load R through MOS tube V1; if the closed-loop PI makes the drive signal Q2 of MOS tube V2 not zero, MOS tube V1 and MOS tube V2 are in the off and on states respectively, and the A-phase power flows back to the FADEC system dedicated generator through MOS tube V2, MOS tube V4 and MOS tube V6, and the equivalent load R is powered by capacitor C1. When the B-phase current of the dedicated generator of the FADEC system is in the positive direction, it is closed-loop PI control at this time. If the closed-loop PI makes the drive signal Q4 of the MOS tube V4 zero, the MOS tube V3 and the MOS tube V4 are respectively in the on and off states, and the B-phase power is transmitted to the equivalent load R through the MOS tube V3; if the closed-loop PI makes the drive signal Q4 of the MOS tube V4 not zero, the MOS tube V3 and the MOS tube V4 are respectively in the off and on states, and the B-phase power flows back to the dedicated generator of the FADEC system through the MOS tubes V2, V4 and V6, and the equivalent load R is powered by the capacitor C1. When the C-phase current of the dedicated generator of the FADEC system is in the positive direction, it is closed-loop PI control at this time. If the closed-loop PI makes the drive signal Q6 of the MOS tube V6 zero, the MOS tube V5 and the MOS tube V6 are respectively in the on and off states, and the C-phase power is transmitted to the equivalent load R through the MOS tube V5; if the closed-loop PI makes the drive signal Q6 of the MOS tube V6 not zero, the MOS tube V5 and the MOS tube V6 are respectively in the off and on states, and the C-phase power flows back to the dedicated generator of the FADEC system through the MOS tubes V2, V4 and V6, and the equivalent load R is powered by the capacitor C1.

[0039] Figure 5 The working mode diagram of a power converter for a dedicated generator for a FADEC system provided by an exemplary embodiment of the present invention when the current of phase A is in the negative direction under closed-loop control is shown. Taking phase A as an example, when the current of phase A of the dedicated generator for the FADEC system is in the negative direction, if the closed-loop PI makes the drive signal Q2 of the MOS tube V2 zero, the MOS tube V2 will be in the off state. However, since the current of phase A is in the negative direction, the current of phase A will flow to the dedicated generator for the FADEC system through the parasitic body diode of the MOS tube V2, which will generate a large power consumption. Therefore, the phase current direction is also used as a control condition. When the current of phase A is in the negative direction, in order to reduce power consumption, a closed-loop high-efficiency control is adopted at this time, so that the MOS tube V2 is always turned on and the MOS tube V1 is always turned off until the current of phase A is in the positive direction and then controlled by the closed-loop PI.

[0040] Similarly, when the B-phase current of the FADEC system dedicated generator is in the negative direction, it is a closed-loop high-efficiency control, the MOS tube V4 is always turned on, and the MOS tube V3 is always turned off until the B-phase current is in the positive direction and then controlled by the closed-loop PI.

[0041] Similarly, when the C-phase current of the FADEC system dedicated generator is in the negative direction, it is a closed-loop high-efficiency control, the MOS tube V6 is always turned on, and the MOS tube V5 is always turned off until the C-phase current is in the positive direction and then controlled by the closed-loop PI.

[0042] It is worth mentioning that the FPGA circuit compares the collected output voltage with the set value to obtain an error signal, then performs PI calculation on the error signal to obtain the duty cycle, and controls the time when MOS tubes V2, MOS tubes V4 and MOS tubes V6 are turned on at the same time through drive signals Q2, Q4 and Q6.

[0043] This step allows the power converter to dynamically adjust its behavior based on real-time feedback, ensuring that the output voltage always remains at the desired level, providing a stable power supply even in the face of load changes or fluctuating input conditions. In addition, this can also reduce the overshoot that may occur during startup and improve the overall efficiency and reliability of the system.

[0044] Step S3: When it is detected that the input current frequency is continuously decreasing until it is less than the set value, it is determined that the dedicated generator of the FADEC system stops running and the power converter stops working.

[0045] In the embodiment of the present application, when it is detected that the input current frequency is continuously decreasing until it is lower than the set value, this usually means that the dedicated generator of the FADEC system is about to or has stopped operating. At this time, the power converter will determine the status of the generator based on this signal and stop working accordingly. The main function of this setting is to protect the entire power supply system and its downstream electronic equipment from potential damage, while ensuring energy saving when power is not required. Specifically, the dedicated generator of the FADEC system will generate alternating current within a specific frequency range during normal operation, and this frequency is directly related to the engine speed. When the engine slows down or stops, the frequency of the current generated by the generator will also decrease. Therefore, by monitoring the changes in the input current frequency, it can be accurately determined whether the generator is still working normally. Once the frequency drops below the preset threshold, it means that the generator no longer provides effective power output. At this time, it is not only unnecessary to keep the power converter activated, but it may also bring risks, such as voltage surges due to the sudden disappearance of the load.

[0046] To cope with this situation, the power converter has logic designed inside to respond to frequency changes. When it detects that the frequency has dropped below the set value, the converter will take steps to gradually shut down its operation, disconnecting the generator in a safe manner and stopping power supply to the load. This process helps prevent any damage that may be caused by unexpected electrical behavior, while also reducing unnecessary energy consumption. In addition, stopping work in a timely manner can also avoid interference with other avionics systems that rely on a stable power supply.

[0047] It is worth noting that in actual applications, in order to ensure the reliability and safety of the system, there may be additional safety mechanisms and redundant designs to assist this decision-making process. For example, in addition to relying on the input current frequency as a basis for judgment, other parameters such as voltage level and temperature can also be combined for comprehensive evaluation to ensure that even if one parameter is abnormal, the system can still respond correctly.

[0048] It should be understood that the specific examples herein are only intended to help those skilled in the art to better understand the present disclosure, rather than to limit the scope of the present invention.

[0049] It is understood that in the various implementations of this specification, the size of the sequence number of each process does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the present disclosure.

[0050] It can be understood that the various implementation modes described in this specification can be implemented individually or in combination, and the present disclosure is not limited to this.

[0051] Unless otherwise stated, all technical and scientific terms used in this disclosure have the same meaning as those generally understood by those skilled in the art of the technical field of this specification. The terms used in this specification are only for the purpose of describing specific embodiments and are not intended to limit the scope of this specification. The term "and / or" used in this specification includes any and all combinations of one or more related listed items. The singular forms of "a", "above", and "the" used in this disclosure and the appended claims are also intended to include plural forms, unless the context clearly indicates other meanings.

[0052] The above is only a specific implementation of this specification, but the protection scope of the present invention is not limited thereto. Any person skilled in the art who is familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in this specification, which should be included in the protection scope of this specification. Therefore, the protection scope of the present invention should be based on the protection scope of the claims.

Claims

1. A power converter suitable for a generator dedicated to a FADEC system, characterized in that: include: A main power circuit (2) connected to a three-phase alternating current output terminal of a generator (1) dedicated to the FADEC system and converting the three-phase alternating current into a direct current voltage through electric energy conversion; An input current collection circuit (3) connected to the three-phase alternating current output terminal of the FADEC system dedicated generator (1) and used to collect current value information of the three-phase alternating current; an output voltage acquisition circuit (4), which is connected to the DC voltage output terminal of the main power circuit (2) and is used to acquire output voltage information of the main power circuit (2); and An FPGA circuit (5) connected to the input current acquisition circuit (3) and the output voltage acquisition circuit (4), and used for receiving the current value information acquired by the input current acquisition circuit (3) and the output voltage information acquired by the output voltage acquisition circuit (4), and generating a drive signal for transmission to the drive circuit (6); The drive circuit (6) is connected to the MOS tube in the main power circuit (2) and is used to control the on and off of the MOS tube in the main power circuit (2) to achieve AC / DC power conversion.

2. The power converter suitable for a generator dedicated to a FADEC system according to claim 1, characterized in that: The FADEC system dedicated generator (1) is a permanent magnet synchronous three-phase AC generator, which is driven by the aircraft engine to rotate and generate electricity during operation, and its three-phase AC output terminal is allowed to be short-circuited for a long time; The equivalent circuit of the FADEC system dedicated generator (1) is a variable frequency constant current three-phase current source, the output three-phase current is a sine wave, the effective value is a constant value, the frequency is proportional to the aircraft engine speed, and the phase difference is 120° electrical angle.

3. The power converter suitable for a generator dedicated to a FADEC system according to claim 1, characterized in that: The main power circuit (2) is a three-phase full-bridge circuit, comprising a MOS tube V1, a MOS tube V2, a MOS tube V3, a MOS tube V4, a MOS tube V5, a MOS tube V6 and an output capacitor C1, wherein the source of the MOS tube V1 is connected to the drain of the MOS tube V2 and is connected to the output end of the A-phase winding of the generator (1) dedicated to the FADEC system; The source of the MOS tube V3 is connected to the drain of the MOS tube V4, and is connected to the output end of the B-phase winding of the FADEC system dedicated generator (1); The source of the MOS tube V5 is connected to the drain of the MOS tube V6, and is connected to the C-phase winding output end of the FADEC system dedicated generator (1); The drains of the MOS transistors V1, V3 and V5 are connected to each other as a positive output terminal, and the sources of the MOS transistors V2, V4 and V6 are connected to each other as a negative output terminal; Wherein, two ends of the capacitor C1 are connected to the positive output end and the negative output end respectively.

4. The power converter suitable for a generator dedicated to a FADEC system according to claim 3, characterized in that: The drive signal Q1, the drive signal Q2, the drive signal Q3, the drive signal Q4, the drive signal Q5, and the drive signal Q6 of the drive circuit (6) are respectively connected to the gates of the MOS transistor V1, the MOS transistor V2, the MOS transistor V3, the MOS transistor V4, the MOS transistor V5, and the MOS transistor V6 to control the corresponding MOS transistors to be turned on and off, thereby realizing AC / DC power conversion.

5. The power converter suitable for a generator dedicated to a FADEC system according to claim 1, characterized in that: The input current acquisition circuit (3) comprises a Hall current sensor, a first operational amplifier and a first A / D conversion chip, wherein the Hall current sensor is connected in series to the three-phase AC output end of the FADEC system dedicated generator (1) and is used to acquire the three-phase line current and convert it into a voltage signal; The first operational amplifier amplifies the voltage signal output by the Hall current sensor and transmits the amplified voltage signal to the first A / D conversion chip; The first A / D conversion chip realizes the conversion from analog quantity to digital quantity and transmits the conversion result to the FPGA circuit (5).

6. The power converter suitable for a generator dedicated to a FADEC system according to claim 1, characterized in that: The output voltage acquisition circuit (4) comprises a voltage dividing resistor, a second operational amplifier and a second A / D conversion chip, wherein the voltage dividing resistor is connected to the positive output end of the main power circuit (2) and is used to divide the voltage at the positive output end and transmit it to the second operational amplifier; The second operational amplifier amplifies the received signal and transmits it to the second A / D conversion chip; The second A / D conversion chip realizes the conversion from analog quantity to digital quantity and transmits the conversion result to the FPGA circuit (5).

7. A control method for a power converter of a generator dedicated to a FADEC system, characterized in that: The method is applied to a power converter for a dedicated generator for a FADEC system as claimed in any one of claims 1 to 6, and the method comprises: S1, the power converter starts to work. When it is detected that the input current frequency increases continuously until it is greater than the set value, it is determined that the FADEC system dedicated generator starts to operate. The power converter will enter the soft start state and the output voltage will increase slowly by controlling the duty cycle of MOS tubes V2, MOS tubes V4 and MOS tubes V6; S2. When it is detected that the output voltage is close to the set value, the power converter will enter a closed-loop control state, and the output voltage is maintained at the set value by controlling the duty cycle of the MOS tube V2, the MOS tube V4 and the MOS tube V6; S3. When it is detected that the input current frequency decreases continuously until it is less than the set value, it is determined that the FADEC system dedicated generator stops running and the power converter stops working.

8. The control method of the power converter suitable for the dedicated generator of the FADEC system according to claim 7, characterized in that: In step S1: The duty ratios of the MOS transistor V2, MOS transistor V4 and MOS transistor V6 are equal and gradually decrease from 1; The drive signals Q1, Q3 and Q5 corresponding to the MOS transistors V1, V3 and V5 are always zero; When the drive signals Q2, Q4, and Q6 corresponding to the MOS transistors V2, V4, and V6 are zero, the main power circuit is in an uncontrolled rectification state, and the power is transmitted to the equivalent load R through the parasitic body diodes of the MOS transistors V1 to V6; When the drive signals Q2, Q4, and Q6 corresponding to the MOS transistors V2, V4, and V6 are not zero, the MOS transistors V2, V4, and V6 are turned on at the same time, the output end of the FADEC system dedicated generator is short-circuited, power cannot be transmitted, and the capacitor C1 supplies power to the equivalent load R.

9. The control method of the power converter suitable for the dedicated generator of the FADEC system according to claim 7, characterized in that: In step S2: When the A-phase current of the FADEC system dedicated generator is in the positive direction, it is closed-loop PI control at this time. If the closed-loop PI makes the drive signal Q2 of the MOS tube V2 zero, the MOS tube V1 and the MOS tube V2 are respectively in the on and off states, and the A-phase power is transmitted to the equivalent load R through the MOS tube V1; if the closed-loop PI makes the drive signal Q2 of the MOS tube V2 not zero, the MOS tube V1 and the MOS tube V2 are respectively in the off and on states, and the A-phase power flows back to the FADEC system dedicated generator through the MOS tube V2, the MOS tube V4 and the MOS tube V6, and the equivalent load R is powered by the capacitor C1; when the A-phase current of the FADEC system dedicated generator is in the negative direction, it is closed-loop high-efficiency control at this time, the MOS tube V2 is always on, and the MOS tube V1 is always off until the A-phase current is in the positive direction and then controlled by the closed-loop PI; When the B-phase current of the FADEC system dedicated generator is in the positive direction, it is closed-loop PI control at this time. If the closed-loop PI makes the drive signal Q4 of the MOS tube V4 zero, the MOS tube V3 and the MOS tube V4 are respectively in the on and off states, and the B-phase power is transmitted to the equivalent load R through the MOS tube V3; if the closed-loop PI makes the drive signal Q4 of the MOS tube V4 not zero, the MOS tube V3 and the MOS tube V4 are respectively in the off and on states, and the B-phase power flows back to the FADEC system dedicated generator through the MOS tube V2, the MOS tube V4 and the MOS tube V6, and the equivalent load R is powered by the capacitor C1; when the B-phase current of the FADEC system dedicated generator is in the negative direction, it is closed-loop high-efficiency control at this time, the MOS tube V4 is always on, and the MOS tube V3 is always off until the B-phase current is in the positive direction and then controlled by the closed-loop PI; When the C-phase current of the FADEC system dedicated generator is in the positive direction, it is closed-loop PI control at this time. If the closed-loop PI makes the drive signal Q6 of the MOS tube V6 zero, the MOS tube V5 and the MOS tube V6 are respectively in the on and off states, and the C-phase power is transmitted to the equivalent load R through the MOS tube V5; if the closed-loop PI makes the drive signal Q6 of the MOS tube V6 not zero, the MOS tube V5 and the MOS tube V6 are respectively in the off and on states, and the C-phase power flows back to the FADEC system dedicated generator through the MOS tube V2, the MOS tube V4 and the MOS tube V6, and the equivalent load R is powered by the capacitor C1; when the C-phase current of the FADEC system dedicated generator is in the negative direction, it is closed-loop high-efficiency control at this time, the MOS tube V6 is always on, and the MOS tube V5 is always off until the C-phase current is in the positive direction and then controlled by the closed-loop PI.

10. The control method of the power converter suitable for the dedicated generator of the FADEC system according to claim 9, characterized in that: In step S2: The FPGA circuit compares the collected output voltage with the set value to obtain an error signal, performs PI calculation on the error signal to obtain a duty cycle, and controls the time when the MOS tubes V2, V4 and V6 are simultaneously turned on through the drive signal Q2, the drive signal Q4 and the drive signal Q6.

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