Double-MCU control digital isolation double-voltage output inverter

Abstract

The invention relates to a double-MCU control digital isolation double-voltage output inverter. A main circuit MCU control unit supplies power to a main driving inverter circuit. The slave MCU control unit supplies power to the slave driving inverter circuit, the master MCU control unit directly detects a current signal and a voltage signal of a master path, the current signal and the voltage signal of the slave path are detected by the slave MCU control unit and are sent to the master MCU control unit through a digital isolator, and the two paths of signals are synchronously detected by the master MCU control unit. And the MCU control unit respectively sends four paths of PWM wave signals to the main driving inverter circuit and the slave driving inverter circuit and outputs two paths of 120V alternating current. According to the scheme, real-time information interaction between the two MCU control units is achieved through the digital isolator, interference is isolated, normal communication of the two inversion units is achieved, and the inversion efficiency and the overall working stability are greatly improved. One module system can output two paths of 120V alternating current at the same time, so that the reliability of the whole system is improved, and the system cost is reduced.

Description

Technical Field

[0001] The present application relates to the technical field of inverters, and in particular to a dual-MCU controlled digital isolation dual-voltage output inverter. Background Art

[0002] An inverter refers to the reverse converter of a rectifier, which is a power electronic converter that converts DC power into AC power through the opening and closing of semiconductor power switching devices. The existing inverters on the market generally obtain AC power from a permanent magnet generator, rectify it through a rectifier circuit, and then output the required AC voltage through an H-bridge inverter. In addition, voltage, current, speed and other detection circuits are added to protect and control the inverter to form a stable inverter system. Traditional inverters can only output one AC voltage and cannot meet the demand for simultaneous output of multiple voltages. To this end, it is necessary to propose a dual MCU controlled digital isolation dual voltage output inverter to address the defect that traditional inverters can only output one AC voltage. Summary of the invention

[0003] Based on this, it is necessary to propose a dual MCU controlled digital isolation dual voltage output inverter to address the defect that traditional inverters can only output one AC voltage.

[0004] The present application relates to a dual MCU controlled digital isolation dual voltage output inverter, comprising:

[0005] Main MCU control unit;

[0006] A main current detection unit, electrically connected to the main MCU control unit;

[0007] A main circuit voltage detection unit, electrically connected to the main circuit MCU control unit;

[0008] A main drive inverter circuit is electrically connected to the main MCU control unit;

[0009] A slave MCU control unit, electrically connected to the master MCU control unit;

[0010] A slave current detection unit, electrically connected to the slave MCU control unit;

[0011] A slave voltage detection unit, electrically connected to the slave MCU control unit;

[0012] The slave drive inverter circuit is electrically connected to the main MCU control unit.

[0013] The present application relates to a dual MCU controlled digital isolation dual voltage output inverter, including a main MCU control unit, a slave MCU control unit, a main current detection unit, a main voltage detection unit, a slave current detection unit, a slave voltage detection unit, a main drive inverter circuit, a slave drive inverter circuit, two input power supplies and two AC outputs. The main MCU control unit directly detects the main current signal and voltage signal, and the slave current signal and voltage signal are detected by the slave MCU control unit and sent to the main MCU control unit through a digital isolator, so that the two signals are synchronously detected by the main MCU control unit. The MCU control unit sends 4 PWM wave signals to the main drive inverter circuit and the slave drive inverter circuit respectively, and outputs two 120V AC. This solution uses a digital isolator to realize real-time information interaction between the two MCU control units, isolate interference, realize normal communication between the two inverter units, and greatly improve the inverter efficiency and the stability of the overall work. A module system can output two 120V AC at the same time, improve the reliability of the overall system, and reduce system costs. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 A module connection diagram of a dual MCU-controlled digital isolation dual voltage output inverter provided in one embodiment of the present application.

[0015] Figure 2 A schematic structural diagram of a master single-chip microcomputer control chip and a slave MCU control unit of a dual-MCU controlled digital isolation dual voltage output inverter provided in one embodiment of the present application.

[0016] Figure 3 A schematic diagram of the structure of a main voltage detection unit of a dual-MCU controlled digital isolation dual voltage output inverter provided in one embodiment of the present application.

[0017] Figure 4 A structural schematic diagram of a main current detection unit of a dual-MCU controlled digital isolation dual voltage output inverter provided in another embodiment of the present application.

[0018] Figure 5 A schematic diagram of the structure of a slave voltage detection unit of a dual-MCU controlled digital isolation dual voltage output inverter provided in one embodiment of the present application.

[0019] Figure 6 A schematic structural diagram of a slave current detection unit of a dual-MCU controlled digital isolation dual voltage output inverter provided in another embodiment of the present application.

[0020] Figure 7 A schematic structural diagram of a master MCU control unit and a slave MCU control unit of a dual MCU-controlled digital isolation dual voltage output inverter provided in one embodiment of the present application.

[0021] Figure 8 A schematic structural diagram of a main MCU control unit and a main drive inverter circuit of a dual MCU-controlled digital isolation dual voltage output inverter provided in one embodiment of the present application.

[0022] Fig. 9 A schematic structural diagram of a master MCU control unit and a slave drive inverter circuit of a dual MCU-controlled digital isolation dual voltage output inverter provided in one embodiment of the present application.

[0023] Reference numerals:

[0024] 100-main MCU control unit; 110-main single-chip control chip;

[0025] 120-the first group of PWM output ports; 130-the second group of PWM output ports;

[0026] 200-main current detection unit; 210-current operator; 220-feedback resistor; 230-signal circuit;

[0027] 300-main voltage detection unit; 310-first voltage dividing circuit; 320-second voltage dividing circuit;

[0028] 330 - capacitor assembly; 400 - main drive inverter circuit; 410 - first PWM chip;

[0029] 420 - first P-type MOS tube; 430 - second PWM chip; 440 - second P-type MOS tube;

[0030] 450 - a first feedback capacitor; 460 - a second feedback capacitor; 470 - a third PWM chip;

[0031] 480-third P-type MOS tube; 491-fourth PWM chip; 492-fourth P-type MOS tube;

[0032] 500-slave MCU control unit; 510-slave single-chip control chip; 520-digital isolator;

[0033] 600-slave current detection unit; 610-detection operator; 620-current signal resistor;

[0034] 630-decoupling resistor circuit; 700-slave voltage detection unit; 710-third voltage divider circuit;

[0035] 720 - fourth voltage divider circuit; 730 - filter capacitor component; 800 - slave drive inverter circuit. DETAILED DESCRIPTION

[0036] In order to make the purpose, technical solution and advantages of the present application more clearly understood, the present application is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0037] The present application provides a dual MCU controlled digital isolation dual voltage output inverter.

[0038] like Figure 1 As shown, in one embodiment of the present application, a dual MCU controlled digital isolation dual voltage output inverter includes a main MCU control unit 100, a main current detection unit 200, a main voltage detection unit 300, a main drive inverter circuit 400, a slave MCU control unit 500, a slave current detection unit 600, a slave voltage detection unit 700 and a slave drive inverter circuit 800.

[0039] The main current detection unit 200 is electrically connected to the main MCU control unit 100 .

[0040] The main circuit voltage detection unit 300 is electrically connected to the main circuit MCU control unit 100 .

[0041] The main drive inverter circuit 400 is electrically connected to the main MCU control unit 100 .

[0042] The slave MCU control unit 500 is electrically connected to the master MCU control unit 100 .

[0043] The slave current detection unit 600 is electrically connected to the slave MCU control unit 500 .

[0044] The slave voltage detection unit 700 is electrically connected to the slave MCU control unit 500 .

[0045] The slave drive inverter circuit 800 is electrically connected to the master MCU control unit 100 .

[0046] The present embodiment relates to a dual MCU controlled digital isolation dual voltage output inverter, including a main MCU control unit 100, a slave MCU control unit 500, a main current detection unit 200, a main voltage detection unit 300, a slave current detection unit 600, a slave voltage detection unit 700, a main drive inverter circuit 400, a slave drive inverter circuit 800, two input power supplies and two AC outputs. The main MCU control unit 100 directly detects the main current signal and voltage signal, and the slave current signal and voltage signal are detected by the slave MCU control unit 500 and sent to the main MCU control unit 100 through a digital isolator 520, so that the two signals are synchronously detected by the main MCU control unit 100. The MCU control unit sends 4 PWM wave signals to the main drive inverter circuit 400 and the slave drive inverter circuit 800, respectively, and outputs two 120V AC. This solution uses a digital isolator 520 to realize real-time information interaction between the two MCU control units, isolate interference, realize normal communication between the two inverter units, and greatly improve the inverter efficiency and the stability of the overall work. One module system can output two 120V AC power simultaneously, improving the reliability of the overall system and reducing system costs.

[0047] The main MCU control unit 100 controls two drive inverter circuits at the same time, and uses a digital isolator 520 to synchronize the signal detected by the slave MCU control unit 500 to the main MCU control unit 100 in real time, so that the two MCU control units can work together to achieve dual-voltage output of the inverter. It can output 2 120V AC and 1 240V AC at the same time. By adjusting the output wiring, it can output 2 120V AC and 1 240V AC at the same time. The main MCU drives the inverter by outputting 2 PWM signals. Output 2 AC. The master and slave MCUs are synchronized and serial port data exchanged through the isolator.

[0048] like Figure 7 As shown, in one embodiment of the present application, the main MCU control unit 100 includes a main single-chip control chip 110. The main single-chip control chip 110 is provided with a first group of PWM output ports 120. The main single-chip control chip 110 is provided with a second group of PWM output ports 130. The first group of PWM output ports 120 are all electrically connected to the main drive inverter circuit 400. The second group of PWM output ports 130 are all electrically connected to the slave drive inverter circuit 800.

[0049] Specifically, the main MCU control unit 100, the slave MCU control unit 500, the main current detection unit 200, the main voltage detection unit 300, the slave current detection unit 600, the slave voltage detection unit 700, the main drive inverter circuit 400, the slave drive inverter circuit 800, two input power supplies (not shown in the figure) and two AC outputs. The two input power supplies respectively supply power to the main MCU control unit 100, the slave MCU control unit 500, the main drive inverter circuit 400 and the slave drive inverter circuit 800, the main MCU control unit 100 directly detects the main current and voltage signals, the slave MCU control unit 500 detects the slave current and voltage signals, and sends the detected signals to the main MCU control unit 100 through the digital isolator 520; the MCU control unit sends 4 PWM wave signals to the main drive inverter circuit 400 and the slave drive inverter circuit 800, respectively, and outputs two 120V AC.

[0050] The first group of PWM output ports 120 can send four PWM wave signals so that the main drive inverter circuit 400 outputs two 120V AC power.

[0051] The second group of PWM output ports 130 can send another four PWM wave signals so that two 120V AC currents are output from the driving inverter circuit 800 .

[0052] like Figure 7 As shown, in one embodiment of the present application, the slave MCU control unit 500 includes a slave single-chip control chip 510 and a digital isolator 520. The slave single-chip control chip 510 is electrically connected to the master single-chip control chip 110. The digital isolator 520 is electrically connected to the connection link between the slave single-chip control chip 510 and the master single-chip control chip 110.

[0053] Specifically, the slave microcontroller control chip 510 transmits the current signal and voltage signal collected from the inverter slave part to the master microcontroller control chip 110 through the UART2_RX interface and UART2_TX interface of the digital isolator 520. The two AD synchronization interfaces AD_TBC and AD_TBZ of the digital isolator 520 realize real-time communication between the master microcontroller and the slave microcontroller.

[0054] The master MCU control unit 100 and the slave MCU control unit 500 perform synchronization and serial port data exchange via the slave MCU control unit 500 .

[0055] like Figure 3As shown, in one embodiment of the present application, the main voltage detection unit 300 includes a first voltage divider circuit 310, a second voltage divider circuit 320 and a capacitor component 330. The first end of the first voltage divider circuit 310 is electrically connected to the power supply end of the main single-chip control chip 110. The first end of the second voltage divider circuit 320 is electrically connected to the power supply end of the main single-chip control chip 110. The second end of the first voltage divider circuit 310 is electrically connected to the first voltage signal end of the main single-chip control chip 110. The second end of the second voltage divider circuit 320 is electrically connected to the second voltage signal end of the main single-chip control chip 110. The third end of the first voltage divider circuit 310 is electrically connected to the first end of the capacitor component 330. The third end of the second voltage divider circuit 320 is electrically connected to the second end of the capacitor component 330. The third end of the capacitor component 330 is grounded.

[0056] Specifically, Figure 2 As shown, the inverter is powered on, the main M_POW_X and slave M_POW_Y DC high voltages are stable, the main single-chip microcomputer UC2 and the slave single-chip microcomputer US4 are powered on synchronously, and the main single-chip microcomputer sends 8 PWM wave signals: O_PWMXL, O_PWMXH, O_PWMYL, O_PWMYH four-channel signals are sent to the inverter main road drive inverter module; O_PWMZL, O_PWMZH, O_PWMOL, O_PWMOH four-channel signals are sent to the inverter slave road drive inverter module, and the main road and the slave road output two 120V AC signals.

[0057] The main current detection unit 200, the main AC output OUTX, OUTY collects the voltage signals A_TUX, A_TUY through the voltage dividing resistor and sends them to the main microcontroller for detection.

[0058] like Figure 4 As shown, in one embodiment of the present application, the main current detection unit 200 includes a current operator 210, a feedback resistor 220 and a signal circuit 230. The first end of the signal circuit 230 is electrically connected to the AC input end of the main single-chip control chip 110. The second end of the signal circuit 230 is electrically connected to the positive input end of the current operator 210. The output end of the current operator 210 is electrically connected to the reverse input end of the current operator 210. The feedback resistor 220 is electrically connected to the connection link between the output end of the current operator 210 and the reverse input end of the current operator 210. The output end of the current operator 210 is electrically connected to the current detection end of the main single-chip control chip 110.

[0059] Specifically, the inverter is powered on, the main M_POW_X and slave M_POW_Y DC high voltages are stable, the main single-chip microcomputer UC2 and the slave single-chip microcomputer US4 are powered on synchronously, and the main single-chip microcomputer sends 8 PWM wave signals: O_PWMXL, O_PWMXH, O_PWMYL, and O_PWMYH four-channel signals are sent to the inverter main road drive inverter module; O_PWMZL, O_PWMZH, O_PWMOL, and O_PWMOH four-channel signals are sent to the inverter slave road drive inverter module, and the main road and the slave road output two 120V AC signals.

[0060] The main current detection unit 200 receives the main AC signal as input, collects the current signals A_IIX and A_IIY through the current sampling resistor, amplifies the signals into A_TIX and A_TIY through the operational amplifier, and sends them to the main microcontroller for detection.

[0061] like Figure 5 As shown, in one embodiment of the present application, the slave voltage detection unit 700 includes a third voltage divider circuit 710, a fourth voltage divider circuit 720 and a filter capacitor component 730. The first end of the third voltage divider circuit 710 is grounded. The first end of the fourth voltage divider circuit 720 is grounded. The second end of the third voltage divider circuit 710 is electrically connected to the third voltage signal end of the master single-chip control chip 110. The second end of the fourth voltage divider circuit 720 is electrically connected to the fourth voltage signal end of the master single-chip control chip 110. The third end of the third voltage divider circuit 710 is electrically connected to the first end of the filter capacitor component 730. The third end of the fourth voltage divider circuit 720 is electrically connected to the second end of the filter capacitor component 730. The third end of the filter capacitor component 730 is grounded.

[0062] Specifically, the inverter is powered on, the main M_POW_X and slave M_POW_Y DC high voltages are stable, the main single-chip microcomputer UC2 and the slave single-chip microcomputer US4 are powered on synchronously, and the main single-chip microcomputer sends 8 PWM wave signals: O_PWMXL, O_PWMXH, O_PWMYL, and O_PWMYH four-channel signals are sent to the inverter main road drive inverter module; O_PWMZL, O_PWMZH, O_PWMOL, and O_PWMOH four-channel signals are sent to the inverter slave road drive inverter module, and the main road and the slave road output two 120V AC signals.

[0063] The slave voltage detection unit 700 collects the voltage signals A_TUO and A_TUZ from the slave AC outputs OUTO and OUTY through voltage-dividing resistors and sends them to the slave microcontroller for detection.

[0064] like Figure 6As shown, in one embodiment of the present application, the slave current detection unit 600 includes a detection operator 610, a current signal resistor 620 and a decoupling resistor circuit 630. The first end of the decoupling resistor circuit 630 is electrically connected to the AC input end of the slave single-chip control chip 510. The second end of the decoupling resistor circuit 630 is electrically connected to the positive input end of the detection operator 610. The output end of the detection operator 610 is electrically connected to the reverse input end of the detection operator 610. The current signal resistor 620 is electrically connected to the connection link between the output end of the detection operator 610 and the reverse input end of the detection operator 610. The output end of the detection operator 610 is electrically connected to the current detection end of the slave single-chip control chip 510.

[0065] Specifically, the slave current detection unit 600 divides the input power supply through a voltage-dividing resistor, and sends the collected voltage signal A_THVZ to the slave MCU control unit 500 for detection.

[0066] like Fig. 9 As shown, in one embodiment of the present application, the circuit structure of the master drive inverter circuit 400 is the same as the circuit structure of the slave drive inverter circuit 800 .

[0067] The main drive inverter circuit 400 includes a first PWM chip 410 and a first P-type MOS transistor 420. The signal input end of the first PWM chip 410 is electrically connected to the first signal output end of the first group PWM output port 120. The signal output end of the first PWM chip 410 is electrically connected to the gate of the first P-type MOS transistor 420. The drain of the first P-type MOS transistor 420 is electrically connected to the first input power supply of the main MCU control unit 100. The source of the first P-type MOS transistor 420 is defined as the first output end of the main drive inverter circuit 400. The main drive inverter circuit 400 also includes a second PWM chip 430 and a second P-type MOS transistor 440. The signal input end of the second PWM chip 430 is electrically connected to the second signal output end of the first group PWM output port 120. The signal output end of the second PWM chip 430 is electrically connected to the gate of the second P-type MOS transistor 440. The drain of the second P-type MOS transistor 440 is electrically connected to the source of the first P-type MOS transistor 420. The source of the second P-type MOS transistor 440 is grounded.

[0068] like Figure 8As shown, in one embodiment of the present application, the main drive inverter circuit 400 further includes a first feedback capacitor 450 and a second feedback capacitor 460. The first feedback capacitor 450 is electrically connected to the connection link between the first input power supply terminal of the second PWM chip 430 and the second input power supply terminal of the second PWM chip 430. The second feedback capacitor 460 is electrically connected to the connection link between the first feedback capacitor 450 and the second input power supply terminal of the second PWM chip 430. The connection node between the first feedback capacitor 450 and the second feedback capacitor 460 is grounded. The main drive inverter circuit 400 further includes a third PWM chip 470 and a third P-type MOS transistor 480. The signal input terminal of the third PWM chip 470 is electrically connected to the third signal output terminal of the first group PWM output port 120. The signal output terminal of the third PWM chip 470 is electrically connected to the gate of the third P-type MOS transistor 480. The drain of the third P-type MOS transistor 480 is electrically connected to the second input power supply of the main MCU control unit 100. The source of the third P-type MOS tube 480 is defined as the second output terminal of the main drive inverter circuit 400. The main MCU control unit 100 also includes a fourth PWM chip 491 and a fourth P-type MOS tube 492. The signal input terminal of the fourth PWM chip 491 is electrically connected to the fourth signal output terminal of the first group of PWM output ports 120. The signal output terminal of the fourth PWM chip 491 is electrically connected to the gate of the fourth P-type MOS tube 492. The drain of the fourth P-type MOS tube 492 is electrically connected to the source of the third P-type MOS tube 480. The source of the fourth P-type MOS tube 492 is grounded. It is defined that a load of a digital isolation dual voltage output inverter is connected between the first output terminal of the main drive inverter circuit 400 and the second output terminal of the main drive inverter circuit 400.

[0069] The present embodiment relates to a digital isolation dual voltage output inverter, which realizes the PWM signal output of one circuit branch through the main MCU control unit 100, the main current detection unit 200 and the main voltage detection unit 300. The PWM signal output of another circuit branch is realized by the slave MCU control unit 500, the slave current detection unit 600 and the slave voltage detection unit 700. The main drive inverter circuit 400 realizes the voltage AC output of an input power supply according to the PWM signal of the main MCU control unit 100. The slave drive inverter circuit 800 realizes the voltage AC output of another input power supply according to the PWM signal of the slave MCU control unit 500. The main MCU control unit 100 receives the electrical signals of the main current detection unit 200 and the main voltage detection unit 300, and the slave MCU control unit 500 receives the electrical signals of the slave current detection unit 600 and the slave voltage detection unit 700. The main MCU control unit 100 sends 4 PWM wave signals to the main drive inverter circuit 400 to output 120V AC. The master MCU control unit 100 sends four PWM wave signals to the slave drive inverter circuit 800 to output another 120V AC power.

[0070] The digital isolation dual voltage output inverter is powered on, and the DC high voltage of M_POW_X of the master MCU control unit 100 and M_POW_Y of the slave MCU control unit 500 are stable.

[0071] The main single-chip microcomputer UC2 of the main MCU control unit 100 and the slave single-chip microcomputer US4 of the slave MCU control unit 500 are powered on synchronously, and the main single-chip microcomputer sends 8 PWM wave signals: O_PWMXL, O_PWMXH, O_PWMYL, O_PWMYH four-channel signals are sent to the main drive inverter circuit 400. O_PWMZL, O_PWMZH, O_PWMOL, O_PWMOH four-channel signals are sent to the slave drive inverter circuit 800, and the main drive inverter circuit 400 and the slave drive inverter circuit 800 output two 120V AC signals. In this way, the defect that the H-bridge inverter output voltage of the traditional inverter cannot meet the stable voltage demand is solved.

[0072] The first output end of the main drive inverter circuit 400 and the second output end of the main drive inverter circuit 400. The main single-chip microcomputer of the main MCU control unit 100 simultaneously controls the two drive inverter circuits of the main drive inverter circuit 400 and the slave drive inverter circuit 800, and uses the slave MCU control unit 500 to synchronize the signal detected by the slave drive inverter circuit 800 to the main single-chip microcomputer of the main MCU control unit 100 in real time, so that the main MCU control unit 100 and the slave MCU control unit 500 work together to realize the inverter dual-voltage output, and can output 2 120V AC or 1 240V AC at the same time.

[0073] Simply, the first output terminal and the second output terminal of the main drive inverter circuit 400 can be used as a 120V AC output terminal. Similarly, the circuit structure of the main drive inverter circuit 400 is the same as the circuit structure of the slave drive inverter circuit 800. The first output terminal and the second output terminal of the slave drive inverter circuit 800 can also be used as a 120V AC output terminal.

[0074] When the first output terminal of the master drive inverter circuit 400 is electrically connected to the first output terminal of the slave drive inverter circuit 800, and the second output terminal of the master drive inverter circuit 400 is electrically connected to the second output terminal of the slave drive inverter circuit 800, the master drive inverter circuit 400 and the slave drive inverter circuit 800 can be used as a common whole to form a 240V AC output terminal.

[0075] The technical features of the above-described embodiments can be combined arbitrarily, and the execution order of each method step is not limited. In order to make the description concise, all possible combinations of the technical features in the above-described embodiments are not described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification. The above-described embodiments only express several implementation methods of the present application, and the description is relatively specific and detailed, but it cannot be understood as a limitation on the scope of the patent of this application. It should be pointed out that for ordinary technicians in this field, without departing from the concept of the present application, several deformations and improvements can be made, which all belong to the scope of protection of the present application. Therefore, the scope of protection of the present application shall be based on the attached claims.

Claims

1. A dual MCU controlled digital isolation dual voltage output inverter, characterized in that: include: Main MCU control unit; A main current detection unit, electrically connected to the main MCU control unit; A main circuit voltage detection unit, electrically connected to the main circuit MCU control unit; A main drive inverter circuit is electrically connected to the main MCU control unit; A slave MCU control unit, electrically connected to the master MCU control unit; A slave current detection unit, electrically connected to the slave MCU control unit; A slave voltage detection unit, electrically connected to the slave MCU control unit; The slave drive inverter circuit is electrically connected to the main MCU control unit.

2. The dual MCU controlled digital isolation dual voltage output inverter according to claim 1, characterized in that: The main MCU control unit includes a main single-chip microcomputer control chip; The main single-chip control chip is provided with a first PWM output port; The main single-chip control chip is provided with a second PWM output port; The first PWM output ports are all electrically connected to the main drive inverter circuit; The second PWM output ports are all electrically connected to the slave drive inverter circuit.

3. The dual MCU controlled digital isolation dual voltage output inverter according to claim 2, characterized in that: The slave MCU control unit includes a slave single-chip microcomputer control chip; The slave single-chip microcomputer control chip is electrically connected to the master single-chip microcomputer control chip; The digital isolator is electrically connected to a connection link between the slave single-chip control chip and the master single-chip control chip.

4. The dual MCU controlled digital isolation dual voltage output inverter according to claim 3, characterized in that: The main voltage detection unit includes a first voltage dividing circuit, a second voltage dividing circuit and a capacitor component; The first end of the first voltage divider circuit is electrically connected to the power supply end of the main single-chip control chip; The first end of the second voltage divider circuit is electrically connected to the power supply end of the main single-chip microcomputer control chip; The second end of the first voltage divider circuit is electrically connected to the first voltage signal end of the main single-chip control chip; The second end of the second voltage divider circuit is electrically connected to the second voltage signal end of the main single-chip control chip; The third end of the first voltage divider circuit is electrically connected to the first end of the capacitor component; The third end of the second voltage divider circuit is electrically connected to the second end of the capacitor component; The third terminal of the capacitor component is grounded.

5. The dual MCU controlled digital isolation dual voltage output inverter according to claim 4, characterized in that: The main current detection unit includes a current operator, a feedback resistor and a signal circuit; The first end of the signal circuit is electrically connected to the AC input end of the main single-chip control chip; The second end of the signal circuit is electrically connected to the positive input end of the current operator; The output terminal of the current operator is electrically connected to the reverse input terminal of the current operator; The feedback resistor is electrically connected to a connection link between the output terminal of the current operator and the inverting input terminal of the current operator; The output end of the current operator is electrically connected to the current detection end of the main single-chip control chip.

6. The dual MCU controlled digital isolation dual voltage output inverter according to claim 5, characterized in that: The slave voltage detection unit includes a third voltage dividing circuit, a fourth voltage dividing circuit and a filter capacitor component; A first end of the third voltage divider circuit is grounded; A first terminal of the fourth voltage divider circuit is grounded; The second end of the third voltage divider circuit is electrically connected to the third voltage signal end of the main single-chip control chip; The second end of the fourth voltage divider circuit is electrically connected to the fourth voltage signal end of the main single-chip control chip; The third end of the third voltage divider circuit is electrically connected to the first end of the filter capacitor component; The third end of the fourth voltage divider circuit is electrically connected to the second end of the filter capacitor component; The third end of the filter volume assembly is grounded.

7. The dual MCU controlled digital isolation dual voltage output inverter according to claim 6, characterized in that: The slave current detection unit includes a detection operator, a current signal resistor and a decoupling resistor circuit; The first end of the decoupling resistor circuit is electrically connected to the AC input end of the slave single-chip microcomputer control chip; The second end of the decoupling resistor circuit is electrically connected to the positive input end of the detection operator; The output terminal of the detection operator is electrically connected to the reverse input terminal of the detection operator; The current signal resistor is electrically connected to the connection link between the output end of the detection operator and the reverse input end of the detection operator; The output end of the detection operator is electrically connected to the current detection end of the slave single-chip control chip.

8. The dual MCU controlled digital isolation dual voltage output inverter according to claim 7, characterized in that: The circuit structure of the master drive inverter circuit is the same as the circuit structure of the slave drive inverter circuit.

9. The dual MCU controlled digital isolation dual voltage output inverter according to claim 8, characterized in that: The main drive inverter circuit includes a first PWM chip and a first P-type MOS tube; The signal input terminal of the first PWM chip is electrically connected to the first signal output terminal of the first group of PWM output ports; The signal output terminal of the first PWM chip is electrically connected to the gate of the first P-type MOS tube; The drain of the first P-type MOS tube is electrically connected to the first input power supply of the main MCU control unit; Define the source of the first P-type MOS transistor as the first output end of the main driving inverter circuit; The main drive inverter circuit also includes a second PWM chip and a second P-type MOS tube; The signal input terminal of the second PWM chip is electrically connected to the second signal output terminal of the first group of PWM output ports; The signal output terminal of the second PWM chip is electrically connected to the gate of the second P-type MOS tube; The drain of the second P-type MOS transistor is electrically connected to the source of the first P-type MOS transistor; The source of the second P-type MOS tube is grounded.

10. The dual MCU controlled digital isolation dual voltage output inverter according to claim 9, characterized in that: The main drive inverter circuit also includes a first feedback capacitor and a second feedback capacitor; The first feedback capacitor is electrically connected to a connection link between a first input power terminal of the second PWM chip and a second input power terminal of the second PWM chip; The second feedback capacitor is electrically connected to a connection link between the first feedback capacitor and a second input power supply terminal of the second PWM chip; A connection node between the first feedback capacitor and the second feedback capacitor is grounded; The main drive inverter circuit also includes a third PWM chip and a third P-type MOS tube; The signal input terminal of the third PWM chip is electrically connected to the third signal output terminal of the first group of PWM output ports; The signal output end of the third PWM chip is electrically connected to the gate of the third P-type MOS tube; The drain of the third P-type MOS tube is electrically connected to the second input power supply of the main MCU control unit; Define the source of the third P-type MOS transistor as the second output end of the main driving inverter circuit; The main MCU control unit also includes a fourth PWM chip and a fourth P-type MOS tube; The signal input terminal of the fourth PWM chip is electrically connected to the fourth signal output terminal of the first group of PWM output ports; The signal output end of the fourth PWM chip is electrically connected to the gate of the fourth P-type MOS tube; The drain of the fourth P-type MOS tube is electrically connected to the source of the third P-type MOS tube; The source of the fourth P-type MOS tube is grounded; It is defined that a load of a digital isolation dual voltage output inverter is connected between the first output end of the main drive inverter circuit and the second output end of the main drive inverter circuit.

Images