Reset circuit

Abstract

The invention belongs to the related technical field of BMS hardware key expansion circuit technology, and particularly relates to a reset circuit. A trigger circuit is arranged on a reset circuit and comprises a trigger module, a first trigger circuit and a second trigger circuit, the trigger module is connected with the first trigger circuit and the second trigger circuit, the trigger module is used for receiving an external trigger action and outputting a trigger signal, and a delay circuit and a first switch circuit are arranged for delayed on-off, the first trigger circuit is connected with the timing end of the controlled module so as to detect the rising edge of the trigger signal and achieve software reset. Hardware resetting is performed through the first trigger circuit, and software resetting of the second trigger circuit is set, so that a hardware resetting circuit is added on the basis of original software resetting of the circuit, and resetting can be realized by unpacking when software is stuck.

Description

Technical Field

[0001] The present technology belongs to the technical field related to BMS hardware button expansion circuit technology, and in particular relates to a reset circuit. Background Art

[0002] The battery management BMS system is a lithium battery management system used in communication base station backup batteries and home energy storage. During the operation of the BMS, it may get stuck, and there is usually a reset button on the BMS to reset the BMS.

[0003] In the existing BMS reset button function technology, it is mainly based on the MCU's software reset / sleep / wake-up. When the I / O port detects a signal and determines that software reset / sleep / wake-up is required, the program will automatically run the corresponding software to meet the needs. When the program is stuck, the BMS will not be able to perform software reset. At this time, the battery pack can only be unpacked and the power must be turned off and restarted to restore the BMS to normal operation. This problem will increase the difficulty of BMS maintenance and operation. Summary of the invention

[0004] Based on the above problems, the present invention proposes a reset circuit. By setting hardware reset and software reset modes in the reset circuit, the BMS reset has two different reset modes, avoiding the need to unpack and power off the battery pack to reset when the software is stuck, thereby increasing the difficulty of maintenance and operation of the BMS.

[0005] The purpose of the present invention is achieved through the following technical solutions:

[0006] In a first aspect, the present invention provides a reset circuit, comprising:

[0007] A trigger circuit comprises a trigger module, a first trigger circuit and a second trigger circuit, wherein the trigger module is connected to the first trigger circuit and the second trigger circuit, and the trigger module is used to receive an external trigger action and output a trigger signal;

[0008] A delay circuit is connected to the output end of the second trigger circuit and is used to delay the output of the trigger signal output by the trigger circuit;

[0009] and a first switch circuit connected to the output end of the delay module, for converting the trigger signal output by the delay circuit into a reset signal, and outputting the reset signal to the reset end of the controlled module to achieve hardware reset;

[0010] Wherein, the first trigger circuit is connected to the timing end of the controlled module to detect the rising edge of the trigger signal and implement software reset.

[0011] By setting a trigger circuit on the reset circuit, including a trigger module, a first trigger circuit and a second trigger circuit, the trigger module is connected to the first trigger circuit and the second trigger circuit, and the trigger module is used to receive an external trigger action and output a trigger signal, and a delay circuit and a first switch circuit are set to delay switching, wherein the first trigger circuit is connected to the timing end of the controlled module to detect the rising edge of the trigger signal and implement software reset. The hardware is reset by the first trigger circuit, and the software reset of the second trigger circuit is set at the same time, so as to realize the circuit on the basis of the original software reset, and add a hardware reset circuit, so as to avoid the need to unpack to achieve reset when the software is stuck.

[0012] In some embodiments, the trigger module is provided with a second switch circuit and a third switch circuit. The second switch circuit is connected within the first trigger circuit to switch the first trigger circuit on and off; the third switch circuit is connected within the second trigger circuit to switch the second trigger circuit on and off.

[0013] By setting the second switch circuit and the third switch circuit in the trigger circuit, the reset circuit can control the on and off of the first trigger circuit and the second trigger circuit respectively through the second switch circuit and the third switch circuit to select software reset or hardware reset.

[0014] In some embodiments, the trigger module is a trigger chip, the trigger chip is provided with a trigger button, and the trigger action is pressing the trigger button;

[0015] The trigger chip is provided with a first pin and a second pin, and the first switch circuit is turned on by the first pin and the second pin when the trigger button is pressed, and is turned off otherwise;

[0016] The trigger chip is also provided with a third pin and a fourth pin, through which the second switch circuit is turned on when the trigger button is pressed, and is turned off otherwise.

[0017] The trigger module is a trigger chip, so that when the trigger button of the trigger chip is pressed, an external trigger action can be detected to achieve external active reset.

[0018] In some embodiments, the first trigger circuit is provided with a reset trigger terminal and a first power input terminal, the reset trigger terminal is connected to the timing terminal of the controlled module, and the first power input terminal is input with a voltage from an external power supply and is connected to the reset trigger terminal;

[0019] The second switch circuit is arranged between the first power input terminal and the reset trigger terminal, or the first pin of the second switch circuit is connected to the first power input terminal and the second pin is grounded to realize the voltage change of the timing terminal of the controlled module.

[0020] A reset trigger end is provided through the first trigger circuit. After receiving the signal from the software end, the reset circuit will perform a software reset through the first trigger circuit, and detect the rising edge of the signal of the trigger module and the trigger time of the trigger chip to determine the reset mode, and pull down the input of the timing end through the first switch circuit. When released, the rising edge can be detected to determine the reset signal.

[0021] In some embodiments, the first trigger circuit includes a first resistor, a second resistor, and a first capacitor;

[0022] One end of the first resistor is connected to the first power input terminal, the other end of the first resistor is connected to the first pin, one end of the first capacitor and one end of the second resistor, the other end of the second resistor is connected to the reset trigger end and the timing end of the controlled module, and the other end of the first capacitor and the second pin are grounded.

[0023] In some embodiments, the second trigger circuit is provided with a second power input terminal and a second power output terminal, the third switching circuit is arranged between the second power input terminal and the second power output terminal, the third pin is connected to the second power input terminal, the fourth pin is connected to the second power output terminal, and the second power input terminal is connected to an external power supply.

[0024] By setting the second trigger circuit, when the trigger chip is pressed, the second switch circuit is turned on, and the second trigger circuit outputs a high level signal.

[0025] In some embodiments, the second trigger circuit includes a third resistor and a fourth resistor, one end of the third resistor is connected to the second power supply input terminal, the other end of the third resistor is connected to the third pin, one end of the fourth resistor is connected to the fourth pin, and the other end of the fourth resistor is the output terminal of the second trigger circuit.

[0026] In some embodiments, the delay circuit includes a comparison circuit and a buffer circuit; the comparison circuit is provided with a first comparison terminal and a second comparison terminal; the first comparison terminal is connected to a reference voltage source;

[0027] The input end of the cache circuit is connected to the output end of the second trigger circuit, the output end of the cache circuit is connected to the input end of the comparison circuit, and the output end of the cache circuit is connected to the second comparison end of the comparison circuit; the output end of the second trigger circuit is the output end of the comparison circuit.

[0028] By setting a delay circuit, the signal can be cached and delayed through a cache circuit. After caching for a certain period of time, the input comparison circuit is compared, and after a certain period of time, the second comparison end of the input is greater than the reference first comparison end, thereby outputting a trigger signal through the output end of the output comparison circuit.

[0029] In some embodiments, the comparison circuit includes a comparator, a fifth resistor, a sixth resistor, a seventh resistor, an eighth resistor, a second capacitor, and a third capacitor; the cache circuit includes a fourth capacitor and a fifth capacitor;

[0030] The fourth capacitor and the fifth capacitor are arranged between the ground terminal and the negative terminal of the comparator; the fifth resistor and the second capacitor are connected between the positive terminal of the comparator and the ground terminal; the sixth resistor is connected between the reference voltage source and the positive terminal of the comparator; the seventh resistor and the eighth resistor are connected in series and connected between the reference voltage source and the output terminal of the comparator; one end of the third capacitor is connected between the seventh resistor and the eighth resistor, and the other end of the third capacitor is grounded.

[0031] The trigger signal is cached and delayed by capacitors to avoid false touches and reset failures caused by unstable signals.

[0032] In some implementations, the first switch circuit includes: a first MOS transistor, a second MOS transistor, a ninth resistor, a tenth resistor, an eleventh resistor, a twelfth resistor, a fourth capacitor, and a diode;

[0033] The first MOS tube is a PMOS tube, the second MOS tube is an NMOS tube, the gate of the first MOS tube is connected to the output end of the comparator, the source of the first MOS tube is connected between the seventh resistor and the eighth resistor, the drain of the first MOS tube is connected to one end of the ninth resistor, the other end of the ninth resistor is connected to the gate of the second MOS tube, the source of the second MOS tube is grounded, the tenth resistor is connected between the gate and the source of the second MOS tube, the drain of the second MOS tube is connected to one end of the twelfth resistor, the other end of the twelfth resistor is connected to the reset end of the controlled module, the drain of the second MOS tube is also connected to one end of the eleventh resistor, the other end of the eleventh resistor is connected to the third power input end, one end of the diode is connected to the drain of the second MOS tube, the positive end of the diode is connected to the drain of the second MOS tube, the negative end of the diode is connected to the third power input end, and the sixth capacitor is connected to the drain of the second MOS tube and the ground end.

[0034] By designing a MOS tube switch circuit, after receiving a trigger signal from the delay circuit, the first switch circuit is turned on, so that the reset end of the controlled module is grounded, so that the reset end receives a reset signal.

[0035] The beneficial effects of the reset circuit of the present invention are:

[0036] By setting a trigger circuit on the reset circuit, including a trigger module, a first trigger circuit and a second trigger circuit, the trigger module is connected to the first trigger circuit and the second trigger circuit, and the trigger module is used to receive an external trigger action and output a trigger signal, and a delay circuit and a first switch circuit are set to delay switching, wherein the first trigger circuit is connected to the timing end of the controlled module to detect the rising edge of the trigger signal and implement software reset. The hardware is reset by the first trigger circuit, and the software reset of the second trigger circuit is set at the same time, so as to realize the circuit on the basis of the original software reset, and add a hardware reset circuit, so as to avoid the need to unpack to achieve reset when the software is stuck. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] Figure 1 A framework diagram of a reset circuit of the present invention;

[0038] Figure 2 A framework of a reset circuit of the present invention Figure 2 ;

[0039] Figure 3 The figure is a circuit schematic diagram of a reset circuit of the present invention.

[0040] Reference numerals:

[0041] R1, first resistor; R2, second resistor; R3, third resistor; R4, fourth resistor; R5, fifth resistor; R6, sixth resistor; R7, seventh resistor; R8, eighth resistor; R9, ninth resistor; R10, tenth resistor; R11, eleventh resistor; R12, twelfth resistor;

[0042] C1, first capacitor; C2, second capacitor; C3, third capacitor; C4, fourth capacitor; C5, fifth capacitor;

[0043] D1, diode;

[0044] Q1, the first MOS tube; Q2, the second MOS tube;

[0045] U1, trigger chip; U2, comparator;

[0046] VCC1, first power input terminal; DELAY, reset trigger terminal; VCC2, reference voltage source; PC1, timing terminal of controlled module; VCC3, third power input terminal; RESET, reset terminal of controlled module;

[0047] MCU, controlled module; 21, trigger module; 211, second switch circuit; 212, third switch circuit; 22, first trigger circuit; 22, second trigger circuit; 3, first switch circuit; 4, delay circuit. DETAILED DESCRIPTION

[0048] The preferred embodiments of the present application are described in detail below in conjunction with the accompanying drawings so that the advantages and features of the present application can be more easily understood by those skilled in the art, thereby making a clearer definition of the protection scope of the present application.

[0049] Please refer to the drawings, where the same component symbols represent the same components, and the principles of the present application are illustrated by implementing them in an appropriate computing environment. The following description is based on the illustrated specific embodiments of the present application, which should not be considered as limiting other specific embodiments of the present application that are not described in detail herein.

[0050] The term "module" as used herein may be a software or hardware object executed on the computing system. The different components, modules, engines, and services described herein may be implementation objects on the computing system. The apparatus and methods described herein may be implemented in software, or in hardware, and all are within the scope of protection of this application.

[0051] Reference to "embodiments" herein means that a particular feature, structure, or characteristic described in conjunction with the embodiments may be included in at least one embodiment of the present application. The appearance of the phrase in various locations in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment that is mutually exclusive with other embodiments. It is explicitly and implicitly understood by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0052] In the description of this application, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, an electrical connection, or mutual communication; it can be a direct connection, or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0053] Embodiment 1:

[0054] like Figure 1 As shown, this embodiment provides a reset circuit, which includes:

[0055] The trigger circuit includes a trigger module 21, a first trigger circuit 22 and a second trigger circuit 22, wherein the trigger module 21 is connected to the first trigger circuit 22 and the second trigger circuit 22, and the trigger module 21 is used to receive an external trigger action and output a trigger signal;

[0056] The delay circuit 4 is connected to the output end of the second trigger circuit 22 and is used to delay the output of the trigger signal output by the trigger circuit;

[0057] and a first switch circuit 3 connected to the output end of the delay module, for converting the trigger signal output by the delay circuit 4 into a reset signal, and outputting the reset signal to the reset end RESET of the controlled module MCU to achieve hardware reset;

[0058] The first trigger circuit 22 is connected to the timing terminal PC1 of the controlled module MCU to detect the rising edge of the trigger signal and implement software reset.

[0059] Specifically, a trigger circuit is provided, and the trigger circuit is provided with a trigger module 21 to accept an external trigger action and output a trigger signal. The trigger module 21 can be a pressing member, such as a key, a button, a switch, etc. The trigger module 21 can also be a sensor module, such as an infrared sensor, a temperature sensor, etc. The trigger module 21 can also be a relay. After accepting an external trigger action, the relay is turned off and a trigger signal is output. A first trigger circuit 22 and a second trigger circuit 22 are provided, which are respectively used to implement software reset and hardware reset, and the reset mode can be selected by signal selection, such as selecting software reset and hardware reset by judging the high and low levels of the signal, or by switch selection, and can be selected when the circuit reaches certain conditions. For example, if multiple trigger actions and trigger signals are detected, it can be judged that the software trigger is invalid, and hardware triggering is selected. Further, when the hardware is triggered, a delay circuit 4 is provided, and the delay circuit 4 is used to delay the trigger signal to avoid abnormal reset caused by hardware mis-touch. The delay circuit 4 can adopt capacitor delay, chip delay, delay on and off, etc. The reset end is usually in a low level state, so a first switch circuit 3 can be provided in the delay circuit 4. The first switch circuit 3 is used to pull down the reset end RESET signal of the controlled module MCU to change the trigger circuit into a reset signal of a low level signal. Furthermore, a pull-up power supply can be set at the reset end RESET of the controlled module MCU so that the reset end RESET of the controlled module MCU is at a high level when in normal working non-reset state.

[0060] More specifically, the controlled module MCU may be the MCU of the BMS, and the reset terminal RESET of the controlled module MCU is the reset terminal of the MCU.

[0061] By setting a trigger circuit on the reset circuit, including a trigger module 21, a first trigger circuit 22 and a second trigger circuit 22, the trigger module 21 is connected to the first trigger circuit 22 and the second trigger circuit 22, and the trigger module 21 is used to receive an external trigger action and output a trigger signal, and a delay circuit 4 and a first switch circuit 3 are set to delay switching, wherein the first trigger circuit 22 is connected to the timing terminal PC1 of the controlled module MCU to detect the rising edge of the trigger signal and implement software reset. The hardware is reset by the first trigger circuit 22, and the software reset of the second trigger circuit 22 is set at the same time, so as to realize the circuit on the basis of the original software reset, and add a hardware reset circuit to avoid the software stuck. Unpacking is required to achieve reset.

[0062] Embodiment 2:

[0063] like Figure 2-3 As shown, this embodiment further optimizes and explains the circuit structure proposed in Example 1:

[0064] In some embodiments, the trigger module 21 is provided with a second switch circuit 211 and a third switch circuit 212. The second switch circuit 211 is connected within the first trigger circuit 22 to switch the first trigger circuit 22 on and off; the third switch circuit 212 is connected within the second trigger circuit 22 to switch the second trigger circuit 22 on and off.

[0065] Specifically, the trigger module 21 is provided with a second switch circuit 211 and a third switch circuit 212 to respectively realize the on and off of the first trigger circuit 22 and the on and off of the second trigger circuit 22, so that after the trigger module 21 sends a trigger signal, it can turn on and off the second switch circuit 211 and the third switch circuit 212, so that the first trigger circuit 22, or the second trigger circuit 22 can output the trigger signal normally.

[0066] Furthermore, the second switch circuit 211 and the third switch circuit 212 can be simultaneously controlled by the trigger module 21 to switch on and off simultaneously, so as to realize the simultaneous switching on and off of the first trigger circuit 22 and the second trigger circuit 22. However, in order to distinguish between hardware reset and software reset, an additional trigger signal can be set in the first trigger circuit 22, so that when the additional trigger signal is triggered, the trigger signal can flow normally to the timing terminal PC1 of the controlled module MCU only after receiving the additional trigger signal. At the same time, the additional trigger signal can make the reset terminal RESET of the controlled module MCU invalid, avoiding the reset failure problem caused by the simultaneous appearance of two reset signals.

[0067] By setting the second switch circuit 211 and the third switch circuit 212 in the trigger circuit, the reset circuit can control the on and off of the first trigger circuit 22 and the second trigger circuit 22 respectively through the second switch circuit 211 and the third switch circuit 212 to select software reset or hardware reset.

[0068] In some embodiments, the trigger module 21 is a trigger chip U1, the trigger chip U1 is provided with a trigger button, and the trigger action is pressing the trigger button;

[0069] The trigger chip U1 is provided with a first pin and a second pin, and the first switch circuit 3 is turned on through the first pin and the second pin when the trigger button is pressed, and is turned off otherwise;

[0070] The trigger chip U1 is further provided with a third pin and a fourth pin. The second switch circuit 211 is turned on through the third pin and the fourth pin when the trigger button is pressed, and is turned off otherwise.

[0071] Specifically, the trigger module 21 may be a trigger chip U1, and the trigger chip U1 is provided with a trigger button to close the first switch circuit 3 and the second switch circuit 211 through a trigger pressing action, so as to output a trigger signal through the first trigger circuit 22 and the second trigger circuit 22. When the trigger chip U1 is pressed, the first pin and the second pin are turned on, and the third pin and the fourth pin are turned on, so as to realize the normal operation of the first trigger circuit 22 and the second trigger circuit 22.

[0072] The trigger module 21 is used as the trigger chip U1 , so that when the trigger button of the trigger chip U1 is pressed, an external trigger action can be detected to achieve an external active reset.

[0073] In some embodiments, the first trigger circuit 22 is provided with a reset trigger terminal DELAY and a first power input terminal VCC1, the reset trigger terminal DELAY is connected to the timing terminal PC1 of the controlled module MCU, the first power input terminal VCC1 is input with voltage from an external power supply and is connected to the reset trigger terminal DELAY;

[0074] The second switch circuit 211 is arranged between the first power input terminal VCC1 and the reset trigger terminal DELAY, or the first pin of the second switch circuit 211 is connected to the first power input terminal VCC1 and the second pin is grounded to realize the voltage change of the timing terminal PC1 of the controlled module MCU.

[0075] Specifically, a reset trigger terminal DELAY is provided, and the reset trigger terminal DELAY is used as an additional trigger signal for software reset, so as to determine the trigger reset mode through the pin. At the same time, when the reset trigger terminal DELAY is triggered, the timing terminal PC1 of the controlled module MCU connected to the first trigger signal will be valid, and the software reset can be performed. On the contrary, when the reset trigger terminal DELAY is not triggered, the reset terminal RESET of the controlled module MCU is valid, and the hardware reset can be performed. A first power input terminal VCC1 is provided, and an external power input voltage is connected, which is usually 3.3V. The first power input terminal VCC1 realizes that the controlled module MCU is at a high level in normal state. After being triggered, after the second switch circuit 211 is turned on, the potential of the timing terminal PC1 of the controlled module MCU is pulled down, and timing starts. After releasing the trigger module 21, the timing terminal PC1 of the controlled module MCU restores the high potential, so that the presence of the rising edge of the level signal can be detected, and the rising edge and duration at this time are recorded. According to the duration, the reset mode is selected, such as the reset / sleep / wake-up function. More specifically, the reset function is 1S, the sleep function is 2S, and the wake-up function is 3S.

[0076] A reset trigger terminal DELAY is set through the first trigger circuit 22. After receiving the signal from the software end, the reset circuit will perform a software reset through the first trigger circuit 22, and detect the rising edge of the signal of the trigger module 21 and the trigger time of the trigger chip U1 to determine the reset mode, and pull down the input of the timing end through the first switch circuit 3. When released, the rising edge can be detected to determine the reset signal.

[0077] In some embodiments, the first trigger circuit 22 includes a first resistor R1, a second resistor R2, and a first capacitor C1;

[0078] One end of the first resistor R1 is connected to the first power input terminal VCC1, the other end of the first resistor R1 is connected to the first pin, one end of the first capacitor C1 and one end of the second resistor R2, the other end of the second resistor R2 is connected to the reset trigger terminal DELAY and the timing terminal PC1 of the controlled module MCU, and the other end of the first capacitor C1 and the second pin are grounded.

[0079] Specifically, the first resistor R1 is a 1K resistor of 0603, and the second resistor R2 is a 10K resistor of 0603. The first capacitor C1 is a 0.1uF capacitor of 0603. The first resistor R1 can be used as a voltage divider resistor, or form a filter circuit with the first capacitor C1 to filter the signal. The second resistor R2 can be used as a pull-up resistor to divide the 3.3V voltage.

[0080] In some embodiments, the second trigger circuit 22 is provided with a second power input terminal and a second power output terminal, the third switch circuit 212 is arranged between the second power input terminal and the second power output terminal, the third pin is connected to the second power input terminal, the fourth pin is connected to the second power output terminal, and the second power input terminal is connected to an external power supply.

[0081] Specifically, the second trigger circuit 22 outputs a high level to the second power output terminal through the second power input terminal. The second trigger circuit 22 is generally connected to 3.3V to realize the on-off of the subsequent switch circuit. The trigger signal from the second power input terminal to the second power output terminal is blocked or conducted through the third switch circuit 212, so that when the trigger module 21 is pressed, the high level can be output from the second power input terminal to the second power output terminal.

[0082] The first power input terminal VCC1 and the second power input terminal may be consistent, both of which are 3.3V, and may also be the same port for power input.

[0083] The second trigger circuit 22 is provided so that when the trigger chip U1 is pressed, the second switch circuit 211 is turned on, and the second trigger circuit 22 outputs a high level signal.

[0084] In some embodiments, the second trigger circuit 22 includes a third resistor R3 and a fourth resistor R4, one end of the third resistor R3 is connected to the second power supply input terminal, the other end of the third resistor R3 is connected to the third pin, one end of the fourth resistor R4 is connected to the fourth pin, and the other end of the fourth resistor R4 is the output end of the second trigger circuit 22.

[0085] Specifically, the third resistor R3 may be a 220K resistor of 0603, the fourth resistor R4 may be a 1K resistor of 0603, and the third resistor R3 may be a voltage dividing resistor.

[0086] In some embodiments, the delay circuit 4 includes a comparison circuit and a buffer circuit; the comparison circuit is provided with a first comparison terminal and a second comparison terminal; the first comparison terminal is connected to a reference voltage source VCC2;

[0087] The input end of the cache circuit is connected to the output end of the second trigger circuit 22, the output end of the cache circuit is connected to the input end of the comparison circuit, and the output end of the cache circuit is connected to the second comparison end of the comparison circuit; the output end of the second trigger circuit 22 is the output end of the comparison circuit.

[0088] Specifically, the delay circuit 4 is provided with a comparison circuit and a buffer circuit, and the comparison circuit is provided with a first comparison terminal and a second comparison terminal. After being buffered by the buffer circuit for a certain period of time, the output is output to the comparison circuit for comparison output to avoid abnormal reset caused by false touch. After the output terminal of the second trigger circuit 22 passes through the comparison circuit and meets the output voltage, it outputs a high level at the output terminal of the comparison circuit, thereby realizing the subsequent triggering of the first switch circuit 3.

[0089] By setting a delay circuit 4, the signal can be cached and delayed through a cache circuit. After caching for a certain period of time, the input comparison circuit is compared, and after a certain period of time, the second comparison end of the input is greater than the reference first comparison end, thereby outputting a trigger signal through the output end of the output comparison circuit.

[0090] In some embodiments, the comparison circuit includes a comparator U2, a fifth resistor R5, a sixth resistor R6, a seventh resistor R7, an eighth resistor R8, a second capacitor C2, and a third capacitor C3; the cache circuit includes a fourth capacitor C4 and a fifth capacitor C5;

[0091] The fourth capacitor C4 and the fifth capacitor C5 are arranged between the ground terminal and the negative terminal of the comparator U2; the fifth resistor R5 and the second capacitor C2 are connected between the positive terminal of the comparator U2 and the ground terminal; the sixth resistor R6 is connected between the reference voltage source VCC2 and the positive terminal of the comparator U2; the seventh resistor R7 and the eighth resistor R8 are connected in series and connected between the reference voltage source VCC2 and the output terminal of the comparator U2; one end of the third capacitor C3 is connected between the seventh resistor R7 and the eighth resistor R8, and the other end of the third capacitor C3 is grounded.

[0092] More specifically, the fourth capacitor C4 and the fifth capacitor C5 are 10uF capacitors of 0603, the fifth resistor R5 is a 510K resistor of 0603, the sixth resistor R6 is a 100K resistor of 0603, the seventh resistor R7 is a 10K resistor of 0603, and the eighth resistor R8 is a 100K resistor of 0603. The comparator U2 is a comparator U2 of LTC331YT5, the second capacitor C2 is a 0.1uF capacitor of 0603, and the third capacitor C3 is a 0.1uF capacitor of 0603. Among them, the fourth capacitor C4 and the fifth capacitor C5 can both be delay capacitors to delay the input end of the comparator U2. After the fourth capacitor C4 and the fifth capacitor C5 are charged, the voltage can be continuously output to the comparator U2, and the others such as the second capacitor C2 and the third capacitor C3 are all conventional filter capacitors. The fifth resistor R5, the sixth resistor R6, the seventh resistor R7 and the eighth resistor R8 are also voltage-dividing filter resistors.

[0093] The trigger signal is cached and delayed by capacitors to avoid false touches and reset failures caused by unstable signals.

[0094] In some embodiments, the first switch circuit 3 includes: a first MOS transistor Q1, a second MOS transistor Q2, a ninth resistor R9, a tenth resistor R10, an eleventh resistor R11, a twelfth resistor R12, a sixth capacitor and a diode D1;

[0095] The first MOS tube Q1 is a PMOS tube, the second MOS tube Q2 is an NMOS tube, the gate of the first MOS tube Q1 is connected to the output end of the comparator U2, the source of the first MOS tube Q1 is connected between the seventh resistor R7 and the eighth resistor R8, the drain of the first MOS tube Q1 is connected to one end of the ninth resistor R9, the other end of the ninth resistor R9 is connected to the gate of the second MOS tube Q2, the source of the second MOS tube Q2 is grounded, the tenth resistor R10 is connected between the gate and the source of the second MOS tube Q2, the drain of the second MOS tube Q2 is connected to The sixth capacitor is connected to one end of the twelfth resistor R12, the other end of the twelfth resistor R12 is connected to the reset end RESET of the controlled module MCU, the drain of the second MOS tube Q2 is also connected to one end of the eleventh resistor R11, the other end of the eleventh resistor R11 is connected to the third power input end VCC3, one end of the diode D1 is connected to the drain of the second MOS tube Q2, the positive end of the diode D1 is connected to the drain of the second MOS tube Q2, the negative end of the diode D1 is connected to the third power input end VCC3, and the sixth capacitor is connected to the drain of the second MOS tube Q2 and the ground end.

[0096] Specifically, the first MOS transistor Q1 may be MEBSS84, the second MOS transistor Q2 may be ME2N7002E, the ninth resistor R9 may be a 1K resistor of 0603, the tenth resistor R10 may be a 1M resistor of 0603, the eleventh resistor R11 may be a 10K resistor of 0603, the twelfth resistor R12 may be a 1K resistor of 0603, the diode D1 may be 1SS355, and the sixth capacitor may be a 0.1uF capacitor of 0603. The ninth resistor R9, the eighth resistor R8, the tenth resistor R10, the eleventh resistor R11 and the twelfth resistor R12 are all voltage-dividing filter resistors. The fourth capacitor C4 is a filter capacitor.

[0097] By designing the MOS switch circuit, after receiving the trigger signal of the delay circuit 4, the first switch circuit 3 is turned on, so that the reset terminal RESET of the controlled module MCU is grounded, so that the reset terminal receives the reset signal.

[0098] Embodiment 3:

[0099] This embodiment is based on the reset circuit proposed in Example 1 and Example 2, and proposes a specific implementation method in BMS, specifically including: a minimum MCU system of BMS is provided, the MCU is STM32F103VCT6B, and the first trigger circuit 22 of the reset circuit is connected to any interface PC1~PC3 of the MCU to achieve software reset, and the first switch circuit 3 is connected to the NRST port to achieve hardware reset.

[0100] The implementation modes of the present application are described in detail above in conjunction with the accompanying drawings, but the present application is not limited to the above implementation modes, and various changes can be made within the knowledge scope of ordinary technicians in this field without departing from the purpose of the present application.

Claims

1. A reset circuit, characterized in that: include: A trigger circuit, comprising a trigger module (21), a first trigger circuit (22) and a second trigger circuit (22), wherein the trigger module (21) is connected to the first trigger circuit (22) and the second trigger circuit (22), and the trigger module (21) is used to receive an external trigger action and output a trigger signal; A delay circuit (4) connected to the output end of the second trigger circuit (22) and used for delaying the output of the trigger signal output by the trigger circuit; and a first switch circuit (3), connected to the output end of the delay module, for converting the trigger signal output by the delay circuit (4) into a reset signal, and outputting the reset signal to the reset end (RESET) of the controlled module (MCU) to achieve hardware reset; The first trigger circuit (22) is connected to the timing terminal (PC1) of the controlled module (MCU) to detect the rising edge of the trigger signal and implement software reset.

2. The reset circuit according to claim 1, characterized in that: The trigger module (21) is provided with a second switch circuit (211) and a third switch circuit (212); the second switch circuit (211) is connected within the first trigger circuit (22) to switch the first trigger circuit (22) on and off; the third switch circuit (212) is connected within the second trigger circuit (22) to switch the second trigger circuit (22) on and off.

3. The reset circuit according to claim 2, characterized in that: The trigger module (21) is a trigger chip (U1), the trigger chip (U1) is provided with a trigger button, and the trigger action is pressing the trigger button; The trigger chip (U1) is provided with a first pin and a second pin, and the first switch circuit (3) is turned on through the first pin and the second pin when the trigger button is pressed, and is turned off otherwise; The trigger chip (U1) is also provided with a third pin and a fourth pin, and the second switch circuit (211) is turned on through the third pin and the fourth pin when the trigger button is pressed, and is turned off otherwise.

4. The reset circuit according to claim 3, characterized in that: The first trigger circuit (22) is provided with a reset trigger terminal (DELAY) and a first power input terminal (VCC1), the reset trigger terminal (DELAY) is connected to the timing terminal (PC1) of the controlled module (MCU), and the first power input terminal (VCC1) is input with voltage from an external power supply and is connected to the reset trigger terminal (DELAY); The second switch circuit (211) is arranged between the first power input terminal (VCC1) and the reset trigger terminal (DELAY), or the first pin of the second switch circuit (211) is connected to the first power input terminal (VCC1) and the second pin is grounded, so as to realize the voltage change of the timing terminal (PC1) of the controlled module (MCU).

5. The reset circuit according to claim 4, characterized in that: The first trigger circuit (22) comprises a first resistor (R1), a second resistor (R2) and a first capacitor (C1); One end of the first resistor (R1) is connected to the first power input terminal (VCC1), the other end of the first resistor (R1) is connected to the first pin, one end of the first capacitor (C1) and one end of the second resistor (R2), the other end of the second resistor (R2) is connected to the reset trigger terminal (DELAY) and the timing terminal (PC1) of the controlled module (MCU), and the other end of the first capacitor (C1) and the second pin are grounded.

6. The reset circuit according to claim 3, characterized in that: The second trigger circuit (22) is provided with a second power input terminal and a second power output terminal, the third switch circuit (212) is provided between the second power input terminal and the second power output terminal, the third pin is connected to the second power input terminal, the fourth pin is connected to the second power output terminal, and the second power input terminal is connected to an external power supply.

7. The reset circuit according to claim 6, characterized in that: The second trigger circuit (22) comprises a third resistor (R3) and a fourth resistor (R4), one end of the third resistor (R3) is connected to the second power supply input terminal, the other end of the third resistor (R3) is connected to the third pin, one end of the fourth resistor (R4) is connected to the fourth pin, and the other end of the fourth resistor (R4) is the output end of the second trigger circuit (22).

8. The reset circuit according to claim 1, characterized in that: The delay circuit (4) comprises a comparison circuit and a buffer circuit; the comparison circuit is provided with a first comparison terminal and a second comparison terminal; the first comparison terminal is connected to a reference voltage source (VCC2); The input end of the cache circuit is connected to the output end of the second trigger circuit (22), the output end of the cache circuit is connected to the input end of the comparison circuit, and the output end of the cache circuit is connected to the second comparison end of the comparison circuit; the output end of the second trigger circuit (22) is the output end of the comparison circuit.

9. The reset circuit according to claim 8, characterized in that: The comparison circuit includes a comparator (U2), a fifth resistor (R5), a sixth resistor (R6), a seventh resistor (R7), an eighth resistor (R8), a second capacitor (C2) and a third capacitor (C3); the cache circuit includes a fourth capacitor (C4) and a fifth capacitor (C5); The fourth capacitor (C4) and the fifth capacitor (C5) are arranged between the ground terminal and the negative terminal of the comparator (U2); the fifth resistor (R5) and the second capacitor (C2) are connected between the positive terminal of the comparator (U2) and the ground terminal; the sixth resistor (R6) is connected between the reference voltage source (VCC2) and the positive terminal of the comparator (U2); the seventh resistor (R7) and the eighth resistor (R8) are connected in series and connected between the reference voltage source (VCC2) and the output terminal of the comparator (U2); one end of the third capacitor (C3) is connected between the seventh resistor (R7) and the eighth resistor (R8), and the other end of the third capacitor (C3) is grounded.

10. The reset circuit according to claim 9, characterized in that: The first switch circuit (3) comprises: a first MOS transistor (Q1), a second MOS transistor (Q2), a ninth resistor (R9), a tenth resistor (R10), an eleventh resistor (R11), a twelfth resistor (R12), a sixth capacitor and a diode (D1); The first MOS tube (Q1) is a PMOS tube, the second MOS tube (Q2) is an NMOS tube, the gate of the first MOS tube (Q1) is connected to the output end of the comparator (U2), the source of the first MOS tube (Q1) is connected between the seventh resistor (R7) and the eighth resistor (R8), the drain of the first MOS tube (Q1) is connected to one end of the ninth resistor (R9), the other end of the ninth resistor (R9) is connected to the gate of the second MOS tube (Q2), the source of the second MOS tube (Q2) is grounded, the tenth resistor (R10) is connected between the gate and the source of the second MOS tube (Q2), the drain of the second MOS tube (Q2) is connected to the ground, One end of the twelfth resistor (R12) is connected, the other end of the twelfth resistor (R12) is connected to the reset end (RESET) of the controlled module (MCU), the drain of the second MOS tube (Q2) is also connected to one end of the eleventh resistor (R11), the other end of the eleventh resistor (R11) is connected to the third power input end (VCC3), one end of the diode (D1) is connected to the drain of the second MOS tube (Q2), the positive end of the diode (D1) is connected to the drain of the second MOS tube (Q2), the negative end of the diode (D1) is connected to the third power input end (VCC3), and the sixth capacitor is connected to the drain of the second MOS tube (Q2) and the ground end.

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