Satellite-borne platform

Abstract

The invention relates to the technical field of satellite communication and calculation, in particular to a satellite-borne platform which comprises a VPX backboard, a plurality of calculation units, a plurality of switching units and a power supply unit. The calculation unit is used for calculating data and providing determinable network communication capability for the satellite-borne platform; the switching unit is used for providing a time-sensitive network switching capability for the satellite-borne platform, providing a deterministic transmission link for the plurality of computing units and realizing deterministic data exchange; the power supply unit is used for supplying power to the satellite-borne platform comprising the plurality of computing units and the plurality of switching units, and the plurality of computing units, the plurality of switching units and the power supply unit are all embedded in the VPX backboard; therefore, interconnection of the plurality of computing units, the plurality of switching units and the power supply unit is realized. The method has the characteristics of data transmission instantaneity, high reliability and the like, determinable data, low-delay and real-time data can be provided for satellites, and the satellite-borne intelligent calculation capability is enhanced.

Description

Technical Field

[0001] The present invention relates to the field of satellite communication and computing technology, and in particular to a satellite-borne platform. Background Art

[0002] As space missions become increasingly complex and diverse, the demand for onboard internal network communications and computing capabilities is also increasing. Traditional onboard communication networks and computing systems can no longer meet the needs of low latency and high reliability, especially in terms of real-time and reliability of data transmission and efficient processing of computing tasks. Summary of the invention

[0003] The present invention provides a satellite-borne platform to solve the technical problems mentioned in the background technology.

[0004] To achieve the above object, the technical solution of the present invention is achieved as follows:

[0005] The present invention provides a satellite-borne platform, including a VPX backplane, a plurality of computing units, a plurality of switching units and a power supply unit;

[0006] The computing unit is used for data computing and provides multi-channel time-sensitive networking (TSN) communication capabilities for the onboard platform;

[0007] The switching unit is used to provide time-sensitive network switching capabilities for the onboard platform and provide deterministic transmission links for the computing unit to achieve deterministic data exchange;

[0008] The power supply unit is used to supply power to the onboard platform including multiple computing units and several switching units;

[0009] A plurality of computing units, a plurality of switching units, and a power supply unit are embedded in the VPX backplane to realize interconnection among the plurality of computing units, a plurality of switching units, and a power supply unit.

[0010] Furthermore, the number of the computing units is four, the number of the switching units is two, the number of the power supply unit is one, and the four computing units and the two switching units are respectively embedded in the VPX backplane through six VPX connectors.

[0011] Furthermore, the plurality of computing units, the plurality of switching units and the power supply unit are physically and logically independent of each other.

[0012] Furthermore, the onboard platform also includes an intelligent platform manager, which is integrated on the VPX backplane. Multiple computing units, several switching units and power supply units are interconnected through 12V power supply, and the collected power supply monitoring information of each unit is collected to the intelligent platform manager (Intelligent Platform Management Controller, IPMC);

[0013] Multiple computing units and several switching units are interconnected through a general input / output interface GPIO, a serializer / deserializer SerDes, and a medium-dependent / related interface MDI, wherein the general input / output interface GPIO is used for multiple computing units and several switching units to transmit control signals; the serializer / deserializer SerDes is used for multiple computing units and several switching units to convert serial data and parallel data; and the medium-dependent / related interface MDI is used for multiple computing units and several switching units to transmit network data.

[0014] Furthermore, the computing unit includes a processor CPU, an embedded controller BMC, a field programmable gate array FPGA, an embedded neural network processor NPU, a complex programmable logic device CPLD, an Ethernet transceiver, a basic input and output system flash memory BIOS FLASH, a memory DDR4, a USB3.0 controller chip, a USB connector, and an intelligent computing acceleration module NPU;

[0015] Among them, the processor CPU is electrically connected to the complex programmable logic device CPLD-1, the embedded controller BMC, the field programmable logic gate array FPGA-1, the basic input and output system flash memory BIOS FLASH, the memory DDR4, the real-time clock module RTC, and the intelligent computing acceleration module NPU respectively. The processor CPU is electrically connected to the USB connector and the VPX connector on the VPX backplane through the USB3.0 controller chip;

[0016] The computing unit is connected to two Gigabit TSNs and two 10 Gigabit TSNs, wherein the two Gigabit TSNs are connected to the processor CPU in sequence through an Ethernet transceiver 1, a field programmable logic gate array FPGA 1, and a PCIE interface; and the two 10 Gigabit TSNs are directly led out from the field programmable logic gate array FPGA.

[0017] Furthermore, the computing unit also includes an interface chip, a micro rectangular aviation plug, an Ethernet transceiver 2, a transformer, a network interface, a reset button, an LED light, a PCIe packet switch chip, a solid state hard disk, and a bridge chip;

[0018] Among them, the processor CPU is electrically connected to the network interface through Ethernet transceiver 2 and the transformer in sequence; the reset button and the LED light are electrically connected to the complex programmable logic device CPLD 1 respectively; the complex programmable logic device CPLD 1 is electrically connected to the micro-rectangular aviation plug through the interface chip; the processor CPU is electrically connected to the bridge chip through the PCIe packet switch chip, and the bridge chip is electrically connected to the solid hard disk and the VPX connector on the VPX backplane respectively.

[0019] Furthermore, the processor CPU uses a Feiteng D2000 processor to provide high-performance processing capabilities for the computing unit;

[0020] Field Programmable Gate Array FPGA-JFM7VX690T is selected;

[0021] The intelligent computing acceleration module AI uses Ascend 310 to intelligently accelerate the computing unit;

[0022] Ethernet transceiver 1 and Ethernet transceiver 2 are both YT8521SH, which are used for network connection of computing unit;

[0023] The micro rectangular aviation plug uses an HJ30J connector for inter-board connection to achieve data transmission;

[0024] The interface chip is UM3232EESE, which is used for signal transmission and conversion between different electronic devices;

[0025] The network interface uses RJ45, which is used for the termination of data cables to achieve the connection and change between equipment and patch panel modules;

[0026] The USB 3.0 controller chip is uPD720201, which is used to connect devices with USB 3.0 interfaces.

[0027] The PCIe packet switch chip is ASM1184E, which is used to expand one PCIe x1 Gen2 upstream port into four PCIe x1 Gen2 downstream ports;

[0028] The bridge chip is ASM1064, which is used to convert the PCI Express interface into a SATA interface;

[0029] The solid hard disk is mSATA-SSD, which is a solid state hard disk with a mini-SATA interface.

[0030] Furthermore, the switching unit includes a field programmable gate array FPGA 2, a switching chip, and a complex programmable logic device CPLD 2;

[0031] Among them, the field programmable logic gate array FPGA 2, the switching chip, and the complex programmable logic device CPLD 2 are connected to each other, and the field programmable logic gate array FPGA 2 and the complex programmable logic device CPLD 2 are electrically connected to the VPX connector on the VPX backplane respectively.

[0032] Furthermore, the switching unit also includes an RS422 interface chip, five Gigabit electrical ports, and four 10 Gigabit optical ports;

[0033] The field programmable logic gate array FPGA II is electrically connected to the VPX connector on the VPX backplane through an RS422 interface chip; five Gigabit electrical ports and four 10 Gigabit optical ports are all arranged on the field programmable logic gate array FPGA II to improve the TSN switching capability between the computing unit and the switching unit.

[0034] Furthermore, the field programmable gate array FPGA 2 is JFM7VX690T; the switching chip is DS160.

[0035] Beneficial effects of the present invention:

[0036] 1. The present invention discloses a satellite-borne platform, which adopts VPX architecture design, solves the deficiencies of the prior art, and provides more real-time, higher-speed, more reliable network connection and more powerful computing power.

[0037] In addition, the present invention also has the following advantages:

[0038] Real-time performance: Since the present invention adopts deterministic network technology, the entire satellite platform supports time synchronization with an accuracy of better than 400ns, meeting the high real-time performance requirements of modern space missions for data transmission.

[0039] Intelligence: Since each computing unit in the present invention has a built-in intelligent computing acceleration module NPU, the intelligence level of the satellite-borne platform is higher; it can support complex data processing and intelligent recognition applications; after the present invention is installed on the satellite system, the intelligence level of the satellite system can be improved.

[0040] Reliable connection: The present invention realizes high-reliability data transmission through technical means such as time synchronization, bandwidth reservation and priority management.

[0041] Therefore, the present invention has the characteristics of high real-time performance, intelligence, reliable connection, etc., and is suitable for installation in a satellite-borne environment with high-reliability communication and computing.

[0042] 2. The present invention combines TSN switching technology and high-performance intelligent computing functions. By optimizing the network architecture and adopting advanced flow control mechanisms and priority scheduling strategies, the timely transmission of key data is ensured, and stable performance can be maintained even when the network load is high. At the same time, since the present invention has multiple high-performance computing units, the data processing capabilities of the satellite platform can be enhanced, and machine learning model training and reasoning can be supported. In addition, the present invention is equipped with an embedded neural network processor NPU in the computing unit, which can significantly improve the speed and accuracy of satellite platform data processing. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] Figure 1 It is the overall structural diagram of the present invention;

[0044] Figure 2 is a diagram of the internal components of the computing unit in the present invention;

[0045] Figure 3 This is a diagram of the internal components of the switching unit in the present invention. DETAILED DESCRIPTION

[0046] In order to facilitate the understanding of the present invention, the present invention will be described more fully below with reference to the relevant drawings. Preferred embodiments of the present invention are provided in the drawings. However, the present invention can be implemented in many other different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the understanding of the disclosure of the present invention more thorough and comprehensive.

[0047] In addition, the terms "one" and "two" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, a feature defined as "one" or "two" may explicitly or implicitly include one or more of the feature. In the description of the present invention, the meaning of "multiple" is two or more, unless otherwise clearly and specifically defined.

[0048] It should also be noted that, in the embodiments of the present application, the same figure mark is used to represent the same component or the same part. For the same parts in the embodiments of the present application, the figure may only mark one of the parts or components as an example. It should be understood that the figure mark also applies to other identical parts or components.

[0049] Reference Figure 1 , an embodiment of the present application provides a satellite-borne platform, including a VPX backplane, a plurality of computing units, a plurality of switching units, and a power supply unit;

[0050] The computing unit is used for data computing and provides two-way time-sensitive networking (TSN) communication capabilities for the onboard platform;

[0051] The switching unit is used to provide time-sensitive network switching capabilities for the onboard platform and provide deterministic transmission links for the computing unit to achieve deterministic data exchange;

[0052] The power supply unit is used to supply power to the onboard platform including multiple computing units and several switching units;

[0053] A plurality of computing units, a plurality of switching units, and a power supply unit are embedded in the VPX backplane to realize interconnection among the plurality of computing units, a plurality of switching units, and a power supply unit.

[0054] In some embodiments, the number of computing units is four, the number of switching units is two, and the two switching units are redundant with each other; the number of power supply units is one, and the four computing units and the two switching units are respectively embedded in the VPX backplane through six VPX connectors.

[0055] In some embodiments, the plurality of computing units, the two switching units, and the power supply unit are physically and logically independent of each other.

[0056] In some embodiments, each of the computing units is connected to the switching unit via a 2-way time-sensitive network (TSN).

[0057] In some embodiments, the onboard platform further includes an intelligent platform manager, which is integrated on the VPX backplane, and multiple computing units, a plurality of switching units, and a power supply unit are interconnected through a 12V power supply, and the collected power supply monitoring information of each unit is collected to the intelligent platform manager (Intelligent Platform Management Controller, IPMC);

[0058] Multiple computing units and two switching units are connected through the general input / output interface GPIO, serializer / deserializer SerDes (i.e. Figure 1 The SERD in the system) and the medium-dependent / related interface MDI are interconnected, wherein the general input / output interface GPIO is used for multiple computing units and two switching units to transmit control signals; the general input / output interface GPIO on the computing unit is provided with 8 pins on both sides, and each pin is connected to the general input / output interface GPIO of the two switching units through a lead, so Figure 1 The general input / output interface GPIO on the computing unit is displayed as GPIO*16; the general input / output interface GPIO on the switching unit is displayed as GPIO*40;

[0059] The serializer / deserializer SerDes is used for multiple computing units and two switching units to convert serial data and parallel data. Both sides of the serializer / deserializer SerDes on the computing unit are connected to the serializer / deserializer SerDes of the switching unit by wires. Figure 1 The serializer / deserializer SerDes on the computing unit is displayed as SERD*2; the serializer / deserializer SerDes on the switching unit is displayed as SERD*4;

[0060] The medium-dependent / related interface MDI is used for multiple computing units and two switching units to transmit network data. Both sides of the medium-dependent / related interface MDI in the computing unit are connected to the medium-dependent / related interface MDI of the switching unit through leads, so Figure 1 The medium-dependent / related interface MDI on the computing unit is displayed as MDI*2; in addition, if there are multiple switching units, each switching unit is electrically connected through the medium-dependent / related interface MDI; Figure 1 The number of switching units is two, and the media-related / related interface MDI on all switching units is displayed as MDI*5.

[0061] In some embodiments, reference Figure 2 The computing unit includes a processor CPU, an embedded controller BMC, a field programmable gate array FPGA, an embedded neural network processor NPU (i.e. Figure 2 AI Ascend 310), complex programmable logic device CPLD 1, Ethernet transceiver 1, basic input and output system flash memory BIOS FLASH, memory DDR4, USB3.0 controller chip, USB connector, intelligent computing acceleration module NPU;

[0062] Among them, the processor CPU is electrically connected to the complex programmable logic device CPLD-1, the embedded controller BMC, the field programmable logic gate array FPGA-1, the basic input and output system flash memory BIOS FLASH, the memory DDR4, the real-time clock module RTC, and the intelligent computing acceleration module NPU respectively. The processor CPU is electrically connected to the USB connector and the VPX connector on the VPX backplane through the USB3.0 controller chip;

[0063] The memory DDR4 uses dual-channel surface-mount memory, with a single-channel memory of 8GB, for a total of 16GB;

[0064] The computing unit is connected to two Gigabit TSNs (Time-Sensitive Networking) and two 10 Gigabit TSNs, thereby providing deterministic network communication for the computing unit and ensuring the reliability of data transmission; wherein the two Gigabit TSNs are connected to the processor CPU in turn through an Ethernet transceiver 1, a field programmable logic gate array FPGA 1 and a PCIE interface; the two 10 Gigabit TSNs are directly derived from the field programmable logic gate array FPGA.

[0065] In some embodiments, the computing unit further includes an interface chip, a micro rectangular aviation plug, an Ethernet transceiver 2, a transformer, a network interface, a reset button, an LED light, a PCIe packet switch chip, a solid state hard disk, and a bridge chip;

[0066] Among them, the processor CPU is electrically connected to the network interface through Ethernet transceiver 2 and the transformer in sequence; the reset button and the LED light are electrically connected to the complex programmable logic device CPLD 1 respectively; the complex programmable logic device CPLD 1 is electrically connected to the micro-rectangular aviation plug through the interface chip; the processor CPU is electrically connected to the bridge chip through the PCIe packet switch chip, and the bridge chip is electrically connected to the solid hard disk and the VPX connector on the VPX backplane respectively.

[0067] In some embodiments, the processor CPU uses a Feiteng D2000 processor to provide high-performance processing capabilities for the computing unit;

[0068] Field Programmable Gate Array FPGA uses JFM7VX690T; supports logic reconstruction, deterministic sending and receiving, and time synchronization, with a time synchronization accuracy of ≤400ns;

[0069] The intelligent computing acceleration module AI uses Ascend 310 to intelligently accelerate the computing unit;

[0070] Ethernet transceiver 1 and Ethernet transceiver 2 are both YT8521SH, which are used for network connection of computing unit;

[0071] The micro rectangular aviation plug uses an HJ30J connector for inter-board connection to achieve data transmission;

[0072] The interface chip is UM3232EESE, which is used for signal transmission and conversion between different electronic devices;

[0073] The network interface uses RJ45, which is used for the termination of data cables to achieve the connection and change between equipment and patch panel modules;

[0074] The USB 3.0 controller chip is uPD720201, which is used to connect devices with USB 3.0 interfaces.

[0075] The PCIe packet switch chip is ASM1184E, which is used to expand one PCIe x1 Gen2 upstream port into four PCIe x1 Gen2 downstream ports;

[0076] The bridge chip is ASM1064, which is used to convert the PCI Express interface into a SATA interface;

[0077] The solid hard disk is mSATA-SSD, which is a solid state hard disk with a mini-SATA interface.

[0078] In some embodiments, the switching unit includes a field programmable gate array FPGA II, a switching chip, and a complex programmable logic device CPLD II;

[0079] Among them, the field programmable logic gate array FPGA 2, the switching chip, and the complex programmable logic device CPLD 2 are connected to each other, and the field programmable logic gate array FPGA 2 and the complex programmable logic device CPLD 2 are electrically connected to the VPX connector on the VPX backplane respectively.

[0080] In some embodiments, the switching unit further includes an RS422 interface chip, five Gigabit electrical ports, and four 10 Gigabit optical ports;

[0081] The field programmable logic gate array FPGA II is electrically connected to the VPX connector on the VPX backplane through an RS422 interface chip; five Gigabit electrical ports and four 10 Gigabit optical ports are all arranged on the field programmable logic gate array FPGA II to improve the TSN switching capability between the computing unit and the switching unit.

[0082] In some embodiments, the field programmable gate array FPGA 2 uses JFM7VX690T, supports logic reconstruction, supports deterministic transmission and reception, supports time synchronization, and the time synchronization accuracy is ≤400ns; the switching chip uses the National University of Defense Technology DS160, and the National University of Defense Technology DS160 supports 8-way serializer / deserializer SerDes switching.

[0083] In this embodiment, the clock synchronization method adopted by the switching network is as follows:

[0084] Step 1: Set a high-precision clock source inside the switching unit;

[0085] Step 2: Use the IEEE 802.1AS standard to achieve time synchronization between the switching unit and the four computing units;

[0086] Step 3: Use the hardware timestamp function to record the sending and receiving time of the data packet;

[0087] Step 4: Use field programmable logic gate array FPGA 2 to process the time synchronization data to improve synchronization accuracy;

[0088] Step 5: Ensure that the time synchronization accuracy is better than 400ns by optimizing the internal clock management strategy of the switching unit.

[0089] The invention discloses a satellite-borne platform, which solves the deficiencies of the prior art and provides a more real-time, higher-speed, more reliable network connection and more powerful computing capability.

[0090] In addition, the present invention also has the following advantages:

[0091] Real-time performance: Since the present invention adopts deterministic network technology, the entire satellite platform supports time synchronization with an accuracy of better than 400ns, meeting the high real-time performance requirements of modern space missions for data transmission.

[0092] Intelligence: Since each computing unit in the present invention has a built-in intelligent computing acceleration module NPU, the intelligence level of the satellite-borne platform is higher; it can support complex data processing and intelligent recognition applications; after the present invention is installed on the satellite system, the intelligence level of the satellite system can be improved.

[0093] Reliable connection: The present invention realizes high-reliability data transmission through technical means such as time synchronization, bandwidth reservation and priority management.

[0094] In summary, the present invention has the characteristics of high real-time performance, intelligence, reliable connection, etc., and is suitable for installation in a satellite-borne environment of high-reliability communication and computing.

[0095] The above is only a specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed by the present invention, which should be covered within the protection scope of the present invention. In addition, the technical solutions between the various embodiments of the present invention can be combined with each other, but it must be based on the ability of ordinary technicians in the field to implement. When the combination of technical solutions is contradictory or cannot be implemented, it should be considered that such a combination of technical solutions does not exist and is not within the protection scope of the present invention. Therefore, the protection scope of the present invention shall be based on the protection scope of the claims.

Claims

1. A satellite-borne platform, characterized in that: It includes a VPX backplane, multiple computing units, several switching units, and a power supply unit; The computing unit is used for data calculation and provides multi-channel time-sensitive network communication capabilities for the onboard platform; The switching unit is used to provide time-sensitive network switching capabilities for the onboard platform and provide deterministic transmission links for the computing unit to achieve deterministic data exchange; The power supply unit is used to supply power to the onboard platform including multiple computing units and several switching units; A plurality of computing units, a plurality of switching units, and a power supply unit are embedded in the VPX backplane to realize interconnection among the plurality of computing units, a plurality of switching units, and a power supply unit.

2. The satellite-borne platform according to claim 1, characterized in that: The number of the computing units is four, the number of the switching units is two, the number of the power supply unit is one, and the four computing units and the two switching units are respectively embedded in the VPX backplane through six VPX connectors.

3. The satellite-borne platform according to claim 1, characterized in that: The plurality of computing units, the plurality of switching units and the power supply unit are physically and logically independent of each other.

4. The satellite-borne platform according to claim 1, characterized in that: It also includes an intelligent platform manager, which is integrated on the VPX backplane. Multiple computing units, several switching units, and power supply units are interconnected through 12V power supply, and the collected power supply monitoring information of each unit is collected to the intelligent platform manager; Multiple computing units and several switching units are interconnected through a general input / output interface GPIO, a serializer / deserializer SerDes, and a medium-dependent / related interface MDI, wherein the general input / output interface GPIO is used for multiple computing units and several switching units to transmit control signals; the serializer / deserializer SerDes is used for multiple computing units and several switching units to convert serial data and parallel data; and the medium-dependent / related interface MDI is used for multiple computing units and several switching units to transmit network data.

5. The satellite-borne platform according to any one of claims 1 to 4, characterized in that: The computing unit includes a processor CPU, an embedded controller BMC, a field programmable logic gate array FPGA, an embedded neural network processor NPU, a complex programmable logic device CPLD, an Ethernet transceiver, a basic input and output system flash memory BIOS FLASH, a memory DDR4, a USB3.0 controller chip, a USB connector, and an intelligent computing acceleration module NPU; Among them, the processor CPU is electrically connected to the complex programmable logic device CPLD-1, the embedded controller BMC, the field programmable logic gate array FPGA-1, the basic input and output system flash memory BIOS FLASH, the memory DDR4, the real-time clock module RTC, and the intelligent computing acceleration module NPU respectively. The processor CPU is electrically connected to the USB connector and the VPX connector on the VPX backplane through the USB3.0 controller chip; The computing unit is connected to two Gigabit TSNs and two 10 Gigabit TSNs, wherein the two Gigabit TSNs are connected to the processor CPU in sequence through Ethernet transceiver 1, field programmable logic gate array FPGA 1 and PCIE interface; the two 10 Gigabit TSNs are directly led out from the field programmable logic gate array FPGA.

6. The satellite-borne platform according to claim 5, characterized in that: The computing unit also includes an interface chip, a micro rectangular aviation plug, an Ethernet transceiver 2, a transformer, a network interface, a reset button, an LED light, a PCIe packet switch chip, a solid state hard disk, and a bridge chip; Among them, the processor CPU is electrically connected to the network interface through Ethernet transceiver 2 and the transformer in sequence; the reset button and the LED light are electrically connected to the complex programmable logic device CPLD 1 respectively; the complex programmable logic device CPLD 1 is electrically connected to the micro-rectangular aviation plug through the interface chip; the processor CPU is electrically connected to the bridge chip through the PCIe packet switch chip, and the bridge chip is electrically connected to the solid hard disk and the VPX connector on the VPX backplane respectively.

7. The satellite-borne platform according to claim 6, characterized in that: The processor CPU uses the Feiteng D2000 processor to provide high-performance processing capabilities for the computing unit; Field Programmable Gate Array FPGA-JFM7VX690T is selected; The intelligent computing acceleration module AI uses Ascend 310 to intelligently accelerate the computing unit; Ethernet transceiver 1 and Ethernet transceiver 2 are both YT8521SH, which are used for network connection of computing unit; The micro rectangular aviation plug uses an HJ30J connector for inter-board connection to achieve data transmission; The interface chip is UM3232EESE, which is used for signal transmission and conversion between different electronic devices; The network interface uses RJ45, which is used for the termination of data cables to achieve the connection and change between equipment and patch panel modules; The USB 3.0 controller chip is uPD720201, which is used to connect devices with USB 3.0 interfaces. The PCIe packet switch chip is ASM1184E, which is used to expand one PCIe x1 Gen2 upstream port into four PCIe x1 Gen2 downstream ports; The bridge chip is ASM1064, which is used to convert the PCI Express interface into a SATA interface; The solid hard disk is mSATA-SSD, which is a solid state hard disk with a mini-SATA interface.

8. The satellite-borne platform according to claim 1, characterized in that: The switching unit includes a field programmable gate array FPGA 2, a switching chip, and a complex programmable logic device CPLD 2; Among them, the field programmable logic gate array FPGA 2, the switching chip, and the complex programmable logic device CPLD 2 are connected to each other, and the field programmable logic gate array FPGA 2 and the complex programmable logic device CPLD 2 are electrically connected to the VPX connector on the VPX backplane respectively.

9. The satellite-borne platform according to claim 8, characterized in that: The switching unit also includes an RS422 interface chip, five Gigabit electrical ports and four 10 Gigabit optical ports; The field programmable logic gate array FPGA II is electrically connected to the VPX connector on the VPX backplane through an RS422 interface chip; five Gigabit electrical ports and four 10 Gigabit optical ports are all arranged on the field programmable logic gate array FPGA II to improve the TSN switching capability between the computing unit and the switching unit.

10. The satellite-borne platform according to claim 8 or 9, characterized in that: The field programmable gate array FPGA 2 is selected from JFM7VX690T; the switching chip is selected from DS160.

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