High-precision clock synchronization device and method for parallel control of high-power device

Abstract

The invention relates to a high-precision clock synchronization device and method for parallel control of a high-power device, and the high-precision clock synchronization device for parallel control of the high-power device is constructed, and random errors are suppressed in a proportional feedback closed-loop mode according to the constructed device. System damping is introduced to eliminate system oscillation caused by long-period integration of compensation amounts of clock errors of a master controller and a slave controller, meanwhile, the offset of a crystal oscillator can be obtained, screening of consistency of crystal oscillator chips is achieved, and the drift phenomenon of the crystal oscillator is further improved from the aspect of hardware. Compared with a conventional clock synchronization method, the clock synchronization precision can be greatly improved, clock fluctuation can be reduced, and control consistency under direct parallel connection of high-power devices can be improved.

Description

Technical Field

[0001] The present invention belongs to the technical field of clock synchronization, and in particular to a high-precision clock synchronization device and method for parallel control of high-power devices. Background Art

[0002] With the rapid development of industrial power systems, there is an increasing demand for parallel control of high-power equipment in metallurgy, locomotive electric traction, large ship electric propulsion, and power plant generator excitation systems. When high-power equipment is connected in parallel, each slave power device needs to synchronize the control clock with the master clock to coordinate and unify the control. The clock of the controller in each power device comes from the crystal oscillator chip. Even if the model is the same, there is a frequency deviation between different crystal oscillator chips. Clock drift will occur during long-term operation, and clock synchronization is required. There are generally two conventional synchronization methods. One is to use hard-wire synchronization, which will increase additional wiring costs and cause synchronization errors for different line lengths. The other is to use communication protocol synchronization, which also has problems such as optical fiber transmission line delay and communication decoding time fluctuations, which reduce the clock synchronization accuracy and thus affect the consistency of power system control. Summary of the invention

[0003] The purpose of the present invention is to overcome the shortcomings of the prior art, propose a high-precision clock synchronization device and method for parallel control of high-power devices, propose a refined, low-fluctuation high-precision clock synchronization method, and at the same time, obtain the crystal oscillator offset, realize the screening of the consistency of the crystal oscillator chip, and further improve the crystal oscillator drift phenomenon from the hardware. Compared with conventional clock synchronization methods, the present invention can greatly improve the clock synchronization accuracy and reduce clock fluctuations, which is conducive to improving the consistency of control under direct parallel connection of high-power devices.

[0004] The present invention solves the technical problem by adopting the following technical solutions:

[0005] A high-precision clock synchronization device for parallel control of high-power devices includes a master controller and multiple slave controllers, wherein the master controller is connected in parallel with multiple slave controllers, the master controller and the slave controllers use FPGA as the main control chip, and the master controller and the slave controllers perform clock synchronization through 50MHz high-speed communication.

[0006] A clock synchronization method for a high-precision clock synchronization device for parallel control of a high-power device comprises the following steps:

[0007] Step 1, the master controller and the slave controller communicate through optical fiber;

[0008] Step 2: Each time a communication is made, the main controller uses its own clock to record the sending time. and acceptance moment The slave controller uses its own clock to record the receiving time and sending time

[0009] Step 3: Calculate the average fiber line delay of multiple communication transmissions based on the data recorded in step 2

[0010] Step 4: Based on the average fiber line delay calculated in step 3 Calculate the offset of the clock error between the master controller and the slave controller after each transmission i ;

[0011] Step 5: Suppress random errors through proportional feedback closed loop and introduce system damping to eliminate the offset i System oscillation caused by long-period integration.

[0012] Moreover, the specific implementation method of step 3 is:

[0013]

[0014] Wherein, i=1~n, and n is the number of communications.

[0015] Moreover, the specific implementation method of step 4 is:

[0016]

[0017] Where k is the damping feedback coefficient, For offset i The integrated average clock offset.

[0018] Moreover, the specific implementation method of step 5 is: Perform large inertia filtering to obtain the compensation clock T C ; Slave station control clock T SC = Slave station communication clock T S + Compensation clock T C , slave station controls the clock T SC It is a high-precision, low-fluctuation synchronous clock.

[0019] The advantages and positive effects of the present invention are:

[0020] The present invention constructs a high-precision clock synchronization device for parallel control of high-power devices, and suppresses random errors through a proportional feedback closed-loop method according to the constructed device, introduces system damping to eliminate system oscillations caused by long-period integration of the compensation amount of the clock errors of the master controller and the slave controller, and can obtain the crystal oscillator offset at the same time, realize the screening of the consistency of the crystal oscillator chip, and further improve the crystal oscillator drift phenomenon from the hardware. Compared with conventional clock synchronization methods, the present invention can greatly improve the clock synchronization accuracy and reduce clock fluctuations, which is conducive to improving the consistency of control under direct parallel connection of high-power devices. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 It is a structural diagram of the device of the present invention;

[0022] Figure 2 A transmission line delay measurement method according to the present invention;

[0023] Figure 3 This is a schematic diagram of the high-precision clock closed-loop control principle of the present invention;

[0024] Figure 4 This is the principle diagram of the inertial filter block of the present invention. DETAILED DESCRIPTION

[0025] The present invention is further described in detail below with reference to the accompanying drawings.

[0026] A high-precision clock synchronization device for parallel control of high-power devices, such as Figure 1 As shown, it includes a master controller and multiple slave controllers, wherein the master controller is connected in parallel to multiple slave controllers, the master controller and the slave controller use FPGA as the main control chip, and the master controller and the slave controller are clock synchronized through 50MHz high-speed communication.

[0027] The master controller clock and slave controller clock synchronization method is as follows Figure 2 As shown:

[0028] The master controller and slave controller communicate using 50MHz optical fiber communication with a communication cycle of 10us / time.

[0029] During each communication, the main controller uses its own clock to record the sending time. and acceptance moment The slave controller uses its own clock to record the receiving time and sending time So we can get the total delay of each transmission

[0030]

[0031] Calculate the average one-way delay of the optical fiber line for multiple communication transmissions After each transmission, the compensation amount of the master and slave station clock errors should be (where i=1~n).

[0032] The above is the basic principle of transmission delay measurement, but due to the fluctuation of protocol parsing time, the time recorded by the slave station (where i=1-n) will also fluctuate, and the random error needs to be filtered and then compensated.

[0033] A clock synchronization method for a high-precision clock synchronization device for parallel control of a large-power device, such as Figure 3 As shown, the following steps are included:

[0034] Step 1, the master controller and the slave controller communicate through optical fiber; the master station communication clock and the slave station communication clock use 200MHz (unit time 5ns) counting, 8 values ​​are added every 5ns, and the counting cycle is 0.5ms, and the value change range is 0 to 800k.

[0035] Step 2: Each time a communication is made, the main controller uses its own clock to record the sending time. and acceptance moment The slave controller uses its own clock to record the receiving time and sending time

[0036] Step 3: Calculate the average fiber line delay of multiple communication transmissions based on the data recorded in step 2

[0037]

[0038] Wherein, i=1~n, and n is the number of communications.

[0039] Step 4: Based on the average fiber line delay calculated in step 3 Calculate the offset of the clock error between the master controller and the slave controller after each transmission i .

[0040]

[0041] Where k is the damping feedback coefficient, For offset i The integrated average clock offset.

[0042] Every 0.5ms Calibrate the slave station communication clock. Since n is a large value, The numerical value can be kept stable, so that the fluctuation of the slave station control clock is very small.

[0043] Since the range of the master and slave clock values ​​is extended from 0 to 100 k to 0 to 800 k, offset i , The resolution of numerical calculations has also been improved by 8 times.

[0044] Step 5: Suppress random errors through proportional feedback closed loop and introduce system damping to eliminate the offset i System oscillation caused by long-period integration.

[0045] like Figure 4 As shown, Perform large inertia filtering to obtain the compensation clock T C ; Slave station control clock T SC = Slave station communication clock T S + Compensation clock T C , slave station controls the clock T SC It is a high-precision, low-fluctuation synchronous clock.

[0046] The Represents the crystal oscillator offset, by selecting Crystal oscillator chips with similar values ​​can further reduce the clock drift of the master-slave control system.

[0047] It should be emphasized that the embodiments described in the present invention are illustrative rather than restrictive. Therefore, the present invention includes but is not limited to the embodiments described in the specific implementation manner. Any other implementation manners derived by those skilled in the art based on the technical solution of the present invention also fall within the scope of protection of the present invention.

Claims

1. A high-precision clock synchronization device for parallel control of high-power devices, characterized in that: It includes a main controller and multiple slave controllers, wherein the main controller is connected to multiple slave controllers in parallel, the main controller and the slave controllers use FPGA as the main control chip, and the main controller and the slave controllers are synchronized in clock through 50MHz high-speed communication.

2. A clock synchronization method for a high-precision clock synchronization device for parallel control of a high-power device, characterized in that: The following steps are involved: Step 1, the master controller and the slave controller communicate through optical fiber; Step 2: Each time a communication is made, the main controller uses its own clock to record the sending time. and acceptance moment The slave controller uses its own clock to record the receiving time and sending time Step 3: Calculate the average fiber line delay of multiple communication transmissions based on the data recorded in step 2 Step 4: Based on the average fiber line delay calculated in step 3 Calculate the offset of the clock error between the master controller and the slave controller after each transmission i ; Step 5: Suppress random errors through proportional feedback closed loop and introduce system damping to eliminate the offset i System oscillation caused by long-period integration.

3. The clock synchronization method of a high-precision clock synchronization device for parallel control of a high-power device according to claim 2, characterized in that: The specific implementation method of step 3 is: Wherein, i=1~n, and n is the number of communications.

4. The clock synchronization method of a high-precision clock synchronization device for parallel control of high-power devices according to claim 3, characterized in that: The specific implementation method of step 4 is: Where k is the damping feedback coefficient, For offset i The integrated average clock offset.

5. The clock synchronization method of a high-precision clock synchronization device for parallel control of high-power devices according to claim 4, characterized in that: The specific implementation method of step 5 is: Perform large inertia filtering to obtain the compensation clock T C ; Slave station control clock T SC = Slave station communication clock T S + Compensation clock T C , slave station controls the clock T SC It is a high-precision, low-fluctuation synchronous clock.

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