High-bit-rate real-time key extraction method, device, equipment and medium

Abstract

The invention discloses a high-bit-rate real-time secret key extraction method, relates to the technical field of quantum secret keys, and is used for solving the problem of low decoding efficiency in the prior art, and the method comprises the following steps: in a CUDA environment, reading an LDPC check matrix file, and introducing a noise adding signal through a simulated BSC channel; performing iterative calculation on the LDPC check matrix file node through an LLRBP decoding algorithm according to a noise adding signal initialized by probability information so as to update a check node and a variable node; after each round of iterative calculation, probability information of the variable nodes is judged, if the probability information is larger than 0, the judgment result is marked as 0, otherwise, the judgment result is marked as 1, and a decoding result is obtained and stored. The invention also discloses a high-bit-rate real-time key extraction device, electronic equipment and a computer storage medium. According to the invention, the LDCP code parallel computing is carried out through the CUDA architecture, and the decoding efficiency is improved.

Description

Technical Field

[0001] The present invention relates to the field of quantum key technology, and in particular to a high-rate real-time key extraction method, device, equipment and medium for use in a quantum key distribution system. Background Art

[0002] High-rate data transmission has become an important research direction in modern communication technology. Among them, one of the main challenges facing high-rate data transmission is how to effectively handle errors in the channel. During the data transmission process, due to the presence of various noises and interferences, information bits may be erroneous, thus affecting the reliability of transmission. In order to solve this problem, existing technologies have begun to apply error correction coding technology to communication systems. Among them, low-density parity check (LDPC) codes have attracted widespread attention due to their error correction capabilities close to the Shannon limit. LDPC codes use sparse parity check matrices for encoding and decoding, which can effectively improve the reliability of data transmission.

[0003] The decoding algorithm is the key to realize the error correction capability of LDPC code, and its performance directly affects the efficiency of the entire communication system. Among many decoding algorithms, the minimum sum algorithm is widely used due to its low computational complexity and fast convergence speed. This algorithm decodes by iteratively updating the messages between the check nodes and the variable nodes, and is often used to handle error correction tasks in high-rate data.

[0004] However, the decoding efficiency of the existing technology is still low and the implementation complexity is also high. Summary of the invention

[0005] In order to overcome the deficiencies of the prior art, one of the objectives of the present invention is to provide a high-rate real-time key extraction method, which uses a CUDA architecture for parallel computing combined with LDPC decoding to quickly obtain decoding results.

[0006] One of the purposes of the present invention is achieved by the following technical solution:

[0007] A high code rate real-time key extraction method comprises the following steps:

[0008] In the CUDA environment, the LDPC check matrix file is read and the noise signal is introduced through the simulated BSC channel;

[0009] Initializing probability information of a noise-added signal in the randomly generated signal by using the LDPC check matrix file and a minimum-sum decoding algorithm, wherein the noise-added signal is a signal that introduces the noise through the BSC channel;

[0010] According to the noise-added signal initialized by the probability information, the LDPC check matrix file nodes are iteratively calculated by the LLRBP decoding algorithm to update the check nodes and the variable nodes;

[0011] After each round of iterative calculation, the probability information of the variable node is judged. If the probability information is greater than 0, the judgment result is recorded as 0, otherwise the judgment result is recorded as 1 to obtain the decoding result.

[0012] Further, the LDPC check matrix file is read and a noise signal is introduced through a simulated BSC channel, including:

[0013] Initialize a random number generator, wherein the random number generator is used to generate an original codeword and generate a flip bit according to an error probability, the original codeword is a randomly generated signal, the flip bit is generated as a randomly generated noise, and the signal and the noise are combined through a simulated BSC channel to obtain a noisy signal.

[0014] Further, the probability information of the noisy signal is initialized by using the LDPC check matrix file with a minimum sum decoding algorithm, including:

[0015] Read the noisy signal and store it in array form;

[0016] Reorder the array elements according to the order of the variable nodes;

[0017] Sending the noisy signal and the LDPC check matrix information to be used to the GPU in the form of an array;

[0018] Calculate the message value L(q) transmitted by the variable node to the check node ij ), satisfying: L (0) (q ij )=L(P i ), Among them, L(P i ) is the initial probability likelihood ratio transmitted by the channel to the variable node, i is the variable node, and j is the check node;

[0019] Perform thread synchronization to ensure that all calculations are completed before the next operation.

[0020] Furthermore, the check node is updated by using the Normalized BP-Based algorithm and / or the Offset BP-Based algorithm.

[0021] Further, updating the check node comprises the following steps:

[0022] Get the preset number of iterations; preset weight factors and bias factors;

[0023] The check node update calculation is performed by using the bias factor β and the weight factor α, satisfying:

[0024]

[0025] L(r ji )←sgn(L(r ji ))·max(|L(r ji )||-β,0);

[0026] Send the calculation results and the LDPC check matrix information to be used to the GPU in the form of an array;

[0027] Calculate the message value transmitted by the variable node to the check node;

[0028] Perform thread synchronization to ensure that all calculations are completed before the next iteration.

[0029] Furthermore, the update calculation of the variable node satisfies:

[0030]

[0031] Further, the probability information of the variable node is determined, including: after each round of iterative calculation, the probability information at the variable node is determined to satisfy:

[0032] If L (l) (q i )>0, then otherwise is the decoding result.

[0033] A second object of the present invention is to provide a high-code rate real-time key extraction device.

[0034] The second object of the present invention is achieved by adopting the following technical solution:

[0035] A high code rate real-time key extraction device, comprising:

[0036] A simulation module is used to read the LDPC check matrix file and introduce the noise signal through the simulated BSC channel in the CUDA environment;

[0037] An iterative calculation module is used to initialize the probability information of the noisy signal in the randomly generated signal by using the LDPC check matrix file and the minimum sum decoding algorithm; according to the noisy signal initialized by the probability information, iteratively calculate the nodes of the LDPC check matrix file by using the LLRBP decoding algorithm to update the check nodes and the variable nodes;

[0038] The determination module is used to determine the probability information of the variable node after each round of iterative calculation. If the probability information is greater than 0, the determination result is recorded as 0, otherwise the determination result is recorded as 1, and the decoding result is obtained and stored.

[0039] Preferably, reading the LDPC check matrix file and introducing the noise signal through the simulated BSC channel includes:

[0040] Initialize a random number generator, the random number generator is used to generate an original codeword and generate a flip bit according to an error probability, the original codeword is a randomly generated signal, the flip bit is generated as a randomly generated noise, the signal and the noise are combined through a simulated BSC channel to obtain a noisy signal.

[0041] Preferably, initializing probability information of the noisy signal using the LDPC check matrix file with a minimum sum decoding algorithm includes:

[0042] Read the noisy signal and store it in array form;

[0043] Reorder the array elements according to the order of the variable nodes;

[0044] Sending the noisy signal and the LDPC check matrix information to be used to the GPU in the form of an array;

[0045] Calculate the message value L(q) transmitted by the variable node to the check node ij ), satisfying: L (0) (q ij )=L(P i ), Among them, P i is the initial probability value passed to the variable node by the channel, L(P i ) is the initial probability likelihood ratio of the channel transmitted to the variable node, i is the variable node, j is the check node, q ij Represents the external probability information transmitted from variable node i to check node j;

[0046] Perform thread synchronization to ensure that all calculations are completed before the next operation.

[0047] Preferably, the check nodes are updated by using a Normalized BP-Based algorithm and / or an Offset BP-Based algorithm.

[0048] Preferably, updating the check node comprises the following steps:

[0049] Get the preset number of iterations;

[0050] Get the preset weight factor and bias factor;

[0051] The check node update calculation is performed by using the bias factor β and the weight factor α, satisfying:

[0052]

[0053]

[0054] L(r ji )←sgn(L(r ji ))·max(|L(r ji )|-β,0), where L is the probability likelihood ratio, r ij represents the external probability information transmitted from check node j to variable node i, R j\i represents the set of variable nodes connected to the check node except i;

[0055] Send the calculation results and the LDPC check matrix information to be used to the GPU in the form of an array;

[0056] Calculate the message value transmitted by the variable node to the check node;

[0057] Perform thread synchronization to ensure that all calculations are completed before the next operation.

[0058] Preferably, the update L of the variable node (l) (q i ) calculation satisfies: Among them, r ij represents the external probability information transmitted from check node j to variable node i, C i is the original codeword, q i It is the probability information transmitted by variable node i to all the check nodes connected to it.

[0059] Preferably, determining the probability information of the variable node includes: after each round of iterative calculation, determining the probability information at the variable node to satisfy:

[0060] If L (l) (q i )>0, then otherwise is the decoding result.

[0061] The third object of the present invention is to provide an electronic device for performing one of the objects of the invention, which includes a processor, a storage medium and a computer program, wherein the computer program is stored in the storage medium, and when the computer program is executed by the processor, the above-mentioned high-rate real-time key extraction method is implemented.

[0062] A fourth object of the present invention is to provide a computer-readable storage medium storing one of the objects of the invention, on which a computer program is stored, and when the computer program is executed by a processor, the above-mentioned high-rate real-time key extraction method is implemented.

[0063] Compared with the prior art, the present invention has the following beneficial effects:

[0064] The present invention utilizes the CUDA architecture for parallel computing, parallelizes the decoding process of LDPC codes, and significantly improves the processing speed of computationally intensive tasks. By using low-density parity check LDPC codes and a minimum-sum algorithm for post-processing decoding, and utilizing the fact that check node and variable node message updates do not affect each other during the decoding process, the CUDA architecture is used to parallelize the decoding process of the minimum-sum algorithm, thereby significantly reducing the time required for the error correction process, being able to process more data in a limited time, and effectively meeting the needs of high-rate transmission. BRIEF DESCRIPTION OF THE DRAWINGS

[0065] Figure 1 is a flow chart of a high code rate real-time key extraction method of embodiment 1;

[0066] Figure 2 is a structural block diagram of a high-rate real-time key extraction device of Embodiment 2;

[0067] Figure 3 It is a structural block diagram of an electronic device of Embodiment 3. DETAILED DESCRIPTION

[0068] The present invention will be described in more detail below in conjunction with the accompanying drawings. It should be noted that the following description of the present invention with reference to the accompanying drawings is only illustrative and not restrictive. The various embodiments can be combined with each other to form other embodiments not shown in the following description.

[0069] Embodiment 1

[0070] Embodiment 1 provides a high-rate real-time key extraction method, which aims to use parallel computing technology as a solution to improve the decoding rate; through the parallel computing platform and programming model of the Compute Unified Device Architecture (CUDA) architecture, and using the general computing capabilities of the graphics processing unit (GPU), a large number of small, parallel computing tasks are effectively managed and executed, significantly accelerating the processing speed of computing-intensive tasks; by parallelizing the decoding process of LDPC codes, the CUDA architecture can significantly reduce the time required for error correction and meet the needs of high-rate data transmission.

[0071] The CUDA architecture can efficiently manage and execute thousands of small, parallel computing tasks that are designed to run on multiple CUDA cores simultaneously, thereby achieving high parallelism and high throughput in data processing.

[0072] This embodiment uses low-density parity check (LDPC) codes and the minimum sum algorithm for post-processing decoding. By utilizing the fact that the check node and variable node message updates do not affect each other during the decoding process, the CUDA architecture is used to parallelize the decoding process of the minimum sum algorithm, thereby significantly reducing the time required for the error correction process, being able to process more data in a limited time, and effectively meeting the needs of high-rate transmission.

[0073] The application feature of LDPC codes is the use of a specifically constructed sparse parity-check matrix, which, with its low-density 1 and high-density 0 structure, is designed to optimize the efficiency and error correction capability of the decoding process to meet the needs of high-rate data transmission.

[0074] The method of this embodiment is applied to a binary symmetric channel (BSC). BSC is an idealized communication model. The method is optimized according to the characteristics of the BSC channel, and can effectively resist errors in the BSC channel and significantly improve the reliability of data transmission.

[0075] Based on the above principles, please refer to Figure 1 As shown, a high code rate real-time key extraction method comprises the following steps:

[0076] S1. In the CUDA environment, read the LDPC check matrix file and introduce the noise signal through the simulated BSC channel;

[0077] S1 includes:

[0078] After obtaining these data, a data structure for storing connection information can also be created. Two lists are used to record the index of the check node connected to a variable node and the index of the variable node connected to a check node, and a unique index is assigned to each information flow for subsequent error correction operations.

[0079] Initialize a random number generator, the random number generator is used to generate an original codeword and generate a flip bit according to an error probability, the original codeword is a randomly generated signal, the flip bit is generated as a randomly generated noise, the signal and the noise are combined through a simulated BSC channel to obtain a noisy signal.

[0080] The above error probability can be set as a noise according to actual conditions to simulate the signal, which is not limited in this embodiment.

[0081] In this embodiment, there are two random number generators, the first one is used to generate original codewords, and the second one is used to generate flipped bits according to a given error probability to simulate noise in the BSC channel, ensuring that the generation of codewords and the introduction of noise are independent of each other.

[0082] S2. Initializing probability information of the noisy signal using the LDPC check matrix file and a minimum sum decoding algorithm, wherein the noisy signal is a signal that introduces the noise through the BSC channel;

[0083] S2 includes:

[0084] Read the noisy signal and store it in array form;

[0085] Rearrange the array elements according to the order of the variable nodes; the ordering is to assign the noise-added signal to the new array according to the order of the variable nodes so that it can be quickly accessed through the index of the variable node order;

[0086] The noise-added signal and the LDPC check matrix information to be used are sent to the GPU in the form of an array; a video memory needs to be opened on the GPU and data needs to be transmitted;

[0087] Calculate the message value L(q) transmitted by the variable node to the check node ij ),satisfy:

[0088] L (0) (q ij )=L(P i ), Among them, L(P i ) is the initial probability likelihood ratio of the channel transmitted to the variable node, i is the variable node, j is the check node, q ij (b) (b = 0, 1) represents the external probability information transmitted by variable node i to check node j, that is, after obtaining the external information of all check nodes and channels except j, the probability of judging the variable node ci = b;

[0089] Execute thread synchronization to ensure that all calculations are completed before the next operation. The calculation results do not need to be sent back to the CPU, which not only reduces data transmission time, but also makes the next kernel function for calculation and execution more convenient to use.

[0090] Before the above thread synchronization, it is necessary to set an appropriate number of threads to fully utilize the computing power of the GPU, usually a multiple of 32. If the number of threads remaining after the total number of variable nodes is divided by an integer is less than 32, another thread block needs to be set for calculation. The message value transmitted is calculated and stored in another GPU array. The number of threads can be adjusted according to the actual effect, and this embodiment does not limit this.

[0091] S3, according to the noise-added signal initialized by the probability information, iteratively calculating the nodes of the LDPC check matrix file through the LLRBP decoding algorithm to update the check nodes and the variable nodes;

[0092] Before performing iterative calculations, you also need to obtain the information required for the iteration, including:

[0093] Load the LDPC check matrix and extract information. The information to be extracted includes: the number of check nodes, the number of variable nodes, the number of information bits, and the code rate;

[0094] Get the degree of each variable node, the degree of each check node, and the total number of information flows.

[0095] In this embodiment, the above LLRBP decoding algorithm uses the Normalized BP-Based algorithm and / or the Offset BP-Based algorithm that are improved on the basis of the LLRBP decoding algorithm to update the check nodes.

[0096] For all check nodes j and their adjacent variable nodes i∈R(j), at the lth iteration, the message sent from the computation variable node to the check node satisfies:

[0097] r ij (b) (b=0,1) indicates check

[0098] The external probability information transmitted by node j to variable node i is the probability that the check equation j satisfies the given information bit and the other information bits have independent probability distributions.

[0099] In fact, the approximation process will sacrifice the accuracy of the trust message handled by the check node. In order to compensate for the problem of high amplitude of the trust message caused by the approximation process, the Normalized BP-Based algorithm and the OffsetBP-Based algorithm that can correct the amplitude are proposed. In the Normalized BP-Based algorithm, it is corrected by dividing it by the scale factor. In the Offset BP-Based algorithm, it can be reduced by subtracting a value from the check node information. Therefore, this embodiment combines the Normalized BP-Based algorithm with the Offset BP-Based algorithm, that is, adding a scale factor coefficient, i.e., a weight factor α, and an offset factor, i.e., a bias factor β, to the approximate item in the minimum sum decoding algorithm check node information update process. Among them, the compensation factor and the relevant information of the LDPC matrix to be used are sent to the GPU in the form of an array, and the specific operation is to open up video memory on the GPU and transmit data. The weight factor and bias factor added in this embodiment are input into the iterative process to compensate for the error caused by the simplified formula and reduce the error rate.

[0100] Specifically, updating the check node includes the following steps:

[0101] Obtain a preset number of iterations; it should be noted that different numbers of iterations result in different error correction performances. As the number of iterations increases, the error correction performance gradually improves. After reaching a certain number of times, the change in error correction performance tends to be flat. The number of iterations can be set according to the actual amount of calculation, and this embodiment does not limit this.

[0102] Get the preset weight factor and bias factor;

[0103] The check node update calculation is performed by using the bias factor β and the weight factor α, satisfying:

[0104]

[0105]

[0106] L(r ji )←sgn(L(r ji ))·max(|L(r ji )|-β,0);

[0107] Among them, α>1, the improved algorithm at this time is the Normalized BP-Based algorithm. The improved algorithm corresponding to the β offset factor is the Offset BP-Based algorithm. All check messages less than β are set to 0, because these messages have no effect on the message calculation of the variable node.

[0108] Send the calculation results and the LDPC check matrix information to be used to the GPU in the form of an array;

[0109] Calculate the message value transmitted by the variable node to the check node;

[0110] Perform thread synchronization to ensure that all calculations are completed before the next iteration. Each thread processes and calculates the information transmitted by a check node. The calculation results of thread synchronization do not need to be sent back to the GPU.

[0111] The update of variable nodes is also an iterative process. The iterative process can refer to the update process of the check node described above. In the minimum sum decoding algorithm, the probability information in the form of log-likelihood ratio converts the large number of multiplications and divisions required in the update process of variable nodes in the classic BP decoding algorithm into additions. The update calculation of the variable node satisfies:

[0112] S4. After each round of iterative calculation, the probability information of the variable node is judged. If the probability information is greater than 0, the judgment result is recorded as 0, otherwise the judgment result is recorded as 1 to obtain a decoding result.

[0113] S4 determines the probability information of the variable node, including: after each round of iterative calculation, determining the probability information at the variable node to satisfy:

[0114] If L (l) (q i )>0, then otherwise is the decoding result.

[0115] After the determination is completed, the data with the determination results can be stored again in order through the CPU.

[0116] After the judgment is completed and stored, the calculation result can be compared with the bits of the transmitted signal, and the erroneous bits can be recorded to calculate the bit error rate BER; the calculation result can be compared with the bits of the transmitted signal one by one. If there is a bit error in the transmitted data block, the data block is considered to have a decoding error, and the number of erroneous data blocks is recorded. The ratio with the total data blocks is calculated to obtain the frame error rate FER, etc., so as to evaluate the error correction performance.

[0117] In summary, the method described in this embodiment proposes an efficient high-rate real-time post-processing method under the BSC channel model by combining LDPC codes, the minimum sum algorithm, and the parallel computing capabilities of the CUDA architecture. This method can not only effectively resist errors in the channel and improve the reliability of data transmission, but also utilize the parallel processing capabilities of the GPU to significantly accelerate the decoding process and ensure the real-time and high-efficiency of high-rate data transmission.

[0118] Embodiment 2

[0119] Embodiment 2 discloses a device corresponding to the high bit rate real-time key extraction method of the above embodiment, which is a virtual device structure of the above embodiment. Please refer to Figure 2 As shown, including:

[0120] A simulation module 210 is used to read an LDPC check matrix file and introduce a noise signal through a simulated BSC channel in a CUDA environment;

[0121] The iterative calculation module 220 is used to initialize the probability information of the noisy signal in the randomly generated signal by using the LDPC check matrix file and the minimum sum decoding algorithm; according to the noisy signal initialized with the probability information, iteratively calculate the nodes of the LDPC check matrix file by using the LLRBP decoding algorithm to update the check nodes and the variable nodes;

[0122] The determination module 230 is used to determine the probability information of the variable node after each round of iterative calculation. If the probability information is greater than 0, the determination result is recorded as 0, otherwise the determination result is recorded as 1, and the decoding result is obtained and stored.

[0123] Preferably, reading the LDPC check matrix file and introducing the noise signal through the simulated BSC channel includes:

[0124] Initialize a random number generator, the random number generator is used to generate an original codeword and generate a flip bit according to an error probability, the original codeword is a randomly generated signal, the flip bit is generated as a randomly generated noise, the signal and the noise are combined through a simulated BSC channel to obtain a noisy signal.

[0125] Preferably, initializing probability information of the noisy signal using the LDPC check matrix file with a minimum sum decoding algorithm includes:

[0126] Read the noisy signal and store it in array form;

[0127] Reorder the array elements according to the order of the variable nodes;

[0128] Sending the noisy signal and the LDPC check matrix information to be used to the GPU in the form of an array;

[0129] Calculate the message value L(q) transmitted by the variable node to the check node ij ), satisfying: L (0) (q ij )=L(R i ), Among them, P iis the initial probability value passed to the variable node by the channel, L(P i ) is the initial probability likelihood ratio of the channel transmitted to the variable node, i is the variable node, j is the check node, q ij Represents the external probability information transmitted from variable node i to check node j;

[0130] Perform thread synchronization to ensure that all calculations are completed before the next operation.

[0131] Preferably, the check nodes are updated by using a Normalized BP-Based algorithm and an Offset BP-Based algorithm.

[0132] Preferably, updating the check node comprises the following steps:

[0133] Get the preset number of iterations;

[0134] Get the preset weight factor and bias factor;

[0135] The check node update calculation is performed by using the bias factor β and the weight factor α, satisfying:

[0136]

[0137] L(r ji )←sgn(L(r ji ))·max0 L(r ji )||-β,0) where L is the probability likelihood ratio, r ij represents the external probability information transmitted from check node j to variable node i, R j\i represents the set of variable nodes connected to the check node except i;

[0138] Send the calculation results and the LDPC check matrix information to be used to the GPU in the form of an array;

[0139] Calculate the message value transmitted by the variable node to the check node;

[0140] Perform thread synchronization to ensure that all calculations are completed before the next operation.

[0141] Preferably, the update L of the variable node (l) (q i ) calculation satisfies: Among them, r ij represents the external probability information transmitted from check node j to variable node i, C i is the original codeword, q i It is the probability information transmitted by variable node i to all the check nodes connected to it.

[0142] Preferably, determining the probability information of the variable node includes: after each round of iterative calculation, determining the probability information at the variable node to satisfy: if L (l) (q i )>0, then otherwise is the decoding result.

[0143] Embodiment 3

[0144] Figure 3 A schematic diagram of the structure of an electronic device provided in Embodiment 3 of the present invention is shown in FIG. Figure 3 As shown, the electronic device includes a processor 310, a memory 320, an input device 330 and an output device 340; the number of processors 310 in the computer device can be one or more. Figure 3 A processor 310 is taken as an example; the processor 310, the memory 320, the input device 330 and the output device 340 in the electronic device can be connected via a bus or other means. Figure 3 The example of connecting through bus is taken in the following.

[0145] The memory 320 is a computer-readable storage medium that can be used to store software programs, computer executable programs and modules, such as program instructions / modules corresponding to the high bit rate real-time key extraction method in the embodiment of the present invention. The processor 310 executes various functional applications and data processing of the electronic device by running the software programs, instructions and modules stored in the memory 320, that is, the high bit rate real-time key extraction method in the above-mentioned embodiment 1 is implemented.

[0146] The memory 320 may mainly include a program storage area and a data storage area, wherein the program storage area may store an operating system and at least one application required for a function; the data storage area may store data created according to the use of the terminal, etc. In addition, the memory 320 may include a high-speed random access memory, and may also include a non-volatile memory, such as at least one disk storage device, a flash memory device, or other non-volatile solid-state storage device. In some instances, the memory 320 may further include a memory remotely arranged relative to the processor 310, and these remote memories may be connected to the electronic device via a network. Examples of the above-mentioned network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.

[0147] The input device 330 may be used to receive input user identity information, LDPC check matrix files, etc. The output device 340 may include a display device such as a display screen.

[0148] Embodiment 4

[0149] Embodiment 4 of the present invention further provides a storage medium containing computer executable instructions, which can be used for a computer to execute a high bit rate real-time key extraction method, the method comprising:

[0150] In the CUDA environment, the LDPC check matrix file is read and the noise signal is introduced through the simulated BSC channel;

[0151] Initializing probability information of the noisy signal using the LDPC check matrix file and a minimum sum decoding algorithm;

[0152] According to the noise-added signal initialized by the probability information, the LDPC check matrix file nodes are iteratively calculated by the LLRBP decoding algorithm to update the check nodes and the variable nodes;

[0153] After each round of iterative calculation, the probability information of the variable node is judged. If the probability information is greater than 0, the judgment result is recorded as 0, otherwise the judgment result is recorded as 1, and the decoding result is obtained and stored.

[0154] Of course, the computer executable instructions of a storage medium including computer executable instructions provided in an embodiment of the present invention are not limited to the method operations described above, and can also execute related operations in the high-code-rate real-time key extraction method provided in any embodiment of the present invention.

[0155] Through the above description of the implementation methods, the technicians in the relevant field can clearly understand that the present invention can be implemented by means of software and necessary general hardware, and of course can also be implemented by hardware, but in many cases the former is a better implementation method. Based on such an understanding, the technical solution of the present invention is essentially or the part that contributes to the prior art can be embodied in the form of a software product, and the computer software product can be stored in a computer-readable storage medium, such as a computer floppy disk, read-only memory (ROM), random access memory (RAM), flash memory (FLASH), hard disk or optical disk, etc., including a number of instructions for an electronic device (which can be a mobile phone, a personal computer, a server, or a network device, etc.) to execute the methods described in each embodiment of the present invention.

[0156] It is worth noting that in the above-mentioned embodiment of the high-code rate real-time key extraction method device, the various units and modules included are only divided according to functional logic, but are not limited to the above-mentioned division, as long as the corresponding functions can be achieved; in addition, the specific names of the functional units are only for the convenience of distinguishing each other, and are not used to limit the scope of protection of the present invention.

[0157] For those skilled in the art, various other corresponding changes and deformations can be made according to the technical solutions and concepts described above, and all of these changes and deformations should fall within the protection scope of the claims of the present invention.

Claims

1. A high code rate real-time key extraction method, characterized in that: The following steps are involved: In the CUDA environment, the LDPC check matrix file is read and the noise signal is introduced through the simulated BSC channel; Initializing probability information of the noisy signal using the LDPC check matrix file and a minimum sum decoding algorithm; According to the noise-added signal initialized by the probability information, the LDPC check matrix file nodes are iteratively calculated by the LLRBP decoding algorithm to update the check nodes and the variable nodes; After each round of iterative calculation, the probability information of the variable node is judged. If the probability information is greater than 0, the judgment result is recorded as 0, otherwise the judgment result is recorded as 1 to obtain the decoding result.

2. The high code rate real-time key extraction method according to claim 1, characterized in that: Read the LDPC check matrix file and introduce the noise signal through the simulated BSC channel, including: Initializing a random number generator, wherein the random number generator is used to generate an original codeword and generate a flip bit according to an error probability, wherein the original codeword is a randomly generated signal generating a flip bit as a randomly generated noise; The signal and the noise are combined through a simulated BSC channel to obtain a noisy signal.

3. The high code rate real-time key extraction method according to claim 1 or 2, characterized in that: Initializing probability information of the noisy signal using the LDPC check matrix file with a minimum sum decoding algorithm, including: Read the noisy signal and store it in array form; Reorder the array elements according to the order of the variable nodes; Sending the noisy signal and the LDPC check matrix information to be used to the GPU in the form of an array; Calculate the message value L(q) transmitted by the variable node to the check node ij ), satisfying: L (0) (q ij )=L(P i ), Among them, P i is the initial probability value passed to the variable node by the channel, L(P i ) is the initial probability likelihood ratio of the channel transmitted to the variable node, i is the variable node, j is the check node, q ij Represents the external probability information transmitted from variable node i to check node j; Perform thread synchronization to ensure that all calculations are completed before the next operation.

4. The high code rate real-time key extraction method according to claim 1, characterized in that: The check nodes are updated by using a Normalized BP-Based algorithm and / or an Offset BP-Based algorithm.

5. The high code rate real-time key extraction method according to claim 4, characterized in that: Updating a check node includes the following steps: Obtain the preset number of iterations, preset weight factors and bias factors; The check node update calculation is performed by using the bias factor β and the weight factor α, satisfying: L(r ji )←sgn(L(r ji ))·max)|L(r ji )|-β, 0), where L is the probability likelihood ratio, r ij represents the external probability information transmitted from check node j to variable node i, R j\i represents the set of variable nodes connected to the check node except i; Send the calculation results and the LDPC check matrix information to be used to the GPU in the form of an array; Calculate the message value transmitted by the variable node to the check node; Perform thread synchronization to ensure that all calculations are completed before the next iteration.

6. The high code rate real-time key extraction method according to claim 1, characterized in that: The update L of the variable node (l) (q i ) calculation satisfies: Among them, ri j represents the external probability information transmitted from check node j to variable node i, C i is the original codeword, q i It is the probability information transmitted by variable node i to all the check nodes connected to it.

7. The high code rate real-time key extraction method according to claim 1, characterized in that: The probability information of the variable node is determined, including: after each round of iterative calculation, the probability information at the variable node is determined to satisfy: If L (l) (q i )>0, then otherwise is the decoding result.

8. A high-rate real-time key extraction device, characterized in that: It includes: A simulation module is used to read the LDPC check matrix file and introduce the noise signal through the simulated BSC channel in the CUDA environment; An iterative calculation module, used for initializing probability information of a noise-added signal in the randomly generated signal by using the LDPC check matrix file and a minimum sum decoding algorithm; According to the noise-added signal initialized by the probability information, the LDPC check matrix file nodes are iteratively calculated by the LLRBP decoding algorithm to update the check nodes and the variable nodes; The determination module is used to determine the probability information of the variable node after each round of iterative calculation. If the probability information is greater than 0, the determination result is recorded as 0, otherwise the determination result is recorded as 1, and the decoding result is obtained and stored.

9. An electronic device comprising a processor, a storage medium and a computer program, wherein the computer program is stored in the storage medium, wherein: When the computer program is executed by a processor, the high-rate real-time key extraction method according to any one of claims 1 to 7 is implemented.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the high-rate real-time key extraction method according to any one of claims 1 to 7 is implemented.

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